Voltage contrast measurement mark

Abstract

A measurement mark is disclosed. According to certain embodiments, the measurement mark includes a first set of test structures developed in a first layer on a substrate, each first test structure in the first set of test structures including a plurality of first features made of a first conductive material. The measurement mark also includes a second set of test structures developed in a second layer adjacent the first layer, each second test structure in the second set of test structures including a plurality of second features made of a second conductive material. The measurement mark is configured to indicate connectivity between the first set of test structures and an associated second test structure of the second set of test structures when imaged using a voltage contrast imaging method.

Description

[0001] Description of the case

[0002] This application is a divisional application of the Chinese national phase patent application of the PCT application with international application number PCT / EP2018 / 083994, Chinese national application number 201880079555.6, and invention name “Voltage Comparison Measurement Mark”. Technical Field

[0003] The present disclosure relates generally to overlay metrology during semiconductor device fabrication, and more particularly to metrology marks for measuring alignment errors and critical dimensions of two layers based on voltage contrast. Background Art

[0004] A lithographic apparatus is a machine that applies a desired pattern to a substrate, usually to a target portion of a substrate. A lithographic apparatus can be used, for example, in the manufacture of an integrated circuit (IC). In this case, a patterning device (which is alternatively referred to as a mask or reticle) can be used to generate a circuit pattern to be formed on a single layer of an IC. The pattern can be transferred to a target portion (e.g., a portion including one or more dies) on a substrate (e.g., a silicon wafer). The transfer of the pattern is usually performed via imaging onto a layer of radiation-sensitive material (resist) disposed on the substrate. Typically, a single substrate will contain a network of adjacent target portions that are patterned continuously. Known lithographic apparatus include: a so-called stepper, in which each target portion is irradiated by exposing the entire pattern to the target portion at one time; and a so-called scanner, in which each target portion is irradiated by scanning the pattern by a radiation beam in a given direction (the "scanning" direction) and simultaneously scanning the substrate in parallel or antiparallel to the direction. The pattern can also be transferred from a patterning device to a substrate by imprinting the pattern onto the substrate.

[0005] In a lithographic process, it is desirable to frequently measure the structures produced, for example for process control and verification. Typically, one or more parameters of the structure are measured or determined, for example, the overlay error between successive layers formed in or on a substrate. There are a variety of metrology techniques for measuring microstructures formed in a lithographic process. An example of such a tool is an optical scatterometer developed for use in the field of lithography. The device directs a radiation beam onto a target on the surface of a substrate and measures one or more properties of the redirected radiation, for example, the intensity versus wavelength at a single reflection angle; the intensity versus reflection angle at one or more wavelengths; or the polarization angle versus reflection angle, to obtain a set of data from which properties of interest of the target can be determined. The determination of the properties of interest can be performed by various techniques, such as reconstructing the target structure by iterative methods such as rigorous coupled wave analysis or finite element methods, library searches, and principal components.

[0006] However, as the physical size of IC components continues to decrease to sub-100 nm or even sub-10 nm, optical scatterometers become increasingly inadequate because their resolution is limited by the wavelength of light. Due to this difference in optical resolution and device size, i.e., because the optical test structures have a different pitch than the device structures, a non-zero offset needs to be applied to the measurement results. Typically, the non-zero offset must be estimated based on manual calibration measurements or using other complex methods. Summary of the invention

[0007] Embodiments of the present disclosure relate to voltage contrast measurement marks. In some embodiments, a measurement mark is provided. The measurement mark includes a first test structure set developed in a first layer on a substrate, each first test structure in the first test structure set including a plurality of first features made of a first conductive material. The measurement mark also includes a second test structure set developed in a second layer adjacent to the first layer, each second test structure in the second test structure set including a plurality of second features made of a second conductive material. The measurement mark is configured to indicate connectivity between the first test structure set and an associated second test structure in the second test structure set when imaged using a voltage contrast imaging method.

[0008] In some embodiments, a measurement mark is provided. The measurement mark includes a first array of first features having a first pitch and a second array of second features having a second pitch, the first array and the second array being arranged in two consecutive layers on a substrate. The measurement mark is configured to determine an overlay value between the first feature relative to an associated second feature, or is configured to determine a critical dimension value of the first feature or the second feature when imaged using a voltage contrast imaging method.

[0009] In some embodiments, a system is provided. The system includes a particle beam tool for scanning a measurement mark and detecting scattered electrons from the measurement mark. The system also includes a controller coupled to the particle beam tool. The controller includes a circuit system to: generate a voltage contrast image based on the detected scattered electrons; and determine an overlay value or a critical dimension value based on the generated voltage contrast image.

[0010] In some embodiments, a method is provided. The method includes scanning a first set of test structures of measurement marks with a charged particle beam and detecting scattered electrons from the measurement marks. The method also includes generating a voltage contrast image based on the detected scattered electrons. The method also includes determining an overlay value or a critical dimension value based on the generated voltage contrast image.

[0011] In some embodiments, a non-transitory computer readable medium storing instructions is provided, which when executed by one or more processors causes the processor to perform a method. The method includes scanning a first set of test structures of measurement marks with a charged particle beam, and detecting scattered electrons from the measurement marks. The method also includes generating a voltage contrast image based on the detected scattered electrons. The method also includes determining an overlay value or a critical dimension value based on the generated voltage contrast image. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram illustrating an exemplary lithographic apparatus consistent with an embodiment of the present disclosure.

[0013] Figure 2 is a schematic diagram illustrating an exemplary lithography cell consistent with an embodiment of the present disclosure.

[0014] Figure 3 is a schematic diagram illustrating an exemplary optical metrology tool consistent with embodiments of the present disclosure.

[0015] Figure 4 is a schematic diagram illustrating an exemplary electron beam tool consistent with embodiments of the present disclosure.

[0016] Figure 5 is a schematic diagram showing voltage versus response of a substrate to electron beam irradiation consistent with an embodiment of the present disclosure.

[0017] Figure 6 is a schematic diagram showing voltage comparison measurement marks consistent with an embodiment of the present disclosure.

[0018] Figure 7 is a schematic diagram showing voltage comparison measurement marks consistent with an embodiment of the present disclosure.

[0019] Figure 8 It is consistent with the embodiment of the present disclosure. Figure 7 Schematic diagram of programmed overlay offset and CD variation in the marks shown.

[0020] Fig. 9 is a schematic diagram showing combined voltage contrast and optical metrology markings consistent with embodiments of the present disclosure.

[0021] Fig.10 is a schematic diagram showing features in combined voltage contrast and optical marking according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to exemplary embodiments, examples of which are shown in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present invention. Instead, they are merely examples of devices and methods consistent with various aspects related to the present invention as described in the appended claims.

[0023] The increased computing power of electronic devices while the physical size of the devices is reduced can be achieved by significantly increasing the packaging density of circuit components such as transistors, capacitors, diodes, etc. on IC chips. For example, in a smart phone, an IC chip (i.e., the size of a thumbnail) can include more than 2 billion transistors, each of which is less than 1 / 1000 the size of a human hair. Not surprisingly, semiconductor IC manufacturing is a complex process that requires hundreds of individual steps. Even a mistake in one step can greatly affect the functionality of the final product.

[0024] In particular, as dimensions decrease, the number of mask layers may increase and the size of features (lines, cuts, etc.) that need to be aligned continues to shrink. For example, at 10 or 7 nm, there may be 80 or more mask layers, while at 28 nm there are 40 layers. If these layers are not accurately measured, the features being patterned, deposited, and etched may not align well between layers.

[0025] In one aspect of the present disclosure, there is provided a method for providing an overlay mark (such as Figure 6 The overlay mark 60 shown is used to measure the overlay offset between two adjacent layers and the critical dimension (CD) of the features on each layer. The accuracy of the overlay mark is determined by the resolution of the pattern formed on the overlay mark. Therefore, the overlay mark can be scanned by an electron beam tool with low resolution but high throughput.

[0026] As used throughout this disclosure, unless expressly stated otherwise, the term "or" encompasses all possible combinations unless not feasible. For example, if it is stated that a device may include A or B, then unless expressly stated otherwise or not feasible, the device may include A or B or A and B. As a second example, if it is stated that a device may include A, B, or C, then unless expressly stated otherwise or not feasible, the device may include A, B, or C, A and B, A and C, B and C, or A and B and C.

[0027] Figure 1 is a schematic diagram showing an exemplary lithographic apparatus LA consistent with an embodiment of the present disclosure. Figure 1The lithography apparatus LA comprises: a source collector module SO; an illumination system (illuminator) IL configured to condition a radiation beam B (e.g., EUV radiation); a support (e.g., a mask table) MT constructed to support a patterning device (e.g., a mask or reticle) MA and connected to a first positioner PM configured to precisely position the patterning device; a substrate table (e.g., a wafer table) WT constructed to hold a substrate (e.g., a resist-coated wafer) W and connected to a second positioner PW configured to precisely position the substrate; and a projection system (e.g., a refractive projection system) PS configured to project a pattern imparted to the radiation beam B onto a target portion C (e.g., comprising one or more dies) of the substrate W through the patterning device MA.

[0028] The illumination system IL may include various types of optical components for directing, shaping or controlling the radiation, such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof.

[0029] The patterning device support structure holds the patterning device in a manner that depends on the orientation of the patterning device, the design of the lithographic apparatus, and other conditions (such as, for example, whether the patterning device is held in a vacuum environment). The patterning device support structure can use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device. For example, the patterning device support structure can be a frame or table that can be fixed or movable as needed. The patterning device support structure can ensure that the patterning device is in a desired position, for example relative to a projection system. The patterning device can be referred to as a reticle or mask.

[0030] The patterning device may be any device for imparting a pattern in its cross-section to a radiation beam so as to produce a pattern in a target portion of the substrate. It should be noted that the pattern imparted to the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate, for example when the pattern includes phase-shifting features or so called assist features. Typically, the pattern imparted to the radiation beam will correspond to a specific functional layer to be produced in the target portion of a device such as an integrated circuit.

[0031] The patterning device can be transmissive or reflective. Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels. Masks are well known in lithography and include various mask types (such as binary, alternating phase shift, and attenuated phase shift), as well as various hybrid mask types. An example of a programmable mirror array employs a matrix arrangement of small mirrors, each of which can be individually tilted to reflect an incident radiation beam in different directions. The tilted mirrors impart a pattern in the radiation beam, which is reflected by the mirror matrix.

[0032] The projection system can be any type of projection system including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation used or other factors such as the use of immersion liquid or the use of a vacuum. The projection system may be referred to as a projection lens.

[0033] As depicted here, the device is transmissive (eg, employing a transmissive mask). Alternatively, the device may be reflective (eg, employing a programmable mirror array of the type described above, or employing a reflective mask).

[0034] The lithographic apparatus LA may be of a type having two (dual stage) or more tables (e.g. two or more substrate tables, two or more patterning device supports, or a substrate table and a metrology table.) In such a "multi-stage" machine, the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposure.

[0035] The lithographic apparatus LA may also be of a type in which at least a portion of the substrate may be covered by a liquid having a relatively high refractive index, such as water, so as to fill the space between the projection system and the substrate. Immersion liquid may also be applied to other spaces in the lithographic apparatus, for example, between the mask and the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of the projection system. Immersion does not necessarily mean that structures such as the substrate must be submerged in the liquid, but only that the liquid is located between the projection system and the substrate during exposure.

[0036] refer to Figure 1 , the illuminator IL receives a radiation beam from a radiation source SO. The source and the lithographic apparatus may be separate entities, for example when the source is an excimer laser. In this case, the source is considered not to form part of the lithographic apparatus and the radiation beam is transferred from the source SO to the illuminator IL by means of a beam delivery system BD, which comprises, for example, suitable directing mirrors or a beam expander. In other cases, the source may be an integral part of the lithographic apparatus, for example when the source is a mercury lamp. The source SO and the illuminator IL and, if necessary, the beam delivery system BD may be referred to as a radiation system.

[0037] The illuminator IL may include an adjuster AD for adjusting the angular intensity distribution of the radiation beam. Typically, at least the outer and inner radial extents (commonly referred to as outer σ and inner σ, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. In addition, the illuminator IL may include various other components, such as an integrator IN and a converger CO. The illuminator may be used to adjust the radiation beam to have a desired uniformity and intensity distribution in its cross-section.

[0038] The radiation beam B is incident on and patterned by a patterning device (e.g., a mask) MA, which is held on a patterning device support (e.g., a mask table MT). After passing through the patterning device (e.g., a mask) MA, the radiation beam B passes through a projection system PS, which focuses the beam onto a target portion C of the substrate W. With the aid of a second positioner PW and a position sensor IF (e.g., an interferometric device, a linear encoder, a 2D encoder or a capacitive sensor), the substrate table WTa can be precisely moved, for example, in order to position a different target portion C in the path of the radiation beam B. Similarly, a first positioner PM and a further position sensor ( Figure 1 The first positioner PM is a first positioner that is preferably located at a positioner device (not explicitly shown in the figure) and a short-stroke module (not explicitly shown in the figure) can be used to accurately position the patterning device (e.g. mask) MA relative to the path of the radiation beam B, for example after mechanical retrieval from a mask library, or during scanning. Typically, movement of the patterning device support (e.g. mask table) MT can be achieved with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the first positioner PM. Similarly, movement of the substrate table WTa can be achieved using a long-stroke module and a short-stroke module, which form part of the second positioner PW. In the case of a stepper (as opposed to a scanner), the patterning device support (e.g. mask table) MT may be connected to the short-stroke actuator only, or may be fixed.

[0039] The patterning device (e.g., mask) MA and substrate W can be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2. In the present disclosure, "mask" and "target" are used interchangeably. Although the substrate alignment marks as shown occupy dedicated target portions, they can be located in the spaces between target portions (these are called scribe alignment marks). Similarly, in the case where more than one die is provided on the patterning device (e.g., mask) MA, the mask alignment marks can be located between the dies. Small alignment marks can also be included within the die, among the device features, in which case it is desirable that the mark be as small as possible and do not require any imaging or processing conditions that are different from adjacent features. The alignment system for detecting alignment marks will be further described below.

[0040] The depicted device can be used in at least one of the following modes:

[0041] 1. In step mode, the patterning device support (e.g. mask table) MT and the substrate table WTa are kept substantially stationary while the entire pattern imparted to the radiation beam is projected onto a target portion C at one time (i.e. a single static exposure). The substrate table WTa is then shifted in the X and / or Y direction so that a different target portion C can be exposed. In step mode, the maximum size of the exposure field limits the size of the target portion C imaged in a single static exposure.

[0042] 2. In scan mode, the patterning device support (e.g. mask table) MT and the substrate table WTa are scanned synchronously while a pattern imparted to the radiation beam is projected onto a target portion C (i.e. a single dynamic exposure). The speed and direction of the substrate table WTa relative to the patterning device support (e.g. mask table) MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS. In scan mode, the maximum size of the exposure field limits the width of the target portion in a single dynamic exposure (in the non-scanning direction), while the length of the scanning movement determines the height of the target portion (in the scanning direction).

[0043] 3. In another mode, the patterning device support (e.g., mask table) MT remains substantially stationary to hold the programmable patterning device, and the substrate table WTa is moved or scanned while a pattern imparted to the radiation beam is projected onto a target portion C. In this mode, typically a pulsed radiation source is employed, and the programmable patterning device is updated as required after each movement of the substrate table WTa or between consecutive radiation pulses during scanning. This mode of operation can be readily applied to maskless lithography utilizing a programmable patterning device, such as a programmable mirror array of the type described above.

[0044] Combinations or variations on the above described modes of use or entirely different modes of use may also be employed.

[0045] The lithographic apparatus LA is of a so-called dual-stage type, having two tables WTa, WTb (e.g., two substrate tables) and two stations (exposure station and measurement station), between which the table can be exchanged. For example, while a substrate on one table is exposed at the exposure station, another substrate can be loaded onto another substrate table at the measurement station and various preparatory steps can be performed. The preparatory steps may include: using a level sensor LS to draw a surface control map of the substrate, and using an alignment sensor AS to measure the position of alignment marks on the substrate, the two sensors being supported by a reference frame RF. If the position sensor IF cannot measure the position of the table when the table is located at the measurement station and the exposure station, a second position sensor may be provided to track the position of the table at the two stations. As another example, while a substrate on one table is being exposed at the exposure station, another table without a substrate is waiting at the measurement station (where measurement activities may occur). The other table has one or more measurement devices and may optionally have other tools (e.g., cleaning equipment). When the substrate has finished exposure, the table without a substrate moves to the exposure station to perform, for example, measurement, and the table with a substrate moves to a position (e.g., measurement station) to unload the substrate and load another substrate. These multiple arrangements enable the throughput of the device to be increased significantly.

[0046] Figure 1 The lithographic apparatus LA shown may form part of a lithography unit, sometimes also referred to as a lithography cell or lithography cluster, which comprises apparatus for performing one or more pre-exposure and post-exposure processes on a substrate. Figure 2 is a schematic diagram showing an exemplary lithographic cell LC consistent with an embodiment of the present disclosure. Figure 2 , the lithography cell LC may include one or more spin coaters SC for depositing a resist layer, one or more developers DE for developing the exposed resist, one or more cooling plates CH, and one or more baking plates BK. The substrate handler or robot RO picks up the substrate from the input / output ports I / O1, I / O2, moves the substrate between different processing devices, and transfers the substrate to the loading station LB of the lithography equipment. These devices, which are generally referred to as tracks, are under the control of the track control unit TCU, which itself is controlled by the supervisory control system SCS, which also controls the lithography equipment via the lithography control unit LACU. Therefore, different devices can be operated to maximize throughput and processing efficiency.

[0047] In order to correctly and consistently expose the substrate exposed by the lithographic equipment, it is desirable to check the exposed substrate to measure one or more properties. These properties can include overlay errors, line widths, critical dimensions (CD) between subsequent layers, etc. In addition, as described below, inspection can be used to derive process parameters, such as sidewall angle imbalance. If an error is detected, the exposure of one or more subsequent substrates can be adjusted, especially when the inspection should be performed as soon as possible and fast enough to make another substrate of the same batch still exposed. In addition, the exposed substrate can be peeled off and reprocessed (to increase yield) or discarded to avoid exposure on a known defective substrate. In the case where only some target portions of the substrate are defective, further exposure can be performed only on those good target portions. Another possibility is to adjust the settings of the subsequent process steps to compensate for errors, such as the time of the trimming etching step can be adjusted to compensate for the change of substrate to substrate CD caused by the lithographic process step.

[0048] The inspection device is used to determine one or more properties of the substrate, especially to determine how one or more properties of different substrates or different layers of the same substrate vary from layer to layer or across substrates. The inspection device can be integrated into the lithographic device LA or the lithographic cell LC, or can be a stand-alone device. In order to be able to perform the fastest measurement, it is desirable that the inspection device measures one or more properties in the exposed resist layer immediately after exposure. However, the latent image in the resist has a very low contrast (there is only a small difference in the refractive index between the part of the resist that has been exposed to radiation and the part that has not been exposed to radiation), and not all inspection devices have sufficient sensitivity to perform useful measurements on the latent image. Therefore, the measurement can be performed after the post-exposure baking step (PEB), which is usually the first step performed on the exposed substrate and will increase the contrast between the exposed and unexposed parts of the resist. At this stage, the image in the resist can be referred to as a semi-latent image. It is also possible to measure the image of the developed resist (the exposed or unexposed part of the resist has been removed at this time), or it can also be measured after a pattern transfer step (such as etching). The latter possibility limits the possibilities for reworking defective substrates, but may still provide useful information, e.g. for process control purposes.

[0049] In disclosed embodiments, the inspection device may be an optical metrology tool, such as a scatterometer. Figure 3 is a schematic diagram illustrating an exemplary scatterometer 10 consistent with embodiments of the present disclosure. Figure 3, the scatterometer 10 includes a broadband (white light) radiation projector 102 that projects radiation onto a substrate 106. The reflected radiation is passed to a spectrometer detector 104, which measures a spectrum 110 of the reflected radiation (i.e., a measurement of intensity versus wavelength). From this data, the structure or profile that produced the detected spectrum can be reconstructed by a controller 30 in communication with the scatterometer 10. For example, the controller 30 can perform a coupled wave analysis and nonlinear regression or by communicating with, for example, Figure 3 The structure or profile is reconstructed by comparing it to the simulated spectral library shown at the bottom of FIG. 1 . Generally speaking, for reconstruction, the general form of the structure is known, and some parameters are assumed from knowledge of the fabrication process of the structure, leaving only some structural parameters to be determined from the scatterometry data. In various embodiments, the scatterometer 10 can be configured as a normal scatterometer or an oblique incidence scatterometer.

[0050] The resolution of optical metrology tools is limited by the wavelength of light, which is typically a few hundred nanometers. In the disclosed embodiments, the inspection apparatus may also be a charged particle (eg, electron) beam microscope capable of resolving less than a nanometer, such as a scanning electron microscope (SEM). Figure 4 is a schematic diagram illustrating an exemplary electron beam tool 20 consistent with the disclosed embodiments. Figure 4 As shown, the electron beam tool 20 includes a motorized stage 200 and a wafer holder 202 supported by the motorized stage 200 to hold a wafer 203 to be inspected. The electron beam tool 20 also includes a composite objective 204, an electron detector 206 (which includes electron sensor surfaces 206a and 206b), an objective aperture 208, a focusing lens 210, a beam limiting aperture 212, a gun aperture 214, an anode 216, and a cathode 218, one or more of which can be aligned with the optical axis 270 of the electron beam tool 20.

[0051] In some embodiments, the composite objective 204 may include a modified swing retarder immersion objective (SORIL) including a pole piece 204a, a control electrode 204b, a deflector or a set of deflectors 204c, and an excitation coil 204d. The electron beam tool 20 may additionally include an energy dispersive X-ray spectrometer (EDS) detector (not shown) to characterize materials on the wafer.

[0052] A primary electron beam 220 is emitted from the cathode 218 by applying a voltage between the anode 216 and the cathode 218. The primary electron beam 220 passes through the gun aperture 214 and the beam limiting aperture 212, both of which determine the current of the electron beam entering the focusing lens 210, which is located below the beam limiting aperture 212. The focusing lens 210 focuses the primary electron beam before the beam enters the objective lens aperture 208 to set the current of the electron beam before entering the compound objective lens 204.

[0053] The composite objective lens 204 can focus the primary electron beam 220 onto the wafer 203 for inspection, and can form a detection point 222 on the surface of the wafer 203. The deflector 204c deflects the primary electron beam 220 to scan the detection point 222 on the wafer 203. For example, during the scanning process, the deflector 204c can be controlled to deflect the primary electron beam 220 to different positions on the top surface of the wafer 203 at different time points in sequence to provide data for image reconstruction of different parts of the wafer 203. In addition, the deflector 204c can also be controlled to deflect the primary electron beam to a specific position on different sides of the wafer 203, at different tie points, to provide data for stereoscopic image reconstruction of the wafer structure at the position. In addition, in some embodiments, the anode 216 and the cathode 218 can be configured to generate multiple primary electron beams 220, and the electron beam tool 104 can include multiple deflectors 204c to project multiple primary electron beams 220 to different parts / different sides of the wafer 203 at the same time.

[0054] When current is applied to the excitation coil 204d, an axially symmetric (i.e., symmetrical about the optical axis 270) magnetic field will be generated in the wafer surface region. A portion of the wafer 203 scanned by the primary electron beam 220 can be immersed in the magnetic field. Different voltages are applied to the wafer 203, the magnetic objective lens 204a, and the control electrode 204b to generate an axially symmetric retarding electric field near the wafer surface. The electric field reduces the energy of the primary electron beam 220 that strikes near the wafer surface before colliding with the wafer 203. The control electrode 204b, which is electrically isolated from the pole piece 204a, controls the axially symmetric electric field on the wafer to prevent micro-arcing of the wafer and ensure that the appropriate beam is focused on the wafer surface together with the axially symmetric magnetic field.

[0055] When the wafer 203 receives the primary electron beam 220, the secondary electron beam 230 may be emitted from a portion of the wafer 203. The secondary electron beam 230 may be received by the sensor surfaces 206a and 206b of the electron detector 206. The electron detector 206 may generate a signal (e.g., voltage, current, etc.) representing the intensity of the secondary electron beam 230 and provide the signal to the controller 30 in communication with the electron detector 206. The intensity of the secondary electron beam 230 may vary according to the external or internal structure of the wafer 203. In addition, as described above, the primary electron beam 220 may be projected onto different positions of the top surface of the wafer 203 or onto different sides of the wafer 203 at a specific position to generate a secondary electron beam 230 having different intensities. Therefore, by mapping the intensity of the secondary electron beam 230 with the position of the wafer 203, the controller 30 may reconstruct an image reflecting the internal or external structure of the wafer 203.

[0056] In addition, despite Figure 4 The electron beam tool 20 is shown using a single primary electron beam, but it is contemplated that the electron beam tool 20 may also be a multi-beam inspection tool using multiple primary electron beams. The number of primary electron beams used in the electron beam tool 20 is not limited by the present application.

[0057] Consistent with the present disclosure, an e-beam tool may be used to measure overlay misalignment and critical dimension based on the voltage-contrast response of a substrate to e-beam irradiation. Figure 5 is a schematic diagram showing a voltage contrast response model consistent with an embodiment of the present disclosure. Figure 5 , a test structure 52 is developed on top of the substrate 50. The test structure 52 includes a plurality of features 53, 54 separated by insulating material 55. As the electron beam tool 20 scans the surface of the test structure 52, the controller 30 can generate a voltage contrast image 56 of the test structure. Feature 53 is shorted to ground and does not retain a positive charge. As such, feature 53 can repel more secondary electrons and will appear as a bright area on the voltage contrast image. Conversely, feature 54 is disconnected from ground and will have a positive charge accumulation, which causes feature 54 to repel fewer secondary electrons and therefore appear darker on the voltage contrast image.

[0058] The foregoing description has described the presence of a short circuit condition causing the corresponding feature to appear brighter, and the presence of an open circuit condition causing the corresponding feature to appear darker. However, it is clear to those skilled in the art that the light and dark appearance may change or even be reversed depending on the actual processing of the test structure or the setup of the electron beam tool.

[0059] Figure 6is a schematic diagram showing voltage comparison measurement marks consistent with an embodiment of the present disclosure. Figure 6 The left side of FIG. 4 shows a top view of an overlay mark 60. The overlay mark 60 includes a plurality of test structures 62 for determining registration errors between two wafer layers in two different directions, such as edge placement errors. Figure 6 The left side of FIG. 1 shows only the test structures in the top layer (hereinafter also referred to as the “current layer” or the “first layer”), but it is expected that the second layer (hereinafter also referred to as the “previous layer”) immediately below the top layer also includes a plurality of test structures 62. In addition, although Figure 6 Only nine test structures 62 arranged in a 3×3 matrix are shown on the left side of FIG. 1 , but it is contemplated that the disclosed overlay mark may include as many test structures 62 as desired.

[0060] In the illustrated embodiment, the test structures 62 are square and may have dimensions similar to the pixel dimensions of an electron beam tool in order to increase inspection throughput. The test structures 62 are spatially separated from one another so that they do not overlap portions of adjacent test structures of the second layer. As described above, the test structures 62 are configured to provide overlay information in two directions, such as X and Y directions that are orthogonal to one another. Each test structure 62 includes a periodic structure (not shown) that includes features arranged in spaced-apart rows and columns.

[0061] Figure 6 The right side of shows the voltage contrast response of the test structure 62 to electron beam irradiation. The periodic features in the test structure 62 are made of conductive materials. In some embodiments, the conductive material can be a metal, including but not limited to copper, tungsten, nickel, cobalt, tantalum and titanium nitride. In some embodiments, the conductive material can be a semiconductor, including but not limited to crystalline silicon, polycrystalline silicon, amorphous silicon and silicon germanium. Features in different wafer layers can use the same type of conductive material or different types of conductive materials. When the features in the current layer (i.e., the top layer) are connected to the features in the previous layer (i.e., the lower layer), the corresponding test structure 62 will be shown as a bright area on the voltage contrast image of the overlay mark 60. On the contrary, when the features in the current layer are disconnected from the features in the previous layer, the corresponding test structure 62 will be shown as a dark area on the voltage contrast image. As described above, the size of the test structure 62 can be similar to or equal to the pixel size of the electron beam tool 20, so that one pixel of the voltage contrast image corresponds to the test structure 62. In this way, the inspection throughput can be improved.

[0062] In the disclosed embodiment, the test structure 62 is programmed to have different overlay offset values, i.e., X / Y values. Figure 6As shown on the left side of FIG. 6 , the test structure 62 may have varying overlay offset values ​​in the X and Y directions, respectively. Based on the overlay offset values ​​and the voltage contrast image, the overlay error may be determined more accurately.

[0063] The disclosed overlay marks can also be used to measure critical dimensions. Figure 7 is a schematic diagram showing a voltage contrast measurement overlay mark 70 consistent with an embodiment of the present disclosure. Similar to the overlay mark 60, the mark 70 includes a plurality of test structures 72. However, unlike the mark 60, the test structures 72 are designed to have varying critical dimension values ​​in the Y direction. Each test structure 72 includes a periodic structure (not shown) that includes features arranged in spaced rows and columns. The periodic features can be configured to have various sizes, shapes, and distributions. In addition, the pitch of the features can be varied across the test structure 72 to separate proximity effects or random effects.

[0064] Figure 7 A situation is shown in which various overlay offsets or critical dimensions may cause features in the current layer and the previous layer to be connected or disconnected, resulting in different voltage contrast responses. In this way, the mark 70 can be used to measure the critical dimension and the overlay error in the X direction at the same time. The above example is for illustrative purposes only. It should be understood that the disclosed mark can be configured to have any suitable combination of overlay process window values ​​and critical dimension values. For example, a mark can include multiple adjacent test structures to track asymmetric critical dimensions or overlay process windows.

[0065] The disclosed overlay marks can be used with low-resolution modes of electronic scanning tools (e.g., electron beam tools 20) while still achieving accurate overlay measurement / CD measurement. This is because the accuracy of overlay measurement / CD measurement is controlled by the resolution of the features of the overlay mark. Typically, state-of-the-art electron beam tools use a spot size of 1-2 nm to perform high-resolution imaging. However, smaller spot sizes and therefore smaller beam currents require longer scan times and thus reduce the throughput of the system. Since the disclosed overlay marks are not very sensitive to the resolution of the electron beam tool, they can be used with electron beam tools with very high scan rates and spot sizes of about 20 nm pixels, 200 nm pixels, or even 2 μm to infer sub-nanometer overlay. In particular, larger spot sizes allow higher beam currents, which can produce images with sufficient signal-to-noise ratios and contrast resolution. The light and dark patterns formed on the image of the overlay mark can accurately reflect the overlay value and the CD value. Therefore, the disclosed overlay marks allow high-resolution imaging and high beam currents to be achieved simultaneously, thereby allowing high scan speeds to increase system throughput.

[0066] Figure 8is a schematic diagram showing programmed overlay offset and CD variation in an overlay mark 70 consistent with an embodiment of the present disclosure. Figure 8 The overlay mark 70 can be programmed to have an overlay variation along the X direction and a CD variation along the Y direction. The variation range is from a few tenths of a nanometer (e.g., 0.5 nanometer) to several nanometers. In this way, the mark 70 can measure the overlay variation and CD at the device level.

[0067] In some embodiments, different marks can be integrated into a single "multi-patterning" mark. This means that the interaction of multiple masks can have complex overlay and critical dimension interactions, all of which can be studied by combining different masks at a specific overlay offset or CD offset. Multi-patterning marks can be used for a single conductor layer produced by combining multiple lithography steps, which is typically used in devices below 22nm.

[0068] Consistent with the present disclosure, a process window may be characterized as an area or region in a two-dimensional overlay-CD map. When a wafer is exposed in an overlay-CD state within the process window, chips made from the wafer will generally function, whereas when a wafer is exposed in an overlay-CD state outside the process window, chips made from the wafer will generally not function.

[0069] In addition, the process window of the lithography process is further limited because different patterns within a circuit design may have different process windows. These differences may include shifts in the optimal focal plane position, shifts in the optimal exposure, shifts in the optimal overlay position, and changes in the allowed focus or exposure range. Different patterns may also have different successful printing criteria. Although CD deviations can be up to + / -15% for some non-critical features, the tolerance for the most critical structures may be only half that. The failure modes of different patterns may also be very different. Some patterns may be considered unacceptable due to excessive CD variations, others may be considered unacceptable due to excessive variations in their sidewall profiles, and yet others may experience line end pullback or corner rounding. Catastrophic pattern failures are also possible due to interactions with adjacent structures. If a given feature is printed as an isolated structure, acceptable CD variations may result in bridging, necking, or other unacceptable pattern variations in different local environments.

[0070] In some embodiments, a random algorithm can be used to adjust the overlay (or pitch) variation and the CD variation to quantify the process window. The distribution of overlay variation and CD variation can be correlated with a wafer chip yield map. For example, statistical analysis can be used to extract information about which overlay variation or CD variation is a key yield limiting factor or is highly correlated with certain characteristics of yield fluctuations or excursions.

[0071] In some embodiments, the determined process window can be provided as feedback to a lithography process control system that provides data on how the lithography process is performing, for example, whether the CD and layer alignment of all features are within specifications, and which process condition parameters should be adjusted and by how much in order to keep the lithography process and exposure tool in optimal operating conditions. As used in this disclosure, "process condition parameter" refers to any exposure tool parameter or lithography process parameter. Process condition parameters may also be referred to as "input parameters" of the lithography process. This feedback process can be repeated to ensure that the lithography process is strictly controlled.

[0072] The disclosed voltage contrast marks require that the measurements be performed after etching, filling and polishing the current layer and thus may cause delays in acquiring overlay or CD information.To address this problem, the present disclosure also provides combined voltage contrast and optical metrology marks. Fig. 9 is a schematic diagram showing a combined voltage contrast and optical metrology mark 90 consistent with an embodiment of the present disclosure. Fig. 9 , the mark 90 may include a plurality of voltage comparison test structures 92, the configuration of the voltage comparison test structure 92 is similar to the test structure 62 ( Figure 6 ) and 72( Figure 7 ) is similar to the configuration of the electron beam tool 20. In this way, the electron beam tool 20 can scan the test structure 92 and obtain the voltage contrast response of the test structure 92 to determine the overlay information and the critical dimension information.

[0073] Furthermore, the marking 90 may include a plurality of optical test structures 94 . Fig.10 is a schematic diagram illustrating features in an optical test structure 94 consistent with an embodiment of the present disclosure. Fig.10, four optical test structures 94 are placed closely together so that they are all within the field of view of the scatterometer 10 (e.g., within the measurement point formed by the illumination beam of the scatterometer 10). Therefore, the four optical test structures 94 can be illuminated by the scatterometer 10 simultaneously and imaged simultaneously. Each optical test structure 94 includes a plurality of main features forming a grating, and the pitch of the main features is determined by the sensitivity of the scatterometer 10. That is, typically, the pitch is determined by the optical system of the optical measurement tool scatterometer 10. As such, the pitch of the main features is typically on the order of a few hundred nanometers. The grating formed by the main features can have an overlay offset that is biased differently to facilitate measuring the overlay between different wafer layers. As shown in FIG. Fig.10 As shown, the orientation of the grating formed by the main features can also be different so as to diffract the incoming radiation in the X and Y directions. Fig.10 Four gratings are shown in , but another embodiment may include a larger matrix to achieve the desired accuracy. For example, a 3x3 array of nine test structures 94 may be used.

[0074] The test structure 94 described herein may be, for example, a device designed to be used with a metrology tool such as Overlay targets used with stand-alone or integrated metrology tools, and alignment targets such as those commonly used with Alignment targets for use with lithography systems), all of which are available from ASML.

[0075] Still reference Fig.10 , the main features in the test structure 94 can be further divided into a plurality of periodic sub-features, the pitch of the sub-features being determined by the sensitivity of the electron beam 20. For example, the pitch of the sub-features can be set between 10-200 nanometers. In this way, the sub-features can be scanned by the electron beam tool 20 and provide a voltage contrast response at the device resolution. The pitch of the sub-features can be selected so that for each such structure, the overlay range is measured. In addition, the sub-features can be configured as two-dimensional, for example, with pitches in both the X and Y directions.

[0076] As described above, a single mark (e.g., mark 90) can be designed for voltage contrast and optical measurement. Measurements based on voltage contrast marks can be used to calibrate measurements based on optical measurements, and vice versa. Optical measurements can be performed at ADI (development post inspection). Voltage contrast measurements can be performed after etching and polishing. Thus, mark 90 allows ADI overlay and optical measurement of the process window and the position within the window after further processing of the mark. This combination can measure the process window while also performing wafer rework.

[0077] The embodiments may be further described using the following first set of clauses. A reference to a clause in the first set of clauses is a reference to a clause in the same set of clauses.

[0078] 1. A measurement mark, comprising:

[0079] a first set of test structures developed in a first layer on a substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; and

[0080] developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material,

[0081] Wherein the measurement markings are configured to indicate connectivity between the first set of test structures and an associated second test structure in the second set of test structures when imaged using a voltage contrast imaging method.

[0082] 2. The measurement tag of clause 1, wherein the voltage comparison image shows that a second test structure in the second set of test structures has a low voltage when the second test structure forms a short circuit with a first test structure in the first set of test structures.

[0083] 3. The measurement signature of any of clauses 1 and 2, wherein the voltage comparison image shows that one second test structure in the second set of test structures has a high voltage when the second test structure is in an open circuit with the first set of test structures.

[0084] 4. The measurement signature of any of clauses 1 to 3, wherein the combination of the first set of test structures and the second set of test structures is configured to express overlay information in a first direction along a surface of the substrate.

[0085] 5. The measurement signature of clause 4, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying pitch values ​​in the first direction.

[0086] 6. The measurement signature of clause 4, wherein the combination of the first set of test structures and the second set of test structures is further configured to express overlay information in a second direction along the surface of the substrate, the second direction being different from the first direction.

[0087] 7. The measurement marker of clause 6, wherein the second direction is orthogonal to the first direction.

[0088] 8. The measurement signature of clause 4, wherein the combination of the first set of test structures and the second set of test structures is further configured to express critical dimension information in a second direction along the surface of the substrate, the second direction being different from the first direction.

[0089] 9. The measurement signature of clause 4, wherein at least one of the first set of test structures and the second set of test structures has a varying critical dimension value in the second direction.

[0090] 10. The measurement marker of clause 9, wherein the second direction is orthogonal to the first direction.

[0091] 11. The measurement signature of any of clauses 1 to 3, wherein the combination of the first set of test structures and the second set of test structures is further configured to express critical dimension information in a direction along a surface of the substrate.

[0092] 12. The measurement signature of clause 11, wherein at least one of the first set of test structures and the second set of test structures has a varying critical dimension value in the one direction.

[0093] 13. The measurement signature of any of clauses 1 to 12, wherein the measurement signature is a mask comprising the first set of test structures and the second set of test structures.

[0094] 14. A measurement mark according to any one of clauses 1 to 13, further comprising:

[0095] a third set of test structures developed in the first layer, each third test structure in the third set of test structures comprising a plurality of third periodic features having a pitch determined by a sensitivity of an optical metrology tool; and

[0096] A fourth set of test structures is developed in the second layer, each fourth test structure in the fourth set of test structures comprising a plurality of fourth periodic features having a pitch determined by a sensitivity of the optical metrology tool.

[0097] 15. The measurement signature of clause 14, wherein at least one of the third set of test structures and the fourth set of test structures is positioned within a perimeter corresponding to a field of view of the optical metrology tool.

[0098] 16. The measurement mark according to any of clauses 14 and 15, wherein each of the plurality of third periodic features and the plurality of fourth periodic features is further divided into a plurality of sub-features, the pitch of the plurality of sub-features being determined by the sensitivity of an electron beam tool.

[0099] 17. The measurement signature of clause 16, wherein a sub-feature of the third feature is the first periodic feature, and wherein a sub-feature of the periodic feature is the second periodic feature.

[0100] 18. The overlay mark of clause 14, wherein the plurality of third periodic features and the plurality of fourth periodic features are made of the first conductive material and the second conductive material, respectively.

[0101] 19. An overprint mark according to any one of clauses 1 to 18, wherein each of the first conductive material and the second conductive material comprises a semiconductor.

[0102] 20. The overlay mark of clause 19, wherein the semiconductor comprises at least one of crystalline silicon, polycrystalline silicon, amorphous silicon, and silicon germanium.

[0103] 21. An overprint mark according to any one of clauses 1 to 18, wherein each of the first conductive material and the second conductive material comprises a metal.

[0104] 22. The overlay mark of clause 21, wherein the metal comprises at least one of copper, tungsten, nickel, cobalt, tantalum, and titanium nitride.

[0105] 23. A measurement mark comprising:

[0106] A first array of first features having a first pitch and a second array of second features having a second pitch, the first array and the second array being arranged in two consecutive layers on a substrate, wherein the measurement mark is configured to determine an overlay value between the first feature with respect to an associated second feature, or is configured to determine a critical dimension value of the first feature or the second feature when imaged using a voltage contrast imaging method.

[0107] 24. The measurement mark of clause 23, wherein the first pitch and the second pitch are different.

[0108] 25. The measurement mark according to any of clauses 23 and 24, wherein the first pitch and the second pitch vary in one direction or in two directions along the surface of the substrate.

[0109] 26. The measurement signature of any of clauses 23 to 25, wherein at least one of the duty cycle of the first characteristic and the duty cycle of the second characteristic is configured to have a varying value.

[0110] 27. A measurement signature according to any of clauses 23 to 26, wherein at least one of the first features comprises a sub-array of sub-features.

[0111] 28. The measurement mark of any of clauses 23 to 27, at least one of the first array of the first features and the second array of the second features being configured to have a varying critical dimension.

[0112] 29. A system comprising:

[0113] an electron beam tool for scanning a measurement mark according to clause 1 and for detecting scattered electrons from the measurement mark; and

[0114] A controller is coupled to the electron beam tool and is configured to:

[0115] generating a voltage contrast image based on the detected scattered electrons; and

[0116] An overlay value and / or a critical dimension value is determined based on the generated voltage contrast image.

[0117] 30. The system of clause 29, wherein the controller is further configured to:

[0118] When the voltage comparison image shows that one second test structure in the second test structure set has a low voltage, it is determined that the one second test structure forms a short circuit with one first test structure in the first test structure set.

[0119] 31. The system according to any of clauses 29 and 30, wherein the controller is further configured to:

[0120] When the voltage comparison image shows that one second test structure in the second test structure set has a high voltage, it is determined that the one second test structure is in an open circuit with the first test structure set.

[0121] 32. A system according to any of clauses 29 to 31, wherein at least one of the first set of test structures and the second set of test structures is configured to have a varying overlay offset value in a first direction along a surface of the substrate.

[0122] 33. A system according to any of clauses 29 to 32, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying overlay offset values ​​in a second direction along the surface of the substrate, the second direction being different from the first direction.

[0123] 34. A system according to clause 33, wherein the second direction is orthogonal to the first direction.

[0124] 35. The system of any of clauses 32 to 34, wherein the controller is further configured to determine overlay information based on the voltage contrast image and the overlay offset value.

[0125] 36. The system of clause 32, wherein at least one of the first set of test structures and the second set of test structures has a varying critical dimension value in a second direction different from the first direction.

[0126] 37. A system according to clause 36, wherein the second direction is orthogonal to the first direction.

[0127] 38. The system of any of clauses 36 and 37, wherein the controller is further configured to determine critical dimension information based on the voltage contrast image.

[0128] 39. The system of any of clause 38, wherein the controller is further configured to determine critical dimension information based on the voltage contrast image.

[0129] 40. A system according to any one of clauses 29 to 39, further comprising:

[0130] an optical measuring tool for scanning a measuring mark according to clause 14; and

[0131] The controller is further configured to determine at least one of overlay information and critical dimension information based on the voltage contrast image and an output of the optical metrology tool.

[0132] 41. A system according to clause 40, wherein:

[0133] Each of the plurality of third periodic features and the plurality of fourth periodic features is further divided into a plurality of periodic sub-features having a pitch determined by the sensitivity of the electron beam tool;

[0134] The electron beam tool is further configured to scan the fourth set of test structures after etching of the second layer and detect electrons scattered by the fourth set of test structures; and

[0135] The controller is further configured to determine at least one of overlay information and critical dimension information based on an output of the electron beam tool.

[0136] 42. The system of clause 43, wherein the plurality of third periodic features and the plurality of fourth periodic features are made of the first conductive material and the second conductive material, respectively.

[0137] 43. The system of any of clauses 29 to 43, wherein each of the first conductive material and the second conductive material comprises a semiconductor.

[0138] 44. The system of clause 43, wherein the semiconductor comprises at least one of crystalline silicon, polycrystalline silicon, amorphous silicon, and silicon germanium.

[0139] 45. The system of any of clauses 29 to 43, wherein each of the first conductive material and the second conductive material comprises a metal.

[0140] 46. ​​The system of clause 45, wherein the metal comprises at least one of copper, tungsten, nickel, cobalt, tantalum, and titanium nitride.

[0141] 47. A method comprising:

[0142] A measurement mark is scanned by an electron beam tool, and electrons scattered from the measurement mark are detected by the electron beam tool, the measurement mark comprising:

[0143] developing a first set of test structures in a first layer adjacent to the substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; and

[0144] developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material; and

[0145] generating, by a controller, a voltage contrast image of the second set of test structures based on the detected electrons; and

[0146] Connectivity between the first set of test structures and the second set of test structures is determined by the controller based on the voltage comparison image.

[0147] 48. The method according to clause 47, further comprising:

[0148] When the voltage comparison image shows that one second test structure in the second test structure set has a low voltage, it is determined that the one second test structure forms a short circuit with one first test structure in the first test structure set.

[0149] 49. The method according to any of clauses 47 and 48, further comprising:

[0150] When the voltage comparison image shows that one second test structure in the second test structure set has a high voltage, it is determined that the one second test structure is in an open circuit with the first test structure set.

[0151] 50. A method according to any of clauses 47 to 49, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying overlay offset values ​​in a first direction along a surface of the substrate.

[0152] 51. The method of clause 50, wherein at least one of the first set of test structures and the second set of test structures has a varying overlay offset value in a second direction along a surface of the substrate, the second direction being different from the first direction.

[0153] 52. The method of clause 51, wherein the second direction is orthogonal to the first direction.

[0154] 53. The method according to any one of clauses 50 to 52, further comprising:

[0155] Overlay information is determined by the controller based on the voltage contrast image and the overlay offset value.

[0156] 54. The method of clause 50, wherein at least one of the first set of test structures and the second set of test structures has a varying critical dimension value in a second direction along a surface of the substrate, the second direction being different from the first direction.

[0157] 55. The method of clause 54, wherein the second direction is orthogonal to the first direction.

[0158] 56. The method according to any of clauses 54 and 55, further comprising:

[0159] Critical dimension information is determined based on the voltage contrast image.

[0160] 55. A method according to any of clauses 47 to 49, wherein at least one of the first set of test structures and the second set of test structures is configured to have a varying critical dimension in a first direction along a surface of the substrate.

[0161] 56. The method according to clause 55, further comprising:

[0162] Critical dimension information is determined by the controller based on the voltage contrast image.

[0163] 57. A method according to any one of clauses 47 to 56, wherein:

[0164] The measurement mark also includes:

[0165] a third set of test structures developed in the first layer, each third test structure in the third set of test structures comprising a plurality of third features having a pitch determined by a sensitivity of the optical metrology tool; and

[0166] a fourth set of test structures developed in the second layer, each fourth test structure in the fourth set of test structures comprising a plurality of fourth features having a pitch determined by a sensitivity of the optical metrology tool; and

[0167] The method further comprises:

[0168] After the development inspection of the second layer, scanning the fourth set of test structures by the optical metrology tool, and detecting light scattered from the fourth set of test structures by the optical metrology tool; and

[0169] At least one of overlay information and critical dimension information is determined by the controller based on the output of the optical metrology tool.

[0170] 58. A method according to clause 57, wherein:

[0171] Each of the plurality of third periodic features and the plurality of fourth periodic features is further divided into a plurality of periodic sub-features having a pitch determined by the sensitivity of the electron beam tool; and

[0172] The method further comprises:

[0173] After etching of the second layer, scanning the fourth set of test structures by the electron scanning tool, and detecting electrons scattered by the fourth set of test structures by the electron beam tool; and

[0174] At least one of overlay information and critical dimension information is determined by the controller based on an output of the electron beam tool.

[0175] 59. The method of clause 57, wherein the plurality of third periodic features and the plurality of fourth periodic features are made of the first conductive material and the second conductive material, respectively.

[0176] 60. A method according to any of clauses 47 to 59, wherein each of the first conductive material and the second conductive material comprises a semiconductor.

[0177] 61. The method of clause 60, wherein the semiconductor comprises at least one of crystalline silicon, polycrystalline silicon, amorphous silicon, and silicon germanium.

[0178] 62. A method according to any of clauses 47 to 59, wherein each of the first conductive material and the second conductive material comprises a metal.

[0179] 63. The method of clause 64, wherein the metal comprises at least one of copper, tungsten, nickel, cobalt, tantalum, and titanium nitride.

[0180] 64. A non-transitory computer readable medium storing instructions that, when executed by one or more processors, cause the processors to perform a method comprising:

[0181] receiving an output of an electron beam tool, wherein the electron beam tool scans a measurement mark and detects electrons scattered from the measurement mark, the measurement mark comprising:

[0182] developing a first set of test structures in a first layer disposed on a substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; and

[0183] developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material; and

[0184] generating a voltage contrast image of the second set of test structures based on an output of the electron beam tool; and

[0185] Connectivity between the first set of test structures and the second set of test structures is determined based on the voltage comparison image.

[0186] 65. The medium of clause 64, wherein the method further comprises:

[0187] When the voltage comparison image shows that one second test structure in the second test structure set has a low voltage, it is determined that the one second test structure forms a short circuit with one first test structure in the first test structure set.

[0188] 66. The medium of clauses 64 and 65, wherein the method further comprises:

[0189] When the voltage comparison image shows that one second test structure in the second test structure set has a high voltage, it is determined that the one second test structure is in an open circuit with the first test structure set.

[0190] 67. A medium according to any of clauses 64 to 66, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying overlay offset values ​​in a first direction along a surface of the substrate.

[0191] 68. The medium of clause 67, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying overlay offset values ​​in a second direction along a surface of the substrate, the second direction being different from the first direction.

[0192] 69. A medium according to clause 68, wherein the second direction is orthogonal to the first direction.

[0193] 70. The medium of any one of clauses 67 to 69, wherein the method further comprises:

[0194] Overlay information is determined based on the voltage contrast image and the overlay offset value.

[0195] 71. The medium of clause 70, wherein each of the first set of test structures and the second set of test structures has a varying critical dimension value in a second direction different from the first direction.

[0196] 72. A medium according to clause 71, wherein the second direction is orthogonal to the first direction.

[0197] 73. The medium of any one of clauses 10 and 71, wherein the method further comprises:

[0198] Critical dimension information is determined based on the voltage contrast image.

[0199] 74. The medium of any of clauses 64 to 66, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying critical dimension values ​​in a first direction along a surface of the substrate.

[0200] 75. The medium of any one of clause 74, wherein the method further comprises:

[0201] Critical dimension information is determined based on the voltage contrast image.

[0202] 76. A medium according to any one of clauses 64 to 75, wherein:

[0203] The measurement mark also includes:

[0204] a third set of test structures developed in the first layer, each third test structure in the third set of test structures comprising a plurality of third features having a pitch determined by a sensitivity of the optical metrology tool; and

[0205] a fourth set of test structures developed in the second layer, each fourth test structure in the fourth set of test structures comprising a plurality of fourth features having a pitch determined by a sensitivity of the optical metrology tool; and

[0206] The method further comprises:

[0207] receiving an output of the optical metrology tool, wherein after development inspection of the second layer, the optical metrology tool scans the fourth set of test structures and detects light scattered from the fourth set of test structures; and

[0208] At least one of overlay information and critical dimension information is determined based on the output of the optical metrology tool.

[0209] 77. A medium according to clause 76, wherein:

[0210] Each of the plurality of third periodic features and the plurality of fourth periodic features is further divided into a plurality of sub-features having a pitch determined by the sensitivity of an electron beam tool; and

[0211] The method further comprises:

[0212] receiving an output of the electron scanning tool, wherein after etching of the second layer, the electron scanning tool scans the fourth set of test structures and detects electrons scattered by the fourth set of test structures; and

[0213] At least one of overlay information and critical dimension information is determined based on an output of the electron beam tool.

[0214] The embodiments may be further described using the following second set of clauses. A reference to a clause in the second set of clauses is a reference to a clause in the same set of clauses.

[0215] 1. A measurement mark, comprising:

[0216] a first set of test structures developed in a first layer on a substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; and

[0217] developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material,

[0218] Wherein the measurement markings are configured to indicate connectivity between the first set of test structures and an associated second test structure in the second set of test structures when imaged using a voltage contrast imaging method.

[0219] 2. The measurement signature of clause 1, wherein the voltage-versus-voltage image shows that a second test structure in the second set of test structures has low charge accumulation when the second test structure forms a short with a first test structure in the first set of test structures.

[0220] 3. The measurement signature of any of clauses 1 and 2, wherein the voltage-versus-voltage image shows that one second test structure in the second set of test structures has high charge accumulation when the second test structure is in an open circuit with the first set of test structures.

[0221] 4. The measurement signature of any of clauses 1 to 3, wherein the combination of the first set of test structures and the second set of test structures is configured to express overlay information in a first direction along a surface of the substrate.

[0222] 5. The measurement signature of clause 4, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying pitch values ​​in the first direction.

[0223] 6. The measurement signature of clause 4, wherein the combination of the first set of test structures and the second set of test structures is further configured to express overlay information in a second direction along the surface of the substrate, the second direction being different from the first direction.

[0224] 7. The measurement marker of clause 6, wherein the second direction is orthogonal to the first direction.

[0225] 8. The measurement signature of clause 4, wherein the combination of the first set of test structures and the second set of test structures is further configured to express critical dimension information in a second direction along the surface of the substrate, the second direction being different from the first direction.

[0226] 9. The measurement signature of clause 4, wherein at least one of the first set of test structures and the second set of test structures has a varying critical dimension value in the second direction.

[0227] 10. The measurement marker of clause 9, wherein the second direction is orthogonal to the first direction.

[0228] 11. The measurement signature of any of clauses 1 to 3, wherein the combination of the first set of test structures and the second set of test structures is further configured to express critical dimension information in a direction along a surface of the substrate.

[0229] 12. The measurement signature of clause 11, wherein at least one of the first set of test structures and the second set of test structures are configured to have varying critical dimension values.

[0230] 13. The measurement mark according to any one of clauses 1 to 12, further comprising:

[0231] a third set of test structures developed in the first layer, each third test structure in the third set of test structures comprising a plurality of third periodic features having a pitch determined by a sensitivity of an optical metrology tool; and

[0232] A fourth set of test structures is developed in the second layer, each fourth test structure in the fourth set of test structures comprising a plurality of fourth periodic features having a pitch determined by a sensitivity of the optical metrology tool.

[0233] 14. The measurement signature of clause 13, wherein at least one of the third set of test structures and the fourth set of test structures is positioned within a perimeter corresponding to a field of view of the optical metrology tool.

[0234] 15. The measurement mark according to any of clauses 13 and 14, wherein the optical metrology tool is configured to perform image-based overlay measurement or diffraction-based overlay measurement.

[0235] 16. The measurement signature of any of clauses 13 to 15, wherein each of the plurality of third periodic features and the plurality of fourth periodic features is further segmented into a plurality of sub-features having a pitch limited by the sensitivity of a particle beam tool.

[0236] 17. The measurement mark of clause 16, wherein the plurality of sub-features are configured with varying pitches.

[0237] 18. The measurement mark according to any one of clauses 16 and 17, wherein the plurality of sub-features are configured to have segments and pitches in different directions.

[0238] 19. The measurement mark according to any one of clauses 1 to 18, wherein a plurality of measurement marks are integrated into one multi-patterning mark, the plurality of measurement marks being configured to have a varying overlay offset or critical dimension offset.

[0239] 20. The measurement signature of clause 16, wherein a sub-feature of the third feature is the first periodic feature, and wherein a sub-feature of the periodic feature is the second periodic feature.

[0240] 21. The measurement tag of clause 14, wherein the plurality of third periodic features and the plurality of fourth periodic features are made of the first conductive material and the second conductive material, respectively.

[0241] 22. The measurement tag of any of clauses 1 to 21, wherein each of the first conductive material and the second conductive material comprises a semiconductor.

[0242] 23. The measurement tag of clause 22, wherein the semiconductor comprises at least one of crystalline silicon, polycrystalline silicon, amorphous silicon, and silicon germanium.

[0243] 24. The measurement tag of any of clauses 1 to 21, wherein each of the first conductive material and the second conductive material comprises a metal.

[0244] 25. The measurement tag of clause 24, wherein the metal comprises at least one of copper, tungsten, nickel, cobalt, tantalum, and titanium nitride.

[0245] 26. A measurement mark comprising:

[0246] A first array of first features having a first pitch and a second array of second features having a second pitch, the first array and the second array being arranged in two consecutive layers on a substrate, wherein the measurement mark is configured to determine an overlay value between the first feature with respect to an associated second feature, or is configured to determine a critical dimension value of the first feature or the second feature when imaged using a voltage contrast imaging method.

[0247] 27. The measurement mark of clause 26, wherein the first pitch and the second pitch are different.

[0248] 28. Measurement marking according to any of clauses 26 and 27, wherein the first pitch and the second pitch vary in one direction or in two directions along the surface of the substrate.

[0249] 29. The measurement signature of any of clauses 26 to 28, wherein at least one of the duty cycle of the first characteristic and the duty cycle of the second characteristic is configured to have a varying value.

[0250] 30. A measurement signature according to any of clauses 26 to 29, wherein at least one of the first features comprises a sub-array of sub-features.

[0251] 31. The measurement mark of any of clauses 26 to 30, at least one of the first array of the first features and the second array of the second features being configured to have a varying critical dimension.

[0252] 32. A system comprising:

[0253] a particle beam tool for scanning the measurement mark and for detecting scattered electrons from the measurement mark; and

[0254] A controller is coupled to the particle beam tool and is configured to:

[0255] generating a voltage contrast image based on the detected scattered electrons; and

[0256] An overlay value and / or a critical dimension value is determined based on the generated voltage contrast image.

[0257] 33. The system of clause 32, wherein the controller is further configured to:

[0258] When the voltage contrast image shows that one of the second test structures in the marked set of second test structures has low charge accumulation, it is determined that the one of the second test structures forms a short circuit with one of the first test structures in the marked set of first test structures.

[0259] 34. The system according to any of clauses 32 and 33, wherein the controller is further configured to:

[0260] When the voltage contrast image shows that one of the marked set of second test structures has high charge accumulation, it is determined that the one of the second test structures is in an open circuit with the marked set of first test structures.

[0261] 35. The system of any of clauses 33 to 34, wherein the controller is further configured to determine overlay information based on the voltage contrast image and the overlay offset value.

[0262] 36. The system of clause 35, wherein the controller is further configured to determine critical dimension information based on the voltage contrast image.

[0263] 37. A system according to any one of clauses 32 to 36, further comprising:

[0264] an optical metrology tool for scanning the measurement mark; and

[0265] The controller is further configured to determine at least one of overlay information and critical dimension information based on the voltage contrast image and an output of the optical metrology tool.

[0266] 38. The system of clause 37, wherein the controller is further configured to determine at least one of overlay information and critical dimension information based on an output of the particle beam tool.

[0267] 39. The system of any one of clause 38, wherein the controller is further configured to:

[0268] Measuring the measurement mark via the optical metrology tool to determine an overlay offset between the first layer and the second layer during photolithography or after etching;

[0269] measuring the measurement marks via the particle beam tool to determine connectivity between the first layer and the second layer based on the voltage contrast image;

[0270] A critical dimension and an overlay value of the mask are determined based on the measurement results of the optical metrology tool and the measurement results of the particle beam tool.

[0271] 40. A method comprising:

[0272] A measurement mark is scanned by a particle beam tool, and electrons scattered from the measurement mark are detected by the particle beam tool, the measurement mark comprising:

[0273] developing a first set of test structures in a first layer adjacent to the substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; and

[0274] developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material; and

[0275] generating, by a controller, a voltage contrast image of the second set of test structures based on the detected electrons; and

[0276] Connectivity between the first set of test structures and the second set of test structures is determined by the controller based on the voltage comparison image.

[0277] 41. The method according to clause 40, further comprising:

[0278] When the voltage-versus-image shows that one second test structure in the second set of test structures has low charge accumulation, it is determined that the one second test structure forms a short circuit with one first test structure in the first set of test structures.

[0279] 42. The method according to any one of clauses 40 and 41, further comprising:

[0280] When the voltage-versus-image shows that one second test structure in the second set of test structures has high charge accumulation, it is determined that the one second test structure is in an open circuit with the first set of test structures.

[0281] 43. A method according to any of clauses 40 to 42, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying overlay offset values ​​in a first direction along a surface of the substrate.

[0282] 44. The method of clause 43, wherein at least one of the first set of test structures and the second set of test structures has a varying overlay offset value in a second direction along a surface of the substrate, the second direction being different from the first direction.

[0283] 45. The method of clause 44, wherein the second direction is orthogonal to the first direction.

[0284] 46. ​​The method according to any one of clauses 43 to 45, further comprising:

[0285] Overlay information is determined by the controller based on the voltage contrast image and the overlay offset value.

[0286] 47. The method of clause 43, wherein at least one of the first set of test structures and the second set of test structures has a varying critical dimension value in a second direction along a surface of the substrate, the second direction being different from the first direction.

[0287] 48. The method of clause 47, wherein the second direction is orthogonal to the first direction.

[0288] 49. The method according to any of clauses 47 and 48, further comprising:

[0289] Critical dimension information is determined based on the voltage contrast image.

[0290] 50. A method according to any of clauses 40 to 52, wherein at least one of the first set of test structures and the second set of test structures is configured to have a varying critical dimension in a first direction along a surface of the substrate.

[0291] 51. The method according to clause 50, further comprising:

[0292] Critical dimension information is determined by the controller based on the voltage contrast image.

[0293] 52. A method according to any one of clauses 40 to 51, wherein:

[0294] The measurement mark also includes:

[0295] a third set of test structures developed in the first layer, each third test structure in the third set of test structures comprising a plurality of third features having a pitch determined by a sensitivity of the optical metrology tool; and

[0296] a fourth set of test structures developed in the second layer, each fourth test structure in the fourth set of test structures comprising a plurality of fourth features having a pitch determined by a sensitivity of the optical metrology tool; and

[0297] The method further comprises:

[0298] After the development inspection of the second layer, scanning the fourth set of test structures by the optical metrology tool, and detecting light scattered from the fourth set of test structures by the optical metrology tool; and

[0299] At least one of overlay information and critical dimension information is determined by the controller based on the output of the optical metrology tool.

[0300] 53. A method according to clause 52, wherein:

[0301] Each of the plurality of third periodic features and the plurality of fourth periodic features is further divided into a plurality of periodic sub-features having a pitch determined by a sensitivity of a particle beam tool; and

[0302] The method further comprises:

[0303] After etching of the second layer, scanning the fourth set of test structures by the electron scanning tool, and detecting electrons scattered by the fourth set of test structures by the particle beam tool; and

[0304] At least one of overlay information and critical dimension information is determined by the controller based on an output of the particle beam tool.

[0305] 54. The method of clause 52, wherein the plurality of third periodic features and the plurality of fourth periodic features are made of the first conductive material and the second conductive material, respectively.

[0306] 55. The method according to any one of claims 53 and 54, further comprising

[0307] Measuring the measurement mark via the optical metrology tool to determine an overlay offset between the first layer and the second layer during photolithography or after etching;

[0308] measuring the measurement marks via the particle beam tool to determine connectivity between the first layer and the second layer based on the voltage contrast image;

[0309] A critical dimension and an overlay value of the mask are determined based on the measurement results of the optical metrology tool and the measurement results of the particle beam tool.

[0310] 56. The method of claim 53, wherein the plurality of subfeatures are configured to have varying pitches.

[0311] 57. The method of any one of claims 53 and 56, wherein the plurality of sub-features are configured to have segmentation and pitches in different directions.

[0312] 58. A method according to any of clauses 40 to 57, wherein a plurality of measurement marks are integrated into one multi-patterning mark, the plurality of measurement marks being configured to have a varying overlay offset or critical dimension offset.

[0313] 59. A non-transitory computer-readable medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method comprising:

[0314] receiving an output of a particle beam tool, wherein the particle beam tool is configured to scan a measurement mark and is configured to detect electrons scattered from the measurement mark, the measurement mark comprising:

[0315] developing a first set of test structures in a first layer disposed on a substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; and

[0316] developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material; and

[0317] generating a voltage contrast image of the second set of test structures based on an output of the particle beam tool; and

[0318] Connectivity between the first set of test structures and the second set of test structures is determined based on the voltage comparison image.

[0319] 60. The medium of clause 59, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0320] When the voltage-versus-image shows that one second test structure in the second set of test structures has low charge accumulation, it is determined that the one second test structure forms a short circuit with one first test structure in the first set of test structures.

[0321] 61. The medium of clauses 59 and 60, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0322] When the voltage-versus-image shows that one second test structure in the second set of test structures has high charge accumulation, it is determined that the one second test structure is in an open circuit with the first set of test structures.

[0323] 62. A medium according to any of clauses 59 to 61, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying overlay offset values ​​in a first direction along a surface of the substrate.

[0324] 63. The medium of clause 62, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying overlay offset values ​​in a second direction along a surface of the substrate, the second direction being different from the first direction.

[0325] 64. A medium according to clause 63, wherein the second direction is orthogonal to the first direction.

[0326] 65. A medium as described in any of clauses 62 to 64, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0327] Overlay information is determined based on the voltage contrast image and the overlay offset value.

[0328] 66. The medium of clause 65, wherein each of the first set of test structures and the second set of test structures has a varying critical dimension value in a second direction different from the first direction.

[0329] 67. A medium according to clause 66, wherein the second direction is orthogonal to the first direction.

[0330] 68. A medium as described in any of clauses 66 and 67, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0331] Critical dimension information is determined based on the voltage contrast image.

[0332] 69. The medium of any of clauses 59 to 61, wherein at least one of the first set of test structures and the second set of test structures is configured to have varying critical dimension values ​​in a first direction along a surface of the substrate.

[0333] 70. The medium of any of clause 69, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0334] Critical dimension information is determined based on the voltage contrast image.

[0335] 71. A medium according to any one of clauses 59 to 70, wherein:

[0336] The measurement mark also includes:

[0337] a third set of test structures developed in the first layer, each third test structure in the third set of test structures comprising a plurality of third features having a pitch determined by a sensitivity of the optical metrology tool; and

[0338] a fourth set of test structures developed in the second layer, each fourth test structure in the fourth set of test structures comprising a plurality of fourth features having a pitch determined by a sensitivity of the optical metrology tool; and

[0339] The set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0340] receiving an output of the optical metrology tool, wherein after development inspection of the second layer, the optical metrology tool scans the fourth set of test structures and detects light scattered from the fourth set of test structures; and

[0341] At least one of overlay information and critical dimension information is determined based on the output of the optical metrology tool.

[0342] 72. A medium according to clause 71, wherein:

[0343] Each of the plurality of third periodic features and the plurality of fourth periodic features is further divided into a plurality of sub-features having a pitch determined by a sensitivity of a particle beam tool; and

[0344] The set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0345] receiving an output of the electron scanning tool, wherein after etching of the second layer, the electron scanning tool scans the fourth set of test structures and detects electrons scattered by the fourth set of test structures; and

[0346] At least one of overlay information and critical dimension information is determined based on an output of the particle beam tool.

[0347] 73. The medium of clause 72, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0348] Measuring the measurement mark via the optical metrology tool to determine an overlay offset between the first layer and the second layer during photolithography or after etching;

[0349] measuring the measurement marks via the particle beam tool to determine connectivity between the first layer and the second layer based on the voltage contrast image;

[0350] Based on the measurement results of the optical metrology tool and the measurement results of the particle beam tool, a critical dimension and an overlay value of the mask are determined.

[0351] 74. A medium as described in clause 72, wherein the plurality of subfeatures are configured to have a varying pitch.

[0352] 75. A medium according to any of clauses 72 and 74, wherein the plurality of sub-features are configured to have segmentation and pitch in different directions.

[0353] 76. The medium of any of clauses 59 to 75, wherein a plurality of measurement marks are integrated into one multi-patterned mark, the plurality of measurement marks being configured to have a varying overlay offset or critical dimension offset.

[0354] The embodiments may be further described using the following third set of clauses. References to clauses in the third set of clauses are references to clauses in the same set of clauses.

[0355] 1. A measurement mark, comprising:

[0356] a first set of test structures developed in a first layer on a substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; and

[0357] developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material,

[0358] Wherein the measurement markings are configured to indicate connectivity between the first set of test structures and an associated second test structure in the second set of test structures when imaged using a voltage contrast imaging method.

[0359] 2. The measurement signature of clause 1, wherein the voltage contrast image shows that a particular test structure in the second set of test structures has low charge accumulation when the particular test structure in the second set of test structures forms a short circuit with a particular test structure in the first set of test structures.

[0360] 3. A measurement tag according to any one of clauses 1 and 2, wherein when a specific test structure in the second set of test structures is in an open circuit with a specific test structure in the first set of test structures, the voltage contrast image shows that the specific test structure in the second set of test structures has a high charge accumulation.

[0361] 4. The measurement mark according to any one of clauses 1 to 3, wherein a combination of a plurality of test structures in the first test structure set and a plurality of test structures in the second test structure set is configured to express overlay information in a first direction along a surface of the substrate.

[0362] 5. The measurement signature of clause 4, wherein the plurality of test structures in the first set of test structures or the plurality of test structures in the second set of test structures are configured to have varying pitch values ​​in the first direction.

[0363] 6. The measurement mark of clause 4, wherein the combination of the plurality of test structures in the first test structure set and the plurality of test structures in the second test structure set is further configured to express overlay information in a second direction along the surface of the substrate, the second direction being different from the first direction.

[0364] 7. The measurement marker of clause 6, wherein the second direction is orthogonal to the first direction.

[0365] 8. The measurement mark of clause 4, wherein the combination of the plurality of test structures in the first test structure set and the plurality of test structures in the second test structure set is further configured to express critical dimension information in a second direction along the surface of the substrate, the second direction being different from the first direction.

[0366] 9. The measurement signature of clause 4, wherein the plurality of test structures in the first set of test structures or the plurality of test structures in the second set of test structures have varying CD values ​​in the second direction.

[0367] 10. The measurement marker of clause 9, wherein the second direction is orthogonal to the first direction.

[0368] 11. The measurement signature of any one of clauses 1 to 3, wherein a combination of the plurality of test structures of the first test structure set and the plurality of test structures of the second test structure set is further configured to express critical dimension information in a direction along a surface of the substrate.

[0369] 12. The measurement signature of clause 11, wherein the plurality of test structures in the first set of test structures or the plurality of test structures in the second set of test structures are configured to have varying critical dimension values.

[0370] 13. The measurement mark according to any one of clauses 1 to 12, further comprising:

[0371] a third set of test structures developed in the first layer, each third test structure in the third set of test structures comprising a plurality of third periodic features having a pitch determined by a sensitivity of an optical metrology tool; and

[0372] A fourth set of test structures is developed in the second layer, each fourth test structure in the fourth set of test structures comprising a plurality of fourth periodic features having a pitch determined by a sensitivity of the optical metrology tool.

[0373] 14. The measurement mark of clause 13, wherein the plurality of test structures of the third set of test structures or the plurality of test structures of the fourth set of test structures are positioned within a perimeter corresponding to a field of view of the optical metrology tool.

[0374] 15. The measurement mark according to any of clauses 13 and 14, wherein the optical metrology tool is configured to perform image-based overlay measurement or diffraction-based overlay measurement.

[0375] 16. The measurement mark of any of clauses 13 to 15, wherein each of the plurality of third periodic features or the plurality of fourth periodic features is further segmented into a plurality of sub-features having a pitch limited by the sensitivity of a particle beam tool.

[0376] 17. The measurement mark of clause 16, wherein the plurality of sub-features are configured with varying pitches.

[0377] 18. A measurement mark according to any of clauses 16 and 17, wherein the plurality of sub-features are configured to have segments or pitches in different directions.

[0378] 19. The measurement mark according to any one of clauses 1 to 18, wherein a plurality of measurement marks are integrated into one multi-patterning mark, and wherein the plurality of measurement marks are configured to have a varying overlay offset or critical dimension offset.

[0379] 20. The measurement signature of clause 16, wherein a sub-feature of the third periodic feature is the first periodic feature and a sub-feature of the fourth periodic feature is the second periodic feature.

[0380] 21. The measurement tag of clause 14, wherein the plurality of third periodic features and the plurality of fourth periodic features are made of the first conductive material and the second conductive material, respectively.

[0381] 22. The measurement tag of any of clauses 1 to 21, wherein each of the first conductive material and the second conductive material comprises a semiconductor.

[0382] 23. The measurement tag according to clause 22, wherein the semiconductor comprises any one of crystalline silicon, polycrystalline silicon, amorphous silicon or silicon germanium.

[0383] 24. The measurement tag of any of clauses 1 to 21, wherein each of the first conductive material and the second conductive material comprises a metal.

[0384] 25. The measurement marker of clause 24, wherein the metal comprises any one of copper, tungsten, nickel, cobalt, tantalum or titanium nitride.

[0385] 26. A measurement mark comprising:

[0386] A first array of first features having a first pitch and a second array of second features having a second pitch, the first array and the second array being arranged in two consecutive layers on a substrate, wherein the measurement mark is configured to determine an overlay value between the first feature relative to an associated second feature, or is configured to determine a critical dimension value of the first feature or a critical dimension value of the second feature when imaged using a voltage contrast imaging method.

[0387] 27. The measurement mark of clause 26, wherein the first pitch and the second pitch are different.

[0388] 28. Measurement marking according to any of clauses 26 and 27, wherein the first pitch and the second pitch vary in one direction or in two directions along the surface of the substrate.

[0389] 29. A measurement signature according to any of clauses 26 to 28, wherein the duty cycle of the first characteristic or the duty cycle of the second characteristic is configured to have a varying value.

[0390] 30. A measurement signature according to any of clauses 26 to 29, wherein the first feature comprises a sub-array of sub-features.

[0391] 31. The measurement signature of any of clauses 26 to 30, wherein the plurality of test structures of the first array of first features or the plurality of test structures of the second array of second features are configured to have varying critical dimensions.

[0392] 32. A system comprising:

[0393] a particle beam tool for scanning the measurement mark and for detecting secondary electrons from the measurement mark; and

[0394] a controller coupled to the particle beam tool, the controller comprising circuitry to:

[0395] generating a voltage contrast image based on the detected secondary electrons; and

[0396] An overlay value or a critical dimension value is determined based on the generated voltage contrast image.

[0397] 33. The system of clause 32, wherein determining the overlay value or the critical dimension value comprises determining the overlay value and the critical dimension value.

[0398] 34. A system according to any of clauses 32 and 33, wherein the controller comprises circuitry to:

[0399] When the voltage contrast image shows that a particular test structure in a first set of test structures of measurement signature has low charge accumulation, it is determined that the particular test structure in the first set of test structures forms a short circuit with a particular test structure in a second set of test structures of measurement signature.

[0400] 35. A system according to any of clauses 32 to 34, wherein the controller comprises circuitry to:

[0401] When the voltage contrast image shows that a particular test structure in a first set of test structures of measurement signature has high charge accumulation, the particular test structure in the first set of test structures is determined to be in an open circuit with a particular test structure in a second set of test structures of measurement signature.

[0402] 36. The system of any of clauses 32 to 35, wherein the controller comprises circuitry for determining overlay information based on the voltage contrast image or the overlay offset value of the measurement mark.

[0403] 37. The system of clause 36, wherein the controller includes circuitry for determining critical dimension information based on the voltage versus image.

[0404] 38. A system according to any one of clauses 32 to 37, further comprising:

[0405] an optical metrology tool for scanning the measurement mark; and

[0406] The controller further includes circuitry for determining overlay information or critical dimension information based on the voltage contrast image or the output of the optical metrology tool.

[0407] 39. The system of clause 38, wherein the controller further comprises circuitry for:

[0408] measuring the measurement mark via the optical metrology tool during post-development inspection of the wafer to determine an overlay offset between a first layer and a second layer on the substrate;

[0409] measuring the measurement marks via the particle beam tool after etching or polishing of the wafer to determine connectivity between the first layer and the second layer based on the voltage contrast image; and

[0410] Based on the measurement result of the optical metrology tool or the measurement result of the particle beam tool, a critical dimension or an overlay value of the mask on the substrate is determined.

[0411] 40. The system of clause 39, wherein the controller further comprises circuitry to:

[0412] determining mask misalignment data based on the overlay value or the critical dimension value; and

[0413] The mask misalignment data is sent to a lithographic apparatus coupled to the controller.

[0414] 41. A system according to any of clauses 32 to 40, wherein the controller further comprises circuitry to:

[0415] A lithography process window is determined based on the overlay information or the critical dimension information.

[0416] 42. A method comprising:

[0417] scanning a first set of test structures of measurement marks with a charged particle beam and detecting secondary electrons from the measurement marks;

[0418] generating a voltage contrast image based on the detected secondary electrons; and

[0419] An overlay value or a critical dimension value is determined based on the generated voltage contrast image.

[0420] 43. The method of clause 42, wherein determining the overlay value or the critical dimension value comprises determining the overlay value and the critical dimension value.

[0421] 44. The method according to any of clauses 42 and 43, further comprising:

[0422] When the voltage contrast image shows that a particular test structure in the first set of test structures of the measurement signature has low charge accumulation, it is determined that the particular test structure in the first set of test structures is shorted to a particular test structure in a second set of test structures of the measurement signature.

[0423] 45. The method according to any one of clauses 42 to 44, further comprising:

[0424] When the voltage contrast image shows that a particular test structure in the first set of test structures of the measurement signature has high charge accumulation, the particular test structure in the first set of test structures is determined to be in an open circuit with a particular test structure in a second set of test structures of the measurement signature.

[0425] 46. ​​The method according to any one of clauses 42 to 45, further comprising:

[0426] Overlay information is determined based on the voltage contrast image or the overlay offset value of the measurement mark.

[0427] 47. The method according to any one of clauses 42 to 46, further comprising:

[0428] Critical dimension information is determined based on the voltage contrast image.

[0429] 48. The method according to any one of clauses 42 to 47, further comprising:

[0430] scanning the measurement mark with a light beam and detecting light scattered from the measurement mark;

[0431] generating an optical image based on the detected scattered light; and

[0432] Overlay information or critical dimension information is determined based on the voltage contrast image or the optical image.

[0433] 49. The method according to clause 48, further comprising:

[0434] measuring the measurement mark with the light beam during post-development inspection of the wafer to determine an overlay offset of a first layer and a second layer on the substrate based on the optical image;

[0435] measuring the measurement marks with the charged particle beam after etching or polishing of the wafer to determine connectivity between the first layer and the second layer based on the voltage contrast image; and

[0436] A critical dimension or overlay value of a mask on the substrate is determined based on the measurements obtained by the optical beam or the measurements obtained by the charged particle beam.

[0437] 50. The method according to any one of clauses 42 to 49, further comprising:

[0438] determining mask misalignment data based on the overlay value or the critical dimension value; and

[0439] A lithography process parameter is adjusted based on the mask misalignment data.

[0440] 51. A method according to any one of clauses 42 to 50, further comprising:

[0441] A lithography process window is determined based on the overlay information or the critical dimension information.

[0442] 52. A non-transitory computer-readable medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method comprising:

[0443] scanning a first set of test structures of measurement marks with a charged particle beam and detecting secondary electrons from the measurement marks;

[0444] generating a voltage contrast image based on the detected secondary electrons; and

[0445] An overlay value or a critical dimension value is determined based on the generated voltage contrast image.

[0446] 53. The medium of clause 52, wherein determining the overlay value or the critical dimension value comprises determining the overlay value and the critical dimension value.

[0447] 54. The medium of any of clauses 52 and 53, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0448] When the voltage contrast image shows that a particular test structure in the first set of test structures of the measurement signature has low charge accumulation, it is determined that the particular test structure in the first set of test structures is shorted to a particular test structure in a second set of test structures of the measurement signature.

[0449] 55. The medium of clauses 52 to 54, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0450] When the voltage contrast image shows that a particular test structure in the first set of test structures of the measurement signature has high charge accumulation, the particular test structure in the first set of test structures is determined to be in an open circuit with a particular test structure in a second set of test structures of the measurement signature.

[0451] 56. A medium as described in any of clauses 52 to 55, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0452] Overlay information is determined based on the voltage contrast image or the overlay offset value of the measurement mark.

[0453] 57. A medium according to any of clauses 52 to 56, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0454] Critical dimension information is determined based on the voltage contrast image.

[0455] 58. A medium as described in any of clauses 52 to 57, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0456] scanning the measurement mark with a light beam and detecting light scattered from the measurement mark;

[0457] generating an optical image based on the detected scattered light; and

[0458] Overlay information or critical dimension information is determined based on the voltage contrast image or the optical image.

[0459] 59. The medium of clause 58, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0460] During post-development inspection of the wafer, measuring the mark using the beam to determine an overlay offset of a first layer and a second layer on the substrate based on the optical image;

[0461] measuring the measurement marks with the charged particle beam after etching or polishing of the wafer to determine connectivity between the first layer and the second layer based on the voltage contrast image; and

[0462] A critical dimension or overlay value of a mask on the substrate is determined based on the measurements obtained by the optical beam or the measurements obtained by the charged particle beam.

[0463] 60. A medium as described in any of clauses 52 to 59, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0464] determining mask misalignment data based on the overlay value or the critical dimension value; and

[0465] A lithography process parameter is adjusted based on the mask misalignment data.

[0466] 61. A medium as described in any of clauses 52 to 60, wherein the set of instructions is executable by one or more processors of the device to cause the device to further perform:

[0467] A lithography process window is determined based on the overlay information or the critical dimension information.

[0468] It should be understood that the invention is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope of the invention. It is intended that the scope of the invention shall be limited only by the appended claims.

Claims

1. A measurement mark, comprising: a first set of test structures developed in a first layer on a substrate, each first test structure in the first set of test structures comprising a plurality of first features made of a first conductive material; as well as developing a second set of test structures in a second layer adjacent to the first layer, each second test structure in the second set of test structures comprising a plurality of second features made of a second conductive material, Wherein the measurement markings are configured to indicate connectivity between the first set of test structures and an associated second test structure in the second set of test structures when imaged using a voltage contrast imaging method.

2. The measurement tag of claim 1 , wherein the voltage contrast image shows that a specific test structure in the second set of test structures has low charge accumulation when the specific test structure in the second set of test structures forms a short circuit with a specific test structure in the first set of test structures.

3. The measurement signature of claim 1 , wherein the voltage contrast image shows that a particular test structure in the second set of test structures has high charge accumulation when the particular test structure in the second set of test structures is in an open circuit with a particular test structure in the first set of test structures. 4 . The measurement mark according to claim 1 , wherein a combination of the plurality of test structures in the first test structure set and the plurality of test structures in the second test structure set is configured to express overlay information in a first direction along the surface of the substrate. 5 . The measurement mark according to claim 4 , wherein the plurality of test structures in the first test structure set or the plurality of test structures in the second test structure set are configured to have varying pitch values ​​in the first direction.

6. The measurement mark according to claim 4, wherein the combination of the plurality of test structures in the first test structure set and the plurality of test structures in the second test structure set is further configured to express overlay information in a second direction along the surface of the substrate, the second direction being different from the first direction.

7. The measurement mark according to claim 6, wherein the second direction is orthogonal to the first direction.

8. The measurement mark of claim 4, wherein the combination of the plurality of test structures in the first test structure set and the plurality of test structures in the second test structure set is further configured to express critical dimension information in a second direction along the surface of the substrate, the second direction being different from the first direction. 9 . The measurement signature of claim 4 , wherein the plurality of test structures in the first test structure set or the plurality of test structures in the second test structure set have varying CD values ​​in the second direction.

10. The measurement mark according to claim 9, wherein the second direction is orthogonal to the first direction.

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