Triode-free low-voltage low-power-consumption band-gap reference source circuit

Abstract

The invention discloses a triode-free low-voltage low-power-consumption band-gap reference source circuit. The triode-free low-voltage low-power-consumption band-gap reference source circuit comprises a starting and biasing circuit, a band-gap reference core circuit and a temperature compensation circuit. The band-gap reference voltage of first-order temperature compensation is realized by adopting a positive temperature coefficient voltage generated by a difference between gate-source voltages of a PMOS (P-channel Metal Oxide Semiconductor) tube M6 and a PMOS tube M7 working in a sub-threshold region and a gate-source voltage of an NMOS (N-channel Metal Oxide Semiconductor) tube M8 working in the sub-threshold region. A temperature high-order nonlinear current INL is realized by utilizing a technology that an absolute value of a threshold voltage of an MOS (Metal Oxide Semiconductor) tube working in a saturation region has a negative temperature coefficient, so that the temperature high-order nonlinearity of a band-gap reference voltage with first-order temperature compensation provided by a band-gap reference core circuit is compensated, and the band-gap reference voltage with high-order temperature compensation is further obtained; therefore, the triode-free low-voltage low-power-consumption band-gap reference source circuit is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a triode-free low-voltage and low-power bandgap reference source circuit. Background Art

[0002] The bandgap reference source circuit is one of the important functional modules of the integrated circuit chip system, which provides a high-performance reference signal for the integrated circuit chip system. With the development of integrated circuit technology, more and more functional modules are integrated on the same integrated chip, which puts forward higher requirements on the performance of the bandgap reference source circuit.

[0003] Figure 1 It is a traditional bandgap reference source circuit, wherein PMOS tube M1, PMOS tube M2, amplifier AMP, resistor R1, PNP transistor Q1 and PNP transistor Q2 generate positive temperature coefficient current, which flows through resistor R2 to generate positive temperature coefficient voltage and is weighted with the emitter-base voltage of PNP transistor Q3 with negative temperature coefficient to generate bandgap reference voltage. PMOS tube M1, PMOS tube M2 and PMOS tube M3 have the same channel width-to-length ratio, the emitter area of ​​PNP transistor Q2 is m times that of PNP transistor Q1, and resistor R1 and resistor R2 are made of the same material, then the output voltage V of the bandgap reference circuit REF for Among them, V EB1 is the emitter-base voltage of the PNP transistor Q1, R 1 is the impedance of resistor R1, R 2 is the impedance of resistor R2, q is the amount of electron charge, k is the Boltzmann constant, and T is the absolute temperature. By optimizing the relevant parameters of the resistor, a reference voltage V with zero temperature characteristics can be obtained within a certain temperature range. REF . Figure 1 Three transistors are used, which occupy a large physical area and consume a large amount of power, thereby restricting its application in high-performance and low-power integrated circuit chip systems. Summary of the invention

[0004] The present invention aims to solve the above problems of the prior art and proposes a triode-free low-voltage and low-power bandgap reference source circuit. The technical solution of the present invention is as follows:

[0005] A triode-free low-voltage and low-power bandgap reference source circuit includes: a startup and bias circuit, a bandgap reference core circuit, and a temperature compensation circuit. The signal output end of the startup and bias circuit is respectively connected to the signal input end of the bandgap reference core circuit and the signal input end of the temperature compensation circuit, the signal output end of the bandgap reference core circuit is connected to the signal input end of the startup and bias circuit, the signal output end of the temperature compensation circuit is connected to the signal input end of the bandgap reference core circuit, the startup and bias circuit provides bias and startup signals for the bandgap reference core circuit and the temperature compensation circuit, and the temperature compensation circuit provides a high-order temperature compensation signal for the reference voltage generated by the bandgap reference core circuit.

[0006] Further, the startup and bias circuit includes: a PMOS tube MS1, a PMOS tube MS2, a PMOS tube MS3, an NMOS tube MS4, an NMOS tube MS5, an NMOS tube MS6, a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a resistor R1 and a resistor R2, wherein the source of the PMOS tube MS1 is respectively connected to the source of the PMOS tube M1 and the external power supply VDD, the gate of the PMOS tube MS1 is respectively connected to the drain of the PMOS tube MS1 and the source of the PMOS tube MS2, the gate of the PMOS tube MS2 is respectively connected to the drain of the PMOS tube MS2 and the source of the PMOS tube MS3, the gate of the PMOS tube MS3 is respectively connected to the drain of the PMOS tube MS3, the drain of the NMOS tube MS4, the gate of the NMOS tube MS5 and the NMOS tube MS6. The gate of the OS transistor MS6 is connected, the source of the NMOS transistor MS4 is respectively connected to the source of the NMOS transistor MS5, the source of the NMOS transistor M4 and the external ground GND, the source of the NMOS transistor MS6 is respectively connected to the drain of the NMOS transistor MS5, the gate of the PMOS transistor M1 is respectively connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor MS6, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10 and one end of the resistor R1, the other end of the resistor R1 is respectively connected to the gate of the PMOS transistor M13 and one end of the resistor R2, the other end of the resistor R2 is respectively connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M2, the source of the NMOS transistor M2 is respectively connected to the gate of the NMOS transistor M3 and the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4.

[0007] Further, the bandgap reference core circuit includes: a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, an NMOS tube M8, an NMOS tube M9, a resistor R3 and a resistor R4, wherein the source of the PMOS tube M5 is connected to the external power supply VDD, the drain of the PMOS tube M5 is respectively connected to the source of the PMOS tube M6 and the source of the PMOS tube M7, the gate of the PMOS tube M6 is respectively connected to the drain of the PMOS tube M6 and one end of the resistor R3, and the other end of the resistor R3 is respectively connected to the gate of the NMOS tube M8. The drain of the NMOS tube M8 is connected to the gate of the NMOS tube M8 and the gate of the NMOS tube M9. The source of the NMOS tube M8 is respectively connected to the source of the NMOS tube M9 and the external ground GND. The gate of the PMOS tube M7 is respectively connected to the drain of the PMOS tube M7, one end of the resistor R5, one end of the resistor R6, one end of the resistor R7, one end of the resistor R8, one end of the resistor R4, the gate of the NMOS tube M4, the gate of the NMOS tube MS4 and the circuit output terminal VREF. The other end of the resistor R4 is connected to the drain of the NMOS tube M9.

[0008] Further, the temperature compensation circuit includes: a PMOS tube M10, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, an NMOS tube M15, a resistor R5, a resistor R6, a resistor R7 and a resistor R8, wherein the source of the PMOS tube M10 is respectively connected to the source of the PMOS tube M13 and the external power supply VDD, the drain of the PMOS tube M10 is respectively connected to the other end of the resistor R5 and the gate of the NMOS tube M11, and the other end of the resistor R6 is respectively connected to the gate of the NMOS tube M The drain of the NMOS tube M11 is connected to the gate of the NMOS tube M12, the source of the NMOS tube M11 is connected to the drain of the NMOS tube M12, the source of the NMOS tube M12 is respectively connected to the source of the NMOS tube M15 and the external ground GND, the drain of the PMOS tube M13 is connected to the source of the PMOS tube M14, the gate of the PMOS tube M14 is respectively connected to the drain of the PMOS tube M14 and the other end of the resistor R7, and the other end of the resistor R8 is respectively connected to the gate of the NMOS tube M15 and the drain of the NMOS tube M15.

[0009] Furthermore, in the bandgap reference core circuit, the PMOS tube M6, the PMOS tube M7, the NMOS tube M8 and the NMOS tube M9 all work in the subthreshold region, and the drain current I D and the gate-source voltage V GS They are and Where W / L is the channel width-to-length ratio of the MOS tube, I 0 is a process-related parameter, η is a non-ideal factor greater than 1, V THis the threshold voltage of the MOS tube, V GS is the gate-source voltage of the MOS tube, V T is the thermal voltage with a temperature coefficient. And the threshold voltage of MOS tube |V TH |Having negative temperature characteristics, the gate-source voltage V of the MOS tube working in the subthreshold region GS The bandgap reference core circuit provides a voltage V at the output end of the circuit. REF1 for Among them, V GS8 is the gate-source voltage of NMOS tube M8, R 3 is the impedance of resistor R3, I D8-0 is the drain current of the NMOS tube M8 when the bandgap reference core circuit is working, (W / L) 6 is the channel width-to-length ratio of the PMOS tube M6, (W / L) 7 is the channel width-to-length ratio of the PMOS tube M7, (W / L) 8 is the channel width-to-length ratio of the NMOS tube M8, (W / L) 9 is the channel width-to-length ratio of the NMOS tube M9. Factor V GS8 +I D8-0 R 3 Has a negative temperature coefficient, factor Has a positive temperature coefficient, so the voltage V REF1 It is a bandgap reference voltage with first-order temperature compensation.

[0010] Furthermore, in the temperature compensation circuit, the NMOS tube M12 works in the linear region, and the PMOS tube M10, the NMOS tube M11, the PMOS tube M13, the PMOS tube M14 and the NMOS tube M15 all work in the saturation region. Then, the current I provided by the temperature compensation circuit to the bandgap reference core circuit is NL For I NL =I D10 +I D13 -I D11 -I D15 , where I D10 is the drain current of PMOS tube M10, I D13 is the drain current of PMOS tube M13, I D11 is the drain current of NMOS tube M11, I D15 is the drain current of NMOS tube M15. At the same time, the threshold voltage of MOS tube |V TH | As the temperature T increases, the current I NL It has high-order temperature nonlinearity.

[0011] Furthermore, the output terminal VREF voltage V REF for Among them, the factor It has high-order nonlinearity over temperature, and can compensate for V by optimizing relevant circuit parameters. REF1 The temperature high-order nonlinearity is obtained to obtain a high-order temperature compensated bandgap reference voltage V REF The advantages and beneficial effects of the present invention are as follows:

[0012] The present invention provides a high-order bandgap reference source circuit with base compensation, adopts the NPN triode base series resistor technology to suppress the influence of the NPN triode base current on the output voltage of the bandgap reference source circuit, and adopts two high-order temperature compensation currents realized by the positive temperature coefficient current generated by the difference between the gate-source voltages of two NMOS tubes working in the subthreshold region and the negative temperature coefficient current generated by the base-emitter voltage of the NPN triode on the resistor to compensate for the high-order nonlinearity of the temperature of the output voltage of the bandgap reference source circuit, thereby obtaining a high-order temperature compensated bandgap reference voltage, thereby realizing a high-order bandgap reference source circuit with base compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the schematic diagram of the traditional bandgap reference source circuit;

[0014] Figure 2 A schematic diagram of a low-voltage and low-power bandgap reference source circuit without a triode is provided for a preferred embodiment of the present invention;

[0015] Figure 3 The present invention provides a simulation diagram of output voltage and temperature of a triode-free low-voltage and low-power bandgap reference source circuit according to a preferred embodiment. DETAILED DESCRIPTION

[0016] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0017] The technical solution of the present invention to solve the above technical problems is:

[0018] In the embodiment of the present application, a first-order bandgap reference voltage is realized by using a technique such as a positive temperature characteristic generated by the difference in gate-source voltage of two MOS tubes working in a subthreshold region and a negative temperature characteristic of the gate-source voltage of the MOS tube working in a subthreshold region. A high-order temperature nonlinear current is generated by using a negative temperature characteristic of the absolute value of the threshold voltage of the MOS tube working in a saturation region and compensating for the high-order temperature nonlinearity of the first-order bandgap reference voltage, thereby obtaining a high-order temperature-compensated bandgap reference voltage, thereby realizing a triode-free low-voltage and low-power bandgap reference source circuit.

[0019] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0020] Example

[0021] A low voltage and low power consumption bandgap reference source circuit without triode, such as Figure 2 As shown, it includes a start-up and bias circuit 1, a bandgap reference core circuit 2 and a temperature compensation circuit 3; wherein, the signal output end of the start-up and bias circuit 1 is respectively connected to the signal input end of the bandgap reference core circuit 2 and the signal input end of the temperature compensation circuit 3, the signal output end of the bandgap reference core circuit 2 is connected to the signal input end of the start-up and bias circuit 1, and the signal output end of the temperature compensation circuit 3 is connected to the signal input end of the bandgap reference core circuit 2, the start-up and bias circuit 1 provides bias and start-up signals for the bandgap reference core circuit 2 and the temperature compensation circuit 3, and the temperature compensation circuit 3 provides a high-order temperature compensation signal for the reference voltage generated by the bandgap reference core circuit 2.

[0022] As a preferred technical solution, Figure 2As shown, the startup and bias circuit 1 includes: a PMOS tube MS1, a PMOS tube MS2, a PMOS tube MS3, an NMOS tube MS4, an NMOS tube MS5, an NMOS tube MS6, a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a resistor R1 and a resistor R2, wherein the source of the PMOS tube MS1 is respectively connected to the source of the PMOS tube M1 and the external power supply VDD, the gate of the PMOS tube MS1 is respectively connected to the drain of the PMOS tube MS1 and the source of the PMOS tube MS2, the gate of the PMOS tube MS2 is respectively connected to the drain of the PMOS tube MS2 and the source of the PMOS tube MS3, the gate of the PMOS tube MS3 is respectively connected to the drain of the PMOS tube MS3, the drain of the NMOS tube MS4, the gate of the NMOS tube MS5 and the NMOS The gate of the S transistor MS6 is connected, the source of the NMOS transistor MS4 is respectively connected to the source of the NMOS transistor MS5, the source of the NMOS transistor M4 and the external ground GND, the source of the NMOS transistor MS6 is respectively connected to the drain of the NMOS transistor MS5, the gate of the PMOS transistor M1 is respectively connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor MS6, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10 and one end of the resistor R1, the other end of the resistor R1 is respectively connected to the gate of the PMOS transistor M13 and one end of the resistor R2, the other end of the resistor R2 is respectively connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M2, the source of the NMOS transistor M2 is respectively connected to the gate of the NMOS transistor M3 and the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4.

[0023] The bandgap reference core circuit 2 includes: a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, an NMOS tube M8, an NMOS tube M9, a resistor R3 and a resistor R4, wherein the source of the PMOS tube M5 is connected to the external power supply VDD, the drain of the PMOS tube M5 is respectively connected to the source of the PMOS tube M6 and the source of the PMOS tube M7, the gate of the PMOS tube M6 is respectively connected to the drain of the PMOS tube M6 and one end of the resistor R3, and the other end of the resistor R3 is respectively connected to the drain of the NMOS tube M8. , the gate of the NMOS tube M8 and the gate of the NMOS tube M9, the source of the NMOS tube M8 is respectively connected to the source of the NMOS tube M9 and the external ground GND, the gate of the PMOS tube M7 is respectively connected to the drain of the PMOS tube M7, one end of the resistor R5, one end of the resistor R6, one end of the resistor R7, one end of the resistor R8, one end of the resistor R4, the gate of the NMOS tube M4, the gate of the NMOS tube MS4 and the circuit output terminal VREF, and the other end of the resistor R4 is connected to the drain of the NMOS tube M9.

[0024] The temperature compensation circuit 3 includes: a PMOS tube M10, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, an NMOS tube M15, a resistor R5, a resistor R6, a resistor R7 and a resistor R8, wherein the source of the PMOS tube M10 is respectively connected to the source of the PMOS tube M13 and the external power supply VDD, the drain of the PMOS tube M10 is respectively connected to the other end of the resistor R5 and the gate of the NMOS tube M11, the other end of the resistor R6 is respectively connected to the gate of the NMOS tube M11, and the The drain of the NMOS tube M13 is connected to the source of the PMOS tube M14, the gate of the PMOS tube M14 is connected to the drain of the PMOS tube M14 and the other end of the resistor R7, and the other end of the resistor R8 is connected to the gate of the NMOS tube M15 and the drain of the NMOS tube M15.

[0025] In the bandgap reference core circuit 2, the PMOS tube M6, the PMOS tube M7, the NMOS tube M8 and the NMOS tube M9 all work in the subthreshold region, and the drain current I D for

[0026]

[0027] Where W / L is the channel width-to-length ratio of the MOS tube, I 0 is a process-related parameter, η is a non-ideal factor greater than 1, V TH is the threshold voltage of the MOS tube, V GS is the gate-source voltage of the MOS tube, V T is the thermal voltage with a temperature coefficient. Then, the gate-source voltage V GS for

[0028]

[0029] In the formula, the factor And the threshold voltage of MOS tube |V TH |Having negative temperature characteristics, the gate-source voltage V of the MOS tube working in the subthreshold region GS The bandgap reference core circuit 2 provides a voltage V at the output end of the circuit. REF1 for

[0030]

[0031] Where VGS8 is the gate-source voltage of NMOS tube M8, R 3 is the impedance of resistor R3, I D8-0 is the drain current of the NMOS tube M8 when the bandgap reference core circuit 2 is working, (W / L) 6 is the channel width-to-length ratio of the PMOS tube M6, (W / L) 7 is the channel width-to-length ratio of the PMOS tube M7, (W / L) 8 is the channel width-to-length ratio of the NMOS tube M8, (W / L) 9 is the channel width-to-length ratio of the NMOS tube M9. Factor V GS8 +I D8-0 R 3 Has a negative temperature coefficient, factor has a positive temperature coefficient, so the voltage V provided by the bandgap reference core circuit 2 at the circuit output terminal is REF1 It is a bandgap reference voltage with first-order temperature compensation.

[0032] In the temperature compensation circuit 3, the NMOS transistor M12 works in the linear region, and the PMOS transistor M10, NMOS transistor M11, PMOS transistor M13, PMOS transistor M14 and NMOS transistor M15 all work in the saturation region. Then, the current I provided by the temperature compensation circuit 3 to the bandgap reference core circuit 2 NL for

[0033] I NL =I D10 +I D13 -I D11 -I D15 (4)

[0034] In the formula, I D10 is the drain current of PMOS tube M10, I D13 is the drain current of PMOS tube M13, I D11 is the drain current of NMOS tube M11, I D15 is the drain current of NMOS tube M15. At the same time, the threshold voltage of MOS tube |V TH | As the temperature T increases, the current I NL The output terminal VREF voltage V of the triode-free low-voltage and low-power bandgap reference source circuit is REF for

[0035]

[0036] In the formula, the factor It has high-order nonlinearity over temperature, and can compensate for V by optimizing relevant circuit parameters. REF1The temperature high-order nonlinearity is obtained to obtain a high-order temperature compensated bandgap reference voltage V REF .

[0037] Figure 3 The output voltage V of the triode-free low-voltage and low-power bandgap reference source circuit of the present invention is REF The temperature characteristic simulation curve of the circuit is shown in Figure 1, where the horizontal axis is temperature and the vertical axis is output voltage. The simulation results show that within the temperature range of -40℃ to 125℃, the output voltage V of a low-voltage and low-power bandgap reference source circuit without a transistor is REF The temperature coefficient is 2.26ppm / ℃.

[0038] In the above embodiment of the present application, a triode-free low-voltage and low-power bandgap reference source circuit includes a startup and bias circuit, a bandgap reference core circuit, and a temperature compensation circuit. The embodiment of the present application uses the difference between the gate-source voltages of two MOS tubes working in the subthreshold region to generate a positive temperature characteristic and the gate-source voltage of the MOS tube working in the subthreshold region has a negative temperature characteristic to realize a first-order bandgap reference voltage, and uses the threshold voltage absolute value of the MOS tube working in the saturation region to have a negative temperature characteristic to generate a high-order temperature nonlinear current and compensate for the high-order nonlinearity of the temperature of the first-order bandgap reference voltage, thereby obtaining a high-order temperature-compensated bandgap reference voltage, thereby realizing a triode-free low-voltage and low-power bandgap reference source circuit.

[0039] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0040] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A triode-free low-voltage and low-power bandgap reference source circuit, characterized in that: include: A start-up and bias circuit (1), a bandgap reference core circuit (2) and a temperature compensation circuit (3), wherein the signal output end of the start-up and bias circuit (1) is respectively connected to the signal input end of the bandgap reference core circuit (2) and the signal input end of the temperature compensation circuit (3), the signal output end of the bandgap reference core circuit (2) is connected to the signal input end of the start-up and bias circuit (1), and the signal output end of the temperature compensation circuit (3) is connected to the signal input end of the bandgap reference core circuit (2); the start-up and bias circuit (1) provides bias and start-up signals for the bandgap reference core circuit (2) and the temperature compensation circuit (3), and the temperature compensation circuit (3) provides a high-order temperature compensation signal for the reference voltage generated by the bandgap reference core circuit (2).

2. A triode-free low-voltage and low-power bandgap reference source circuit according to claim 1, characterized in that: The startup and bias circuit (1) comprises: a PMOS tube MS1, a PMOS tube MS2, a PMOS tube MS3, an NMOS tube MS4, an NMOS tube MS5, an NMOS tube MS6, a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a resistor R1 and a resistor R2, wherein the source of the PMOS tube MS1 is respectively connected to the source of the PMOS tube M1 and an external power supply VDD, the gate of the PMOS tube MS1 is respectively connected to the drain of the PMOS tube MS1 and the source of the PMOS tube MS2, the gate of the PMOS tube MS2 is respectively connected to the drain of the PMOS tube MS2 and the source of the PMOS tube MS3, the gate of the PMOS tube MS3 is respectively connected to the drain of the PMOS tube MS3, the drain of the NMOS tube MS4, the gate of the NMOS tube MS5 and the NMOS tube MS6. The gate of the S transistor MS6 is connected, the source of the NMOS transistor MS4 is respectively connected to the source of the NMOS transistor MS5, the source of the NMOS transistor M4 and the external ground GND, the source of the NMOS transistor MS6 is respectively connected to the drain of the NMOS transistor MS5, the gate of the PMOS transistor M1 is respectively connected to the drain of the PMOS transistor M1, the drain of the NMOS transistor MS6, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10 and one end of the resistor R1, the other end of the resistor R1 is respectively connected to the gate of the PMOS transistor M13 and one end of the resistor R2, the other end of the resistor R2 is respectively connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M2, the source of the NMOS transistor M2 is respectively connected to the gate of the NMOS transistor M3 and the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4.

3. The triode-free low-voltage and low-power bandgap reference source circuit according to claim 1, characterized in that: The bandgap reference core circuit (2) comprises: a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, an NMOS tube M8, an NMOS tube M9, a resistor R3 and a resistor R4, wherein the source of the PMOS tube M5 is connected to an external power supply VDD, the drain of the PMOS tube M5 is respectively connected to the source of the PMOS tube M6 and the source of the PMOS tube M7, the gate of the PMOS tube M6 is respectively connected to the drain of the PMOS tube M6 and one end of the resistor R3, and the other end of the resistor R3 is respectively connected to the drain of the NMOS tube M8. The gate of the NMOS tube M8 is connected to the gate of the NMOS tube M9, the source of the NMOS tube M8 is connected to the source of the NMOS tube M9 and the external ground GND, the gate of the PMOS tube M7 is connected to the drain of the PMOS tube M7, one end of the resistor R5, one end of the resistor R6, one end of the resistor R7, one end of the resistor R8, one end of the resistor R4, the gate of the NMOS tube M4, the gate of the NMOS tube MS4 and the circuit output terminal VREF, and the other end of the resistor R4 is connected to the drain of the NMOS tube M9.

4. The triode-free low-voltage and low-power bandgap reference source circuit according to claim 1, characterized in that: The temperature compensation circuit (3) comprises: a PMOS tube M10, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, an NMOS tube M15, a resistor R5, a resistor R6, a resistor R7 and a resistor R8, wherein the source of the PMOS tube M10 is respectively connected to the source of the PMOS tube M13 and the external power supply VDD, the drain of the PMOS tube M10 is respectively connected to the other end of the resistor R5 and the gate of the NMOS tube M11, and the other end of the resistor R6 is respectively connected to the gate of the NMOS tube M11. The drain of the NMOS tube M1 is connected to the gate of the NMOS tube M12, the source of the NMOS tube M11 is connected to the drain of the NMOS tube M12, the source of the NMOS tube M12 is respectively connected to the source of the NMOS tube M15 and the external ground GND, the drain of the PMOS tube M13 is connected to the source of the PMOS tube M14, the gate of the PMOS tube M14 is respectively connected to the drain of the PMOS tube M14 and the other end of the resistor R7, and the other end of the resistor R8 is respectively connected to the gate of the NMOS tube M15 and the drain of the NMOS tube M15.

5. The triode-free low-voltage and low-power bandgap reference source circuit according to claim 3, characterized in that: In the bandgap reference core circuit (2), the PMOS tube M6, the PMOS tube M7, the NMOS tube M8 and the NMOS tube M9 all work in the subthreshold region, and the drain current I D and the gate-source voltage V GS They are and Where W / L is the channel width-to-length ratio of the MOS tube, I0 is a parameter related to the process, η is a non-ideal factor greater than 1, and V TH is the threshold voltage of the MOS tube, V GS is the gate-source voltage of the MOS tube, V T is the thermal voltage with a temperature coefficient. And the threshold voltage of MOS tube |V TH |Having negative temperature characteristics, the gate-source voltage V of the MOS tube working in the subthreshold region GS The bandgap reference core circuit provides a voltage V at the circuit output terminal VREF. REF1 for Among them, V GS8 is the gate-source voltage of the NMOS tube M8 in the working subthreshold region, R3 is the impedance of the resistor R3, I D8-0 is the drain current of the NMOS tube M8 when the bandgap reference core circuit is working, (W / L)6 is the channel width-to-length ratio of the PMOS tube M6, (W / L)7 is the channel width-to-length ratio of the PMOS tube M7, (W / L)8 is the channel width-to-length ratio of the NMOS tube M8, and (W / L)9 is the channel width-to-length ratio of the NMOS tube M9. Factor V GS8 +I D8-0 R3 has a negative temperature coefficient, factor It has a positive temperature coefficient, so by optimizing the corresponding parameter voltage, V REF1 It is a bandgap reference voltage with first-order temperature compensation.

6. According to the triode-free low-voltage and low-power bandgap reference source circuit of claim 4, in the temperature compensation circuit (3), the NMOS tube M12 operates in the linear region, and the PMOS tube M10, the NMOS tube M11, the PMOS tube M13, the PMOS tube M14 and the NMOS tube M15 all operate in the saturation region. Then, the current I provided by the temperature compensation circuit (3) to the bandgap reference core circuit (2) is NL For I NL =I D10 +I D13 -I D11 -I D15 , where I D10 is the drain current of PMOS tube M10, I D13 is the drain current of PMOS tube M13, I D11 is the drain current of NMOS tube M11, I D15 is the drain current of NMOS tube M15. At the same time, the threshold voltage of MOS tube |V TH | As the temperature T increases, the current I NL It has high-order temperature nonlinearity.

7. A triode-free low-voltage and low-power bandgap reference source circuit according to any one of claims 5 to 6, wherein the output terminal VREF voltage V REF for Where V REF1 is the first-order bandgap reference voltage provided by the bandgap reference core circuit (2), (W / L)8 is the channel width-to-length ratio of the NMOS tube M8, (W / L)9 is the channel width-to-length ratio of the NMOS tube M9, I NL is the temperature high-order nonlinear current provided by the temperature compensation circuit (3), and R3 is the impedance of the resistor R3. Factor It has high-order nonlinearity over temperature, and can compensate for V by optimizing relevant circuit parameters. REF1 The temperature high-order nonlinearity is obtained to obtain a high-order temperature compensated bandgap reference voltage V REF .

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