Str / dtr mode implementation method for flash controller

Abstract

This invention discloses a method for implementing str / dtr mode for a flash controller, including setting a clock frequency of doubled clock as a reference clock; outputting a flash clock signal from a register using the doubled clock as the clock signal and outputting it to the flash chip; setting a clock gate signal for the reference clock to obtain the application clock; using the application clock to control the chip select signal and data signal of the flash chip; in str mode, setting the clock gate signal to toggle according to the rising and falling edges of the reference clock; in dtr mode, setting the clock gate signal to be valid, ensuring that the application clock and the reference clock are synchronized; repeating the above steps to complete the implementation of str / dtr mode for the flash controller. This invention can implement str / dtr mode for flash controllers, and has a short development cycle, low power consumption, low resource consumption, high reliability, and good accuracy.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing, and specifically relates to a method for implementing str / dtr mode for flash controllers. Background Technology

[0002] Many large-scale integrated circuits (such as satellite positioning, artificial intelligence, and computer vision) include a System-on-a-Chip (SoC) component. SoCs typically store a portion of the operating system and business firmware in off-chip NVM (non-volatile memory). Among commonly used NVM memories, QSPI (4-wire synchronous serial interface) type Nor flash memory has become the most popular choice today due to its fast read speed, stable data storage, simple interface, and ability to perform immediate execution (XIP).

[0003] The data read rate of QSPI flash memory is crucial to system performance; especially during the system boot process, the data read rate of QSPI flash memory plays a decisive role in the rapid operation of the system.

[0004] Previous QSPI interface flash memory used the str (single cycle transfer rate) mode, meaning that each rising edge of the sclk pin aligned with the center position of a data signal (including command, address, and data). Both read (flash to chip) and write (chip to flash) operations used the str mode.

[0005] To improve system performance, a new type of flash device has emerged in recent years. Besides supporting the traditional STR mode, it also supports DTR (Double Transfer Rate) transmission mode. During data reading, the command code is the same as in STR mode: the command signal transitions on the falling edge of SClk, and the rising edge of SClk is aligned with the center of the effective level of the command signal. However, the address signal sent transitions once on each rising and falling edge of SClk. Similarly, the read data returned from the flash memory transitions once on each rising and falling edge of SClk. The DTR mode is reflected in the read address sent by the chip's flash controller and the read data returned by the flash memory, achieving twice the signal rate of the previous STR method.

[0006] For flash controllers that support DTR, traditional str operations must still be supported. This is because, apart from reading data and setting DLP (Data Learning Mode), which can be performed using either str or DTR, all other operations, such as writing data and reading the status register, still require str operations.

[0007] To ensure Flash is compatible with both str and dtr modes, common implementation methods include:

[0008] 1) Two functional modules: One is the str function, which operates on the same clock frequency as sclk; the other is the dtr function, which operates on a clock frequency twice that of sclk. However, this method has the drawbacks of consuming more resources and consuming more power. In addition, the port signals of this method have two clocks, and both clocks need to be calculated when calculating the timing of the path.

[0009] 2) Both operate at the SCIL frequency clock, using dual-edge clock registers at the ports: In this method, some FPGA versions have dual-edge clock registers, ODD and IDD. An ODD has two data inputs and one data output. The rising edge of the ODD clock samples the signal from one data input, and the falling edge samples the signal from the other. Originally, both data input signals were single-clock-edge, full-cycle signals; a parallel-to-serial conversion is performed, resulting in a double-rate signal with two clock edges, changing every half-cycle, at the data output port. The IDD works the opposite: one data input receives a double-rate signal with two clock edges; a serial-to-parallel conversion is performed, resulting in two single-clock-edge, single-rate signals, changing once per cycle, output from the two data outputs. However, this method requires corresponding process technology devices, but ODD and IDD devices are generally not available in ASIC processes.

[0010] 3) All signals operate at twice the frequency of sclk, with signal updates controlled by a synchronization enable signal: The entire module is synchronized with the rising edge of a clock twice the frequency of sclk (qspi_clk_2x). Sclk port signals are always output using a clock twice the frequency. This is controlled by the synchronization signal sclk_tglen (sclk_toggle enable), which toggles once on each rising edge of the twice-frequency clock when a toggle is needed. When no toggle is needed, the signal remains high or low depending on the mode selection. This method increases the logical computation of the data path, increases logic resources, and results in a longer timing path. Furthermore, this method has higher dynamic power consumption. Summary of the Invention

[0011] The purpose of this invention is to provide a highly reliable, accurate, and simple implementation method for the str / dtr mode of a flash controller.

[0012] The str / dtr mode implementation method for a flash controller provided by this invention includes the following steps:

[0013] S1. Set the clock frequency of the doubled clock and use the set doubled clock as the reference clock;

[0014] S2. The register that uses a doubled clock frequency as the clock signal outputs the Flash clock signal and outputs it to the corresponding pin of the Flash chip;

[0015] S3. Set the clock gating signal for the reference clock, control the reference clock through the clock gating signal, and obtain the application clock;

[0016] S4. Use the application clock obtained in step S3 to control the chip select signal and data signal of the Flash chip;

[0017] S5. In str mode, the clock gate signal is set to flip according to the rising and falling edges of the reference clock to ensure that the application clock is a division of the reference clock by two.

[0018] S6. In DTR mode, the clock gating signal is enabled to ensure that the application clock and the reference clock are synchronized.

[0019] S7. Repeat steps S1 to S6 to complete the implementation of str / dtr mode for the flash controller.

[0020] Step S5 specifically involves setting the clock gate signal qspi_clk_en to flip once on the rising edge of each reference clock qspi_clk_2x in str mode, thereby ensuring that the application clock qspi_clk is a division of the reference clock by two; in str mode, the data signal of the Flash chip corresponds to one data cycle in each Flash clock signal period.

[0021] Step S6 specifically involves setting the clock gate signal qspi_clk_en to be continuously valid in DTR mode, at which time the application clock qspi_clk and the reference clock qspi_clk_2x are at the same frequency; in DTR mode, all signals of the circuit are synchronized with the rising edge of the application clock qspi_clk.

[0022] The method for implementing the str / dtr mode of a flash controller provided by this invention, through simple algorithm design and innovative use of gating enable signals, enables the method to implement the str / dtr mode of the flash controller. Moreover, it has a short development cycle, low power consumption, low resource consumption, high reliability, and good accuracy. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the method flow of the present invention.

[0024] Figure 2 This is a timing diagram of the method of the present invention. Detailed Implementation

[0025] like Figure 1 The diagram shown is a flowchart of the method of the present invention: The str / dtr mode implementation method for flash controllers provided by the present invention includes the following steps:

[0026] S1. Set the clock frequency of the doubled clock qspi_clk_2x, and use the set doubled clock as the reference clock;

[0027] S2. The register that uses the doubled clock qspi_clk_2x as the clock signal outputs the Flash clock signal sclk and outputs it to the corresponding pin of the Flash chip;

[0028] S3. Set the clock gating signal qspi_clk_en for the reference clock, control the reference clock through the clock gating signal, and obtain the application clock qspi_clk;

[0029] S4. Use the application clock qspi_clk obtained in step S3 to control the chip select signal scs and data signal data of the Flash chip;

[0030] S5. In str mode, the clock gate signal is set to toggle based on the rising and falling edges of the reference clock to ensure that the application clock is a division of the reference clock by 2. Specifically, in str mode, the clock gate signal qspi_clk_en is set to toggle once on the rising edge of each reference clock qspi_clk_2x, thereby ensuring that the application clock is a division of the reference clock by 2. In str mode, the data signal of the Flash chip corresponds to one data clock cycle.

[0031] S6. In DTR mode, the clock gating signal is set to be valid, ensuring that the application clock and the reference clock are at the same frequency. Specifically, in DTR mode, the clock gating signal qspi_clk_en is set to be valid continuously, at which time the application clock qspi_clk and the reference clock qspi_clk_2x are at the same frequency. In DTR mode, all signals of the circuit are synchronized with the rising edge of the application clock qspi_clk.

[0032] S7. Repeat steps S1 to S6 to complete the implementation of str / dtr mode for the flash controller.

[0033] like Figure 2 The diagram shown is a timing illustration of the method of the present invention: From Figure 2As can be seen, the clock frequency of the doubled clock qspi_clk_2x is set; the register that uses the doubled clock qspi_clk_2x as the clock signal outputs the Flash clock signal sclk. sclk flips once on the rising edge of the doubled clock qspi_clk_2x, so sclk is a division of qspi_clk_2x by two.

[0034] Set the clock gate signal qspi_clk_en for the reference clock, control the reference clock through the clock gate signal, and obtain the application clock qspi_clk;

[0035] In practice, in the str model (where the dtr signal is low), the clock gate signal qspi_clk_en is set to toggle once on the rising edge of each reference clock qspi_clk_2x. The waveform of the applied clock is shown below. Figure 2 As shown in qspi_clk; in this case, the data pins data[3:0] transmit data once per cycle of sclk;

[0036] In DTR mode, the clock gate signal qspi_clk_en is set to be continuously active in DTR mode (the DTR signal is continuously high). At this time, the application clock qspi_clk and the reference clock qspi_clk_2x are in the same frequency. In this case, the data pins data[3:0] transmit data twice in each cycle of sclk.

[0037] During an ongoing operation, switching between SDR and DTR modes only occurs in one scenario: when sending commands, both modes are initially in STR mode. Once the command transmission ends and the system switches to the address for sending / reading, a switch from STR to DTR is required. Otherwise, there is no switching between STR and DTR modes during the operation.

[0038] Therefore, qspi_clk_en is a register output triggered by the rising edge of the qspi_clk_2x clock. Besides str and dtr modes, when switching from str to dtr is required, changing qspi_clk_en from a one-time transition to a continuous high level will achieve the switch.

[0039] In this invention, the signal transitions of the synchronization circuit follow the clock while meeting the setup and hold timing requirements. If clock gating is used to select whether the entire module operates at its original frequency or half its original frequency, dynamic frequency changes in the synchronization circuit can be achieved.

[0040] Although the frequency of qspi_clk might be half the frequency of qspi_clk_2x, meaning it's used at half the frequency, it's still set to the same frequency as qspi_clk_2x because there are cases where it operates at the same frequency. With the high-frequency timings satisfied, using it at half the frequency in str mode will definitely not cause any problems.

[0041] Furthermore, due to the introduction of the DTR mode, a clock frequency of 2 times the SCIL frequency, qspi_clk_2x, is used to output DTR data. The SCIL clock no longer requires a gated clock implementation; instead, it uses the qspi_clk_2x register for output, just like SCS and data. This simplifies and clarifies the path constraints from the SCIL, SCS, and data register outputs to the pins, facilitating timing balance of the output paths.

[0042] The design of digital circuits for chips has a history of several decades, with synchronous design gradually becoming the mainstream, facilitating automation tools. The most common and stable solution for synchronous circuits is to use a single clock: this clock cycles twice, once rising and once falling, and all functions follow this single clock; generally, all registers either toggle or remain unchanged on the rising edge of the clock based on the calculation result.

[0043] However, this invention breaks with convention by determining, based on functional requirements and a specific time period, or even a specific clock cycle, whether the signal for a certain function needs to be changed. If no change is needed, the clock can be decisively stopped during that time period, or even precisely within the clock cycle where no signal change is required.

[0044] The method to stop a clock from toggling is called clock gating. Clock gating is a common technique in low-power design, generally used to turn the clock on or off to determine whether a circuit is working.

[0045] However, dynamically and precisely controlling the on and off of a specific part of the circuit clock, down to the clock cycle, is extremely difficult.

[0046] Challenge 1: Feasibility; Many design experts with over ten years of experience in the chip industry, after seeing the solution of this invention, stated that it was not a standard practice and no one would dare to do it. Questions also exist: How can we ensure there are no issues with the phase relationship between dynamic clock enable, the original clock, and the gated clock? How can we ensure there are no problems when transferring data between circuits using dynamic gating based on function, circuits using the original clock instead of gated clocks, or circuits using other dynamic gating functions?

[0047] Challenge 2: Risk and Cost; Chip development has a long cycle, high costs, and very high risks. Every step of the process must be executed flawlessly. For a new design methodology, there are processes such as RTL pre-simulation, netlist post-simulation, static timing analysis, formal verification, and FPGA testing. However, even with a circuit implementation method that is not used before and is only available to many, it still faces enormous pressure.

[0048] However, the solution of this invention ultimately successfully achieved the intended function. The method of this invention will be further described below with reference to an embodiment:

[0049] This invention has been applied to over a hundred Xilinx FPGA tests. During these tests, each version demonstrated exceptional stability, passing all full functionalities and performance tests. Three wafers have already been fabricated using SMIC 28nm and other processes. After comprehensive sample testing, their superior performance has been demonstrated, and the technology is ready for commercial application.

[0050] The test results and statistical results of the method of the present invention are shown in Table 1 below:

[0051] Table 1. Schematic diagram of test and statistical results

[0052]

[0053] As can be seen from Table 1, the solution of the present invention has a short development cycle, low power consumption, low resource consumption, and high reliability and accuracy.

[0054] The advantages of the method of the present invention are:

[0055] Short development cycle: The traditional str method has specific operational requirements for the device; however, the function of str, apart from the sclk signal being a single clock signal, has no rate change during operation. Therefore, the implementation process is the same as that of ordinary synchronous circuits, without needing to consider too many additional factors; modifications are relatively simple based on the already implemented, fully verified, and tested str; the key is to consider both str and dtr modes, and then determine the timing of qspi_clk_en transition based on the stage of operation execution, thus achieving compatibility between str and dtr.

[0056] Low power consumption: This invention is used in circuits that require adjustable high and low speeds, accounting for a large proportion (over 98%). Because it uses a gated clock method, the clock frequency is halved when full speed is required, and the dynamic power consumption is reduced accordingly. According to theoretical analysis and test statistics, a large part of the dynamic power consumption of the circuit is occupied by the clock tree flipping. By turning off the clock at the root of the clock tree, the signals of all devices in the clock tree stop flipping, which can significantly reduce the dynamic power consumption of the clock tree, especially in the case of large circuit size and high operating frequency.

[0057] Low resource consumption: If the entire design uses a fast clock, and synchronous logic is used to control the circuit registers in the mode that requires slowing down, the data will toggle every two clock cycles, while the register level remains the same as the previous clock cycle in the other clock cycle. In this case, each register's data input will have an additional logic control to determine whether to toggle or jump, thus increasing logic resources. It is precisely because of the use of a gated clock that the entire circuit uses a fast clock that can be dynamically turned on or off. Only one gating device is needed to remove the synchronous control logic of each register, thereby achieving the function of this invention.

[0058] Timing constraints are convenient: Using a clock with double frequency to synchronize logic to control whether a transition occurs increases the amount of logic operations and makes the synchronization path slightly more complex. In contrast, this invention uses a gated clock method, transferring the signal hold or transition from the data path to the clock's on / off state, which is more conducive to the timing convergence of the synchronized data path. On the other hand, the output signal paths sclk, scs, and data need to be balanced to ensure that the pin delays are the same. In the existing str method, scs and data are ordinary data paths, while sclk uses a gated clock output, which is not conducive to timing constraints. In this invention, sclk is uniformly changed to qspi_clk_2x output, the same as scs and data, which facilitates timing constraints.

Claims

1. A method for implementing str / dtr mode for a flash controller, characterized in that... Includes the following steps: S1. Set the clock frequency of the doubled clock and use the set doubled clock as the reference clock; S2. The register that uses a doubled clock frequency as the clock signal outputs the Flash clock signal and outputs it to the corresponding pin of the Flash chip; S3. Set the clock gating signal for the reference clock, control the reference clock through the clock gating signal, and obtain the application clock; S4. Use the application clock obtained in step S3 to control the chip select signal and data signal of the Flash chip; S5. In str mode, the clock gate signal is set to flip according to the rising and falling edges of the reference clock to ensure that the application clock is a division of the reference clock by two. S6. In DTR mode, the clock gating signal is enabled to ensure that the application clock and the reference clock are synchronized. S7. Repeat steps S1 to S6 to complete the implementation of str / dtr mode for the flash controller.

2. The method for implementing str / dtr mode for a flash controller according to claim 1, characterized in that... Step S5 specifically involves setting the clock gate signal qspi_clk_en to flip once on the rising edge of each reference clock qspi_clk_2x in str mode, thereby ensuring that the application clock qspi_clk is a division of the reference clock by two; in str mode, the data signal of the Flash chip corresponds to one data cycle in each Flash clock signal period.

3. The method for implementing str / dtr mode for a flash controller according to claim 2, characterized in that... Step S6 specifically involves setting the clock gate signal qspi_clk_en to be continuously valid in DTR mode, at which time the application clock qspi_clk and the reference clock qspi_clk_2x are at the same frequency; in DTR mode, all signals of the circuit are synchronized with the rising edge of the application clock qspi_clk.

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