Dynamic Power Management Method for In-Memory Computing Chip and Related Devices

Abstract

The present invention relates to a dynamic power consumption management method and related devices for a computing-in-memory integrated chip, including the following steps: collecting temperature data of the target chip to obtain a temperature distribution map of the target chip; performing power consumption-temperature correlation analysis on the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip to obtain a power consumption-temperature correlation matrix; performing power consumption management planning on the target chip based on the power consumption-temperature correlation matrix to obtain a dynamic power consumption management strategy; performing voltage-frequency regulation on the target chip based on the dynamic power consumption management strategy to obtain voltage-frequency control parameters; and performing power consumption management on the target chip based on the voltage-frequency control parameters to obtain a chip power consumption management scheme, solving the technical problem that due to the complex non-linear relationship between power consumption and temperature, traditional optimization strategies based on a single parameter are difficult to meet the requirements of high efficiency and energy conservation.

Description

Technical Field

[0001] The present invention relates to the technical field of in-memory computing integrated chips, and particularly to a dynamic power consumption management method and related devices for in-memory computing integrated chips. Background Art

[0002] With the rapid development of information technology, the demand for performance of computing devices is continuously increasing. As an emerging technology, in-memory computing integrated chips have shown great potential in improving data processing speed and efficiency. However, the high power consumption problem brought by this high performance has gradually become one of the bottlenecks restricting its development. Traditional power consumption management methods often focus on optimization under static conditions and have limited ability to adjust dynamic power consumption caused by load changes during operation. Especially in the case of increasing integration, the difference in working states of different regions inside the chip may lead to local hot spots, thereby affecting the overall performance and lifespan. Therefore, it is particularly urgent to explore an effective power consumption management scheme that can adapt to the characteristics of in-memory computing integrated chips.

[0003] In practical applications, in-memory computing integrated chips not only need to process a large amount of data operations but also perform frequent data access operations, which requires the power consumption management system to be able to respond to these complex and changing task requirements in real time. The current challenges include how to accurately obtain and analyze the power consumption distribution and temperature change trend of each part inside the chip, so as to provide a reliable basis for power consumption management. In addition, due to the complex non-linear relationship between power consumption and temperature, traditional optimization strategies based on a single parameter are difficult to meet the requirements of high efficiency and energy saving. Therefore, it is necessary to introduce advanced algorithms and technical means to achieve more refined and intelligent power consumption control.

[0004] To overcome the above problems, researchers have proposed a new dynamic power consumption management method for in-memory computing integrated chips. This method realizes precise monitoring of the power consumption and temperature distribution of the target chip by deploying an on-chip sensor array and a temperature sensor network. On this basis, a mathematical model reflecting the interaction mechanism between the two is constructed using power consumption-temperature correlation analysis, and a flexible and effective power consumption management plan is formulated in combination with a multi-objective optimization algorithm. Finally, specific adjustment of voltage and frequency is completed by means of advanced technologies such as adaptive clock gating, forming a closed-loop control system. This method not only improves the accuracy and response speed of power consumption management but also provides a new idea for solving the power consumption problems faced by in-memory computing integrated chips. Summary of the Invention

[0005] The main object of the present invention is to provide a dynamic power consumption management method and related devices for in-memory computing integrated chips, and solve the technical problem that due to the complex non-linear relationship between power consumption and temperature, traditional optimization strategies based on a single parameter are difficult to meet the requirements of high efficiency and energy saving.

[0006] To achieve the above object, the present invention provides a dynamic power consumption management method for a memory - in - computing integrated chip, including the following steps:

[0007] Collect real - time power consumption data of a target chip through a preset on - chip sensor array to obtain a power consumption distribution map of the target chip; wherein, the memory - in - computing integrated chip is used as the target chip;

[0008] Collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution map of the target chip;

[0009] Perform power - temperature correlation analysis on the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip to obtain a power - temperature correlation matrix;

[0010] Through a multi - objective optimization algorithm, perform power consumption management planning on the target chip based on the power - temperature correlation matrix to obtain a dynamic power consumption management strategy;

[0011] Perform voltage - frequency regulation on the target chip based on the dynamic power consumption management strategy to obtain voltage - frequency control parameters;

[0012] Through an adaptive clock gating technology, perform power consumption management on the target chip based on the voltage - frequency control parameters to obtain a chip power consumption management scheme.

[0013] Further, the step of collecting real - time power consumption data of a target chip through a preset on - chip sensor array to obtain a power consumption distribution map of the target chip includes:

[0014] Perform power consumption scanning and collection on the target chip through a preset on - chip sensor array to obtain a power consumption feature set of the target chip;

[0015] Perform time - domain analysis on the power consumption feature set of the target chip through a preset piece - wise linear interpolation algorithm to obtain power consumption time - series feature data; wherein, the power consumption time - series feature data includes power consumption fluctuation period, power consumption peak moment, and power consumption trough interval;

[0016] Perform instantaneous frequency analysis on the power consumption time - series feature data to obtain a power consumption spectrum distribution map; wherein, the power consumption spectrum distribution map includes main frequency component features, harmonic component features, and mixed - frequency component features;

[0017] Perform time - frequency joint analysis on the power consumption spectrum distribution map based on the Wigner - Ville distribution algorithm to obtain power consumption time - frequency features; wherein, the power consumption time - frequency features include power consumption frequency migration trajectory, power consumption energy aggregation region, and power consumption transient mutation point;

[0018] Through the conditional entropy estimation algorithm, spatial mapping is performed on the target chip based on the power consumption time-frequency characteristics to obtain a power consumption distribution map of the target chip; wherein, the power consumption distribution map of the target chip includes a high-power consumption area positioning map, power consumption density contour lines, and a power consumption change trend map.

[0019] Further, the temperature data of the target chip is collected through a temperature sensor network to obtain a temperature distribution map of the target chip, including:

[0020] Real-time temperature data of the target chip is collected through a preset temperature sensor network to obtain a temperature sampling data set of the target chip; wherein, the temperature sampling data set includes the temperature value, timestamp, and position coordinates of each sensor in the temperature sensor network;

[0021] Noise filtering and data fusion are performed on the temperature sampling data set to obtain a denoised temperature data sequence;

[0022] Based on the finite element analysis method, temperature field reconstruction is performed based on the denoised temperature data sequence to obtain a three-dimensional temperature field distribution of the target chip; wherein, the three-dimensional temperature field distribution includes the temperature values and temperature gradient information of each point inside the target chip;

[0023] Hot spot area identification is performed on the three-dimensional temperature field distribution to obtain a hot spot area distribution map of the target chip; wherein, the hot spot area distribution map includes the hot spot position, hot spot temperature peak value, and hot spot area;

[0024] Heat source power estimation is performed on the hot spot area distribution map of the target chip through the reverse heat transfer analysis method to obtain heat source power distribution data of the target chip; wherein, the heat source power distribution data includes the power value and power density of each hot spot area;

[0025] Based on the heat source power distribution data, a temperature distribution map is generated to obtain a temperature distribution map of the target chip; wherein, the temperature distribution map of the target chip includes the temperature values of each computing unit and storage unit in the target chip and is visually presented in the form of a color heat map.

[0026] Further, the power consumption-temperature correlation analysis is performed on the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip to obtain a power consumption-temperature correlation matrix, including:

[0027] Perform multi-scale decomposition on the power consumption distribution map and the temperature distribution map of the target chip through adaptive wavelet transform to obtain a power consumption-temperature feature component set, and perform local singular value decomposition on the power consumption-temperature feature component set to obtain a power consumption-temperature basis vector matrix; wherein, the power consumption-temperature basis vector matrix includes a computing unit power consumption-temperature mapping matrix, a storage unit power consumption-temperature mapping coefficient, and an on-chip bus power consumption-temperature coupling factor;

[0028] Perform empirical mode decomposition on the power consumption-temperature basis vector matrix based on Hilbert-Huang transform to obtain a power consumption-temperature intrinsic component sequence, and perform bispectrum analysis on the power consumption-temperature intrinsic component sequence to obtain power consumption-temperature cross-spectrum features; wherein, the power consumption-temperature cross-spectrum features include a power consumption-temperature oscillation period, a power consumption-temperature phase difference, and a power consumption-temperature amplitude ratio;

[0029] Perform non-linear dynamics reconstruction on the power consumption-temperature cross-spectrum features through a preset local projection embedding algorithm to obtain a power consumption-temperature state space trajectory;

[0030] Perform time-series correlation analysis based on the power consumption-temperature state space trajectory to obtain a power consumption-temperature coupling feature sequence, and perform transfer entropy calculation on the power consumption-temperature coupling feature sequence to obtain a power consumption-temperature causal network;

[0031] Perform community detection on the power consumption-temperature causal network to obtain a power consumption-temperature coupling subgraph set, and perform spectral clustering analysis on the power consumption-temperature coupling subgraph set to obtain a power consumption-temperature correlation region; wherein, the power consumption-temperature correlation region includes a strong coupling region identifier, a weak coupling region boundary, and a critical coupling region feature;

[0032] Perform dynamic feature extraction on the power consumption-temperature correlation region based on recursive quantification analysis to obtain a power consumption-temperature time-varying feature set, and perform tensor decomposition on the power consumption-temperature time-varying feature set to obtain a power consumption-temperature correlation matrix.

[0033] Further, through a multi-objective optimization algorithm, perform power consumption management planning on the target chip based on the power consumption-temperature correlation matrix to obtain a dynamic power management strategy, including:

[0034] Perform singular value decomposition on the power consumption-temperature correlation matrix to obtain a power consumption-temperature feature vector set, and perform principal component analysis on the power consumption-temperature feature vector set to obtain power consumption-temperature principal component features;

[0035] Optimize the power consumption-temperature principal component features through a multi-objective genetic algorithm to obtain a power consumption-temperature Pareto optimal solution set;

[0036] Construct a power consumption - temperature objective function for the target chip using the power consumption - temperature Pareto optimal solution set, obtain a multi - objective optimization function, and solve the multi - objective optimization function using the Lagrange multiplier method to obtain a Lagrange multiplier vector; wherein, the Lagrange multiplier vector includes a power consumption weight coefficient, a temperature weight coefficient, and a performance weight coefficient.

[0037] Based on the Lagrange multiplier vector, perform dynamic power consumption budget allocation for the target chip to obtain a power consumption budget allocation plan, and optimize the power consumption budget allocation plan using a resource competition strategy based on game theory to obtain a Nash equilibrium point; wherein, the Nash equilibrium point includes a computing unit power consumption budget, a storage unit power consumption budget, and a communication unit power consumption budget.

[0038] Based on the Nash equilibrium point, perform power consumption management planning for the target chip to obtain a dynamic power consumption management strategy.

[0039] Furthermore, the voltage - frequency regulation of the target chip based on the dynamic power consumption management strategy to obtain voltage - frequency control parameters includes:

[0040] Perform clustering analysis on the power consumption characteristics of the target chip through the dynamic power consumption management strategy to obtain a power consumption cluster set, and perform principal component analysis on the power consumption cluster set to obtain a power consumption feature vector; wherein, the power consumption feature vector includes the chip power consumption mean, power consumption variance, and power consumption peak characteristic parameters.

[0041] Based on the power consumption feature vector, perform voltage regulation analysis on the target chip to obtain a voltage regulation plan.

[0042] Through the voltage regulation plan, perform frequency configuration analysis on the target chip to obtain a frequency configuration plan.

[0043] Based on the frequency control parameters, perform power consumption allocation analysis on the target chip to obtain a power consumption allocation plan, and optimize the power consumption allocation plan using the ant colony algorithm to obtain power consumption allocation parameters; wherein, the power consumption allocation parameters include a power consumption allocation ratio, a power consumption allocation threshold, and a power consumption allocation delay parameter.

[0044] Through the power consumption allocation parameters, perform voltage - frequency regulation on the target chip to obtain a voltage - frequency control signal.

[0045] Based on the voltage - frequency control signal, perform voltage - frequency regulation on the target chip to obtain voltage - frequency control parameters.

[0046] Furthermore, through the adaptive clock gating technology, perform power consumption management on the target chip based on the voltage - frequency control parameters to obtain a chip power consumption management plan, including:

[0047] Extract the timing characteristics of the voltage-frequency control parameters through the adaptive clock gating technology to obtain a clock adjustment scheme, and perform Fourier transform analysis on the clock adjustment scheme to obtain the clock spectrum characteristics; wherein, the clock spectrum characteristics include clock frequency components, clock phase offsets, and clock amplitude adjustment characteristic parameters.

[0048] Perform power consumption prediction analysis on the target chip based on the clock spectrum characteristics to obtain a power consumption prediction sequence; wherein, the power consumption prediction sequence includes the power consumption timing mean, power consumption fluctuation variance, and power consumption peak characteristic parameters.

[0049] Perform power consumption allocation planning on the target chip through the power consumption prediction sequence to obtain a power consumption allocation strategy, and perform parameter analysis on the power consumption allocation strategy to obtain power consumption allocation control parameters.

[0050] Perform dynamic voltage-frequency adjustment on the target chip based on the power consumption allocation control parameters to obtain a voltage-frequency configuration scheme, and perform instruction conversion on the voltage-frequency configuration scheme to obtain voltage-frequency control instructions.

[0051] Perform power consumption management on the target chip based on the voltage-frequency control instructions to obtain a chip power consumption management scheme.

[0052] The present invention also provides a dynamic power consumption management device for a memory-computation integrated chip, including:

[0053] A first acquisition module, configured to collect real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution map of the target chip; wherein, the memory-computation integrated chip is used as the target chip.

[0054] A second acquisition module, configured to collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution map of the target chip.

[0055] An analysis module, configured to perform power consumption-temperature correlation analysis on the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip to obtain a power consumption-temperature correlation matrix.

[0056] A generation module, configured to perform power consumption management planning on the target chip based on the power consumption-temperature correlation matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy.

[0057] An adjustment module, configured to perform voltage-frequency adjustment on the target chip based on the dynamic power consumption management strategy to obtain voltage-frequency control parameters.

[0058] A management module, configured to perform power consumption management on the target chip based on the voltage-frequency control parameters through the adaptive clock gating technology to obtain a chip power consumption management scheme.

[0059] The present invention also provides a computer device, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the steps of the method described in any one of the above are implemented.

[0060] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of the above are implemented.

[0061] The method for dynamic power consumption management of the integrated memory and computing chip provided by the present invention includes the following steps: collecting real-time power consumption data of a target chip through a preset on-chip sensor array to obtain a power consumption distribution map of the target chip; where the integrated memory and computing chip is used as the target chip; collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution map of the target chip; performing power consumption-temperature correlation analysis on the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip to obtain a power consumption-temperature correlation matrix; performing power consumption management planning on the target chip based on the power consumption-temperature correlation matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy; adjusting the voltage frequency of the target chip based on the dynamic power consumption management strategy to obtain voltage frequency control parameters; performing power consumption management on the target chip based on the voltage frequency control parameters through an adaptive clock gating technique to obtain a chip power consumption management scheme, solving the technical problem that due to the complex non-linear relationship between power consumption and temperature, traditional optimization strategies based on a single parameter are difficult to meet the requirements of high efficiency and energy saving, realizing in-depth power consumption-temperature correlation analysis using the power consumption distribution map and the temperature distribution map, and constructing a detailed power consumption-temperature correlation matrix. This correlation analysis helps to more profoundly understand the complex relationship between the two, and then formulate a more scientific and reasonable power consumption management strategy to ensure controlling the chip temperature while optimizing the power consumption, and avoiding the technical effects of performance degradation or hardware damage caused by local overheating. Description of the Drawings

[0062] Figure 1 is a schematic diagram of the steps of the method for dynamic power consumption management of the integrated memory and computing chip in an embodiment of the present invention;

[0063] Figure 2 is a block diagram of the structure of the device for dynamic power consumption management of the integrated memory and computing chip in an embodiment of the present invention;

[0064] Figure 3 is a schematic block diagram of the structure of the computer device in an embodiment of the present invention.

[0065] The realization, functional characteristics and advantages of the object of the present invention will be further described with reference to the embodiments and the drawings. Detailed Embodiments

[0066] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0067] As Figure 1 shown, Figure 1 is a schematic diagram of the steps of a dynamic power consumption management method for a memory-computation integrated chip in an embodiment of the present invention;

[0068] An embodiment of the present invention provides a dynamic power consumption management method for a memory-computation integrated chip, including the following steps:

[0069] Step S1, collect real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution map of the target chip; wherein, the memory-computation integrated chip is used as the target chip.

[0070] Specifically, the step of "collecting real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution map of the target chip; where the in-memory computing integrated chip is used as the target chip" mentioned above is the basis for implementing the dynamic power management method. To achieve this process, a series of specially designed sensors need to be integrated on the in-memory computing integrated chip first, and these sensors constitute the so-called on-chip sensor array. The on-chip sensor array can monitor the current consumption in various regions inside the chip and collect power consumption data with extremely high time resolution. For example, in a high-performance server environment, the in-memory computing integrated chip may be responsible for processing a large number of concurrent requests and data exchanges. At this time, the on-chip sensor array will continuously track the power consumption changes during the execution of different computing tasks. Next, as the data is continuously collected, the system will process these raw data and then generate an intuitive power consumption distribution map. This map details the power consumption characteristics of the chip during a specific period, including information such as which regions are in a high-load state and which regions are relatively idle. For the above server application scenario, when some cores are running complex algorithms at full capacity while other parts may only maintain basic operations, then the power consumption distribution map will show obvious power consumption concentration areas and low-power areas. Further, the power consumption distribution map is not only a simple visual display, but also provides a basis for further in-depth analysis. By analyzing these power consumption data, potential problem points or optimization opportunities can be discovered, such as whether there are unnecessary high-power consumption activities or whether it is possible to save energy by adjusting the working mode. In addition, due to the characteristics of the in-memory computing integrated chip that it integrates storage units and computing units, the power consumption distribution map can also help identify hot spots with high storage access frequencies and how they affect the overall power consumption level. All in all, by carefully arranging the preset on-chip sensor array and effectively using the obtained data, we can accurately draw the power consumption distribution map of the target chip, that is, the in-memory computing integrated chip, without affecting normal operations, thus laying a solid foundation for further implementing precise power management and performance optimization. This not only helps improve the energy efficiency ratio of the system, but also ensures stable and reliable operation in various complex application scenarios.

[0071] Step S2, collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution map of the target chip.

[0072] Specifically, the process of "collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution map of the target chip" mentioned above is an important part of monitoring the working state of the in-memory computing integrated chip. To achieve this goal, it is first necessary to deploy a carefully designed temperature sensor network inside and around the chip. These temperature sensors are distributed in key areas of the chip, including computing units, memory units, and data paths between the two, ensuring that they can comprehensively cover and accurately reflect the temperature changes of each part. For example, in a high-performance server environment, the in-memory computing integrated chip undertakes a large number of concurrent requests and complex data processing tasks, and the temperature sensor network continuously records the temperature fluctuations in each area during the execution of different computing tasks. As the temperature data accumulates, the system will analyze and process the collected information, and then generate a detailed temperature distribution map of the target chip. This map not only intuitively shows the temperature gradient on the chip surface, but also reveals the direction and intensity of heat flow, enabling engineers to clearly identify which areas are heat source points and where there are heat dissipation bottlenecks. For the aforementioned server application scenario, when certain cores heat up due to high-intensity operations, the temperature distribution map can show the specific locations of these hot spots, and at the same time can also indicate relatively low-temperature idle areas, which helps to understand the dynamic characteristics of heat transfer inside the chip. Further, the temperature distribution map is not just a static image display, but also a dynamic monitoring tool. By real-time tracking of temperature data, the system can timely detect abnormal temperature rises and take preventive measures to avoid performance degradation or hardware damage caused by overheating. In addition, combined with the power consumption distribution map, the correlation between power consumption and temperature can be studied more deeply, providing important references for subsequent algorithm optimization. For example, if a certain computing unit shows an unreasonable high temperature under high load, it may mean that the working frequency of this unit is too high or the power supply voltage setting is inappropriate, then corresponding parameters can be adjusted to improve this situation. In short, by constructing and using a temperature sensor network, we can accurately draw the temperature distribution map of the target chip, that is, the in-memory computing integrated chip, without affecting normal operations, thus laying a solid foundation for realizing efficient power consumption management and thermal management strategies. This not only helps to improve the energy efficiency ratio of the system, but also ensures stable and reliable operation in various complex application scenarios. For applications in high-performance servers, this precise temperature monitoring and control ability is particularly important.

[0073] Step S3, perform power consumption-temperature correlation analysis on the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip, to obtain a power consumption-temperature correlation matrix.

[0074] Specifically, the process of performing power-temperature correlation analysis on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power-temperature correlation matrix is the core link in the dynamic power management method. This process not only depends on the detailed power consumption and temperature data obtained in the previous steps but also requires the use of advanced data analysis techniques to reveal the complex relationship between the two. Specifically, in a high-performance server environment, when the in-memory computing integrated chip runs a large number of concurrent requests and complex data processing tasks, power consumption and temperature information about each area of the chip have been collected through a preset on-chip sensor array and temperature sensor network. After these information are respectively sorted into intuitive power consumption distribution maps and temperature distribution maps, the next task is to deeply explore the internal connection between the two. To achieve power-temperature correlation analysis, it is first necessary to match the corresponding points in the power consumption distribution map and the temperature distribution map to ensure that each power consumption measurement value can find the corresponding temperature measurement value. For example, during the process of the computing unit performing high-intensity operations, if it is found that the power consumption in a certain area increases significantly while the temperature in this area also rises correspondingly, then it can be initially judged that there is a positive correlation between the two. However, this relationship is not always linear because factors such as heat conduction, diffusion, and external cooling conditions will affect the final temperature performance. Therefore, further analysis requires the use of mathematical modeling methods to consider the influence of more variables and construct a model that can accurately describe the non-linear relationship between power consumption and temperature. After establishing a preliminary correlation model, researchers will use multi-dimensional statistical analysis and other advanced algorithms to optimize the model parameters so that the power-temperature correlation matrix can more accurately reflect the actual situation. This matrix is not just a static result display; it also provides an important decision-making basis for subsequent power management and thermal management strategies. For example, in the above server application scenario, if it is found according to the power-temperature correlation matrix that the temperature of some computing units rises abnormally under specific workloads, it may be due to insufficient heat dissipation design or improper power management. At this time, the operating frequency or voltage settings of these units can be adjusted based on the information provided by the matrix, thereby effectively reducing the temperature and avoiding potential performance bottlenecks or hardware failure risks. In addition, the power-temperature correlation matrix can also be used to guide the design and optimization of future chips. By studying the changing trends of power consumption and temperature under different operating conditions, engineers can identify which design factors are most likely to cause problems such as excessive power consumption or poor heat dissipation and propose improvement solutions accordingly. In summary, through in-depth analysis of the target chip power consumption distribution map and temperature distribution map, we can not only establish a detailed power-temperature correlation matrix but also provide a scientific basis for achieving efficient power control and thermal management, ensuring the stability and reliability of the system in various complex application scenarios. In applications such as high-performance servers, this precise correlation analysis ability is particularly crucial.

[0075] Step S4, through a multi-objective optimization algorithm, perform power consumption management planning on the target chip based on the power consumption-temperature correlation matrix to obtain a dynamic power management strategy.

[0076] Specifically, the process of performing power management planning for the target chip based on the power consumption-temperature correlation matrix through a multi-objective optimization algorithm to obtain a dynamic power management strategy is a key step in ensuring that the in-memory computing integrated chip achieves high performance and low power consumption in complex application scenarios such as high-performance servers. This process relies on the previously constructed power consumption-temperature correlation matrix, which details the complex relationship between the power consumption and temperature of each part of the chip, providing a solid data foundation for the subsequent optimization. When facing the diversity and uncertainty in actual operation, the multi-objective optimization algorithm can comprehensively consider multiple mutually restrictive factors, such as performance requirements, power consumption limits, and temperature control, to find the optimal solution. Specifically, in a high-performance server environment, the in-memory computing integrated chip may simultaneously process a large number of concurrent requests and complex computing tasks. At this time, through the analysis of the previous power consumption distribution map and temperature distribution map, it has been clear which areas are prone to becoming heat source points and the correlation between these hot spots and power consumption. Based on this, the multi-objective optimization algorithm begins to play a role. It will dynamically adjust the working state of each computing unit according to the current task load situation and the information provided by the power consumption-temperature correlation matrix. For example, if a certain computing unit has a high power consumption and a rapid temperature rise when executing a specific type of task, then the optimization algorithm may choose to reduce the working frequency of this unit or allocate tasks to other relatively low-temperature areas to balance the overall power consumption and temperature distribution. Further, the multi-objective optimization algorithm is not limited to static configuration, but continuously monitors the state changes of the chip and responds in real time. As the workload changes, some originally inactive areas may suddenly undertake more computing tasks, resulting in a sudden increase in power consumption and temperature. At this time, the optimization algorithm will quickly re-evaluate the power consumption-temperature situation of the entire system and adjust the strategy accordingly to ensure that the overall performance is not affected by local overheating. In addition, considering the reliability and energy consumption cost under long-term operation, the optimization algorithm will also introduce some forward-looking indicators, such as predicting future load trends and corresponding power consumption changes, and making preparations in advance to avoid unnecessary high-power consumption periods. To achieve the above functions, the optimization algorithm usually combines machine learning techniques and continuously improves the accuracy and efficiency of decision-making through learning historical data and pattern recognition. For example, in a high-performance server scenario, over time, the system has accumulated a large amount of power consumption and temperature data. The optimization algorithm can learn the most effective power management scheme under different task combinations from this data, thereby forming a set of adaptive dynamic power management strategies. This set of strategies can not only minimize power consumption to the greatest extent while ensuring performance, but also effectively prevent hardware failures caused by overheating and improve the stability and reliability of the system. In short, through the application of the multi-objective optimization algorithm, we can formulate a more intelligent and flexible dynamic power management strategy based on the power consumption-temperature correlation matrix, providing strong support for high-performance servers and other similar application scenarios.

[0077] Step S5, perform voltage and frequency regulation on the target chip based on the dynamic power management policy to obtain voltage and frequency control parameters.

[0078] Specifically, the process of adjusting the voltage and frequency of the target chip based on the dynamic power management strategy to obtain voltage-frequency control parameters is one of the key links in achieving high performance and low power consumption of the in-memory computing chip. This process closely depends on the dynamic power management strategy formulated through the multi-objective optimization algorithm before. This strategy comprehensively considers various factors such as power consumption, temperature, and performance requirements, providing clear guidance for the specific voltage-frequency adjustment. In a high-performance server environment, when the in-memory computing chip processes a large number of concurrent requests and complex computing tasks, voltage-frequency adjustment can ensure that the system meets the performance requirements while minimizing unnecessary power consumption and maintaining a safe operating temperature. Specifically, after determining the dynamic power management strategy, the next step is to convert these strategies into actual operation instructions, that is, voltage-frequency control parameters. This involves precisely adjusting the supply voltage and operating frequency of each working unit inside the target chip. For example, according to the analysis results of the power consumption-temperature correlation matrix and the current task load situation, if a certain computing unit is in a high-load state and the temperature is close to the critical value, the dynamic power management strategy may instruct to appropriately reduce its operating frequency and fine-tune the supply voltage to ensure that the performance is not affected too much. This adjustment is not fixed but will be dynamically updated as the task changes to ensure that the best voltage-frequency combination can be found at any time. To achieve this, a programmable power management and clock control system is usually introduced at the chip design stage, allowing the software layer to flexibly set voltage and frequency parameters. In practical applications, these control systems will adjust the working state of each computing unit in real time according to the instructions issued by the dynamic power management strategy. For example, in a high-performance server scenario, when it is detected that the temperature in some areas rises too fast due to high-intensity operations, the system can automatically reduce the operating frequency of those areas and adjust the supply voltage according to the pre-set rules, thus quickly alleviating the local hot spot problem. At the same time, for relatively idle or low-load areas, the operating frequency can be appropriately increased to accelerate the completion of the remaining tasks, or the voltage can be reduced to save energy. In addition, to ensure the safety and effectiveness of voltage-frequency adjustment, the whole process is strictly monitored. By continuously collecting data feedback from the on-chip sensor array and temperature sensor network, the system can respond to any abnormal conditions in a timely manner, such as excessive voltage fluctuations or temperatures exceeding the safe range, and then take emergency measures to protect the hardware from damage. To sum up, adjusting the voltage and frequency of the target chip based on the dynamic power management strategy not only helps to optimize the balance between performance and power consumption, but also effectively prevents potential failures caused by overheating, providing a more intelligent and reliable solution for high-performance servers and other similar application scenarios. In this way, we can significantly improve the energy efficiency ratio of the system without affecting normal operations, ensuring its long-term stable and reliable operation.

[0079] Step S6, through the adaptive clock gating technology, perform power consumption management on the target chip based on the voltage-frequency control parameter to obtain a chip power consumption management scheme.

[0080] Specifically, through the adaptive clock gating technology, the process of performing power consumption management on the target chip based on the voltage-frequency control parameters to obtain a chip power consumption management solution is the last link for the in-memory computing chip to achieve the balance between high performance and low power consumption in a high-performance server environment. This process is built on top of all the previous steps, that is, first, detailed power consumption and temperature data are collected through the on-chip sensor array and the temperature sensor network, then a power consumption-temperature correlation matrix is constructed, and then a dynamic power management strategy is formulated using a multi-objective optimization algorithm, and finally the voltage and frequency parameters are adjusted according to these strategies. On this basis, the adaptive clock gating technology further finely controls the clock signals inside the chip to ensure that each computing unit is only activated when it is truly needed, thus minimizing the static power consumption to the greatest extent. Specifically, in a high-performance server, when the in-memory computing chip executes complex data processing tasks, the workloads in different regions may vary greatly. Some computing units may be in a high-load state, while other parts are relatively idle or only undertake minor tasks. In this case, through the adaptive clock gating technology, it is possible to dynamically determine which clock signals should be turned on or off according to the voltage-frequency control parameters. For example, if a certain computing unit has no task currently or its workload is very small, then the system can temporarily turn off the clock signal of this unit and make it enter a low-power standby mode until a new task arrives. On the contrary, for those computing units that are in a busy state, the normal supply of clock signals is maintained to ensure that the performance is not affected. In addition, the adaptive clock gating technology can also respond to real-time changing working conditions and provide more flexible power consumption management. As the task load changes, the system will continuously re-evaluate the needs of each computing unit and adjust the clock gating strategy accordingly. For example, in a high-performance server scenario, when it is detected that some regions become idle due to task completion, the adaptive clock gating technology will immediately stop sending clock signals to these regions to avoid unnecessary power consumption. At the same time, for the regions that are about to receive new tasks, the system prepares the required clock resources in advance to ensure that the tasks can be started quickly and executed efficiently. To ensure that this dynamic adjustment will not have a negative impact on the overall performance, the adaptive clock gating technology usually combines intelligent prediction algorithms to identify potential task demand changes in advance. This can not only respond to the actual situation in a timely manner but also anticipate future load fluctuations and make preparations in advance. For example, when dealing with a large number of concurrent requests, the system may predict the upcoming traffic peak based on historical data and current trends and activate the clock signals of relevant computing units in advance to ensure that there is sufficient processing power to handle the upcoming tasks. In short, through the adaptive clock gating technology, performing power consumption management on the target chip based on the voltage-frequency control parameters can not only further reduce the static power consumption and improve the energy efficiency ratio of the system but also ensure stable performance in various complex application scenarios.This method provides a more intelligent and refined power consumption management solution for high-performance servers, enabling the memory-compute integrated chip to effectively control energy consumption, extend the hardware lifespan, and reduce heat dissipation pressure while meeting high-performance requirements. In this way, we can significantly improve the overall operation effect of the system without affecting the computing efficiency, ensuring its long-term stable and reliable service for complex computing tasks.

[0081] In a specific embodiment, the real-time power consumption data of the target chip is collected through a preset on-chip sensor array to obtain a power consumption distribution map of the target chip, including:

[0082] The power consumption of the target chip is scanned and collected through a preset on-chip sensor array to obtain a power consumption feature set of the target chip;

[0083] The time-domain analysis of the power consumption feature set of the target chip is performed through a preset piecewise linear interpolation algorithm to obtain power consumption time-series feature data; wherein, the power consumption time-series feature data includes a power consumption fluctuation period, a power consumption peak moment, and a power consumption valley value interval;

[0084] The instantaneous frequency analysis of the power consumption time-series feature data is performed to obtain a power consumption frequency spectrum distribution map; wherein, the power consumption frequency spectrum distribution map includes a main frequency component feature, a harmonic component feature, and a mixed frequency component feature;

[0085] The time-frequency joint analysis of the power consumption frequency spectrum distribution map is performed based on the Wigner-Ville distribution algorithm to obtain power consumption time-frequency features; wherein, the power consumption time-frequency features include a power consumption frequency migration trajectory, a power consumption energy aggregation region, and a power consumption transient mutation point;

[0086] Through a conditional entropy estimation algorithm, the target chip is spatially mapped based on the power consumption time-frequency features to obtain a power consumption distribution map of the target chip; wherein, the power consumption distribution map of the target chip includes a high-power consumption area positioning map, power consumption density contour lines, and a power consumption change trend map.

[0087] Specifically, the process of collecting real-time power consumption data of the target chip through a preset on-chip sensor array to obtain the power consumption distribution map of the target chip is a complex and delicate technical implementation. First, the system uses the preset on-chip sensor array to conduct a comprehensive power consumption scan and collection of the target chip. This process aims to capture the power consumption characteristics of the chip at different time points, forming a target chip power consumption feature set containing detailed power consumption information. For example, in a high-performance server environment, a memory-compute integrated chip may need to process a large number of concurrent requests. The sensor array will record the power consumption of each computing unit and storage unit during these operations to ensure that no key data is missed. Next, in order to understand the variation law of power consumption characteristics over time in more depth, the system uses a preset piecewise linear interpolation algorithm to perform time-domain analysis on the obtained target chip power consumption feature set. This step can reveal timing feature data such as the power consumption fluctuation period, the moment of power consumption peak, and the power consumption valley interval. Taking a high-performance server as an example, when certain computing tasks are executed intensively, the power consumption may show an obvious peak, while it drops to the valley during the task interval. By accurately measuring these timing characteristics, future power consumption requirements can be better predicted and managed. Further, in order to explore the frequency-domain characteristics of power consumption changes, the system performs instantaneous frequency analysis on the above power consumption timing feature data to generate a power consumption spectrum distribution map. This map not only shows the main frequency component characteristics but also reveals the harmonic component characteristics and the mixed-frequency component characteristics, which are crucial for understanding complex power consumption behaviors. For example, in a high-performance server, if a certain computing unit frequently switches its working state, its power consumption spectrum may show significant harmonic components, which provides important reference information for optimizing algorithms and helps identify which operations may cause unnecessary high power consumption. In order to comprehensively grasp the spatio-temporal characteristics of power consumption, the system performs time-frequency joint analysis on the power consumption spectrum distribution map based on the Wigner-Ville distribution algorithm. In this way, power consumption time-frequency characteristics including the power consumption frequency migration trajectory, the power consumption energy aggregation region, and the power consumption transient mutation points can be obtained. This means that we can track how power consumption evolves over time and frequency and identify those specific events or operation patterns that have a greater impact on the overall power consumption. For example, in a high-performance server scenario, when a new batch of tasks starts to be executed, we can quickly locate the reason for the sudden increase in power consumption through time-frequency joint analysis and then take measures for optimization. Finally, in order to convert these rich power consumption characteristics into an intuitive spatial mapping result, the system uses a conditional entropy estimation algorithm to perform spatial mapping on the target chip based on the power consumption time-frequency characteristics, and finally obtains the power consumption distribution map of the target chip. This map includes a high-power consumption area location map, power consumption density contour lines, and a power consumption change trend map, enabling engineers to clearly see the power consumption status of each part inside the chip at a glance.For example, in high-performance server applications, by observing the power consumption distribution map, we can clearly identify which computing units or storage areas are in a high-load state and where there is potential for energy savings, thus providing strong support for subsequent power management and performance optimization. In summary, through the above series of steps, from the acquisition of the power consumption feature set to the generation of the power consumption distribution map, we have not only achieved a deep analysis of the power consumption status of the target chip but also found a scientific basis for the balance between high performance and low power consumption. This method ensures that, without affecting normal operations, the power consumption performance of the system can be accurately controlled and optimized, providing strong guarantee for high-performance servers and other similar application scenarios.

[0088] In a specific embodiment, the temperature data of the target chip is collected through a temperature sensor network to obtain a temperature distribution map of the target chip, including:

[0089] Real-time temperature data of the target chip is collected through a preset temperature sensor network to obtain a temperature sampling data set of the target chip; wherein, the temperature sampling data set includes the temperature value, timestamp, and position coordinates of each sensor in the temperature sensor network;

[0090] The temperature sampling data set is subjected to noise filtering and data fusion to obtain a denoised temperature data sequence;

[0091] Based on the finite element analysis method, a temperature field reconstruction is performed based on the denoised temperature data sequence to obtain a three-dimensional temperature field distribution of the target chip; wherein, the three-dimensional temperature field distribution includes the temperature values and temperature gradient information of each point inside the target chip;

[0092] The hot spot area of the target chip is identified from the three-dimensional temperature field distribution to obtain a hot spot area distribution map of the target chip; wherein, the hot spot area distribution map includes the hot spot position, hot spot temperature peak value, and hot spot area;

[0093] The heat source power of the target chip is estimated from the hot spot area distribution map of the target chip through a reverse heat transfer analysis method to obtain heat source power distribution data of the target chip; wherein, the heat source power distribution data includes the power value and power density of each hot spot area;

[0094] Based on the heat source power distribution data, a temperature distribution map is generated to obtain a temperature distribution map of the target chip; wherein, the temperature distribution map of the target chip includes the temperature values of each computing unit and storage unit in the target chip and is visually presented in the form of a color heat map.

[0095] Specifically, the process of collecting temperature data of the target chip through the temperature sensor network to obtain the temperature distribution map of the target chip is a systematic and multi-step technical implementation. First, to ensure the accuracy and comprehensiveness of temperature data, it is necessary to collect real-time temperature data of the target chip through a preset temperature sensor network, so as to obtain the temperature sampling data set of the target chip. In a high-performance server environment, the memory-computation integrated chip may simultaneously undertake multiple concurrent requests and complex data processing tasks, which makes the working states of different regions inside it vary greatly and the temperature changes are also very complex. Therefore, each sensor in the temperature sensor network not only records the temperature value at its respective position, but also attaches accurate timestamp and position coordinate information. For example, in a typical high-performance server application scenario, these sensors are distributed at key positions such as computing units, storage units, and data paths between the two to ensure that the temperature changes at each point on the entire chip surface and inside can be captured. Next, due to the inevitable presence of various interference factors in the actual environment, the collected temperature data may contain noise. To solve this problem, the system will perform noise filtering and data fusion processing on the temperature sampling data set, aiming to remove outliers and random fluctuations and obtain a more smooth and stable denoised temperature data sequence. This process is crucial for improving the reliability of subsequent analysis results. For example, in a high-performance server, when some sensors are affected by external electromagnetic interference or short-term ambient temperature fluctuations, inaccurate readings may occur. Through advanced filtering algorithms and data fusion techniques, these interferences can be effectively eliminated to ensure that the finally obtained temperature data truly reflects the actual working state of the chip. Based on the above denoised temperature data sequence, the next step is to use the finite element analysis method to reconstruct the temperature field and then generate the three-dimensional temperature field distribution of the target chip. This method can accurately simulate the heat conduction process inside the chip and provide detailed information including temperature values and temperature gradients at each point. In a high-performance server environment, the three-dimensional temperature field distribution of the memory-computation integrated chip provides important clues for understanding how heat is transferred and accumulated inside the chip. For example, when a certain computing unit is in a high-load state for a long time, the temperature in this area will gradually rise and spread to the surrounding through heat conduction. Through finite element analysis, we can clearly see this temperature propagation path and its influence range, which is very helpful for formulating effective heat dissipation strategies. On this basis, the system further identifies the hot spot areas in the three-dimensional temperature field distribution to obtain the hot spot area distribution map of the target chip. This step aims to highlight the specific areas where the temperature abnormally rises, that is, the so-called "hot spots", and describe in detail the characteristics such as the position, temperature peak, and coverage area of the hot spots. In high-performance server applications, identifying these hot spot areas helps to timely discover potential risk points and take necessary preventive measures.For example, if a computing unit becomes a hot spot due to continuous high-intensity operations, then the performance degradation or even hardware damage caused by overheating can be avoided by adjusting the task allocation or optimizing the cooling system. To understand the root cause of hot spot formation more deeply, the system uses the reverse heat transfer analysis method to estimate the heat source power of the hot spot area distribution map, and obtains the heat source power distribution data of the target chip. This analysis can not only reveal which operating or design factors lead to local high temperatures, but also quantify the power value and its density of each hot spot area. In the high-performance server scenario, by estimating the heat source power, engineers can better evaluate whether the current workload settings are reasonable and whether there is unnecessary power consumption waste. For example, if the access frequency of a storage unit is too high and causes it to become a hot spot, then the data access pattern can be optimized to reduce unnecessary read and write operations, thereby reducing power consumption and temperature. Finally, based on the heat source power distribution data, the system generates a temperature distribution map, and finally obtains the temperature distribution map of the target chip. This map not only intuitively shows the temperature values of each computing unit and storage unit in the target chip, but also presents it in the form of a color heat map for visualization, so that users can clearly see which areas have higher temperatures and which areas have relatively lower temperatures. In the application of high-performance servers, such a temperature distribution map plays an irreplaceable role in monitoring the health status of the system, optimizing the power consumption management strategy, and guiding future chip designs. For example, by observing the temperature distribution map, the operation and maintenance personnel can quickly locate the areas that may have heat dissipation problems, and accordingly adjust the server configuration or maintenance plan to ensure that the system always operates within a safe and reliable temperature range. To sum up, through a series of fine processing and analysis of the data collected by the temperature sensor network, we can not only construct a detailed three-dimensional temperature field distribution, but also identify the hot spot areas and deeply explore their causes. The finally generated temperature distribution map of the target chip provides a solid scientific basis for achieving the balance between high performance and low power consumption, ensuring that the stability and reliability of the system are maximally improved without affecting normal operations. This method provides strong guarantees for high-performance servers and other similar application scenarios, enabling complex data centers to effectively control energy consumption and heat dissipation pressure while maintaining high performance.

[0096] In a specific embodiment, the power consumption-temperature correlation analysis of the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip to obtain a power consumption-temperature correlation matrix includes:

[0097] Perform multi-scale decomposition on the power consumption distribution map and the temperature distribution map of the target chip through adaptive wavelet transform to obtain a power consumption-temperature feature component set, and perform local singular value decomposition on the power consumption-temperature feature component set to obtain a power consumption-temperature basis vector matrix; wherein, the power consumption-temperature basis vector matrix calculates the power consumption-temperature mapping matrix of the unit, the power consumption-temperature mapping coefficient of the storage unit, and the power consumption-temperature coupling factor of the on-chip bus.

[0098] Perform intrinsic mode decomposition on the power consumption-temperature basis vector matrix based on Hilbert-Huang transform to obtain a power consumption-temperature intrinsic component sequence, and perform bispectral analysis on the power consumption-temperature intrinsic component sequence to obtain power consumption-temperature cross-spectrum features; wherein, the power consumption-temperature cross-spectrum features include power consumption-temperature oscillation period, power consumption-temperature phase difference, and power consumption-temperature amplitude ratio.

[0099] Perform non-linear dynamics reconstruction on the power consumption-temperature cross-spectrum features through a preset local projection embedding algorithm to obtain a power consumption-temperature state space trajectory.

[0100] Perform time series correlation analysis based on the power consumption-temperature state space trajectory to obtain a power consumption-temperature coupling feature sequence, and perform transfer entropy calculation on the power consumption-temperature coupling feature sequence to obtain a power consumption-temperature causal network.

[0101] Perform community detection on the power consumption-temperature causal network to obtain a power consumption-temperature coupled subgraph set, and perform spectral clustering analysis on the power consumption-temperature coupled subgraph set to obtain a power consumption-temperature association region; wherein, the power consumption-temperature association region includes strong coupling region identification, weak coupling region boundary, and critical coupling region features.

[0102] Perform dynamic feature extraction on the power consumption-temperature association region based on recursive quantification analysis to obtain a power consumption-temperature time-varying feature set, and perform tensor decomposition on the power consumption-temperature time-varying feature set to obtain a power consumption-temperature association matrix.

[0103] Specifically, in order to perform power-temperature correlation analysis on the target chip based on the power consumption distribution map and the temperature distribution map of the target chip, and finally obtain a power-temperature correlation matrix, the whole process is a multi-step complex analysis process. First, the system performs multi-scale decomposition on the power consumption distribution map and the temperature distribution map of the target chip through adaptive wavelet transform. This process aims to capture the relationship characteristics between power consumption and temperature at different time scales, so as to obtain a set of power-temperature feature components containing multi-level information. In the application scenario of high-performance servers, different functional areas inside the memory-computation integrated chip (such as computing units, storage units, and on-chip buses) may exhibit different power consumption and temperature characteristics due to changes in task loads. Adaptive wavelet transform can reveal the variation laws of these characteristics at different time scales, enabling us to understand the working states of each area more accurately. Next, the system performs local singular value decomposition (SVD) on the obtained set of power-temperature feature components to extract the basis vectors that can best reflect the essential connection between power consumption and temperature, forming a power-temperature basis vector matrix. This matrix not only contains the power-temperature mapping matrix of the computing unit, the power-temperature mapping coefficients of the storage unit, but also covers the power-temperature coupling factors of the on-chip bus. For example, in a high-performance server environment, when a certain computing unit generates a large amount of power consumption due to executing intensive tasks, the temperature nearby will also rise accordingly. Through local SVD, we can quantify this direct connection between power consumption and temperature, laying a foundation for more in-depth analysis in the follow-up. In addition, for the storage unit, frequent data read and write operations will lead to an increase in power consumption and also cause a temperature rise; for the on-chip bus, changes in data transfer rate and frequency will also affect its power consumption level and heat conduction efficiency. Then, based on the Hilbert-Huang transform (HHT), intrinsic mode decomposition (EMD) is performed on the power-temperature basis vector matrix. HHT is a method suitable for non-stationary signal processing. It can decompose the complex power-temperature basis vector matrix into a series of intrinsic mode functions (IMFs) with physical meanings, namely the so-called power-temperature intrinsic component sequence. These intrinsic component sequences reflect different oscillation modes of the evolution of power consumption and temperature over time. Further, by performing bispectral analysis on the power-temperature intrinsic component sequence, power-temperature cross-spectrum features can be obtained, including power-temperature oscillation period, power-temperature phase difference, and power-temperature amplitude ratio. For example, during the operation of a high-performance server, some periodic load changes may cause regular power consumption fluctuations in specific computing units or storage units, and correspondingly affect their temperature changes. Through bispectral analysis, we can discover this periodic and synchronous information hidden behind the data, which is crucial for understanding the relationship between power consumption and temperature.Subsequently, the preset local projection embedding algorithm is used to perform non-linear dynamic reconstruction on the power consumption-temperature cross-spectrum features, and the power consumption-temperature state space trajectory is constructed. This method can help us visually observe the evolution path of power consumption and temperature in the high-dimensional state space, revealing the complex non-linear interaction between the two. In a high-performance server environment, when multiple computing units work together, the power consumption and temperature interaction between them may form a complex dynamic pattern. Through the state space trajectory, we can track the development process of this dynamic pattern, providing a basis for further analysis. Based on the above power consumption-temperature state space trajectory, the system will perform time series correlation analysis to extract the power consumption-temperature coupling feature sequence. This sequence contains the correlation information between power consumption and temperature changing over time. Next, through transfer entropy calculation, a power consumption-temperature causal network can be constructed. Transfer entropy is a method to measure the direction and intensity of information flow between two random variables, and here it is used to evaluate the causal relationship between power consumption and temperature. For example, in a high-performance server, if the increase in the power consumption of a certain computing unit precedes the rise in the temperature of the adjacent area, it indicates that the former may be one of the reasons for the latter. By constructing the causal network, we can more clearly understand the causal link between power consumption and temperature. To further analyze the power consumption-temperature causal network, the system will perform community detection on this network to divide it into different power consumption-temperature coupling subgraph sets. Each subgraph represents a relatively independent power consumption-temperature coupling region. Through spectral clustering analysis of these subgraph sets, the power consumption-temperature correlation regions are finally obtained. These correlation regions include strong coupling region identifiers, weak coupling region boundaries, and critical coupling region characteristics. In the application of high-performance servers, this helps to identify which regions have the most significant mutual influence on power consumption and temperature, which regions have a weaker influence, and the regions with critical transition points. For example, there may be a strong power consumption-temperature coupling between a certain computing unit and its adjacent storage unit, while other components far away from it show a weaker coupling degree. Finally, based on recursive quantification analysis, dynamic features of the power consumption-temperature correlation regions are extracted to generate a power consumption-temperature time-varying feature set. This method can capture the trends and patterns of power consumption and temperature changing over time. Then, through tensor decomposition, the power consumption-temperature time-varying feature set can be comprehensively analyzed from a multi-dimensional perspective, and finally a power consumption-temperature correlation matrix is obtained. This matrix comprehensively describes the interaction relationship between power consumption and temperature among various parts inside the target chip, providing an important reference basis for optimization design, fault prediction, and performance improvement. For example, in a high-performance server, using the power consumption-temperature correlation matrix, engineers can formulate more effective heat dissipation strategies to ensure the stable operation of the system while minimizing energy consumption as much as possible. In summary, through the above series of steps, we can deeply explore the complex relationship between power consumption and temperature inside the target chip, not only revealing their associations in the static structure but also discovering their interactions in the dynamic behavior.This process provides strong scientific support for power consumption management, thermal design optimization, and reliability enhancement in high-performance servers and other similar application scenarios. In this way, we can maximize the energy efficiency ratio of the system without affecting normal operations, ensuring its long-term stable and reliable service for complex computing tasks.

[0104] In a specific embodiment, through the multi-objective optimization algorithm, based on the power consumption-temperature correlation matrix, power consumption management planning is performed on the target chip to obtain a dynamic power consumption management strategy, including:

[0105] Perform singular value decomposition on the power consumption-temperature correlation matrix to obtain a power consumption-temperature eigenvector set, and perform principal component analysis on the power consumption-temperature eigenvector set to obtain power consumption-temperature principal component features;

[0106] Optimize the power consumption-temperature principal component features through a multi-objective genetic algorithm to obtain a power consumption-temperature Pareto optimal solution set;

[0107] Construct a power consumption-temperature objective function for the target chip through the power consumption-temperature Pareto optimal solution set to obtain a multi-objective optimization function, and solve the multi-objective optimization function using the Lagrange multiplier method to obtain a Lagrange multiplier vector; where the Lagrange multiplier vector includes a power consumption weight coefficient, a temperature weight coefficient, and a performance weight coefficient;

[0108] Based on the Lagrange multiplier vector, perform dynamic power consumption budget allocation on the target chip to obtain a power consumption budget allocation plan, and optimize the power consumption budget allocation plan based on a game theory-based resource competition strategy to obtain a Nash equilibrium point; where the Nash equilibrium point includes a computing unit power consumption budget, a storage unit power consumption budget, and a communication unit power consumption budget;

[0109] Based on the Nash equilibrium point, perform power consumption management planning on the target chip to obtain a dynamic power consumption management strategy.

[0110] Specifically, in order to implement power consumption management planning for the target chip based on the power consumption-temperature correlation matrix and finally obtain a dynamic power management strategy, the whole process is a complex process that combines various advanced mathematical and optimization techniques. First, the system needs to perform singular value decomposition (SVD) on the power consumption-temperature correlation matrix. This process aims to extract the most essential relationship characteristics between power consumption and temperature, thereby obtaining a power consumption-temperature eigenvector set. In the application scenario of high-performance servers, this decomposition can help us identify which factors have the greatest impact on power consumption and temperature, and which interactions between regions are the most significant. For example, in a typical computing-in-memory chip, the operating states of different functional modules such as computing units, storage units, and on-chip buses will directly affect their power consumption and heat generation. Through singular value decomposition, we can reveal the characteristic changes at these different levels, enabling us to more accurately capture the power consumption and temperature patterns in each region. Next, perform principal component analysis (PCA) on the obtained power consumption-temperature eigenvector set to obtain the power consumption-temperature principal component characteristics. Principal component analysis is a dimensionality reduction technique that can reduce the data dimension while retaining the most information, allowing us to focus on the key factors that have the greatest impact on power consumption and temperature. Taking high-performance servers as an example, when a certain computing unit generates a large amount of power consumption due to executing intensive tasks, the temperature nearby will also increase. Through principal component analysis, we can quantify this direct relationship between power consumption and temperature and extract the most important several eigenvectors from it, providing a basis for further in-depth optimization. Then, the system uses the multi-objective genetic algorithm (MOGA) to optimize the power consumption-temperature principal component characteristics to obtain the power consumption-temperature Pareto optimal solution set. The multi-objective genetic algorithm is a search method that simulates natural selection and genetic mechanisms. It can simultaneously consider multiple conflicting objectives, such as power consumption minimization, temperature control, and performance maximization, to find a set of optimal solutions. In a high-performance server environment, this means that we need to minimize power consumption and maintain a safe operating temperature as much as possible while ensuring that the system performance is not affected. Through the multi-objective genetic algorithm, a series of possible solutions can be explored, and each solution finds the best balance point between power consumption, temperature, and performance, forming a Pareto optimal solution set. Based on the above power consumption-temperature Pareto optimal solution set, the system further constructs a power consumption-temperature objective function, that is, a multi-objective optimization function. This function comprehensively considers multiple objective variables such as power consumption, temperature, and performance, and reflects their importance by assigning different weight coefficients to these variables. Specifically, the Lagrange multiplier method is used to solve this multi-objective optimization function, and finally the Lagrange multiplier vector is obtained. This vector includes the power consumption weight coefficient, the temperature weight coefficient, and the performance weight coefficient, which determine the importance degree of each objective in the optimization process.For example, during the operation of a high-performance server, if the current task has high performance requirements, the performance weight coefficient can be appropriately increased; while when the load is light, more attention can be paid to power consumption and temperature control, and other weight coefficients can be adjusted accordingly. After obtaining the Lagrange multiplier vector, the system dynamically allocates the power consumption budget for the target chip according to its guidance, generating a power consumption budget allocation plan. This plan details the power consumption budgets of various parts such as the computing unit, storage unit, and communication unit. To ensure the effective utilization of resources, it is also necessary to optimize the power consumption budget allocation plan based on game theory's resource competition strategy to find the Nash equilibrium point. The Nash equilibrium point refers to a situation in a multi-player system where each player's strategy is the best response to the strategies of other players, and at this time, no party is willing to unilaterally change its strategy. In high-performance server applications, this means finding a resource allocation method that enables all computing units, storage units, and communication units to work efficiently within their power consumption budgets without performance degradation or overheating problems caused by resource contention. For example, the Nash equilibrium point optimized through game theory will indicate that certain computing units undertake more tasks within a specific time window, while allowing other areas to enter a low-power standby state, thus minimizing the overall energy consumption. Finally, based on the Nash equilibrium point, the system formulates a detailed power consumption management plan, forming a dynamic power consumption management strategy. This strategy not only takes into account the current task requirements but also considers the stability and reliability during long-term operation. For example, in a high-performance server, when it is detected that the temperature of certain areas rises too fast due to high-intensity operations, the dynamic power consumption management strategy may indicate appropriately reducing the operating frequency of these areas and fine-tuning the power supply voltage to ensure that the performance is not affected too much. At the same time, for relatively idle or low-load areas, the operating frequency can be appropriately increased to accelerate the completion of the remaining tasks, or the voltage can be reduced to save energy. In summary, through a series of steps such as singular value decomposition, principal component analysis, and multi-objective genetic algorithm optimization of the power consumption-temperature correlation matrix, we can not only reveal the complex relationship between power consumption and temperature inside the target chip but also formulate a scientific and reasonable dynamic power consumption management strategy on this basis. This method ensures that, without affecting normal operations, the energy efficiency ratio of the system is maximized, ensuring its long-term stable and reliable service for complex computing tasks. In this way, we can achieve a perfect balance between high performance and low power consumption in high-performance servers and other similar application scenarios, providing strong support for complex data centers. For example: Suppose in a high-performance server cluster, at a certain moment, multiple virtual machines are executing complex computing tasks, resulting in a sharp increase in the power consumption of some computing units and a corresponding increase in temperature. At this time, through the above power consumption-temperature correlation analysis and optimization process, the system can quickly identify which computing units are in a high-load state and adjust the operating frequency and power supply voltage of these units according to the pre-set power consumption-temperature Pareto optimal solution set.Meanwhile, the optimization of resource competition strategies based on game theory can help determine the optimal power consumption budget allocation for each computing unit, storage unit, and communication unit, ensuring the effective utilization of resources without causing overheating or other performance issues. The final dynamic power management strategy will ensure that the entire server cluster maintains a low power consumption level and a stable temperature distribution while meeting high-performance requirements, thereby extending the hardware lifespan and improving the overall efficiency of the system.

[0111] In a specific embodiment, the voltage-frequency regulation of the target chip based on the dynamic power management strategy to obtain voltage-frequency control parameters includes:

[0112] Performing cluster analysis on the power consumption characteristics of the target chip through the dynamic power management strategy to obtain a set of power consumption clusters, and performing principal component analysis on the set of power consumption clusters to obtain a power consumption feature vector; wherein, the power consumption feature vector includes the chip power consumption mean, power consumption variance, and power consumption peak feature parameters;

[0113] Performing voltage regulation analysis on the target chip based on the power consumption feature vector to obtain a voltage regulation scheme;

[0114] Performing frequency configuration analysis on the target chip through the voltage regulation scheme to obtain a frequency configuration scheme;

[0115] Performing power consumption allocation analysis on the target chip based on the frequency control parameters to obtain a power consumption allocation scheme, and optimizing the power consumption allocation scheme using the ant colony algorithm to obtain power consumption allocation parameters; wherein, the power consumption allocation parameters include the power consumption allocation ratio, power consumption allocation threshold, and power consumption allocation delay parameter;

[0116] Performing voltage-frequency regulation on the target chip through the power consumption allocation parameters to obtain a voltage-frequency control signal;

[0117] Performing voltage-frequency regulation on the target chip based on the voltage-frequency control signal to obtain voltage-frequency control parameters.

[0118] Specifically, in order to implement voltage-frequency regulation for the target chip based on the dynamic power management strategy and finally obtain the voltage-frequency control parameters, the whole process involves a series of complex data analysis and optimization steps. First of all, the system needs to perform cluster analysis on the power consumption characteristics of the target chip through the dynamic power management strategy to identify regions or operating modes with similar power consumption behaviors and form a set of power consumption clusters. This process is particularly important in a high-performance server environment because different computing tasks may cause significant differences in the power consumption of various parts inside the target chip. For example, when processing a large number of concurrent requests, some computing units may be in a high-load state while other parts are relatively idle. By performing cluster analysis on these power consumption characteristics, we can divide the chip into several power consumption clusters, and each cluster represents a group of regions or operating modes with similar power consumption characteristics. Next, perform principal component analysis (PCA) on the obtained set of power consumption clusters to extract the key feature vectors that can best reflect the power consumption changes. These power consumption feature vectors contain important parameters such as the mean power consumption, power consumption variance, and power consumption peak of the chip, which can help us understand the differences and internal connections between various power consumption clusters more deeply. For example, in a typical high-performance server application scenario, the mean power consumption of a certain computing unit is high and fluctuates greatly, which may mean that this unit undertakes more intensive computing tasks; while the power consumption peak of another storage unit is low but relatively stable, indicating that it is mainly responsible for data reading and writing operations. Through principal component analysis, we can quantify these characteristics and provide a scientific basis for subsequent voltage regulation. Based on the above power consumption feature vectors, the system further conducts voltage regulation analysis on the target chip to formulate a specific voltage regulation plan. This plan aims to reasonably adjust the supply voltage according to the current task requirements and power consumption characteristics to achieve the purpose of ensuring performance while reducing energy consumption. For example, during the operation of a high-performance server, if it is detected that the power consumption of a certain computing unit continues to increase, then its supply voltage can be appropriately increased to ensure sufficient processing power; on the contrary, for those regions with low power consumption or in an idle state, the voltage can be reduced to save power. This dynamic adjustment not only helps to optimize the instantaneous power consumption performance, but also extends the hardware life and reduces the heat dissipation pressure. After having the voltage regulation plan, the system continues to perform frequency configuration analysis on the target chip through the voltage regulation plan to generate a frequency configuration plan. The frequency configuration plan takes into account the working characteristics and task load conditions of different computing units and determines the optimal frequency at which each unit should operate. In a high-performance server environment, this means flexibly adjusting the working frequencies of various computing units according to the requirements of different computing tasks. For example, when some tasks require quick response, the relevant computing units may be set to a higher frequency to speed up the processing speed; while during periods with fewer tasks or non-critical periods, the frequency can be appropriately reduced to save energy.In addition, the frequency configuration also needs to be coordinated with the voltage regulation to ensure a good match between the two and avoid problems such as a sharp increase in power consumption or overheating due to too high a frequency. Based on the frequency control parameters, the system conducts a power consumption distribution analysis on the target chip to obtain a power consumption distribution plan. This plan details parameters such as the power consumption distribution ratio, threshold, and delay among the computing unit, storage unit, and other functional modules. To ensure the effective utilization of resources and achieve the optimal power consumption management effect, the system also uses the ant colony algorithm to optimize the power consumption distribution plan and obtains more refined power consumption distribution parameters. The ant colony algorithm is a heuristic search method that simulates the foraging behavior of ants in nature and can find the global optimal solution in a complex multi-dimensional space. In high-performance server applications, the ant colony algorithm can help us identify which areas have the most reasonable power consumption distribution and which areas have room for optimization. For example, the power consumption distribution plan optimized by the ant colony algorithm may indicate that certain computing units undertake more tasks within a specific time window, while allowing other areas to enter a low-power standby state, thereby minimizing the overall energy consumption. Finally, based on the optimized power consumption distribution parameters, the system adjusts the voltage and frequency of the target chip, generates a voltage-frequency control signal, and accordingly adjusts the actual voltage-frequency control parameters. This process ensures that all adjustment measures can be accurately applied to the target chip, enabling it to minimize power consumption and maintain a safe operating temperature while meeting performance requirements. For example, in a high-performance server, when it is detected that the temperature of certain areas rises too quickly due to high-intensity operations, the dynamic power management strategy will indicate an appropriate reduction in the operating frequency of these areas and fine-tune the supply voltage to ensure that the performance is not greatly affected. At the same time, for relatively idle or low-load areas, the operating frequency can be appropriately increased to accelerate the completion of the remaining tasks, or the voltage can be reduced to save energy. In summary, through a series of steps such as clustering analysis, principal component analysis, voltage regulation analysis, and frequency configuration analysis of the power consumption characteristics of the target chip, we can not only reveal the complex relationship between the internal power consumption and frequency of the chip, but also formulate a scientific and reasonable voltage-frequency regulation plan on this basis. This method ensures that the energy efficiency ratio of the system is maximized without affecting normal operations, ensuring its long-term stable and reliable service for complex computing tasks. In this way, we can achieve a perfect balance between high performance and low power consumption in high-performance servers and other similar application scenarios, providing strong support for complex data centers. For example: Suppose in a high-performance server cluster, at a certain moment, multiple virtual machines are performing complex computing tasks, resulting in a sharp increase in the power consumption of some computing units and a corresponding increase in temperature. At this time, through the above power consumption characteristic analysis and optimization process, the system can quickly identify which computing units are in a high-load state and adjust the operating frequency and supply voltage of these units according to the pre-set power consumption characteristic vector.Meanwhile, the power consumption allocation scheme optimized by the ant colony algorithm can help determine the optimal power consumption budget allocation for each computing unit, storage unit, and communication unit, ensuring the effective utilization of resources without causing overheating or other performance issues. The final voltage-frequency control parameters will ensure that the entire server cluster maintains a low power consumption level and a stable temperature distribution while meeting high-performance requirements, thereby extending the hardware lifespan and improving the overall efficiency of the system.

[0119] In a specific embodiment, through the adaptive clock gating technology, based on the voltage-frequency control parameters, power consumption management is performed on the target chip to obtain a chip power consumption management scheme, including:

[0120] Extract the timing characteristics of the voltage-frequency control parameters through the adaptive clock gating technology to obtain a clock adjustment scheme, and perform Fourier transform analysis on the clock adjustment scheme to obtain clock spectrum characteristics; among them, the clock spectrum characteristics include clock frequency components, clock phase offsets, and clock amplitude adjustment characteristic parameters;

[0121] Perform power consumption prediction analysis on the target chip based on the clock spectrum characteristics to obtain a power consumption prediction sequence; among them, the power consumption prediction sequence includes power consumption timing mean, power consumption fluctuation variance, and power consumption peak characteristic parameters;

[0122] Perform power consumption allocation planning on the target chip through the power consumption prediction sequence to obtain a power consumption allocation strategy, and perform parameter analysis on the power consumption allocation strategy to obtain power consumption allocation control parameters;

[0123] Perform dynamic voltage-frequency adjustment on the target chip based on the power consumption allocation control parameters to obtain a voltage-frequency configuration scheme, and perform instruction conversion on the voltage-frequency configuration scheme to obtain voltage-frequency control instructions;

[0124] Perform power consumption management on the target chip based on the voltage-frequency control instructions to obtain a chip power consumption management scheme.

[0125] Specifically, in order to achieve power consumption management of the target chip through adaptive clock gating technology and ultimately obtain a chip power consumption management solution, the whole process is a complex process that combines multiple advanced technologies and algorithms. First of all, the system needs to use adaptive clock gating technology to extract the timing characteristics of the voltage-frequency control parameters, so as to formulate a clock adjustment plan. This process aims to capture the changing rules of the clock signal of the target chip in different working states, including its frequency, phase and amplitude characteristics. For example, in a high-performance server environment, when the integrated memory and computing chip processes a large number of concurrent requests, some computing units may be in a high-load state, while other parts are relatively idle. By extracting the timing characteristics of the voltage-frequency control parameters in these areas, we can identify which computing units have more frequent working modes and which are relatively stable. Based on this information, the system can generate a specific clock adjustment plan to ensure that each computing unit is only activated when it is really needed, reducing unnecessary static power consumption. Next, in order to understand the frequency-domain characteristics of the clock signal more deeply, the system will perform Fourier transform analysis on the formulated clock adjustment plan to obtain the clock spectrum characteristics. This step can reveal the frequency components, phase offsets and amplitude adjustment characteristic parameters in the clock signal, helping us better understand the relationship between clock behavior and power consumption. For example, in a high-performance server, if a computing unit frequently switches its working state, its clock signal may show significant harmonic components or phase fluctuations. Through Fourier transform analysis, we can quantify these characteristics, providing an important basis for subsequent power consumption prediction. In addition, this frequency-domain analysis can also help identify potential instability factors, such as clock jitter or noise interference, and take measures to eliminate them in advance. Based on the above clock spectrum characteristics, the system further conducts power consumption prediction analysis on the target chip to obtain a power consumption prediction sequence. This sequence contains characteristic parameters such as the power consumption timing mean, power consumption fluctuation variance and power consumption peak value, which reflect the power consumption change trend of the target chip in the future for a period of time. In the application scenario of high-performance servers, this prediction analysis is crucial for optimizing resource allocation and preventing overheating. For example, if it is found according to the power consumption prediction that a certain computing unit is about to enter a high-load state, then the system can appropriately adjust its supply voltage and working frequency before the task starts to ensure that the performance is not affected while minimizing the power consumption. At the same time, for those areas that are expected to remain in a low-load or idle state, they can enter the low-power standby mode in advance to save power. After obtaining the power consumption prediction sequence, the system will perform power consumption allocation planning on it to formulate a specific power consumption allocation strategy. This strategy details the power consumption allocation ratio, threshold and delay and other parameters among various computing units, storage units and other functional modules. In order to ensure the effective utilization of resources and achieve the optimal power consumption management effect, the system also needs to perform parameter parsing on the power consumption allocation strategy to obtain more refined power consumption allocation control parameters.For example, in a high-performance server, the power consumption allocation control parameters may indicate that certain computing units undertake more tasks within a specific time window, while putting other areas into a low-power standby state, thereby minimizing the overall energy consumption. In addition, these control parameters may also include some forward-looking indicators, such as predicting future load trends and corresponding power consumption changes, making preparations in advance to avoid unnecessary high-power consumption periods. Based on the power consumption allocation control parameters, the system dynamically adjusts the voltage and frequency of the target chip to generate a voltage-frequency configuration scheme. This scheme comprehensively considers the current task requirements, power consumption prediction results, and power consumption allocation strategy, and determines the optimal operating voltage and frequency for each computing unit. To ensure that all adjustment measures can be accurately applied to the target chip, the system also needs to convert the voltage-frequency configuration scheme into instructions to obtain specific voltage-frequency control instructions. These instructions will directly guide the operations at the hardware level to ensure that each computing unit can operate under the most suitable conditions. For example, in a high-performance server, when it is detected that the temperature of certain areas rises too fast due to high-intensity operations, the dynamic power management strategy will instruct to appropriately reduce the operating frequency of these areas and fine-tune the supply voltage to ensure that the performance is not affected too much. At the same time, for relatively idle or low-load areas, the operating frequency can be appropriately increased to accelerate the completion of the remaining tasks, or the voltage can be reduced to save energy. Finally, based on the voltage-frequency control instructions, the system conducts power consumption management on the target chip to form a complete chip power consumption management scheme. This scheme not only covers the whole process from clock signal adjustment to dynamic voltage-frequency adjustment, but also ensures that all operations are carried out without affecting normal operations, maximizing the energy efficiency ratio of the system. For example, in a high-performance server, through this refined power consumption management, not only can the overall energy consumption be effectively reduced, but also the reliability and stability of the system can be significantly improved, the hardware life can be extended, and the heat dissipation pressure can be reduced. To sum up, through a series of steps such as adaptive clock gating technology, timing feature extraction, and Fourier transform analysis, we can not only reveal the complex relationship between the internal power consumption and frequency of the target chip, but also formulate a scientific and reasonable power consumption management scheme on this basis. This method ensures the perfect balance between high performance and low power consumption in high-performance servers and other similar application scenarios, providing strong guarantee for complex data centers. For example: Suppose in a high-performance server cluster, at a certain moment, multiple virtual machines are performing complex computing tasks, resulting in a sharp increase in the power consumption of some computing units and a corresponding rise in temperature. At this time, through the above-mentioned clock gating technology and frequency-domain analysis, the system can quickly identify which computing units are in a high-load state and adjust the clock signal frequency and phase of these units according to the pre-set clock spectrum characteristics. At the same time, based on the results of power consumption prediction analysis, the system can plan the power consumption allocation strategy in advance to ensure the effective utilization of resources without causing overheating or other performance problems.The finally formed voltage-frequency control instruction will ensure that the entire server cluster maintains a low power consumption level and a stable temperature distribution while meeting high-performance requirements, thereby extending the hardware lifespan and improving the overall efficiency of the system. For example, for those computing units that are expected to continue working under high load, the system may maintain a high operating frequency and supply voltage; while for areas that are about to enter the idle state, the frequency and voltage can be quickly reduced to enter the low-power mode to save energy.

[0126] The dynamic power consumption management method of the in-memory computing integrated chip in the embodiment of the present invention has been described above. Next, the dynamic power consumption management device of the in-memory computing integrated chip in the embodiment of the present invention will be described. Please refer to Figure 2 One embodiment of the dynamic power consumption management device of the in-memory computing integrated chip in the embodiment of the present invention includes:

[0127] The first acquisition module 21 is used to collect real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution map of the target chip; wherein, the in-memory computing integrated chip is used as the target chip;

[0128] The second acquisition module 22 is used to collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution map of the target chip;

[0129] The analysis module 23 is used to perform power consumption-temperature correlation analysis on the target chip based on the power consumption distribution map of the target chip and the temperature distribution map of the target chip to obtain a power consumption-temperature correlation matrix;

[0130] The generation module 24 is used to perform power consumption management planning on the target chip based on the power consumption-temperature correlation matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy;

[0131] The adjustment module 25 is used to adjust the voltage and frequency of the target chip based on the dynamic power consumption management strategy to obtain voltage-frequency control parameters;

[0132] The management module 26 is used to perform power consumption management on the target chip based on the voltage-frequency control parameters through an adaptive clock gating technology to obtain a chip power consumption management scheme.

[0133] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to that described in the above method embodiment, and details will not be repeated here.

[0134] Refer to Figure 3 In the embodiment of the present invention, a computer device is further provided. The internal structure of the computer device can be as Figure 3As shown in the figure. The computer device includes a processor, a memory, a display screen, an input device, a network interface, and a database connected through a system bus. Among them, the processor of the computer design is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0135] Those skilled in the art can understand that Figure 3 the structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0136] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0137] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium provided by the present invention and used in the embodiments can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or an external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM, etc.

[0138] It should be noted that in this text, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article or method comprising a series of elements not only includes those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article or method. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, apparatus, article or method comprising such element.

[0139] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A dynamic power consumption management method for a storage and computing integrated chip, characterized in that: The following steps are involved: The power consumption data of the target chip is collected in real time through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; Collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; Performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power consumption-temperature correlation matrix; By using a multi-objective optimization algorithm, power consumption management planning is performed on the target chip based on the power consumption-temperature association matrix to obtain a dynamic power consumption management strategy; Based on the dynamic power management strategy, the voltage and frequency of the target chip are adjusted to obtain voltage and frequency control parameters; By using an adaptive clock gating technology, power consumption management is performed on the target chip based on the voltage and frequency control parameters to obtain a chip power consumption management solution; The real-time power consumption data of the target chip is collected by a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip, including: The power consumption of the target chip is scanned and collected through a preset on-chip sensor array to obtain a power consumption feature set of the target chip; The target chip power consumption characteristic set is analyzed in the time domain by a preset piecewise linear interpolation algorithm to obtain power consumption timing characteristic data; wherein the power consumption timing characteristic data includes power consumption fluctuation period, power consumption peak moment and power consumption valley interval; Performing instantaneous frequency analysis on the power consumption timing characteristic data to obtain a power consumption spectrum distribution diagram; wherein the power consumption spectrum distribution diagram includes main frequency component characteristics, harmonic component characteristics, and mixed frequency component characteristics; Based on the Wigner-Ville distribution algorithm, a time-frequency joint analysis is performed on the power consumption spectrum distribution diagram to obtain the power consumption time-frequency characteristics; wherein the power consumption time-frequency characteristics include the power consumption frequency migration trajectory, the power consumption energy concentration area, and the power consumption transient mutation point; Through the conditional entropy estimation algorithm, the target chip is spatially mapped based on the power consumption time-frequency characteristics to obtain a target chip power consumption distribution map; wherein the target chip power consumption distribution map includes a high power consumption area location map, power consumption density contour lines, and a power consumption change trend map.

2. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The step of collecting temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip includes: Real-time temperature data collection is performed on the target chip through a preset temperature sensor network to obtain a temperature sampling data set of the target chip; wherein the temperature sampling data set includes a temperature value, a timestamp, and a position coordinate of each sensor in the temperature sensor network; Performing noise filtering and data fusion on the temperature sampling data set to obtain a denoised temperature data sequence; Based on the finite element analysis method, the temperature field is reconstructed based on the denoised temperature data sequence to obtain a three-dimensional temperature field distribution of the target chip; wherein the three-dimensional temperature field distribution includes the temperature value of each point inside the target chip and the temperature gradient information; Performing hot spot identification on the three-dimensional temperature field distribution to obtain a hot spot distribution map of the target chip; wherein the hot spot distribution map includes a hot spot position, a hot spot temperature peak, and a hot spot area; The heat source power is estimated by using a reverse heat transfer analysis method on the hot spot area distribution map of the target chip to obtain the heat source power distribution data of the target chip; wherein the heat source power distribution data includes the power value and power density of each hot spot area; A temperature distribution map is generated based on the heat source power distribution data to obtain a target chip temperature distribution map; wherein the target chip temperature distribution map includes the temperature value of each computing unit and storage unit in the target chip, and is visually presented in the form of a color heat map.

3. The dynamic power consumption management method of the storage and computing integrated chip according to claim 1, characterized in that: The performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution map and the target chip temperature distribution map to obtain a power consumption-temperature correlation matrix includes: Perform multi-scale decomposition on the target chip power consumption distribution map and the temperature distribution map through adaptive wavelet transform to obtain a power consumption-temperature feature component set, and perform local singular value decomposition on the power consumption-temperature feature component set to obtain a power consumption-temperature basis vector matrix; wherein the power consumption-temperature basis vector matrix includes a computing unit power consumption-temperature mapping matrix, a storage unit power consumption-temperature mapping coefficient, and an on-chip bus power consumption-temperature coupling factor; Based on the Hilbert-Huang transform, the power consumption-temperature basis vector matrix is ​​subjected to intrinsic mode decomposition to obtain a power consumption-temperature intrinsic component sequence, and a bispectral analysis is performed on the power consumption-temperature intrinsic component sequence to obtain a power consumption-temperature cross-spectral feature; wherein the power consumption-temperature cross-spectral feature includes a power consumption-temperature oscillation period, a power consumption-temperature phase difference, and a power consumption-temperature amplitude ratio; The power consumption-temperature cross-spectral characteristics are nonlinearly reconstructed by a preset local projection embedding algorithm to obtain a power consumption-temperature state space trajectory; Performing a time series correlation analysis based on the power consumption-temperature state space trajectory to obtain a power consumption-temperature coupling feature sequence, and performing transfer entropy calculation on the power consumption-temperature coupling feature sequence to obtain a power consumption-temperature causal network; Perform community detection on the power consumption-temperature causal network to obtain a power consumption-temperature coupling subgraph set, and perform spectral clustering analysis on the power consumption-temperature coupling subgraph set to obtain a power consumption-temperature associated region; wherein the power consumption-temperature associated region includes a strong coupling region identifier, a weak coupling region boundary, and a critical coupling region feature; Based on recursive quantization analysis, dynamic feature extraction is performed on the power consumption-temperature association region to obtain a power consumption-temperature time-varying feature set, and tensor decomposition is performed on the power consumption-temperature time-varying feature set to obtain a power consumption-temperature association matrix.

4. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The method of performing power consumption management planning on the target chip based on the power consumption-temperature association matrix by using a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy includes: Performing singular value decomposition on the power consumption-temperature association matrix to obtain a power consumption-temperature feature vector set, and performing principal component analysis on the power consumption-temperature feature vector set to obtain power consumption-temperature principal component features; The power consumption-temperature principal component characteristics are optimized by a multi-objective genetic algorithm to obtain a power consumption-temperature Pareto optimal solution set; The power consumption-temperature objective function of the target chip is constructed by using the power consumption-temperature Pareto optimal solution set to obtain a multi-objective optimization function, and the multi-objective optimization function is solved by the Lagrange multiplier method to obtain a Lagrange multiplier vector; wherein the Lagrange multiplier vector includes a power consumption weight coefficient, a temperature weight coefficient, and a performance weight coefficient; Dynamically allocate power consumption budget to the target chip based on the Lagrange multiplier vector to obtain a power consumption budget allocation scheme, and optimize the power consumption budget allocation scheme based on game theory to obtain a Nash equilibrium point; wherein the Nash equilibrium point includes a computing unit power consumption budget, a storage unit power consumption budget, and a communication unit power consumption budget; Power consumption management planning is performed on the target chip based on the Nash equilibrium point to obtain a dynamic power consumption management strategy.

5. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The step of adjusting the voltage and frequency of the target chip based on the dynamic power management strategy to obtain voltage and frequency control parameters includes: Performing cluster analysis on the power consumption characteristics of the target chip through a dynamic power consumption management strategy to obtain a power consumption cluster set, and performing principal component analysis on the power consumption cluster set to obtain a power consumption feature vector; wherein the power consumption feature vector includes chip power consumption mean, power consumption variance, and power consumption peak feature parameters; Performing voltage regulation analysis on the target chip based on the power consumption characteristic vector to obtain a voltage regulation solution; Performing frequency configuration analysis on the target chip through the voltage regulation scheme to obtain a frequency configuration scheme; Based on the frequency control parameters, the target chip is subjected to power consumption allocation analysis to obtain a power consumption allocation scheme, and the power consumption allocation scheme is optimized by an ant colony algorithm to obtain power consumption allocation parameters; wherein the power consumption allocation parameters include a power consumption allocation ratio, a power consumption allocation threshold, and a power consumption allocation delay parameter; The voltage and frequency of the target chip are adjusted according to the power consumption allocation parameter to obtain a voltage and frequency control signal; The voltage and frequency of the target chip are adjusted based on the voltage and frequency control signal to obtain voltage and frequency control parameters.

6. The method for dynamic power consumption management of a storage and computing integrated chip according to claim 1, characterized in that: The method of performing power consumption management on the target chip based on the voltage and frequency control parameters by using the adaptive clock gating technology to obtain a chip power consumption management solution includes: Extracting the timing characteristics of the voltage frequency control parameters through the adaptive clock gating technology to obtain a clock adjustment scheme, and performing Fourier transform analysis on the clock adjustment scheme to obtain clock spectrum characteristics; wherein the clock spectrum characteristics include clock frequency components, clock phase offsets, and clock amplitude adjustment characteristic parameters; Based on the clock spectrum characteristics, the target chip is subjected to power consumption prediction analysis to obtain a power consumption prediction sequence; wherein the power consumption prediction sequence includes a power consumption timing mean, a power consumption fluctuation variance, and a power consumption peak characteristic parameter; Performing power consumption allocation planning on the target chip through the power consumption prediction sequence to obtain a power consumption allocation strategy, and performing parameter analysis on the power consumption allocation strategy to obtain a power consumption allocation control parameter; Dynamically adjusting the voltage and frequency of the target chip based on the power consumption allocation control parameter to obtain a voltage and frequency configuration scheme, and converting the voltage and frequency configuration scheme into an instruction to obtain a voltage and frequency control instruction; Power consumption management is performed on the target chip based on the voltage and frequency control instruction to obtain a chip power consumption management solution.

7. A dynamic power consumption management device for a storage and computing integrated chip, characterized in that: include: The first acquisition module is used to collect real-time power consumption data of the target chip through a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip; wherein the storage and computing integrated chip is used as the target chip; A second acquisition module is used to collect temperature data of the target chip through a temperature sensor network to obtain a temperature distribution diagram of the target chip; An analysis module, configured to perform a power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram, and obtain a power consumption-temperature correlation matrix; A generation module, used to perform power management planning on the target chip based on the power consumption-temperature association matrix through a multi-objective optimization algorithm to obtain a dynamic power consumption management strategy; An adjustment module, used to adjust the voltage and frequency of the target chip based on the dynamic power management strategy to obtain voltage and frequency control parameters; A management module, configured to perform power consumption management on the target chip based on the voltage and frequency control parameters by using an adaptive clock gating technology to obtain a chip power consumption management solution; The real-time power consumption data of the target chip is collected by a preset on-chip sensor array to obtain a power consumption distribution diagram of the target chip, including: The power consumption of the target chip is scanned and collected through a preset on-chip sensor array to obtain a power consumption feature set of the target chip; The target chip power consumption characteristic set is analyzed in the time domain by a preset piecewise linear interpolation algorithm to obtain power consumption timing characteristic data; wherein the power consumption timing characteristic data includes power consumption fluctuation period, power consumption peak moment and power consumption valley interval; Performing instantaneous frequency analysis on the power consumption timing characteristic data to obtain a power consumption spectrum distribution diagram; wherein the power consumption spectrum distribution diagram includes main frequency component characteristics, harmonic component characteristics, and mixed frequency component characteristics; Based on the Wigner-Ville distribution algorithm, a time-frequency joint analysis is performed on the power consumption spectrum distribution diagram to obtain the power consumption time-frequency characteristics; wherein the power consumption time-frequency characteristics include the power consumption frequency migration trajectory, the power consumption energy concentration area, and the power consumption transient mutation point; Through the conditional entropy estimation algorithm, the target chip is spatially mapped based on the power consumption time-frequency characteristics to obtain a target chip power consumption distribution map; wherein the target chip power consumption distribution map includes a high power consumption area location map, power consumption density contour lines, and a power consumption change trend map.

8. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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