Instruction execution methods, electronic devices and readable media

Abstract

This application provides an instruction execution method, an electronic device, and a readable medium. The method includes: a processor detecting a first instruction; the processor determining that a first entry exists in a branch prediction structure, wherein the value bundle corresponding to the first entry is a first value bundle to which the first instruction belongs, the position field of the first entry matches a first position value in the instruction pointer of the first instruction, and the first position value indicates the position of the first instruction within its first value bundle; and jumping to a first address, where the first address is the target address in the target address field of the first entry corresponding to the first position value. In this embodiment, the branch prediction structure can record the position information of a branch instruction within its value bundle. By using the branch prediction structure to predict jump information for different branch instructions individually, prediction accuracy can be improved.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to an instruction execution method, an electronic device, and a readable medium. Background Technology

[0002] In modern computer architectures, branch instruction predictors are crucial for improving processor performance. Because processors process instructions sequentially, when a branch instruction is encountered, the processor needs the branch instruction predictor to predict the execution state of the branch (i.e., whether the branch instruction will jump and to which new address the program will jump to continue execution) in order to continue executing the next instruction in the pipeline. However, if the branch instruction predictor makes an error, the processor may need to flush the pipeline and reload the instructions, which can lead to performance penalties. Summary of the Invention

[0003] This application provides an instruction execution method, an electronic device, and a readable medium.

[0004] In a first aspect, embodiments of this application provide an instruction execution method applied to an electronic device. The processor of the electronic device stores a branch prediction structure, which includes multiple entries. Each entry corresponds to at least a portion of branch instructions in a value bundle. Each entry includes a position field and a target address field. The position field includes a position value that corresponds one-to-one with at least a portion of the branch instructions in the corresponding value bundle, and the target address field includes a target address that corresponds one-to-one with at least a portion of the branch instructions in the corresponding value bundle. The position value indicates the position of the corresponding branch instruction within its value bundle, and the target address indicates the address to which the corresponding branch instruction jumps. The method includes: the processor detecting a first instruction; the processor determining that a first entry exists in the branch prediction structure, wherein the value bundle corresponding to the first entry is the first value bundle to which the first instruction belongs, the position field of the first entry matches a first position value in the instruction pointer of the first instruction, and the first position value indicates the position of the first instruction within its first value bundle; and jumping to a first address, where the first address is the target address in the target address field of the first entry that corresponds to the first position value.

[0005] The branch prediction structure can be a branch target buffer (BTB), and the execution pointer can be a program counter (PC) value. At least some branch instructions in the fetch bundle can be a single branch instruction, or all branch instructions in the fetch bundle.

[0006] In this embodiment of the application, the branch prediction structure can record the position information of the branch instruction in its respective value bundle, distinguish different branch instructions in the value bundle, and improve the prediction accuracy by using the branch prediction structure to predict the jump information of different branch instructions separately.

[0007] In one possible implementation of the first aspect above, each entry further includes a predictive execution field, which includes a jump count value that corresponds one-to-one with at least a portion of the branch instructions in the corresponding value bundle. The jump count value is used to indicate the number of historical jumps of the corresponding branch instruction. Jumping to the first address includes: jumping to the first address when the predictive execution field of the first entry indicates a branch instruction jump, wherein the predictive execution field indicates a corresponding branch instruction jump when the jump count value is greater than a threshold or the jump count value is a preset value.

[0008] In one possible implementation of the first aspect described above, the first location value and the first address are stored in the branch prediction structure when the processor history detects a jump to the first instruction.

[0009] In one possible implementation of the first aspect described above, each entry further includes a tag field and an index field. The tag field includes a tag value that corresponds one-to-one with the value bundle corresponding to the branch instruction. Each entry in the branch prediction structure corresponds to an index value. The tag value is the first to the nth bit from high to low in the instruction pointer of the branch instruction. The index value is the (n+1)th to the (n+k)th bit from high to low in the instruction pointer of the branch instruction. The position value is the (n+k+1)th to the (n+k+m)th bit from high to low in the instruction pointer of the branch instruction.

[0010] In one possible implementation of the first aspect described above, the processor stores the first address and the first position value in the branch prediction structure in the following manner: detecting a first instruction jump to the first address; corresponding to the existence of a second entry in the branch prediction structure corresponding to the first value bundle and the position field of the second entry including the first position value, updating the third address in the target address field of the second entry corresponding to the first position value to the first address, thus obtaining the first entry; or corresponding to the existence of a second entry in the branch prediction structure corresponding to the first value bundle and the position field of the second entry not including the first position value, writing the first address into the target address field of the second entry and writing the first position value into the position field of the second entry, thus obtaining the first entry; or corresponding to the absence of an entry in the branch prediction structure corresponding to the first value bundle, adding a first entry corresponding to the first value bundle in the branch prediction structure, writing the first address into the target address field of the first entry and writing the first position value into the position field of the first entry, wherein the tag field of the first entry is the 1st to the nth bit from high to low in the execution pointer of the first instruction, and the index value of the first entry is the (n+1)th to the (n+k)th bit from high to low in the execution pointer of the first instruction.

[0011] In one possible implementation of the first aspect above, the processor stores the first address and the first position value in the branch prediction structure in the following manner: a first instruction is detected to jump to the first address; corresponding to the existence of a second entry in the branch prediction structure corresponding to the first instruction, and the position field of the second entry is the first position value, the third address in the target address field of the second entry corresponding to the first position value is updated to the first address, thus obtaining the first entry; or corresponding to the absence of an entry matching the first instruction in the branch prediction structure, a first entry corresponding to the first instruction is added to the branch prediction structure, the first address is written into the target address field of the first entry, the first position value is written into the position field of the first entry, and the tag field of the first entry is the 1st to the nth bit from high to low in the execution pointer of the first instruction, wherein the index value of the first entry is the (n+1)th to the (n+k)th bit from high to low in the execution pointer of the first instruction.

[0012] In one possible implementation of the first aspect described above, the first to nth bits of the instruction pointer of the first instruction from high to low are the same as the first tag value of the tag field in the first entry; the (n+1)th to (n+k)th bits of the instruction pointer of the first instruction from high to low are the same as the first index value corresponding to the first entry; the (n+k+1)th to (n+k+m)th bits of the instruction pointer of the first instruction from high to low are the same as the first tag value of the tag field in the first entry; the index value is the (n+1)th to (n+k)th bits of the instruction pointer of the branch instruction from high to low; and the position value is the (n+k+1)th to (n+k+m)th bits of the instruction pointer of the branch instruction from high to low.

[0013] In one possible implementation of the first aspect above, jumping to the first address includes: incrementing the jump count value in the prediction execution field of the first entry, and then jumping to the first address.

[0014] Secondly, embodiments of this application provide an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device; and a processor, one of the processors of the electronic device, for running instructions to enable the electronic device to implement the above-described instruction execution method.

[0015] Thirdly, embodiments of this application provide a readable medium containing instructions that, when executed by the processor of an electronic device, enable the electronic device to implement the aforementioned instruction execution method. Attached Figure Description

[0016] Figure 1 A schematic diagram of the structure of a branch instruction predictor (BHR) and PHT is shown according to one embodiment;

[0017] Figure 2 A schematic diagram of the structure of a branch instruction predictor (BTB) is shown according to one embodiment;

[0018] Figure 3 A first structural schematic diagram of an incremental BTB is shown according to an embodiment of this application;

[0019] Figure 4 A schematic diagram of a second structure of an incremental BTB is shown according to an embodiment of this application;

[0020] Figure 5 A schematic diagram of a third structure for an incremental BTB is shown according to an embodiment of this application;

[0021] Figure 6 A schematic diagram of a fourth structure of an incremental BTB is shown according to an embodiment of this application;

[0022] Figure 7 An exemplary flow of a method for updating a branch prediction structure is shown according to an embodiment of this application;

[0023] Figure 8 An exemplary flow of an instruction execution method is shown according to an embodiment of this application;

[0024] Figure 9 A schematic diagram of the structure of an electronic device 100 is shown according to an embodiment of this application. Detailed Implementation

[0025] The illustrative embodiments of this application include, but are not limited to, instruction execution methods, readable electronic devices, and readable media.

[0026] For ease of understanding, the terminology used in the embodiments of this application will be introduced below.

[0027] Branch instructions: Instructions used in computer programs to change the execution flow. They tell the processor to jump to a different program address to continue execution when a specific condition is met.

[0028] Branch instruction predictor: A component of the CPU used to predict the outcome of a branch before executing it. A branch instruction predictor includes at least a history register, a pattern history table (PHT), and a branch target buffer (BTB). Branch instruction predictors can be used in various scenarios, such as determining which pixels to render or omit in rendering, deciding which encoding / decoding method to use in video processing, and predicting user actions in user interaction, etc.

[0029] History registers: For example, a history register can be a branch history register (BHR), with an n-bit width, used to record the execution results of the n most recent branch instructions in the program. Each bit in the branch history register corresponds to one branch instruction execution; if the branch instruction resulted in a jump, it is recorded as 1; otherwise, it is recorded as 0. It can be understood that a branch instruction jump means that after the branch instruction is executed, the processor jumps to a different program address to continue execution.

[0030] PHT: PHT is used to predict the direction of branch instructions, that is, to predict whether a branch will occur. It dynamically adjusts its prediction strategy by recording the historical behavior of branch instructions. PHT can capture the past behavior patterns of branch instructions and predict future branch paths based on these patterns. For example, if a branch instruction has caused a jump multiple times in the past, PHT will record the jump history and predict that the branch will also cause a jump in the future.

[0031] BTB (Branch Target Address): The BTB is used to predict the target address of branch instructions, that is, where the program should jump to continue execution if a branch occurs. The BTB stores the addresses of branch instructions and their target addresses. When the processor detects a branch instruction, it can retrieve the BTB to determine the target address of the branch instruction. The address of the branch instruction refers to its storage location within the program; the target address of the branch instruction refers to the address the program should jump to if the branch instruction is predicted or determined to be executed—that is, the address of the next branch instruction to be executed. For example, when a branch instruction is executed for the first time, the processor can store its target address and store it in the corresponding entry in the BTB.

[0032] The following is based on Figure 1This paper introduces an example of predicting whether a branch instruction will jump based on the historical execution state of a branch instruction before it, using BHR and PHT.

[0033] Figure 1 A schematic diagram of the structure of the BHR and PHT of a branch instruction predictor is shown according to one embodiment.

[0034] according to Figure 1 As shown, the BHR stores the execution status of the six most recent historical branch instructions, i.e., "111010". According to some embodiments, "1" in the BHR indicates that a branch jump (taken), and "0" in the BRT indicates that the branch instruction did not jump (not taken). For example, "111010" means that the execution status of the six most recent historical branch instructions were jump, jump, jump, no jump, jump, no jump.

[0035] The PHT stores prediction information associated with the execution results of specific historical branch instructions. Different prediction information can indicate whether the next branch instruction will jump or not. It can be understood that the next branch instruction is the 7th branch instruction after the last 6 historical branch instructions. According to some embodiments, prediction information of "00" and "01" in the PHT indicates that the branch instruction will not jump, while prediction information of "10" and "11" indicates that the branch instruction will jump.

[0036] The PHT predicts whether a branch instruction will jump or not based on the "111010" sequence in the BHR. The results of the six most recent branch instruction executions, stored in the BHR, with the sequence "111010", can be used as an index. The PHT searches for the index corresponding to "111010" in the PHT to obtain the prediction information for the next branch instruction. For example, refer to... Figure 1 According to the historical branch instruction execution result "111010" in BRT, the prediction information corresponding to index "111010" in PHT is "10", indicating that the prediction information for the next branch instruction is a jump.

[0037] However, in some processor designs, such as superscalar processors, multiple instructions may be combined into a fetch bundle or a set of instructions. A fetch bundle can be understood as a collection of multiple instructions fetched by the processor from instruction memory at one time, which can be processed in parallel or serially. Within the same fetch bundle, the program counter (PC) value of each instruction has the same tag value from the first to the nth bit (from high to low), the same index value from the (n+1)th to the (n+k)th bit, and different values ​​for the (n+k+1)th bit and beyond. Instructions in a fetch bundle can include various types of instructions, such as branch instructions, arithmetic logic instructions, load / store instructions, and data transfer instructions. In some embodiments, before the processor executes the operation corresponding to the instruction, the processor can parse the instruction, obtain the corresponding opcode, and determine the type of instruction based on the opcode. For example, the instruction may be determined to be a branch instruction based on its opcode.

[0038] In superscalar processors, if through Figure 1 The BHR and PHT in the table are used to predict instruction jumps, and the prediction is done on a per-fetch basis. Each bit in the BHR corresponds to the execution status of a per-fetch. Whenever a per-fetch contains at least one branch instruction that jumps, the corresponding bit in the BHR table is updated to "1". If the next instruction to be executed is a per-fetch, the prediction information in the PHT table is updated accordingly. Figure 1 The "10" in the PHT shown corresponds to a value bundle. In this case, multiple branch instructions within that value bundle share a single prediction information within the PHT. When executing any branch instruction within that value bundle, the processor uses the same prediction information from the PHT to determine whether the branch instruction should jump. That is, even if the instruction executed by the processor is one whose historical execution state is non-jumping within the value bundle, if there are other instructions in the value bundle whose historical execution state is jumping, then for those instructions whose historical execution state is non-jumping, the prediction information obtained from the PHT will indicate a jump, leading to a prediction error.

[0039] Therefore, if a value bundle includes multiple branch instructions, since the BHR or PHT cannot record the information of each branch instruction in the value bundle individually, when using PHT to perform branch prediction based on the BHR, a single branch instruction in the value bundle cannot be predicted independently, thus reducing the prediction accuracy. In addition to the above... Figure 1 In addition to the scenario shown, in some embodiments, the BTB target address prediction method also suffers from low accuracy during the operation of a superscalar processor.

[0040] The following is based on Figure 2 This paper introduces an example of predicting the target address of a branch instruction based on its PC value using BTB.

[0041] It's understandable that for a branch instruction, if the prediction result using BHR and PHT indicates a jump, then the target address predicted using BTB is the jump address for that branch instruction. Conversely, if the prediction result using BHR and PHT indicates no jump, then the target address predicted using BTB is ineffective.

[0042] Figure 2 A schematic diagram of the structure of a branch instruction predictor (BTB) is shown according to one embodiment.

[0043] according to Figure 2 As shown, the BTB includes multiple entries, each corresponding to an index. Each entry includes a tag field, a valid field, and a target address field. The tag field provides the tag information and records the high-order bits of the program counter (PC) value of the branch instruction. The valid field indicates whether the corresponding entry is valid, and the target field records the jump address of the branch instruction.

[0044] In some embodiments, the PC value serves as an instruction pointer, informing the processor which instruction to execute next. After each instruction is executed, the PC value can be updated to point to the address of the next instruction. For example, during the execution of a branch instruction, the PC value can be updated to point to the target address corresponding to the branch instruction, instructing the processor to read from and execute the next instruction from that target address.

[0045] For a branch instruction, the PC value can include N bits of data. This multi-bit data can be divided into a tag value, an index value, and other values ​​based on the high and low bits. The tag value is n bits, and the index value can be up to 4 bits. The index value and tag value are used together to determine the entry corresponding to the branch instruction in the BTB. For example, refer to... Figure 2 The highest n bits of the PC value can be the tag value, and the next 4 bits can be the index value. When a branch instruction is detected, the processor can use the index value as an index to find an entry in the BTB whose index field content matches that index value, and verify if the tag field content of that entry is the same as the tag value. If they are the same, the entry is determined to be the entry corresponding to the branch instruction. Then, if the valid field in the entry indicates that the entry is valid, the address in the target field of that entry is determined as the target address of the predicted branch instruction. For example, if the valid field is "1" indicating validity and "0" indicating invalidity, then if the valid field is "1", the address in the target field is determined as the target address.

[0046] However, because multiple instructions within a value bundle share the same PC index and tag value, but differ in other values, when one or more branch instructions within a value bundle contain jumps, the BTB table stores the entry corresponding to that value bundle and updates the target field with the address jumped to by the last branch instruction among those instructions. When executing any branch instruction within that value bundle, the processor will look up the target address corresponding to the last branch instruction and jump to that address. In other words, even if the instruction executed by the processor is a branch instruction other than the last one within the value bundle, the processor will still jump to the target address corresponding to the last branch instruction, resulting in an incorrect jump.

[0047] When using, such as Figure 2 In the BTB example shown, multiple branch instructions within a value bundle correspond to the same entry in the BTB, meaning these multiple branch instructions correspond to the same target field. If only a portion of the branch instructions in the value bundle jump to a certain address, the predicted target address for all branch instructions in that value bundle will be that address. Thus, even if multiple branch instructions might jump to different target addresses, they share the same target address as the prediction result in the BTB. This makes it impossible to predict the target address for individual branch instructions, thereby reducing the overall branch prediction accuracy.

[0048] To address the aforementioned problems, this application proposes an instruction execution method applicable to superscalar processors, employing the methods described above. Figure 2 The BTB table shown has different branch prediction structures (or incremental BTBs). In the incremental BTB, each entry, except as described above... Figure 2 In addition to the tag, valid, and target fields, the BTB (Branch Pointer) can also include a position (pos) field. The pos field records the high m bits of the other values ​​in the PC (Prognostic Code) of a branch instruction. For example, m can be 2. The value in the pos field indicates the position information of the branch instruction within its value bundle.

[0049] During processor instruction execution, when a branch instruction is detected, the processor can write to or update the corresponding entry in the incremental BTB based on the PC value of that branch instruction. The PC value can include N bits of data, which can be divided into a tag value, an index value, a position value, and other values, with the tag value being n bits, the index value being k bits, and the position value being m bits. Based on the branch instruction's PC value, the processor identifies the entry corresponding to the branch instruction as the one whose index field matches its index value, writes the tag value to the tag field of that entry, and writes the position value to the pos field of that entry. In this way, the incremental BTB can record the position information of the branch instruction within its respective value bundle, thus distinguishing different branch instructions within the value bundle.

[0050] Based on the aforementioned incremental BTB, when the processor detects a branch instruction to be executed, it can determine whether there is an entry in the incremental BTB corresponding to the reference information (including at least one of index value, tag value, and position value) in the PC value of the branch instruction to be executed. If there is, the address in the target field of the entry is determined as the target address of the branch instruction to be executed, so as to jump to the target address to fetch and execute the next instruction.

[0051] According to some embodiments, the index value in the reference information can be used as an index to find entries in the incremental BTB whose index field content is the same as the index value, that is, to determine the entry corresponding to the index value.

[0052] According to some embodiments, the pos field includes a value. After determining the entry corresponding to the index value, the address of the target field can be determined as the target address of the branch instruction to be executed, provided that the tag field content in the entry is the same as the tag value, the pos field content is the same as the position value, and the valid field indicates that the entry is valid.

[0053] According to some embodiments, the `pos` field may include one or more values, and the `target` field may include one or more addresses. One or more values ​​in the `pos` field correspond one-to-one with one or more addresses in the `target` field. After determining the entry corresponding to the index value, if the content of the `tag` field in that entry is the same as the tag value, the multiple values ​​in the `pos` field include a position value, and the `valid` field indicates that the entry is valid, the address corresponding to the position value among the multiple addresses in the `target` field can be determined as the target address of the branch instruction to be executed.

[0054] In this way, BTB can distinguish between multiple branch instructions within the same fetch block. For example, when a jump occurs during the execution of a fetch block, the processor can directly obtain the location information of the branch instruction that caused the jump, and determine which branch instruction within the fetch block caused the jump based on the location information. The jump address is then stored in the target field of the entry for that branch instruction, ensuring that the target address corresponds to the pos field in the entry. Moreover, even if multiple branch instructions jump to the same target address, the pos field can be used to distinguish between the two branch instructions, thereby improving branch prediction accuracy.

[0055] According to some embodiments, the incremental BTB also includes prediction information. For example, the prediction information may be as follows: Figure 1 The prediction information in the PHT table shown. It can be understood that incremental BTB can be compared to... Figure 2 The BTB table in the incremental BTB has a newly added "predtaken" field. This means that for an entry in the incremental BTB, if the "predtaken" field indicates that the corresponding branch instruction will not jump, the processor will not jump to the target address under the "target" field. In this way, jump prediction can be made based on the incremental BTB. Since this prediction does not need to be based on the execution state of historical branch instructions, there is no need to use a PHT (Prognostics and Execution Time), thus saving storage space.

[0056] In one example, the `pred taken` field can be a jump count value, which increments by one each time a jump occurs for the branch instruction corresponding to this entry. For instance, the jump count value can be represented in binary, where jump count values ​​"00" and "01" indicate that the branch instruction does not jump, and jump count values ​​"10" and "11" indicate that the branch instruction jumps.

[0057] In some embodiments, the pred taken field includes a value. After determining the entry corresponding to the index value, if the tag field content of the entry is the same as the tag value, the pos field content is the same as the position value, and the valid field indicates that the entry is valid, the content of the pred taken field can be used to determine whether the branch instruction to be executed should jump.

[0058] According to some embodiments, the `pos` field may include one or more values, and the `pred taken` field may include one or more jump count values. The values ​​in the `pos` field and the jump count values ​​in the `pred taken` field correspond one-to-one. After determining the entry corresponding to the index value, if the content of the `tag` field in that entry is the same as the tag value, the multiple values ​​in the `pos` field include a position value, and the `valid` field indicates that the entry is valid, then the decision to jump to the branch instruction to be executed can be determined based on the content of the `pred taken` field.

[0059] The following is based on Figures 3-6 This application introduces an incremental BTB in an instruction execution method provided by an embodiment of the present application.

[0060] Figure 3 A first structural schematic diagram of an incremental BTB is shown according to an embodiment of this application.

[0061] Understandable. Figures 3-6 The PC value shown is the PC value of the branch instruction to be executed. In this embodiment, the PC value may include a total of 32 bits of data. It should be noted that this embodiment does not limit the number of bits in the PC value.

[0062] like Figure 3 As shown, the incremental BTB includes 2^k entries, where the indices of the entries range from 0 to 2^k-1. Exemplarily, the index value corresponds to the index value in the PC value, that is, the value of the (n+1)th to (n+k)th bits in the PC value from high to low. Exemplarily, k can be 5. This application embodiment does not limit the value of k.

[0063] Incremental BTB includes the tag field, valid field, target field, and pos field.

[0064] In this context, the tag field of the incremental BTB corresponds to the tag value in the PC value, that is, the value of the first to the nth position in the PC value from high to low. For example, n can be 8, and this application embodiment does not limit the value of n.

[0065] The valid field in an incremental BTB is used to indicate whether an entry is valid. For example, valid = "1" indicates that the entry is valid, and valid = "0" indicates that the entry is invalid.

[0066] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0067] The `pos` field of the incremental BTB indicates the position of the branch instruction corresponding to the entry within the instruction bundle, specifically the value of bits n+k+1 to n+k+2 from high to low in the PC value. For example, if the branch instruction is the i-th instruction out of four instructions in the instruction bundle, then the `pos` field of the entry corresponding to that branch instruction is the binary representation of i.

[0068] According to an embodiment of this application, the incremental BTB includes a pos field, wherein the pos field is written with the position of the branch instruction in the value bundle to which it belongs, so that each entry corresponds to each branch instruction in the value bundle, thereby enabling the storage of prediction results for a single branch instruction.

[0069] exist Figure 3 Based on the incremental BTB shown, the target and pos fields can also include one or more items, as detailed below. Figure 4 The target field can include at least one address, and the pos field can include at least one location, which is another incremental BTB.

[0070] Figure 4 A schematic diagram of a second structure for an incremental BTB is shown according to an embodiment of this application. It can be understood that... Figure 4 The PC value shown is the PC value of the branch instruction to be executed.

[0071] like Figure 4 As shown, the incremental BTB includes 2^k entries, where the indices of the entries range from 0 to 2^k-1. For example, the index value corresponds to the index value in the PC value, that is, the value of the (n+1)th to (n+k)th bits in the PC value from high to low.

[0072] Incremental BTB includes the tag field, valid field, target field, and pos field.

[0073] In the incremental BTB, the tag field corresponds to the tag value in the PC value, that is, the value from the 1st to the nth position in the PC value from high to low.

[0074] The valid field in an incremental BTB is used to indicate whether an entry is valid. For example, valid = "1" indicates that the entry is valid, and valid = "0" indicates that the entry is invalid.

[0075] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0076] like Figure 4 As shown, the target field can include one or more addresses. For example, taking the entry with index 2^k-1 as an example, target includes three target addresses: e, f, and g, which correspond to each of the three branch instructions in the same instruction bundle.

[0077] The `pos` field of the incremental BTB indicates the position of the branch instruction corresponding to the entry within the instruction bundle, specifically the value of bits n+k+1 to n+k+2 from high to low in the PC value. For example, if the branch instruction is the i-th instruction out of four instructions in the instruction bundle, then the `pos` field of the entry corresponding to that branch instruction is the binary representation of i.

[0078] like Figure 4As shown, the `pos` field can include one or more positions. For example, taking the entry with index 2^k-1 as an example, the `pos` field includes three positions: "00", "01", and "11", which correspond to each of the three branch instructions in the same instruction bundle. "00" indicates that the branch instruction is the first instruction in the value bundle, "01" indicates that the branch instruction is the second instruction in the value bundle, and "11" indicates that the branch instruction is the fourth instruction in the value bundle. It can be understood that the positions in the `pos` field correspond one-to-one with the addresses in the `target` field. For example, the target address of the branch instruction corresponding to position "00" in the `pos` field is "e", the target address of the branch instruction corresponding to position "01" in the `pos` field is "f", and the target address of the branch instruction corresponding to position "11" in the `pos` field is "g".

[0079] According to the embodiments of this application, multiple pieces of information are written to the pos field and target field of the incremental BTB, which can reduce the number of entries in the incremental BTB and save storage space.

[0080] exist Figure 3 Based on the incremental BTB shown, the incremental BTB can also include a pred taken field, where the predtaken field includes a jump count value to indicate whether the branch instruction jumped. The following section combines... Figure 5 Introduces an incremental BTB that includes a predtaken field.

[0081] Figure 5 A schematic diagram of a third structure for an incremental BTB is shown according to an embodiment of this application.

[0082] like Figure 5 As shown, the incremental BTB includes 2^k entries, where the indices of the entries range from 0 to 2^k-1. Exemplarily, the index value corresponds to the index value in the PC value, that is, the value of the (n+1)th to (n+k)th bits in the PC value from high to low. Exemplarily, k can be 5. This application embodiment does not limit the value of k.

[0083] Incremental BTB includes the tag field, valid field, target field, pos field, and pred taken field.

[0084] In this context, the tag field of the incremental BTB corresponds to the tag value in the PC value, that is, the value of the first to the nth position in the PC value from high to low. For example, n can be 8, and this application embodiment does not limit the value of n.

[0085] The valid field in an incremental BTB is used to indicate whether an entry is valid. For example, valid = "1" indicates that the entry is valid, and valid = "0" indicates that the entry is invalid.

[0086] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0087] The `pos` field of the incremental BTB indicates the position of the branch instruction corresponding to the entry within the instruction bundle, specifically the value of bits n+k+1 to n+k+2 from high to low in the PC value. For example, if the branch instruction is the i-th instruction out of four instructions in the instruction bundle, then the `pos` field of the entry corresponding to that branch instruction is the binary representation of i.

[0088] The pred taken field of an incremental BTB includes a jump count value. It can be understood that each time a branch instruction jumps, the pred taken field of the corresponding entry for that branch instruction increments by one. According to some embodiments, if the jump count value is "00" and "01", it indicates that the branch instruction does not jump; if the jump count value is "10" and "11", it indicates that the branch instruction jumps.

[0089] According to embodiments of this application, the incremental BTB includes a pre-taken field, that is, the incremental BTB in... Figure 2 The BTB shown incorporates information from the PHT and adds content for predicting whether a branch instruction will jump, saving storage resources compared to using PHT and BTB separately.

[0090] exist Figure 5 Based on the incremental BTB shown, the pred taken, target, and pos fields can also include one or more contents, as detailed below. Figure 6 Another incremental BTB is introduced, in which the pred taken field may include at least one jump count value, the target field may include at least one address, and the pos field may include at least one location.

[0091] Figure 6 A fourth structural schematic diagram of an incremental BTB is shown according to an embodiment of this application.

[0092] like Figure 6 As shown, the incremental BTB includes 2^k entries, where the indices of the entries range from 0 to 2^k-1. For example, the index value corresponds to the index value in the PC value, that is, the value of the (n+1)th to (n+k)th bits in the PC value from high to low.

[0093] Incremental BTB includes the tag field, valid field, target field, pos field, and pred taken field.

[0094] In the incremental BTB, the tag field corresponds to the tag value in the PC value, that is, the value from the 1st to the nth position in the PC value from high to low.

[0095] The valid field in an incremental BTB is used to indicate whether an entry is valid. For example, valid = "1" indicates that the entry is valid, and valid = "0" indicates that the entry is invalid.

[0096] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0097] like Figure 6 As shown, the target field can include one or more addresses. For example, taking the entry with index 2^k-1 as an example, target includes three target addresses: e, f, and g, which correspond to each of the three branch instructions in the same instruction bundle.

[0098] The `pos` field of the incremental BTB indicates the position of the branch instruction corresponding to the entry within the instruction bundle, specifically the value of bits n+k+1 to n+k+2 from high to low in the PC value. For example, if the branch instruction is the i-th instruction out of four instructions in the instruction bundle, then the `pos` field of the entry corresponding to that branch instruction is the binary representation of i.

[0099] like Figure 4 As shown, the `pos` field can include one or more positions. For example, taking the entry with index 2^k-1 as an example, the `pos` field includes three positions: "00", "01", and "11", which correspond to each of the three branch instructions in the same instruction bundle. "00" indicates that the branch instruction is the first instruction in the value bundle, "01" indicates that the branch instruction is the second instruction in the value bundle, and "11" indicates that the branch instruction is the fourth instruction in the value bundle. It can be understood that the positions in the `pos` field correspond one-to-one with the addresses in the `target` field. For example, the target address of the branch instruction corresponding to position "00" in the `pos` field is "e", the target address of the branch instruction corresponding to position "01" in the `pos` field is "f", and the target address of the branch instruction corresponding to position "11" in the `pos` field is "g".

[0100] The pred taken field of an incremental BTB includes a jump count value. It can be understood that each time a branch instruction jumps, the pred taken field of the corresponding entry for that branch instruction increments by one. According to some embodiments, if the jump count value is "00" and "01", it indicates that the branch instruction does not jump; if the jump count value is "10" and "11", it indicates that the branch instruction jumps.

[0101] like Figure 6As shown, the `pred taken` field can include one or more jump count values. For example, taking the entry with index 2^k-1 as an example, the `pred taken` field includes three jump count values: "00", "00", and "11", which correspond to each of the three branch instructions in the same instruction bundle. It can be understood that the positions in the `pos` field and the addresses in the `target` field correspond one-to-one. For example, the jump count value of the branch instruction corresponding to position "00" in the `pos` field is "00", indicating that the branch instruction does not jump; the jump count value of the branch instruction corresponding to position "01" in the `pos` field is "00", indicating that the branch instruction does not jump; the jump count value of the branch instruction corresponding to position "11" in the `pos` field is "11", indicating that the branch instruction jumps; correspondingly, the target address of the branch instruction corresponding to position "11" in the `target` field is "g".

[0102] According to the embodiments of this application, multiple pieces of information are written to the pos field, target field, and pred taken field of the incremental BTB, which can reduce the number of entries in the incremental BTB and save storage space.

[0103] The following is based on Figure 7 In combination with the above Figures 3-6 This application describes an instruction execution method according to an embodiment of the present application. When a branch instruction jump is detected, the processor can write information to the incremental BTB to update the content corresponding to the branch instruction in the incremental BTB. This allows the processor to subsequently use the incremental BTB to accurately predict the jump information of more branch instructions, such as whether the instruction will jump and the target address to which it will jump.

[0104] Figure 7 An exemplary flow of a method for updating a branch prediction structure is shown according to embodiments of this application. Figure 7 As shown, the exemplary process includes the following steps.

[0105] S101: A jump was detected in the first instruction being executed.

[0106] According to some embodiments, the processor can monitor the execution status of instructions in a program to determine whether a jump has occurred, such as when or after executing the instruction, the program jumps to a new address to continue execution. For example, the processor parses the opcode of an instruction, determines that the instruction is a branch instruction based on the opcode, and determines that a jump has occurred when the instruction has jumped; this constitutes the processor detecting a branch instruction jump.

[0107] S102: Store the information of the first instruction in the branch prediction structure.

[0108] When the processor detects a jump to the first instruction during instruction execution, it can determine that the instruction is a branch instruction.

[0109] According to some embodiments, the branch prediction structure is as follows: Figures 3-6 The incremental BTB shown. The stored information of the first instruction may include at least one of the following: the target address of the first instruction jump, the jump count value, and the location information. After a jump of the first instruction is detected, the information of the first instruction can be written to or updated in the incremental BTB.

[0110] It is understandable that in each entry of the incremental BTB, the index value, tag value, and position value of the instruction pointer of the branch instruction corresponding to each entry are the same as the contents of the index, tag, and pos fields of that entry in the incremental BTB.

[0111] As an example, each entry in the incremental BTB corresponds to a branch instruction. Based on the following S1021A or S1022A, the first entry corresponding to the first instruction can be added to the incremental BTB, or the first entry corresponding to the first instruction in the incremental BTB can be updated.

[0112] S1021A: If there is a second entry in the corresponding incremental BTB that corresponds to the first instruction, update the second entry to the first entry.

[0113] According to some embodiments, if a second entry corresponding to the first instruction exists in the incremental BTB, the target field in the entry of the first instruction can be updated to update the other addresses in the target field to the first address to which the first instruction jumps, and the updated second entry is used as the first entry. Here, the pos field of the second entry is the first position value in the PC value of the first instruction, the index of the second entry is the first index value in the PC value of the first instruction, and the tag field of the second entry is the first tag value in the PC value of the first instruction.

[0114] When a jump to the first instruction corresponding to the second entry is detected, the target address to which the jump is made can be updated in the target field of that entry. For example, see reference. Figure 3 or Figure 5Taking the second entry corresponding to the first instruction as an example, where the index is 0, after the first instruction jumps to this entry, the target address "target0" is updated in the target field. Specifically, the values ​​of the first instruction's PC value from the 1st to the nth position from the highest to the lowest are the first tag value, which is equal to "tag0" in the tag field of this entry; the values ​​of the first instruction's PC value from the (n+1)th to the (n+k)th position from the highest to the lowest are the first index value, which is equal to "0"; and the values ​​of the first instruction's PC value from the (n+k+1)th to the (n+k+2)th position from the highest to the lowest are the first position value, which is equal to "00" in the pos field, indicating that the first instruction is the first instruction in the value bundle.

[0115] According to some embodiments, after updating the target field of the second entry corresponding to the first instruction, the valid field of the second entry can also be updated to "1" so that the value of the valid field indicates that the entry is valid.

[0116] In some embodiments, the stored information of the first instruction further includes a jump count value, and the incremental BTB further includes a pred taken field for indicating whether the first instruction jumps. In this embodiment, the jump count value in the pred taken field of the second entry corresponding to the first instruction can also be incremented, such as by adding one to the jump count value.

[0117] Optionally, the jump count in the `pred taken` field stops incrementing after reaching a threshold. For example, the threshold could be 3. When a jump from the first instruction is detected, the jump count in the `pred taken` field of the corresponding entry for that instruction is incremented by one until the threshold of 3 is reached, which is represented as "11" in binary. For example, see [reference]. Figure 5 If the first instruction corresponds to the entry with index 0, after the jump from the first instruction, since the jump count value in the pred taken field is already "11", the value will not be increased further. This application does not limit the threshold value in its embodiments.

[0118] S1022A: If there is no entry corresponding to the first instruction in the incremental BTB, add a first entry corresponding to the first instruction in the incremental BTB.

[0119] According to some embodiments, if there is no entry corresponding to the first instruction in the incremental BTB, a first entry can be added in the incremental BTB. The first index value is the index of the first entry, the first tag value is written to the tag field of the first entry, the first position value is written to the pos field of the first entry, and the first address to which the first instruction jumps is written to the target field of the first entry.

[0120] For example, refer to Figure 3 or Figure 5 The following explanation uses the entry with index 0 corresponding to the first instruction as an example. Specifically, the index values ​​of the (n+1)th to (n+k)th bits of the PC value of the first instruction are 0. When the first instruction jump is detected for the first time, it can be... Figure 3 or Figure 5 The incremental BTB shown adds the first entry, namely the entry with index 0, and writes the tag value "tag0" from the 1st to the nth bit of the PC value of the first instruction from high to low into the tag field of this entry; writes the position value "00" from the n+k+1st to the n+k+2nd bit of the PC value of the first instruction from high to low into the pos field; and writes the first address "target0" of the jump of the first instruction into the target field.

[0121] According to some embodiments, after writing the first address to the target field of the entry corresponding to the first instruction, the valid field of the first entry can also be updated to "1" so that the value of the valid field indicates that the entry is valid.

[0122] In some embodiments, the stored information of the first instruction also includes a jump count value, and the incremental BTB also includes a pred taken field for indicating whether the branch instruction jumps. In this embodiment, the initial jump count value can also be written to the pred taken field. For example, after adding the first entry to the incremental BTB, "01" is written to the pred taken field of the first entry.

[0123] As another example, each entry in the incremental BTB corresponds to a value bundle, or to at least one branch instruction within a value bundle. Based on the following S1021B or S1022B, a first entry corresponding to the first value bundle to which the first instruction belongs can be added to the incremental BTB, or the first entry corresponding to the first value bundle to which the first instruction belongs in the incremental BTB can be updated.

[0124] S1021B: If there is a second entry in the corresponding incremental BTB that corresponds to the first value bundle, update the second entry to the first entry.

[0125] According to some embodiments, when a first instruction jump is detected, the first address to which the first instruction jumps can be updated to the target field of the second entry corresponding to the first value bundle based on the position of the first instruction in its respective value bundle, so that the second entry is updated to the first entry. That is, the updated second entry can be determined as the first entry.

[0126] For example, refer to Figure 4 or Figure 6The following example illustrates the situation with the second entry corresponding to the first value bundle being the entry with index 2^k-1, and the first position value in the PC value of the first instruction being "11".

[0127] Specifically, the values ​​of the first instruction's PC value from the 1st to the nth position from the highest to the lowest are the first tag value, which is equal to "tag(2^k-1)" in the tag field of the second entry; the values ​​of the first instruction's PC value from the (n+1)th to the (n+k)th position from the highest to the lowest are the first index value, which is equal to "2^k-1"; the values ​​of the first instruction's PC value from the (n+k+1)th to the (n+k+2)th position from the highest to the lowest are the first position value, which is equal to "11" in the pos field, indicating that the first instruction is the 4th instruction in the first value bundle.

[0128] It is understandable that in the second entry, the pos field includes three branch instructions: “00”, “01”, and “11”, which correspond to the first, second, and fourth instructions in the first value bundle, respectively.

[0129] The following describes two methods for updating the entry with index 2^k-1 in S1021B.

[0130] For example, if the pos field of the second entry includes the first position value of the PC value of the first instruction, that address can be updated. For instance, in the entry with index 2^k-1, since the position value "11" of the first instruction is the third value in the pos field, after the fourth instruction corresponding to "11" jumps, the third address of the target field can be updated to "g".

[0131] For example, if the pos field of the second entry does not include the first position value of the PC value of the first instruction, the first position value can be written into the second entry, and the first address can be written into the second entry. For example, in the entry with index 2^k-1, if the position value "11" of the first instruction does not exist in the pos field, "11" can be written into the pos field, and the first address "g" can be written into the target field.

[0132] It is understandable that the position of the first address in the target field corresponds to the position of the first value in the pos field, such as 3 in the example above.

[0133] In some embodiments, the stored information of the first instruction further includes a jump count value, and the incremental BTB further includes a pred taken field for indicating whether the first instruction jumps. In this embodiment, the jump count value corresponding to the position in the pred taken field can also be incremented according to the position of the first instruction in its respective first value bundle, such as by incrementing the jump count value by one.

[0134] Optionally, the jump count in the `pred taken` field stops incrementing after reaching a threshold. For example, the threshold could be 3. When a jump from the first instruction is detected, the jump count in the `pred taken` field of the corresponding entry for that instruction is incremented by one until the threshold of 3 is reached, which is represented as "11" in binary. For example, see [reference]. Figure 6 If the second entry corresponding to the first instruction is an entry with index 2^k-1, and the first position value of the first instruction is "11", after the jump of the first instruction, since the third jump count value in the entry with index 2^k-1 in the predtaken field is already "11", the value will not be increased further. It can be understood that the embodiments of this application do not limit the threshold.

[0135] It can be understood that the position of the jump count value in the pred taken field for incremental operations corresponds to the position value in the pos field, such as 3 in the example above.

[0136] S1022B: If there is no entry corresponding to the first value bundle in the incremental BTB, add a first entry corresponding to the first instruction in the incremental BTB.

[0137] According to some embodiments, if there is no entry corresponding to the first value bundle in the incremental BTB, a first entry can be added in the incremental BTB, wherein the first index value is the index of the first entry, the first tag value is written to the tag field of the first entry, the first position value is written to the pos field of the first entry, and the first address to which the first instruction jumps is written in the target field of the first entry.

[0138] For example, refer to Figure 4 or Figure 6 The following explanation uses the entry with index 0 corresponding to the first value bundle as an example. Specifically, the index values ​​of the (n+1)th to (n+k)th bits of the PC value of the first instruction are 0. When a jump to the first instruction is detected, it can... Figure 4 or Figure 6 The incremental BTB shown adds an entry with index 0, and writes the tag value "tag0" from the first to the nth bit of the PC value of the first instruction from high to low into the tag field of the entry; writes the position value "00" from the n+k+1 to n+k+2th bit of the PC value of the first instruction from high to low into the pos field; and writes the first address "target0" of the jump of the first instruction into the target field.

[0139] According to some embodiments, after writing the first address to the target field of the entry corresponding to the first instruction, the valid field of the first entry can also be updated to "1" so that the value of the valid field indicates that the entry is valid.

[0140] In some embodiments, the stored information of the first instruction also includes a jump count value, and the incremental BTB also includes a pred taken field for indicating whether the branch instruction jumps. In this embodiment, the initial jump count value can also be written to the pred taken field. For example, after adding the first entry to the incremental BTB, "01" is written to the pred taken field of the first entry.

[0141] In this embodiment, by writing the target address of the branch instruction jump to the branch prediction structure, the jump address of the branch instruction to be executed can be predicted. When the branch instruction actually jumps, the processor updates the target field, thus enabling quick and accurate access to the correct jump address in future branch predictions. By updating the jump count value representing the historical execution count in the branch prediction structure, the value of the pred taken field corresponding to the branch instruction will increment when the actual jump of the branch instruction occurs. This allows the jump count value to reflect the probability that the branch instruction was predicted to jump historically, improving the accuracy of branch prediction.

[0142] Given that the processor has instructions to execute, a dynamically updated branch prediction structure can be used, for example, based on the above. Figure 7 The method of updating is as follows Figures 3-6 The branch prediction structure shown is used to predict the jump information of branch instructions. The following is based on... Figure 8 An exemplary flow for an instruction execution method is introduced.

[0143] S201: The first instruction to be executed has been detected.

[0144] It is understandable that the first instruction is a branch instruction.

[0145] According to some embodiments, the processor is a superscalar processor. In this case, the instructions corresponding to the processing request can be grouped into a value bundle and executed by the processor. For example, each value bundle may include four instructions, which may or may not include branch instructions. This application does not limit this aspect.

[0146] According to some embodiments, the front end of an electronic device, such as a display screen, can detect user operations, thereby enabling the processor to receive processing requests triggered by the user operations.

[0147] According to some embodiments, an application program of an electronic device can submit a processing request, which causes the processor to receive the processing request from the program.

[0148] According to some embodiments, S201 may further include: determining that the first instruction is a branch instruction by parsing the opcode of the first instruction.

[0149] S202: Determine that there is a first entry in the incremental BTB that corresponds to the first instruction.

[0150] It can be understood that the first entry corresponds to the first value bundle described by the first instruction. For example, the first entry corresponds to all branch instructions in the first value bundle. Or, for another example, the first entry corresponds to a single branch instruction, namely the first instruction in the first value bundle, and not to any other branch instructions.

[0151] According to some embodiments, when the pos field of the first entry is the first position value in the PC value of the first instruction, the index of the first entry is the first index value in the PC value of the first instruction, and the tag field of the first entry is the first tag value in the PC value of the first instruction, it can be determined that the first entry corresponds to the first instruction.

[0152] It can be understood that the incremental BTB, as a dynamically updated branch prediction structure, uses a first index value to locate the entry corresponding to the branch instruction. According to some embodiments, each entry in the incremental BTB corresponds to an index value, which are arranged in ascending order starting from 0. For example, refer to... Figures 3-6 The values ​​are arranged from 0 to 2^k-1. Based on this, the processor can determine the first entry corresponding to the first index value in the incremental BTB.

[0153] For example, refer to Figure 3 or Figure 5 For an entry with index "0", if the index value of the PC value of the first instruction is 0, the "tag0" in the tag field is the first tag value in the PC value of the first instruction, and the "00" in the pos field is the first position value in the PC value of the first instruction, then the entry can be identified as the first entry corresponding to the first instruction.

[0154] For example, refer to Figure 4 or Figure 6 For an entry with index "2^k-1", if the index of the PC value of the first instruction is 2^k-1, the tag field "tag(2^k-1)" is the first tag value in the PC value of the first instruction, and the "00", "01", and "11" in the pos field include the first position value "11" in the PC value of the first instruction, then the entry can be determined as the first entry corresponding to the first instruction.

[0155] According to some embodiments, if there is no first entry corresponding to the first instruction in the incremental BTB macro, the first instruction does not jump, and the processor continues to execute at the current address.

[0156] It is understandable that the information in the first entry can be used to guide the execution of the first instruction and the next instruction following it. For example, it can jump to the first address to execute the instruction, or continue at the current address, i.e., the address where the first instruction is stored, to read and execute the next instruction. The following describes the execution modes of the two processors based on S203A-S203B.

[0157] S203A: Determine the first instruction jump based on the first entry, and jump to the first address.

[0158] According to some embodiments, the first address is the address in the target field of the first entry.

[0159] According to some embodiments, if a first entry exists in the branch prediction structure, the first instruction jump can be determined directly.

[0160] In some scenarios, interference factors such as the capacity limitations of incremental BTB may cause the first entry to become invalid, in which case the valid field changes from "1" to "0". According to some embodiments, the valid field can indicate whether the first instruction should jump. If the valid field is "1", it means that the first entry is valid, and the first instruction is determined to jump.

[0161] For example, refer to Figure 3 If the index of the first entry is "2", since the valid field is "1", the first instruction jump is determined and the jump is to the first address "target0" in the target field.

[0162] According to some embodiments, the first address is the address in the target field of the first entry that corresponds to the first position value of the PC value of the first instruction.

[0163] For example, refer to Figure 4 If the index of the first entry is "2^k-1" and the valid field is "1", then the first instruction will jump. Furthermore, the first position of the PC value of the first instruction is "11". Since "g" is the third of the three addresses in the target field, and "11" is the third of the three position values ​​in the pos field, and "11" and "g" are in the same position in their respective fields, they correspond. Therefore, the "g" in the target field of this entry that corresponds to the first position value "11" is the first address corresponding to the first instruction. Based on this, it can be determined that the jump will be to the first address "g".

[0164] According to some embodiments, the first entry of the incremental BTB also includes a pred taken field.

[0165] According to some embodiments, the pred taken field of the first entry can be used alone to determine whether the first instruction should jump. Specifically, if the pred taken field is greater than a threshold or equal to a preset value, it can be determined that the first instruction should jump.

[0166] For example, the threshold is 1, that is, in the pred taken field, the jump count value corresponding to the first instruction is "11" or "10" which is greater than the threshold, and "00" and "01" which are less than or equal to the threshold.

[0167] For example, refer to Figure 6 If the index of the first entry is "0", since the pred taken field of the first entry is "11", the first instruction jump is determined and the jump is to the first address "target0" in the target field to continue executing the instruction at the first address.

[0168] According to some embodiments, the `pred taken` field and the `valid` field of the first entry can be used together to determine whether the first instruction should jump. Specifically, if the `pred taken` field is greater than a threshold or equal to a preset value, and the `valid` field indicates that the first entry is valid, then it can be determined that the first instruction should jump.

[0169] For example, the preset value in the pred taken field may include "11". This application embodiment does not limit the preset value.

[0170] For example, refer to Figure 6 If the index of the first entry is "2^k-1", and the first position value in the PC value of the first instruction is "11", then since "11" is the third of the three position values ​​in the pos field, the jump count value corresponding to the first instruction is the third jump count value "11" in the predtaken field. Since "11" is greater than the threshold, and the valid field of the first entry is "1", indicating that the first entry is valid, then the first instruction is determined to jump, and the jump is to the first address in the target field, that is, the third address "g", to continue executing the instruction.

[0171] According to some embodiments, if the first instruction jumps to the first address, the jump count value in the predtaken field of the first entry can be incremented, for example, by one.

[0172] S203B: Based on the first entry, the first instruction is determined not to jump and continues execution at the current address.

[0173] According to some embodiments, the first address is the address in the target field of the first entry.

[0174] According to some embodiments, the valid field can indicate whether the first instruction should jump. Specifically, if the valid field is "0", it indicates that the first entry is invalid, determining that the first instruction will not jump, and the processor continues execution at the current address. Here, the current address is the address where the processor reads the first instruction.

[0175] For example, refer to Figure 3 If the index of the first entry is "2", since the valid field of the first entry is "0", it is determined that the first instruction will not jump.

[0176] According to some embodiments, the first entry of the incremental BTB also includes a pred taken field.

[0177] According to some embodiments, the predtaken field can indicate whether the first instruction should jump. Specifically, if the predtaken field is less than or equal to a threshold and is not a preset value, it can be determined that the first instruction will not jump.

[0178] For example, the threshold is 1. In the pred taken field, the jump count value corresponding to the first instruction is "11" or "10", which are greater than the threshold, and "00" or "01", which are less than or equal to the threshold.

[0179] For example, the preset value in the pred taken field may include "11". This application embodiment does not limit the preset value.

[0180] For example, refer to Figure 6 If the index of the first entry is "2^k-1", and the first position of the PC value of the first instruction is "01", then since "01" is the second of the three position values ​​in the pos field, the jump count value corresponding to the first instruction is the second jump count value in the predtaken field, "00". Since "00" is less than the threshold, the processor does not jump and continues to execute instructions at the current address.

[0181] According to some embodiments, the pred taken field and the valid field of the first entry can be used together to determine whether the first instruction jumps to the first address. Specifically, if the pred taken field is less than or equal to a threshold and is not a preset value, or if the valid field indicates that the first entry is invalid, it can be determined that the first instruction does not jump.

[0182] According to some embodiments, after a branch instruction jumps, if there are instructions in the fetch bundle that have not yet been executed, the processor will not execute any other instructions following the branch instruction in the fetch bundle; the processor will retrieve the next fetch bundle from the target address to which it has jumped, and continue to execute the instructions in the next fetch bundle.

[0183] It is understood that the instruction execution methods of S201-S203 described above can be used to handle different processing requests. Two optional embodiments for different application scenarios are described below. It should be noted that the following application scenarios are merely examples and are not intended to limit the scope of this application.

[0184] According to some embodiments, the processing request is triggered by a user operation, and the user's intent in the operation is to request video playback. The processing request includes the video identifier, user identity information, etc. Branch instructions can be used to determine the video quality, such as high definition (HD) or standard definition (SD). Corresponding to the branch instruction, the processor jumps to the target address, where it can render the video based on the determined video quality and send the rendered video to the display.

[0185] According to some embodiments, when a user logs into an online platform, such as an online game, the processor in the server receives a processing request in S201. This processing request may include user information, the user's desired service area, etc., and the corresponding processing task is to assign the user to a server area. The processor can predict which server area the user will register in. Corresponding to a branch instruction jumping to the target address, the processor can assign the user to the predicted server area.

[0186] Through the embodiments of this application, incremental BTB can be used for branch prediction, wherein branch instructions at different positions in the value bundle are distinguished, and jump information prediction is performed separately for different branch instructions, thereby improving prediction accuracy. Furthermore, by merging PHT and BTB in the incremental BTB, the incremental BTB includes execution information (i.e., information indicating whether a branch instruction executes a jump), eliminating the need for branch prediction based on two separate branch prediction structures, thus saving storage space, reducing computational power consumption, and improving prediction efficiency.

[0187] further, Figure 9 According to some embodiments of this application, a schematic diagram of the structure of an electronic device 100 is shown. For example... Figure 9 As shown, the electronic device 100 includes one or more processors 101, system memory 102, non-volatile memory (NVM) 103, communication interface 104, input / output (I / O) device 105, and system control logic 106 for coupling the processor 101, system memory 102, non-volatile memory 103, communication interface 104 and input / output (I / O) device 105.

[0188] The processor 101 may include one or more processing units, such as a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), microprocessor (MCU), AI (Artificial Intelligence) processor, or programmable logic device (FPGA), neural network processing unit (NPU), etc. The processor may include one or more single-core or multi-core processors. According to some embodiments, the processor is a superscalar processor.

[0189] System memory 102 is volatile memory, such as random-access memory (RAM), double data rate synchronous dynamic random-access memory (DDR SDRAM), etc. System memory is used for temporary storage of data and / or instructions.

[0190] Non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, non-volatile memory 103 may include any suitable non-volatile memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, non-volatile memory 103 may also be a removable storage medium, such as a secure digital (SD) memory card, etc. For example, in some embodiments, system memory 102 may be used to store data such as… Figures 3-6 The incremental BTB is shown.

[0191] Specifically, system memory 102 and non-volatile memory 103 may each include a temporary copy and a permanent copy of instruction 107. Instruction 107 may include, when executed by at least one of processors 101, causing electronic device 100 to implement the instruction execution methods provided in the embodiments of this application.

[0192] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby enabling communication with any other suitable device via one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104.

[0193] Input / output (I / O) device 105 can be an input device such as a keyboard or mouse, and an output device such as a monitor. Users can interact with electronic device 100 through input / output (I / O) device 105, such as inputting a neural network model to be run.

[0194] System control logic 106 may include any suitable interface controller to provide any suitable interface to other modules of electronic device 100. For example, in some embodiments, system control logic 106 may include one or more memory controllers to provide an interface to system memory 102 and non-volatile memory 103.

[0195] In some embodiments, at least one of the processors 101 may be packaged together with the logic of one or more controllers for system control logic 106 to form a system-in-package (SiP). In other embodiments, at least one of the processors 101 may also be integrated on the same chip with the logic of one or more controllers for system control logic 106 to form a system-on-chip (SoC).

[0196] Understandable. Figure 9 The structure of the electronic device 100 shown is merely an example. In other embodiments, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0197] It is understood that electronic device 100 can be any electronic device, including but not limited to mobile phones, wearable devices (such as smartwatches), tablets, desktops, laptops, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, etc., and this application embodiment does not limit it.

[0198] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0199] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a Digital Signal Processor (DSP), a microcontroller, an Application Specific Integrated Circuit (ASIC), or a microprocessor.

[0200] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0201] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0202] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0203] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0204] It should be noted that, in the examples and description of this patent, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0205] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A method for executing instructions, applied to an electronic device, characterized in that, The processor of the electronic device stores a branch prediction structure, which includes multiple entries. Each entry corresponds to at least a portion of the branch instructions in a value bundle. The value bundle is a set of multiple instructions fetched by the processor from the instruction memory at one time. Each entry includes a position field and a target address field. The position field includes a position value that corresponds one-to-one with at least a portion of the branch instructions in the corresponding value bundle. The target address field includes a target address that corresponds one-to-one with at least a portion of the branch instructions in the corresponding value bundle. The position value indicates the position of the corresponding branch instruction in its value bundle, and the target address indicates the address to which the corresponding branch instruction jumps. Furthermore, the method includes: The processor detected the first instruction; The processor determines that a first entry exists in the branch prediction structure, wherein the value bundle corresponding to the first entry is the first value bundle to which the first instruction belongs, and the position field of the first entry matches the first position value in the instruction pointer of the first instruction, wherein the first position value indicates the position of the first instruction in the first value bundle to which it belongs; Jump to the first address, where the first address is the target address in the target address field of the first entry that corresponds to the first position value; Each entry further includes a label field and an index field. The label field includes label values ​​that correspond one-to-one with the value bundles corresponding to the branch instruction, and each entry in the branch prediction structure corresponds to an index value. The tag value is from the 1st to the nth bit in the instruction pointer of the branch instruction from high to low, the index value is from the (n+1)th to the (n+k)th bit in the instruction pointer of the branch instruction from high to low, and the position value is from the (n+k+1)th to the (n+k+m)th bit in the instruction pointer of the branch instruction from high to low, where k is a positive integer greater than 1 and m is a positive integer greater than 1.

2. The method according to claim 1, characterized in that, Each of the entries further includes a predicted execution field, which includes a jump count value that corresponds one-to-one with at least a portion of the branch instructions in the corresponding value bundle. The jump count value is used to indicate the number of historical jumps of the corresponding branch instruction. The jump to the first address includes: If the predicted execution field of the first entry indicates a branch instruction jump, then jump to the first address. Specifically, when the jump count value is greater than a threshold or the jump count value is a preset value, the predicted execution field indicates the corresponding branch instruction jump.

3. The method according to claim 1 or 2, characterized in that, The first position value and the first address are stored in the branch prediction structure when the processor history detects that a jump has occurred from the first instruction.

4. The method according to claim 1, characterized in that, The processor stores the first address and the first location value in the branch prediction structure in the following manner: The first instruction was detected, and the user jumped to the first address. If a second entry exists corresponding to the first value bundle in the branch prediction structure, and the position field of the second entry includes the first position value, then the third address corresponding to the first position value in the target address field of the second entry is updated to the first address to obtain the first entry; or If a second entry exists corresponding to the first value bundle in the branch prediction structure, and the position field of the second entry does not include the first position value, then the first address is written into the target address field of the second entry, and the first position value is written into the position field of the second entry to obtain the first entry; or If no entry corresponding to the first value bundle exists in the branch prediction structure, the first entry corresponding to the first value bundle is added to the branch prediction structure. The first address is written into the target address field of the first entry, and the first position value is written into the position field of the first entry. The tag field of the first entry is the first to the nth bit from high to low in the execution pointer of the first instruction, wherein the index value of the first entry is the (n+1)th to the (n+k)th bit from high to low in the execution pointer of the first instruction.

5. The method according to claim 1, characterized in that, The processor stores the first address and the first location value in the branch prediction structure in the following manner: The first instruction was detected, and the user jumped to the first address. If a second entry corresponding to the first instruction exists in the branch prediction structure, and the position field of the second entry is the first position value, then the third address corresponding to the first position value in the target address field of the second entry is updated to the first address to obtain the first entry; or If no entry matching the first instruction exists in the branch prediction structure, the first entry corresponding to the first instruction is added to the branch prediction structure. The first address is written into the target address field of the first entry, and the first position value is written into the position field of the first entry. The tag field of the first entry is the first to the nth bit from high to low in the execution pointer of the first instruction, wherein the index value of the first entry is the (n+1)th to the (n+k)th bit from high to low in the execution pointer of the first instruction.

6. The method according to claim 1, characterized in that, The first digit to the nth digit of the instruction pointer of the first instruction, from high to low, is the same as the first tag value of the tag field in the first entry. The (n+1)th digit to the (n+k)th digit of the instruction pointer of the first instruction, from high to low, is the same as the first index value corresponding to the first entry. The (n+k+1)th digit to the (n+k+m)th digit of the instruction pointer of the first instruction, from high to low, is the same as the first position value of the position field in the first entry. The index value is the (n+1)th digit to the (n+k)th digit of the instruction pointer of the branch instruction, from high to low. The position value is the (n+k+1)th digit to the (n+k+m)th digit of the instruction pointer of the branch instruction, from high to low.

7. The method according to claim 2, characterized in that, The jump to the first address includes: Increment the jump count value in the prediction execution field of the first entry, and jump to the first address.

8. An electronic device, characterized in that, include: Memory is used to store instructions executed by one or more processors of an electronic device; And a processor, one of the processors of the electronic device, for running the instructions to enable the electronic device to implement the instruction execution method of any one of claims 1 to 7.

9. A readable medium, characterized in that, The readable medium contains instructions that, when executed by the processor of the electronic device, cause the electronic device to implement the instruction execution method according to any one of claims 1 to 7.

Images