Priority scheduling module and chip

Abstract

The invention discloses a priority scheduling module and a chip, which are used for realizing priority scheduling under the condition that a CPU (Central Processing Unit) does not participate in. The priority scheduling module comprises a plurality of input data cache units and a priority scheduling unit; the plurality of input data cache units are used for receiving multiple paths of input data; the plurality of input data cache units are not provided with external read-write address lines; the multiple paths of input data have different priorities when being processed by the processing module; the input end of the priority scheduling unit is connected with the output ends of the input data caching units, and the priority scheduling unit is used for sorting the multiple paths of input data according to the priority of each path of input data and inputting the sorted input data into the processing module in sequence; and the processing module is used for processing the multi-path input data according to the priority of the multi-path input data.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a priority scheduling module and chip. Background Art

[0002] Priority refers to the priority assigned to a task by the computer operating system, which determines the priority of tasks in using resources. The priority assigned to a device can determine the order in which the device receives a processor response when making an interrupt request. Task scheduling priority mainly refers to the priority of a task when it is scheduled to run, which is mainly related to the priority of the task itself and the scheduling algorithm. Especially in real-time systems, task scheduling priority reflects the importance and urgency of a task.

[0003] Existing priority scheduling is all allocated and scheduled by the central processing unit (CPU). This priority scheduling method through the CPU requires a lot of CPU response and processing time, resulting in high data delay.

[0004] Therefore, there is an urgent need for a solution to implement priority scheduling without CPU involvement. Summary of the invention

[0005] The present application provides a priority scheduling module and a chip for implementing priority scheduling without the participation of a CPU.

[0006] In a first aspect, the present application provides a priority scheduling module, comprising a plurality of input data cache units and a priority scheduling unit;

[0007] The multiple input data buffer units are used to receive multiple input data; the multiple input data buffer units do not have external read and write address lines; the multiple input data have different priorities when processed by the processing module;

[0008] The input end of the priority scheduling unit is connected to the output ends of the multiple input data cache units, and is used to sort the multiple input data according to the priority of each input data, and input the sorted input data into the processing module in sequence; the processing module is used to process the multiple input data according to the priority of the multiple input data.

[0009] In the above technical solution, a priority scheduling unit is introduced, which sorts multiple input data according to priority, and inputs the sorted input data into the processing module in sequence, so that the processing unit can process the input data according to the priority order. This can realize priority scheduling of multiple input data at the data level without the participation of the CPU, thereby greatly reducing the response time while reducing the use of the CPU, and realizing quick and simple priority scheduling of multiple input data.

[0010] In a possible design, the priority scheduling unit further includes a plurality of data channels with priorities; each data channel corresponds to a storage address;

[0011] The priority scheduling unit is specifically used to obtain corresponding input data from the input data cache unit corresponding to each input data path, and store it in a data channel corresponding to the priority of each input data path;

[0012] The priority scheduling unit is specifically used to input the multiple input data into the processing module according to the priority order of multiple data channels from high to low.

[0013] In the above technical solution, the data channel has a priority, and the input data in the input data cache unit connected to the data channel has the same priority as the data channel. Based on the priority of the data channel, multiple input data are input to the processing module in order from high to low priority to implement priority scheduling of multiple data, which can reduce the load of hardware design and can directly implement priority processing of multiple input data without the involvement of the CPU.

[0014] In a possible design, each data channel of the priority scheduling unit has a respective input flag bit; the input flag bit is used to indicate that the data channel has data input;

[0015] The priority scheduling unit is also used to determine whether the input flag bit of the data channel with the highest priority is a first value; if so, output the input data of the data channel with the highest priority; otherwise, determine whether the input flag bit of the data channel with the next priority is valid, until the input flag bits of the multiple data channels are all second values; the flag bit being the first value indicates that the corresponding data channel has data input; the flag bit being the second value indicates that the corresponding data channel has no data input.

[0016] In the above technical solution, by setting the flag bit of the data channel, it can be clearly known whether there is data input in each data channel, so that the priority scheduling unit can sort the priorities of multiple input data more accurately.

[0017] In one possible design, the priority scheduling module further includes a priority management unit;

[0018] The priority management unit is used to receive a priority adjustment instruction; the priority scheduling instruction includes a corresponding relationship between an input data cache unit and a data channel;

[0019] The priority management unit is further used to change the storage address of the data channel corresponding to the input data cache unit according to the priority adjustment instruction.

[0020] In the above technical solution, the corresponding relationship between the input data cache unit and the data channel can be dynamically adjusted by the priority management unit, thereby adjusting the priority of the input data, so as to more flexibly implement the priority scheduling of multi-channel input data.

[0021] In one possible design, the priority scheduling module further includes a data screening unit;

[0022] The input end of the data screening unit is connected to the multiple input data cache units, and the output end of the data screening unit is connected to the priority scheduling unit, for screening out data satisfying set screening conditions from the multiple input data and directly inputting them into the processing module.

[0023] In the above technical solution, the most needed data can be screened out from multiple data channels before priority scheduling through the data screening unit, so as to increase the flexibility of input data priority scheduling.

[0024] In one possible design, the priority scheduling module further includes a data reassembly unit;

[0025] The input end of the data reorganization unit is connected to the output end of the priority scheduling unit, and is used to adjust the data format of the sorted input data.

[0026] In the above technical solution, the data format of the sorted input data is adjusted by the data reorganization unit, so as to increase the diversity of data processing.

[0027] In one possible design, the priority scheduling module further includes an output data cache unit;

[0028] The input end of the output data cache unit is connected to the output end of the data reorganization unit, and the output end of the output data cache unit is connected to the processing module for temporarily storing the sorted input data and waiting for the processing module to receive it.

[0029] In the above technical solution, data that does not need to be output temporarily can be temporarily stored by the data cache unit and received when needed by the data processing module, so as to increase the flexibility of the priority scheduling module.

[0030] In a possible design, the input data cache unit and the output data cache unit are first-in-first-out storage units.

[0031] In the above technical solution, the first-in-first-out storage unit has a simple structure, the data read and write logic is simple and the read and write speed is fast. The input data cache unit and the output data cache unit use the first-in-first-out storage unit to make the structure of the priority scheduling module simpler and the data processing speed faster.

[0032] In a second aspect, an embodiment of the present application provides a chip, the chip comprising a priority scheduling module, a multi-channel input module, and a processing module in any possible design of the first aspect;

[0033] The multi-channel input module is connected to the multiple input data buffer units in the priority scheduling module respectively, and is used to output the multi-channel input data;

[0034] The processing module is connected to the output end of the priority scheduling module, and is used to obtain and process the input data sorted by the priority scheduling module. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 1 ;

[0037] Figure 2 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 2 ;

[0038] Figure 3 The intention of the priority sorting logic of a priority scheduling unit provided in an embodiment of the present application;

[0039] Figure 4 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 3 ;

[0040] Figure 5 A schematic diagram of the corresponding relationship between the input data buffer unit and the data channel provided in an embodiment of the present application;

[0041] Figure 6 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 4 ;

[0042] Figure 7 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 5 ;

[0043] Figure 8 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 6 ;

[0044] Fig. 9 A schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0046] In the embodiments of the present application, a plurality refers to two or more than two. The words "first", "second" and the like are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance or order.

[0047] Figure 1 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the priority scheduling module 100 includes a plurality of input data buffer units 110 and a priority scheduling unit 120 .

[0048] The multiple input data cache units 110 are used to receive multiple input data. The input data cache unit 100 is scalable. The present application does not specifically limit the number of the input data cache units 110. The data volume of the specific input data cache unit 110 can be set according to actual needs. For example, Figure 1 The priority scheduling module in the embodiment includes input data cache units 110-1 to 110-4, a total of 4 input data cache units. Among them, multiple input data cache units 110 do not have external read and write address lines. Exemplarily, the input data storage unit can be a first-in-first-out storage unit, which has the characteristics of simple structure and high speed. The present application is applied to the scenario where multiple input data are to be input to the same processing module for processing, and the multiple input data have different priorities when being processed by the processing module 200.

[0049] The input end of the priority scheduling unit 120 is connected to the output ends of the multiple input data buffer units 110, and is used to sort the multiple input data according to the priority of each input data, and sequentially input the sorted input data to the processing module 200. The processing module 200 is used to process the multiple input data according to the priority of the multiple input data.

[0050] In the above technical solution, a priority scheduling unit is introduced, which sorts multiple input data according to priority, and inputs the sorted input data into the processing module in sequence, so that the processing unit can process the input data according to the priority order, thereby realizing priority scheduling of multiple input data at the data level without the participation of the CPU, reducing the use of the CPU and greatly reducing the response time, thereby realizing quick and simple priority scheduling of multiple input data.

[0051] Figure 2 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 2 ,like Figure 2 As shown, the priority scheduling unit 120 also includes a plurality of data channels with priorities, and the number of data channels is generally consistent with the number of input data cache units. For example, referring to Figure 2 , corresponding to the four input data cache units 110-1 to 110-4, data channels 1 to 4 are set in the priority scheduling unit. Each data channel corresponds to a storage address, and each storage address is pre-set with a corresponding priority. In this way, when an input data cache unit is connected to a data channel, the input data in the input data storage unit has the same priority as the storage address of the data channel. In other words, the input data cache unit that receives the input data with the highest priority is connected to the storage address with the highest priority, and the input data cache unit that receives the input data with the second priority is connected to the storage address with the second priority, and so on.

[0052] The priority scheduling unit 120 is specifically used to obtain the corresponding input data from the input data cache unit 110 corresponding to each input data path, and store it in the data channel corresponding to the priority of each input data path. The priority scheduling unit 120 is specifically used to input the multiple input data paths into the processing module in the order of the priorities of the multiple data paths from high to low.

[0053] by Figure 2For example, assuming that the storage addresses of data channels 1 to 4 are address 1, address 2, address 3, and address 4, respectively, and the priority order is address 1> address 2> address 3> address 4, the priority of the input data in the input data cache unit is input data cache unit 110-1> input data cache unit 110-2> input data cache unit 110-3> input data cache unit 110-4. Then the input data cache unit 110-1 is connected to data channel 1, that is, connected to address 1, the input data cache unit 110-2 is connected to data channel 2, that is, connected to address 2, the input data cache unit 110-3 is connected to address 3, and the input data cache unit 110-4 is connected to address 4. Then in actual application, the priority scheduling unit 120 obtains the corresponding input data 1 from the input data cache unit 110-1 and stores it in the data channel 1, obtains the corresponding input data 2, input data 3, and input data 4 from the input data cache units 110-2, 110-3, and 110-4, and stores them in the data channels 2, 3, and 4, respectively. In this way, the priority scheduling unit 120 can input the multiple input data into the processing module in the order of input data 1, input data 2, input data 3, and input data 4 according to the order of the data channel priorities from high to low. The processing module processes the data in the order of input data 1, input data 2, input data 3, and input data 4.

[0054] In the above technical solution, the data channel has a priority, and the input data in the input data cache unit connected to the data channel has the same priority as the data channel. Based on the priority of the data channel, multiple input data are input to the processing module in order from high to low priority to implement priority scheduling of multiple data, which can reduce the load of hardware design and can directly implement priority processing of multiple input data without the involvement of the CPU.

[0055] In a possible design, each data channel of the priority scheduling unit has its own input flag bit, and the input flag bit is used to indicate that the data channel has data input. When data is input in the data channel, the input flag bit of the data channel is set to the first value; when there is no data input in the data channel, the input flag bit of the data channel is set to the second value, wherein the first value may be 1 and the second value may be 0. The priority scheduling unit is also used to determine whether the input flag bit of the data channel with the highest priority is the first value; if so, output the input data of the data channel with the highest priority; otherwise, determine whether the input flag bit of the data channel with the next priority is valid, until the input flag bits of multiple data channels are all the second value.

[0056] by Figure 2For example, assuming that the priority order of the data channels is data channel 1> data channel 2> data channel 3> data channel 4, the input flag bits of data channels 1 to 4 are S1, S2, S3 and S4 respectively, and the value of the flag bit is 1, indicating that there is data input in the data channel. The priority sorting logic of the priority scheduling unit refers to Figure 3 , specifically including the following steps:

[0057] Step 301 , determine whether the flag bit S1 is 1; if so, execute step 302 ; otherwise, execute step 303 .

[0058] Step 302: Output data channel 1 data.

[0059] After executing step 302, continue to execute step 301.

[0060] Step 303 , determine whether the flag bit S2 is 1; if so, execute step 304 ; otherwise, execute step 305 .

[0061] Step 304: Output data channel 2 data.

[0062] After executing step 304, continue to execute step 301.

[0063] Step 305 , determine whether the flag bit S3 is 1; if so, execute step 306 ; otherwise, execute step 307 .

[0064] Step 306: Output data channel 3 data.

[0065] After executing step 306 , continue to execute step 301 .

[0066] Step 307 , determine whether the flag bit S4 is 1; if so, execute step 308 ; otherwise, execute step 309 .

[0067] Step 308: Output data channel 4 data.

[0068] After executing step 308 , continue to execute step 301 .

[0069] Step 309: No data output, continue to execute step 301.

[0070] In a possible implementation, for an unenabled data channel, the data flag bit may be set to the second value until the data channel is enabled. For example, when the number of external input data paths is small, some input data cache units and corresponding data channels are idle. In this case, the flag bit of the idle data channel may be set to the second value until the data channel is enabled.

[0071] Figure 4A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 3 ,like Figure 4 As shown, the priority scheduling module also includes a priority management unit 130;

[0072] The priority management unit 130 is used to receive a priority adjustment instruction, wherein the priority scheduling instruction includes a corresponding relationship between the input data buffer unit 110 and the data channel. The priority scheduling instruction can be sent by a host computer or an upper control chip.

[0073] The priority management unit 130 is further configured to change the storage address of the data channel corresponding to the input data cache unit 110 according to the priority adjustment instruction.

[0074] refer to Figure 5 , Figure 5 (a) is the original correspondence between the input data cache units and the data channels. The input data cache units 110-1 to 110-4 are connected to data channels 1 to 4 respectively, that is, the priority order of the storage addresses is storage address 1> storage address 2> storage address 3> storage address 4, and the corresponding data channel priorities are data channel 1> data channel 2> data channel 3> data channel 4. Then the priority of the input data obtained from the input data cache units is input data cache unit 110-1> input data cache unit 110-2> input data cache unit 110-3> input data cache unit 110-4. Now we want to change the priority of the input data obtained from the input data cache units to input data cache unit 110-4> input data cache unit 110-3> input data cache unit 110-2> input data cache unit 110-1. Then, Figure 5 (b) The corresponding relationship between the input data cache units and the data channels can be changed to that the input data cache units 110-1 to 110-4 are connected to data channels 4 to 1 respectively, that is, the storage address of the input data cache unit 110-1 is changed to storage address 4, and the storage addresses of the input data cache units 110-2, 110-3 and 110-4 are changed to storage address 3, storage address 2 and storage address 1 respectively. Then, the priority of the input data is adjusted.

[0075] In the above technical solution, the corresponding relationship between the input data cache unit and the data channel can be dynamically adjusted by the priority management unit, thereby adjusting the priority of the input data, so as to more flexibly implement the priority scheduling of multi-channel input data.

[0076] It should be noted that when the priority scheduling unit is configured, the input data can be connected to the input data cache unit of the corresponding priority in the order of priority. After the priority scheduling unit is configured, the relationship between the input data and the input data cache unit is fixed, and the dynamic adjustment of the input data priority can be achieved by changing the data channel connecting the input data cache unit to the input cache unit.

[0077] Figure 6 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 4 ,like Figure 6 As shown, the priority scheduling module also includes a data screening unit 140 .

[0078] The input end of the data filtering unit 140 is connected to multiple input data cache units 110, and the output end of the data filtering unit 140 is connected to the priority scheduling unit 120, which is used to filter out data that meets the set filtering conditions from multiple input data and directly input it to the processing module 200 to increase the flexibility of input data priority scheduling.

[0079] Specifically, the setting of the screening condition can be set by the host computer or the upper control chip, and the priority management unit 130 receives the screening condition setting instruction of the host computer or the upper control chip. Among them, the setting of the screening condition can be to filter out data starting with a specific data type or a specific character, for example, to filter out data starting with 10374. The data screening unit 140 stores a set data for screening (the specific data meets the set screening condition) at a fixed address, and then compares the input data with the set data respectively. If the comparison results are consistent, the input data meets the set screening condition and is directly input into the processing module 200. For the input data with inconsistent comparison results, it is processed by the priority scheduling unit 120. In another embodiment, the input data that meets the set screening condition can also be temporarily stored and finally input into the processing module 200.

[0080] Figure 7 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 5 ,like Figure 7 As shown, the priority scheduling module further includes a data reassembly unit 150 .

[0081] The input end of the data reorganization unit 150 is connected to the output end of the priority scheduling unit 120, and is used to adjust the data format of the sorted input data. For example, the data reorganization unit 150 can perform processing such as adding header data, adding parity bits, adjusting data bits, changing data length, and adjusting flag bits on the data output by the priority scheduling unit, thereby increasing the diversity of data processing.

[0082] Figure 8 A structural diagram of a priority scheduling module provided in an embodiment of the present application Figure 6 ,like Figure 8 As shown, the priority scheduling module also includes an output data buffer unit 160 .

[0083] The input end of the output data cache unit 160 is connected to the output end of the data reorganization unit 150, and the output end of the output data cache unit 160 is connected to the processing module 200, and is used to temporarily store the sorted input data, waiting for the processing module 200 to receive it, so as to increase the flexibility of the priority scheduling module. Among them, the output data storage unit can be a first-in-first-out storage unit.

[0084] Based on the same technical concept, Fig. 9 A schematic diagram of the structure of a chip provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the chip 900 includes: a priority scheduling module 100, a multi-channel input module 300 and a processing module 200;

[0085] The multi-channel input module 300 is respectively connected to the multiple input data buffer units 110 in the priority scheduling module 100, and is used to output the multi-channel input data.

[0086] The processing module 200 is connected to the output end of the priority scheduling module 100 and is used to obtain and process the input data sorted by the priority scheduling module 100.

[0087] In one application scenario, the above chip can be an RFID chip. After the RFID chip receives the dual-antenna signal, it is internally demodulated and then output. The dual-antenna signal is a 10374 signal and a 18000C signal. The two signals have priorities. When the two signals are input into the RFID chip, the priority scheduling module sorts the input signals according to the priority, and sends the sorted input signals to the encoding and decoding module for modulation and demodulation, and finally outputs them.

[0088] The above chip or priority scheduling module can also be applied in the real-time voice translation module, specifically used in the real-time voice translation process of multi-person dialogue. In the real-time voice translation process of multi-person dialogue, after the audio is input, multiple audio data will be separated according to the band, voiceprint, etc. of the voice, each audio data corresponds to the voice of a user, and the multiple audio data needs to be sent to the translation module for translation according to the priority. Translation speed is a very important indicator for translation software. If the priority of multiple audio data is processed by the CPU, the timing and processing speed of the CPU need to be fast enough. The chip or priority scheduling module provided by this application can realize the priority scheduling of multiple audio without the participation of the CPU, which can save costs and reduce the requirements of the CPU and clock, increase the translation rate, reduce data delay, and finally increase the translation speed of real-time voice. In a possible implementation, the priority scheduling module can also be combined with the CPU to schedule the priority of multiple audio.

[0089] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0090] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A priority scheduling module, characterized in that: including a plurality of input data buffer units and a priority scheduling unit; The multiple input data buffer units are used to receive multiple input data; the multiple input data buffer units do not have external read and write address lines; the multiple input data have different priorities when processed by the processing module; The input end of the priority scheduling unit is connected to the output ends of the multiple input data cache units, and is used to sort the multiple input data according to the priority of each input data, and input the sorted input data into the processing module in sequence; The processing module is used to process the multiple input data according to the priority of the multiple input data.

2. The priority scheduling module according to claim 1, characterized in that: The priority scheduling unit also includes a plurality of data channels with priorities; each data channel corresponds to a storage address; The priority scheduling unit is specifically used to obtain corresponding input data from the input data cache unit corresponding to each input data path, and store it in a data channel corresponding to the priority of each input data path; The priority scheduling unit is specifically used to input the multiple input data into the processing module according to the priority order of multiple data channels from high to low.

3. The priority scheduling module according to claim 2, characterized in that: Each data channel of the priority scheduling unit has a respective input flag bit; the input flag bit is used to indicate that the data channel has data input; The priority scheduling unit is further configured to determine whether the input flag bit of the data channel with the highest priority is the first value; if so, output the input data of the data channel with the highest priority; otherwise, determine whether the input flag bit of the data channel with the next priority is valid, until the input flag bits of the multiple data channels are all the second value; The first value of the flag bit indicates that the corresponding data channel has data input; The flag bit being the second value indicates that there is no data input into the corresponding data channel.

4. The priority scheduling module according to claim 2, characterized in that: The priority scheduling module also includes a priority management unit; The priority management unit is used to receive a priority adjustment instruction; the priority scheduling instruction includes a corresponding relationship between an input data cache unit and a data channel; The priority management unit is further used to change the storage address of the data channel corresponding to the input data cache unit according to the priority adjustment instruction.

5. The priority scheduling module according to any one of claims 1 to 4, characterized in that: The priority scheduling module also includes a data screening unit; The input end of the data screening unit is connected to the multiple input data cache units, and the output end of the data screening unit is connected to the priority scheduling unit, for screening out data satisfying set screening conditions from the multiple input data, and directly inputting the data into the processing module.

6. The priority scheduling module according to any one of claims 1 to 4, characterized in that: The priority scheduling module also includes a data reorganization unit; The input end of the data reorganization unit is connected to the output end of the priority scheduling unit, and is used to adjust the data format of the sorted input data.

7. The priority scheduling module according to claim 6, characterized in that: The priority scheduling module also includes an output data cache unit; The input end of the output data cache unit is connected to the output end of the data reorganization unit, and the output end of the output data cache unit is connected to the processing module for temporarily storing the sorted input data and waiting for the processing module to receive it.

8. The priority scheduling module according to claim 7, characterized in that: The input data cache unit and the output data cache unit are first-in-first-out storage units.

9. A chip, characterized in that: It comprises the priority scheduling module, the multi-channel input module and the processing module according to any one of claims 1 to 8; The multi-channel input module is connected to the multiple input data buffer units in the priority scheduling module respectively, and is used to output the multi-channel input data; The processing module is connected to the output end of the priority scheduling module, and is used to obtain and process the input data sorted by the priority scheduling module.

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