Method and device for memory management based on page linked list, equipment and medium

Abstract

The invention provides a method, device and equipment for memory management based on a page linked list and a medium, and relates to the technical field of memory management. The method comprises the following steps: in response to a received page access request, determining an accessed page based on the page access request; lifting the accessed page from the page sub-linked list of the current level to the page sub-linked list of the higher level; and in response to detection that the page number of the highest-level page sub-linked list reaches a preset threshold value, recovering the memory of the lowest-level page sub-linked list, and executing a degradation operation on each level of page sub-linked list in the page linked list. According to the method and the device, the memory can be managed more reasonably, the recovery and calling efficiency of the memory is improved, the utilization rate of the memory is improved, and delay and lagging caused by page recovery can be effectively reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, specifically to the field of memory management technology, and in particular to a method, device, equipment and medium for performing memory management based on a page linked list. Background Art

[0002] In the actual application of the current memory recycling mechanism, when a page is shared by many processes, such as when there are many processes (for example, 100 processes), it is necessary to use reverse mapping technology to find the memory page table of each process and read the reference bit of PTE (Page Table Entry) one by one. This is a very long process. When entering the memory recycling path, the system usually has very little free memory, and the above process required for recycling often causes system lag. Summary of the invention

[0003] The embodiments of the present disclosure provide a method, apparatus, device and medium for memory management based on a page linked list.

[0004] In the first aspect, an embodiment of the present disclosure proposes a method for memory management based on a page linked list, including: in response to receiving a page access request, determining the accessed page based on the page access request; promoting the accessed page from the current level page sub-linked list to a higher level page sub-linked list; in response to detecting that the number of pages in the highest level page sub-linked list reaches a preset threshold, reclaiming the memory of the lowest level page sub-linked list, and performing downgrade operations on the page sub-linked lists at all levels in the page linked list.

[0005] In the second aspect, the embodiments of the present disclosure propose a device for memory management based on a page linked list, including: an access page determination module, configured to determine the accessed page based on the page access request in response to receiving the page access request; a page sub-link list adjustment module, configured to promote the accessed page from the current level page sub-link list to a higher level page sub-link list; a page sub-link list recycling module, configured to recycle the memory of the lowest level page sub-link list in response to detecting that the number of pages in the highest level page sub-link list reaches a preset threshold, and perform downgrade operations on the page sub-link lists at all levels in the page linked list.

[0006] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that when the at least one processor executes, it is able to implement the method for memory management based on a page linked list as described in any implementation method in the first aspect.

[0007] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, which are used to enable a computer to implement the method of memory management based on a page linked list as described in any implementation method of the first aspect when executed.

[0008] In a fifth aspect, an embodiment of the present disclosure provides a computer program product including a computer program, which, when executed by a processor, can implement the method for memory management based on a page linked list as described in any implementation method in the first aspect.

[0009] Through the constructed multi-level page sub-list architecture, the highest-level page sub-list is supervised, and memory is recycled when the number of pages in the highest-level page sub-list approaches the threshold, without relying on the memory watermark limit. In addition, through this active page recycling method, memory can be managed more reasonably, memory recycling and call efficiency can be improved, memory utilization can be improved, and delays caused by page recycling can be effectively reduced.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Other features, objects and advantages of the present disclosure will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0012] Figure 1 is an exemplary system architecture in which the present disclosure may be applied;

[0013] Figure 2 A flowchart of a method for memory management based on a page linked list provided in an embodiment of the present disclosure;

[0014] Figure 3 A schematic diagram of the structure of a page link list provided in an embodiment of the present disclosure;

[0015] Figure 4 A flowchart of another method for memory management based on a page linked list provided in an embodiment of the present disclosure;

[0016] Figure 5 A schematic diagram of the structure of another page link list provided in an embodiment of the present disclosure;

[0017] Figure 6 A schematic diagram of a method for performing memory management based on a page linked list in an application scenario provided by an embodiment of the present disclosure;

[0018] Figure 7 A structural block diagram of a device for performing memory management based on a page linked list provided in an embodiment of the present disclosure;

[0019] Figure 8 A structural block diagram of another device for performing memory management based on a page linked list provided in an embodiment of the present disclosure;

[0020] Fig. 9 A schematic diagram of the structure of an electronic device suitable for executing a method for memory management based on a page linked list provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description. It should be noted that the embodiments in the present disclosure and the features in the embodiments may be combined with each other without conflict.

[0022] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0023] First, the terms involved in the embodiments of the present disclosure are briefly introduced:

[0024] Memory: It is an important part of the computer, also known as internal memory and main memory, which is used to temporarily store the calculation data in the central processing unit (CPU) and the data exchanged with external memory such as hard disk. Memory can include physical memory and virtual memory.

[0025] SWAP (Exchange): When the physical memory of the computer system is insufficient, part of the storage space in the physical memory is released and temporarily saved in a pre-set storage space. Swap-Out: When a large number of processes are started in the computer system, the computer's operating system temporarily stores the infrequently used physical memory in the SWAP device through memory swap technology.

[0026] Memory page: The heap and stack data pages that are dynamically allocated when a computer system process is running.

[0027] Least Recently Used (LRU) algorithm: refers to a commonly used algorithm in computer systems. By maintaining an LRU linked list, the computer system can quickly find the memory data that has not been used for the longest time.

[0028] Transparent Huge Page (THP): It is a memory management optimization technology in Linux system.

[0029] LS (Latency-Sensitive) is latency-sensitive. LS loads latency-sensitive services, which may generally be online services.

[0030] Figure 1 An exemplary system architecture 100 is shown to which embodiments of the method, apparatus, electronic device, and computer-readable storage medium for performing memory management based on a page linked list of the present disclosure can be applied.

[0031] like Figure 1 As shown, the system architecture 100 may include terminal devices 101, 102, 103, a network 104 and a server 105. The network 104 is used to provide a medium for communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired, wireless communication links or optical fiber cables, etc.

[0032] Users can use terminal devices 101, 102, 103 to interact with server 105 through network 104 to receive or send messages, etc. Terminal devices 101, 102, 103 and server 105 may be installed with various applications for realizing information communication between the two, such as instant messaging applications.

[0033] Terminal devices 101, 102, 103 and server 105 can be hardware or software. When terminal devices 101, 102, 103 are hardware, they can be various electronic devices with display screens, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, etc.; when terminal devices 101, 102, 103 are software, they can be installed in the electronic devices listed above, which can be implemented as multiple software or software modules, or as a single software or software module, and no specific limitation is made here. When server 105 is hardware, it can be implemented as a distributed server cluster composed of multiple servers, or as a single server; when the server is software, it can be implemented as multiple software or software modules, or as a single software or software module, and no specific limitation is made here.

[0034] The methods for memory management based on page linked lists provided in the subsequent embodiments of the present disclosure are generally performed by the server 105 with strong computing power and more computing resources. Accordingly, the device for memory management based on page linked lists is generally also set in the server 105. However, it should also be pointed out that when the terminal devices 101, 102, and 103 also have computing power and computing resources that meet the requirements, the terminal devices 101, 102, and 103 can also complete the above-mentioned various operations that are handed over to the server 105, and then output the same results as the server 105. Especially in the case where there are multiple terminal devices with different computing capabilities at the same time, but the system determines that the terminal device has strong computing power and more remaining computing resources, the terminal device can be allowed to perform the above-mentioned operations, thereby appropriately reducing the computing pressure of the server 105. Accordingly, the device for memory management based on page linked lists can also be set in the terminal devices 101, 102, and 103. In this case, the exemplary system architecture 100 may also not include the server 105 and the network 104.

[0035] It should be understood that Figure 1 The number of terminal devices, networks and servers in the embodiment is only for illustration. Any number of terminal devices, networks and servers may be provided according to implementation requirements.

[0036] Please refer to Figure 2 , Figure 2 A flowchart of a method for memory management based on a page linked list provided in an embodiment of the present disclosure, wherein process 200 includes the following steps:

[0037] Step 201: In response to receiving a page access request, determine an accessed page based on the page access request.

[0038] Memory is a very important resource of the operating system. To run a program, the operating system must first load the instructions of the program code segment and the variables of the data segment from the hard disk into the memory before it can be run. In this embodiment, the execution body of the method for memory management based on the page list (for example Figure 1 The server 105 shown in FIG. 1 mainly manages memory through a paging memory management mechanism, which divides the entire memory into fixed-size pages (usually 4KB). Specifically, memory pages can be managed through a data structure called a page list, which contains multiple levels of page sub-lists, such as Figure 3 When a process requests memory, the execution subject can determine the page to be accessed based on the received page access request.

[0039] Step 202: The accessed page is promoted from the current level page sub-link list to a higher level page sub-link list.

[0040] This step is intended to manage memory pages through a multi-level page sub-link list by the above-mentioned execution subject. When a page at a certain level is accessed, the accessed page is promoted from the page sub-link list of the current level to the page sub-link list of a higher level. For example Figure 3 In the page linked list shown, the levels of the multi-level page sub-linked lists from low to high are: MinList, Min+1List, Min+2List, Min+3List, Max List. When a page in the Min List is accessed, the page is promoted from the Min List to the Min+1List, and so on. Moreover, for the same page, each time it is accessed, it will be promoted to a higher level page sub-linked list. It should be noted that the levels of the page sub-linked lists of different levels described in this embodiment are only used to distinguish the page sub-linked lists of different levels, and do not represent the differences in the priorities of different page sub-linked lists.

[0041] Step 203: In response to detecting that the number of pages in the highest-level page sub-link list reaches a preset threshold, the memory of the lowest-level page sub-link list is reclaimed, and downgrading operations are performed on the page sub-link lists at all levels in the page link list.

[0042] This step is intended to enable the above-mentioned execution subject to detect in real time the number of pages in the highest-level page sub-list of the page list, or the number of members, which usually refers to the number of physical pages that a page table entry (PTE) can point to. If the number of pages reaches the preset threshold, it indicates that the current page list has a large number of pages and the memory needs to be released accordingly. Accordingly, the execution subject can reclaim the memory of the lowest-level page sub-list and perform downgrade operations on the page sub-lists at all levels in the page list. Figure 3 Taking the page list structure shown in FIG. 1 as an example, if the number of pages in the Max List reaches a preset threshold (for a five-level page list, the preset threshold can be set to 512, for example, and for page lists of different levels, the preset threshold can be set accordingly, and is not limited thereto), the memory in the Min List is recycled, and the page sublists of the Min+1List, Min+2List, Min+3List, and Max List are downgraded. In this way, the memory in the original Min List is released.

[0043] The method for memory management based on page linked lists provided by the disclosed embodiment supervises the highest-level page linked lists through the constructed multi-level page sub-link list architecture, and recycles memory when the number of pages in the highest-level page sub-link list approaches a threshold, without relying on the memory waterline limit. Moreover, by actively recycling pages in this way, the memory can be managed more reasonably, the efficiency of memory recycling and calling can be improved, the memory utilization rate can be improved, and the delay caused by page recycling can be effectively reduced.

[0044] In some optional implementations of this embodiment, in the above step 203, the page sub-linked lists at all levels in the page linked list are downgraded, mainly including: downgrading the page sub-linked lists at all levels except the lowest level page sub-linked list by one level, wherein the highest level page sub-linked list after the downgrade is empty. Figure 3 Taking the page list structure shown in the figure as an example, if the number of pages in the Max List reaches the preset threshold, the memory in the Min List will be recycled, and the page sublists of Min+1List, Min+2List, Min+3List, and Max List will be downgraded. Min+1list becomes Min list, Min+2list becomes Min+1list, Min+3List becomes Min+2List, and Max List becomes empty. Since the original Min List page sublist itself is at the lowest level, its memory is recycled and adjusted to Max List accordingly. After such a downgrade operation, the page list is still a hierarchical relationship of Min List, Min+1List, Min+2List, Min+3List, and Max List, but the page content in each level has changed. In the subsequent operation process, if the page in Min+3List is accessed again, the upgrade operation can be continued to promote the page in Min+3List to Max List.

[0045] As an example, the above process of lowering the page sub-lists of all levels except the lowest-level page sub-list by one level does not require moving the pages, but only requires changing the sequence number of the link head. Specifically, the process mainly includes: adjusting the sequence number of the link head of the page sub-lists of all levels except the lowest-level page sub-list to the sequence number of the link head of the lower-level page sub-list; adjusting the sequence number of the link head of the lowest-level page sub-list to the sequence number of the link head of the highest-level page sub-list. Figure 3Taking the page linked list structure shown in the figure as an example, the linked list head numbers of the original Min+1List, Min+2List, Min+3List, and Max List are adjusted to Min List, Min+1List, Min+2List, and Min+3List respectively, and the linked list head number of the original Min List is adjusted to Max List, thus completing the above-mentioned downgrading operation.

[0046] In practical applications, when the execution subject of the method for memory management based on page linked lists performs memory recycling, it can mainly recycle the memory pages that can be directly released, but there are also some pages whose contents cannot be directly released and need to be aligned and transferred before being released and recycled. For such pages, the cold page swap out technology (cold page swap out technology is a strategy in operating system memory management, which is used to replace pages that have not been accessed for a long time or have a very low access frequency from the memory when memory resources are tight, so as to free up space for other more active pages. This technology is usually used in combination with swap space to store the replaced pages in the swap space on the disk so that they can be reloaded into the memory when needed) can be used to transfer the contents of the page to the hard disk before memory recycling. In this way, it is ensured that the contents of the page will not be lost due to memory recycling, and the memory utilization rate can be further improved.

[0047] Please refer to Figure 4 , Figure 4 A flowchart of another method for memory management based on a page linked list provided in an embodiment of the present disclosure, wherein process 400 includes the following steps:

[0048] Step 401: In response to receiving a page access request, determine an accessed page based on the page access request.

[0049] In this embodiment, the execution body of the method for performing memory management based on the page list (for example Figure 1 The server 105 shown in FIG. 1 mainly manages memory through a paging memory management mechanism, which divides the entire memory into fixed-size pages (usually 4KB). Specifically, memory pages can be managed through a data structure called a page list, which contains multiple levels of page sublists. When a process requests memory, the execution subject can determine the page to be accessed based on the received page access request. Figure 5As shown, the page list includes a high-order class page list (HighLevel area) and a low-order class page list (Low Level area). The high-order class page list and the low-order class page list respectively contain multiple levels of page sub-lists. The high-order class page list corresponds to latency-sensitive loads (Latency-SensitiveLoad), and the low-order class page list corresponds to non-latency-sensitive loads (such as best effort load, Best EffortLoad).

[0050] Step 402: Promote the accessed page from the current level page sub-link list to a higher level page sub-link list.

[0051] Step 403: In response to detecting that the number of pages in the highest-level page sub-linked list reaches a preset threshold, the memory of the lowest-level page sub-linked list is reclaimed, and downgrading operations are performed on the page sub-linked lists at all levels in the page linked list.

[0052] The above steps 402-403 are similar to Figure 2 The steps 202-203 shown are consistent, and for the same content, please refer to the corresponding part of the previous embodiment, which will not be repeated here. The different part is that for the high-order class page list and the low-order class page list, the preset threshold for page recycling can be set to different thresholds. For example, for a high-order class page list containing a five-level page sub-list, the preset threshold can be set to 512, and for a low-order class page list containing a five-level page sub-list, the preset threshold can be set to 64. It should be noted that the number of levels of the high-order class page list and the low-order class page list described in this embodiment, as well as the preset threshold, are all examples and are not intended to limit the present disclosure.

[0053] Step 404: In response to detecting that a page in the high-order class page list is accessed more times than the number of levels of the multi-level page sub-list in the high-order class page list, the page is combined with pages in the same middle directory entry of the page into a transparent large page.

[0054] In this embodiment, the content stored in the high-order class page list is mainly adapted to latency-sensitive loads. Therefore, from the perspective of memory management decisions, retention priority is higher and recycling priority is lower. In order to preserve the corresponding content for as long as possible, a transparent huge page (THP) implementation is used. When it is detected that the number of times a page in the high-order class page list is accessed is greater than the number of levels of the multi-level page sub-lists in the high-order class page list, the page is combined with the page in the same middle directory item (Page Middle Directory, PMD) of the page into a transparent huge page. Figure 5Taking the high-order class page linked list shown as an example, the high-order class page linked list contains a five-level page sub-linked list. Therefore, when it is detected that the same page in the high-order class page linked list is accessed more than 5 times (for example, 6 times), the page and the pages under the same PMD of this page are combined into a transparent large page.

[0055] Through this process, on the one hand, transparent large pages can be used to integrate multiple pages to avoid excessive page fragmentation; on the other hand, the content of latency-sensitive loads can be retained for as long as possible.

[0056] Correspondingly, for the pages in the low-order class page list, step 405 may be executed: if it is detected that the number of accesses to the pages in the low-order class page list is greater than the number of levels of the multi-level page sub-lists in the low-order class page list, the pages in the low-order class page list are retained in the highest-level page sub-list of the low-order class page list. Figure 5 Taking the low-order class page linked list shown as an example, the low-order class page linked list contains a five-level page sub-link list. Therefore, when it is detected that the same page in the high-order class page linked list is accessed more than 5 times (for example, 6 times), the page in the low-order class page linked list is retained in the highest-level page sub-link list of the low-order class page linked list.

[0057] Through this process, the content of non-delay-sensitive loads can be retained in the highest-level page sublist of the low-order class page list, so that the number of pages in the highest-level page sublist of the low-order class page list reaches the preset threshold more quickly, thereby achieving more active page recovery, more reasonable memory management, improved memory recovery and call efficiency, and improved memory utilization.

[0058] To deepen understanding, the present disclosure also provides a specific implementation solution in combination with a specific application scenario, see Figure 6 Flow 600 is shown.

[0059] When the execution subject performs memory management, it needs to refer to the configured PageFlags item. PageFlags is a set of flags used to describe page status, attributes and other information in memory management. These flags are defined in the include / linux / page-flags.h file, and the various states of the page are described in detail through the enum pageflags enumeration structure. The flag PG_High can be configured in the PageFlags item. In this flag, 1 indicates that the page is in the high-order class page list (High class list), and 0 indicates that the page is in the low-order class page list (Low class list).

[0060] Step 1: Based on the load type, add the page to the High class linked list or the Low class linked list.

[0061] Step 2: Based on the page access, each access will promote the page to a higher level list. For example, if it is currently in the Min list, if it is accessed, it will be moved to the Min+1 list, and so on.

[0062] Step 3: In the High class linked list, once a page is accessed more than 5 times, the pages under the same PMD will form a THP (Transparent Huge Page). Once the number of members in the High Max list is greater than 512, all pages in the High Min List will be recycled and all lists will be downgraded by one level. The linked list downgrade operation here only needs to change the sequence number of the linked list head without moving the page, that is, the High max list is changed to the High min+3 list, the High min+3 list is changed to the High min+2 list, and finally the High Min list is changed to the High max list.

[0063] Step 4: In the Low class linked list, if a page is accessed more than 5 times, it will be kept in the Low Max list. Once the number of Low Max list members is greater than 64, all pages in the Low Min list are recycled, and all lists are downgraded by one level, that is, the LowMin+1list becomes the Low Min list, and finally the Low Max list becomes empty. If a page in the Low Min+3list is accessed again, it is added to the Low Max list.

[0064] Further references Figure 7 As an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a device for memory management based on a page linked list. Figure 2 Corresponding to the method embodiment shown, the device can be specifically applied to various electronic devices.

[0065] like Figure 7As shown, the apparatus 700 for memory management based on page linked lists of this embodiment may include: an access page determination module 701, a page sub-link list adjustment module 702, and a page sub-link list recovery module 703. Among them, the access page determination module 701 is configured to determine the accessed page based on the page access request in response to receiving the page access request. The page sub-link list adjustment module 702 is configured to promote the accessed page from the current level page sub-link list to the higher level page sub-link list. The page sub-link list recovery module 703 is configured to recover the memory of the lowest level page sub-link list in response to detecting that the number of pages in the highest level page sub-link list reaches a preset threshold, and perform downgrade operations on the page sub-link lists at all levels in the page linked list.

[0066] In the present embodiment, in the device 700 for memory management based on page linked lists, the specific processing of the to-be-accessed page determination module 701, the page sub-link list adjustment module 702, and the page sub-link list recovery module 703 and the technical effects thereof can be referred to in detail. Figure 2 The relevant descriptions of steps 201 - 203 in the corresponding embodiment are not repeated here.

[0067] In some optional implementations of the present embodiment, the downgrading operation of the page sublists at all levels in the page list implemented by the annotation execution unit 703 mainly includes: downgrading the page sublists at all levels except the lowest level page sublist by one level, wherein the highest level page sublist after the downgrading is empty. After such a downgrading operation, the page list is still a hierarchical relationship of Min List, Min+1 List, Min+2 List, Min+3 List, and Max List, but the page content in each level has changed. In the subsequent operation process, if the page in Min+3List is accessed again, the upgrade operation can continue to be performed to promote the page in Min+3List to Max List.

[0068] As an example, the above process of lowering the page sub-linked lists of all levels except the lowest level page sub-linked list by one level does not require moving the pages, but only requires changing the sequence number of the link head.

[0069] In actual applications, when recycling, the device for memory management based on the page list can mainly recycle the memory pages that can be directly released, but there are also some pages whose contents cannot be directly released and need to be aligned and transferred before being released and recycled. The device for memory management based on the page list can also include a paging module (not shown in the figure), which is configured to, for such pages, transfer the contents of the page to the hard disk through the cold page swap out technology, and then recycle the memory. In this way, it is ensured that the contents of the page will not be lost due to memory recycling, and the utilization rate of the memory can be further improved.

[0070] This embodiment exists as a device embodiment corresponding to the above method embodiment. The device for memory management based on page linked lists provided in this embodiment supervises the highest-level page sub-linked lists through the constructed multi-level page sub-linked list architecture, and recycles memory when the number of pages in the highest-level page sub-linked list approaches the threshold, without relying on the memory waterline limit. Moreover, through this active page recycling method, the memory can be managed more reasonably, the memory recycling and calling efficiency can be improved, the memory utilization rate can be improved, and the delay caused by page recycling can be effectively reduced.

[0071] Further references Figure 8 As an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a device for memory management based on a page linked list. Figure 4 Corresponding to the method embodiment shown, the device can be specifically applied to various electronic devices.

[0072] like Figure 8 As shown, the apparatus 800 for memory management based on page linked lists of this embodiment may include: an access page determination module 801, a page sub-link list adjustment module 802, and a page sub-link list recovery module 803. Among them, the access page determination module 801 is configured to determine the accessed page based on the page access request in response to receiving a page access request. Among them, the page linked list includes a high-level class page linked list (High Level area) and a low-level class page linked list (Low Level area), and the high-level class page linked list and the low-level class page linked list respectively contain multiple levels of page sub-link lists, the high-level class page linked list corresponds to a latency-sensitive load (Latency-Sensitive Load), and the low-level class page linked list corresponds to a non-latency-sensitive load (e.g., Best Effort Load). The page sub-link list adjustment module 802 is configured to promote the accessed page from the current level page sub-link list to a higher level page sub-link list. The page sub-link list recycling module 803 is configured to recycle the memory of the lowest-level page sub-link list in response to detecting that the number of pages in the highest-level page sub-link list reaches a preset threshold, and perform downgrade operations on the page sub-link lists at all levels in the page list. The page processing module 804 is configured to form a transparent large page with the page in the same middle directory entry of the page in response to detecting that the number of pages in the high-level class page list is more than the number of levels of the multi-level page sub-link list in the high-level class page list; or, in response to detecting that the number of pages in the low-level class page list is more than the number of levels of the multi-level page sub-link list in the low-level class page list, retain the page in the low-level class page list in the highest-level page sub-link list of the low-level class page list.

[0073] In the present embodiment, in the device 800 for memory management based on page linked lists, the specific processing of the to-be-accessed page determination module 801, the page sub-linked list adjustment module 802, the page sub-linked list recovery module 803, and the page processing module 804 and the technical effects thereof can be referred to in detail. Figure 4 The relevant descriptions of steps 401-404 in the corresponding embodiment are not repeated here.

[0074] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can implement the method for memory management based on a page linked list described in any of the above embodiments when executing.

[0075] According to an embodiment of the present disclosure, the present disclosure further provides a readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to implement the method for memory management based on a page linked list described in any of the above embodiments when executed.

[0076] According to an embodiment of the present disclosure, the present disclosure further provides a computer program product, which, when executed by a processor, can implement the method for performing memory management based on a page linked list as described in any of the above embodiments.

[0077] Fig. 9 A schematic block diagram of an example electronic device 900 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0078] like Fig. 9As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0079] A number of components in the device 900 are connected to the I / O interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0080] The computing unit 901 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 901 performs the various methods and processes described above, such as a method for memory management based on a page list. For example, in some embodiments, the method for memory management based on a page list may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the method for memory management based on a page list described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to execute a method for performing memory management based on a page linked list in any other appropriate manner (eg, by means of firmware).

[0081] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0082] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0083] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0084] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0085] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0086] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.

[0087] According to the technical solution of the embodiment of the present disclosure, the highest-level page sub-list is supervised through the constructed multi-level page sub-list architecture, and memory is recycled when the number of pages in the highest-level page sub-list approaches the threshold, without relying on the memory waterline limit. Moreover, through this active page recycling method, the memory can be managed more reasonably, the memory recycling and calling efficiency can be improved, the memory utilization rate can be improved, and the delay caused by page recycling can be effectively reduced.

[0088] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0089] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for memory management based on a page linked list, wherein the page linked list includes a multi-level page sub-linked list, and the method comprises: In response to receiving a page access request, determining an accessed page based on the page access request; The accessed page is promoted from the current level page sub-link list to a higher level page sub-link list; In response to detecting that the number of pages in the highest-level page sub-link list reaches a preset threshold, the memory of the lowest-level page sub-link list is reclaimed, and downgrading operations are performed on the page sub-link lists at all levels in the page link list.

2. The method for memory management based on page linked list according to claim 1, wherein: Performing a downgrade operation on each level of the page sub-link list in the page link list includes: The page sub-linked lists at all levels except the lowest level page sub-linked list are downgraded by one level, wherein the highest level page sub-linked list after the downgrade is empty.

3. The method for memory management based on page linked list according to claim 2, wherein: The step of lowering the page sub-link lists of all levels except the lowest level page sub-link list by one level includes: Adjust the link head sequence number of each level of page sub-link list except the lowest level page sub-link list to the link head sequence number of the lower level page sub-link list; The link head sequence number of the lowest level page sub-link list is adjusted to the link head sequence number of the highest level page sub-link list.

4. The method for memory management based on page linked list according to claim 1, wherein: The page linked list includes: a high-order class page linked list and a low-order class page linked list, the high-order class page linked list and the low-order class page linked list respectively contain the multi-level page sub-link list, the high-order class page linked list corresponds to a delay-sensitive load, and the low-order class page linked list corresponds to a non-delay-sensitive load.

5. The method for memory management based on page linked lists according to claim 4 further comprises: In response to detecting that a page in the high-order class page list is accessed more times than the number of levels of the multi-level page sub-list in the high-order class page list, the page is combined with a page in the same middle directory entry of the page into a transparent large page.

6. The method for memory management based on page linked lists according to claim 4 further comprises: In response to detecting that pages in the low-order class page list have been accessed more times than the number of levels of the multi-level page sub-lists in the low-order class page list, the pages in the low-order class page list are retained in the highest-level page sub-list of the low-order class page list.

7. The method for memory management based on page linked list according to claim 4, wherein: The preset thresholds of the high-order class page list and the low-order class page list are different.

8. The method for memory management based on page linked lists according to claim 1, further comprising: In response to determining that the content of the accessed page is content that cannot be directly released, the content is transferred to the hard disk through the cold page swap out technology.

9. A device for memory management based on a page linked list, wherein the page linked list includes a multi-level page sub-linked list, and the device comprises: an access page determination module, configured to, in response to receiving a page access request, determine an accessed page based on the page access request; A page sub-link list adjustment module is configured to promote the accessed page from a current level page sub-link list to a higher level page sub-link list; The page sub-link list recycling module is configured to recycle the memory of the lowest-level page sub-link list in response to detecting that the number of pages in the highest-level page sub-link list reaches a preset threshold, and perform downgrade operations on the page sub-link lists at all levels in the page list.

10. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for memory management based on a page linked list according to any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the method for memory management based on a page linked list according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the method for performing memory management based on a page linked list according to any one of claims 1 to 8.

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