Sensor data caching method, device and system, storage medium and product

Abstract

The invention provides a sensor data caching method, device and system, a storage medium and a product, and relates to the field of data processing, in particular to the field of automatic driving. According to the specific implementation scheme, the method comprises the steps of obtaining to-be-cached data collected by any preset sensor, and storing the to-be-cached data to a first cache region associated with the preset sensor in a field programmable logic gate array; in response to meeting the data writing condition, writing the to-be-cached data in the first cache region into a second cache region associated with a preset sensor in a target memory in communication connection with the field programmable logic gate array; and writing the update state of the to-be-cached data into a preset cache region in a first-in first-out manner. Therefore, the sensor data can be cached by initializing the off-chip DDR memory through the FPGA. The technical problem of delay fluctuation of a data processing link caused by reduction of system performance due to sensor data caching through a CPU is solved.

Description

Technical Field

[0001] The present disclosure relates to autonomous driving in data processing, and more particularly to a sensor data caching method, device, system, storage medium and product. Background Art

[0002] In unmanned driving scenarios, vehicles are often pre-installed with a variety of sensors for data collection. Due to the large variety of sensors and inconsistent data volumes, these data need to be pre-processed simultaneously in the time synchronization system. In particular, before data fusion operations, efficient cache management of various types of data is required.

[0003] How to implement cache management for various types of data collected by multiple sensors has become an urgent problem to be solved. Summary of the invention

[0004] The present disclosure provides a sensor data caching method, device, system, storage medium and product for caching a plurality of sensor data before preprocessing the sensor data.

[0005] According to a first aspect of the present disclosure, a sensor data caching method is provided, comprising:

[0006] Acquire the data to be cached collected by any preset sensor, and store the data to be cached in a first cache area associated with the preset sensor in a field programmable logic gate array;

[0007] In response to satisfying a preset data writing condition, writing the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory communicatively connected to the field programmable logic gate array;

[0008] The update status of the data to be cached is written into a preset cache area in a first-in-first-out manner, wherein the update status includes data types and operation lengths of multiple data packets corresponding to the current write operation.

[0009] According to a second aspect of the present disclosure, a data cache system is provided, the data cache system comprising a field programmable logic gate array and a preset target memory; the field programmable logic gate array is respectively connected to a plurality of sensors for communication;

[0010] The field programmable logic gate array includes a plurality of data cache units, and the data cache units correspond one-to-one to a plurality of preset sensors;

[0011] The double rate synchronous dynamic random access memory includes a plurality of second buffer areas, and the second buffer areas correspond to the sensors one by one;

[0012] The data cache unit is used to write the to-be-cached data sent by the sensor into a second cache area corresponding to the sensor in the target memory when a preset writing condition is met, wherein the cache control of the second cache area is dynamically configured based on the data volume of the to-be-cached data and preset transmission parameters;

[0013] The data cache unit includes a preset cache area for storing data in a first-in-first-out manner, and the preset cache area is used to store the update status associated with the current write operation;

[0014] The data cache unit is also used to determine the target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when a preset reading condition is met, and read the target data into the data cache unit.

[0015] According to a third aspect of the present disclosure, a sensor data cache device is provided, comprising:

[0016] An acquisition module, used for acquiring data to be cached collected by any preset sensor, and storing the data to be cached in a first cache area associated with the preset sensor in a field programmable logic gate array;

[0017] a writing module, configured to write the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory communicatively connected to the field programmable logic gate array in response to satisfying a preset data writing condition;

[0018] The update module is used to write the update status of the data to be cached into the preset cache area in a first-in-first-out manner, and the update status includes the data types and operation lengths of multiple data packets corresponding to the current write operation.

[0019] According to a fourth aspect of the present disclosure, there is provided an electronic device, including:

[0020] at least one processor; and

[0021] a memory communicatively connected to the at least one processor; wherein,

[0022] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect.

[0023] According to a fifth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the first aspect.

[0024] According to a sixth aspect of the present disclosure, a computer program product is provided, comprising: a computer program, wherein the computer program is stored in a readable storage medium, at least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program so that the electronic device executes the method described in the first aspect.

[0025] The technology disclosed in the present invention solves the technical problem that sensor data caching by a vehicle central processor causes system performance degradation and causes data processing link delay fluctuations.

[0026] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0028] Figure 1 A schematic diagram of the structure of a data cache system provided by an embodiment of the present disclosure;

[0029] Figure 2 A schematic diagram of the structure of a cache write module provided in an embodiment of the present disclosure;

[0030] Figure 3 A schematic diagram of the structure of a cache read module provided in an embodiment of the present disclosure;

[0031] Figure 4 A schematic diagram of a flow chart of a sensor data caching method provided in an embodiment of the present disclosure;

[0032] Figure 5 A schematic diagram of a flow chart of a sensor data caching method provided by another embodiment of the present disclosure;

[0033] Figure 6 A schematic diagram of a flow chart of a sensor data caching method provided by another embodiment of the present disclosure;

[0034] Figure 7 A schematic diagram of data packet writing into DDR provided by an embodiment of the present disclosure;

[0035] Figure 8 A schematic diagram of a flow chart of a sensor data caching method provided by another embodiment of the present disclosure;

[0036] Fig. 9 A schematic diagram of the structure of a sensor data cache device provided in an embodiment of the present disclosure;

[0037] Fig.10A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0039] Glossary:

[0040] Field Programmable Gate Array (FPGA): A semi-customized circuit in a special integrated circuit. It is a programmable logic array that can effectively solve the problem of the small number of gate circuits in the original device. The basic structure of FPGA includes programmable input and output units, configurable logic blocks, digital clock management modules, embedded block RAM, wiring resources, embedded dedicated hard cores, and bottom-level embedded functional units. FPGA has been widely used in the field of digital circuit design because of its rich wiring resources, repeatable programming, high integration, and low investment.

[0041] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM): SDRAM with double data rate, whose data transmission speed is twice the system clock frequency. Due to the increased speed, its transmission performance is better than traditional SDRAM. Data transmission can be performed on both the rising and falling edges of the system clock.

[0042] First Input First Output (FIFO): A traditional method of sequential execution in which the first instruction to enter is completed and retired first, and then the second instruction is executed.

[0043] The present disclosure provides a sensor data caching method, device, system, storage medium and product, which are applied to autonomous driving in the field of data processing to achieve the technical effect of caching data collected by multiple sensors.

[0044] In unmanned driving scenarios, vehicles are often pre-installed with a variety of sensors for data collection. Due to the large variety of sensors and inconsistent data volumes, the time synchronization system needs to pre-process these data at the same time.

[0045] In the related art, the CPU is generally used to cache the data collected by multiple sensors. However, the above method of data caching often occupies limited system resources and reduces system performance. At the same time, the CPU management method introduces large fluctuations in data processing link delay, which affects functions and poses safety risks.

[0046] In the process of solving the above technical problems, the inventors found through research that the sensor data can be cached by initializing the off-chip DDR memory through FPGA. In addition, for different sensors, a corresponding first-level cache can be set in the FPGA, which can be a BRAM in the FPGA, and a second-level cache can be set in the DDR. When the sensor data is obtained, the sensor data is first temporarily stored in the first-level cache, and when the preset write conditions are met, the data in the first-level cache is written into the second-level cache.

[0047] Optionally, for each sensor, multiple channels can be divided in the DDR memory to achieve storage of different sensor data. In addition, the size of each burst memory access, that is, the amount of data written and read in the DDR, can be preset so that the sensor data cache is more in line with the amount of sensor data collected.

[0048] It should be noted that the head model in this embodiment is not a head model for a specific user and cannot reflect the personal information of a specific user. It should be noted that the two-dimensional face image in this embodiment comes from a public data set.

[0049] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0050] In order to enable readers to more deeply understand the implementation principle of the present disclosure, the following Figure 1-Figure 10 The embodiments provided in the present disclosure are further refined.

[0051] Figure 1 A schematic diagram of the structure of a data cache system provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the data cache system 11 includes a field programmable logic gate array 12 and a preset target memory 13. The field programmable logic gate array 12 is communicatively connected with a plurality of sensors 14 respectively.

[0052] The field programmable logic gate array 12 includes a plurality of data cache units 15 , and the data cache units 15 correspond one-to-one to a plurality of preset sensors 14 .

[0053] The data cache unit 15 is used to write the data to be cached sent by the sensor 14 into the second cache area in the target memory 13 when the preset writing conditions are met, wherein the cache control of the second cache area is dynamically configured based on the data volume of the data to be cached and the preset transmission parameters.

[0054] The data cache unit 15 includes a preset cache area for storing data in a first-in-first-out manner, and the preset cache area is used to store the update status associated with the current write operation;

[0055] The data cache unit 15 is further configured to determine target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when a preset reading condition is met, and read the target data into the data cache unit 15 .

[0056] In this embodiment, the data cache system 11 includes a field programmable logic gate array 12 and a target memory 13. The field programmable logic gate array 12 is respectively connected to multiple sensors 14 for communication. In order to store the data to be cached collected by different sensors, multiple data cache units 15 can be set in the FPGA, and the data cache units 15 correspond to the preset multiple sensors 14 one by one. Among them, the target memory can be a double rate synchronous dynamic random access memory.

[0057] In addition, the target memory 13 may be provided with a plurality of second buffer areas, and the second buffer areas correspond to the sensors 14 one by one. Therefore, the data to be buffered collected by each sensor 14 can be stored in blocks.

[0058] Based on the above system architecture, the target memory 13 includes multiple second cache areas, and the second cache areas correspond one-to-one to the sensors, wherein the cache control corresponding to the second cache area associated with each sensor can be dynamically configured based on the amount of cached data currently to be written and the transmission parameters.

[0059] After the data to be cached sent by the sensor 14 is acquired, it can be temporarily stored in the data cache unit. The data cache unit 15 is used to write the temporarily stored data to be cached into the second cache area in the target memory 13 when a preset writing condition is met.

[0060] The data cache unit includes a preset cache area for storing data in a first-in-first-out manner, and the preset cache area is used to store the update status associated with this write operation. Therefore, the target data can be located and read in the order of data writing based on FIFO.

[0061] The data cache unit 15 is further configured to determine target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when a preset reading condition is met, and read the target data into the data cache unit.

[0062] The storage space of the first cache area and the third cache area is smaller than the storage space of the second cache area.

[0063] The data cache system provided in this embodiment can obtain the data to be cached collected by multiple sensors by setting multiple data cache units in the field programmable logic gate array, and temporarily store the data to be cached. When the preset writing conditions are met, the data to be cached is written into the second cache area matching each sensor in the target memory. Therefore, there is no need to cache the sensor data in the CPU, avoiding the technical problem of system performance degradation caused by caching sensor data through the vehicle central processing unit and causing data processing link delay fluctuations.

[0064] In addition, by storing the updated data in the preset cache area in a FIFO manner, the sensor data cached in the second cache area can be automatically read into the third cache area based on the FIFO when the preset reading condition is met. This can more flexibly implement the read and write operations of the data to be cached collected by the sensor.

[0065] Optionally, based on any of the above embodiments, the data cache unit further includes a cache write module and a cache read module;

[0066] The cache writing module and the cache reading module are respectively connected to the preset cache area for communication;

[0067] The cache writing module is used to cache the to-be-cached data sent by the sensor into a preset first cache area, and when a preset writing condition is met, write the to-be-cached data into a second cache area corresponding to the sensor in the target memory;

[0068] The cache reading module is used to determine the target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when the preset reading condition is met, and read the target data into the third cache area in the cache reading module.

[0069] In this embodiment, the data cache unit may include a cache write module and a cache read module. The cache write module and the cache read module are respectively connected to the preset cache area. Therefore, the cache write module is used to cache the data to be cached sent by the sensor into the preset first cache area, and when the preset write condition is met, the cache data is written into the second cache area corresponding to the sensor in the target memory; the cache read module is used to determine the target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when the preset read condition is met, and read the target data into the third cache area in the cache read module.

[0070] It should be noted that the first cache area and the third cache area may be the same cache area, so that the data to be written and the currently read data can be temporarily stored in the same cache area at the same time.

[0071] Figure 2 A schematic diagram of the structure of a cache write module provided in an embodiment of the present disclosure, based on any of the above embodiments, such as Figure 2 As shown, the cache writing module 21 includes a first cache area 22, a package assembly module 23 and a write state control module 24, and the package assembly module 23 is respectively communicated with the first cache area 22, the write state control module 24 and the second cache area 25.

[0072] The first buffer area 22 is used to perform a buffering operation on the to-be-buffered data collected by the sensor.

[0073] The write state control module 24 is used to control the packet assembly module 23 to perform a packet assembly operation on the data to be cached when a preset data writing condition is met, and write the packetized data to be cached into the second cache area 25 .

[0074] In this embodiment, the cache writing module 21 includes a first cache area 22 , a packet assembly module 23 and a write state control module 24 . The packet assembly module 23 is respectively connected to the first cache area 22 , the write state control module 24 and the second cache area 25 .

[0075] After the sensor collects the data to be cached, the first cache area 22 is used to cache the data to be cached.

[0076] The write state control module 24 is used to determine in real time whether the preset data writing condition is currently met based on the storage state of the first cache area and the second cache area. When the preset data writing condition is met, the control package assembly module 23 performs a package assembly operation on the cached data and writes the packaged cached data into the second cache area 25.

[0077] The data cache system provided in this embodiment can temporarily store the data to be cached collected by the sensor in the first cache area by respectively setting the first cache area, the packet assembly module and the write state control module in the cache write module, and detect the data writing condition through the write state control module. When the data writing condition is met, the packet assembly module performs a packet assembly operation on the data to be cached, and writes the packetized data to be cached into the second cache area. Therefore, it is possible to implement the caching of sensor data in the FPGA initialization off-chip DDR memory.

[0078] Figure 3 A schematic diagram of the structure of a cache reading module provided in an embodiment of the present disclosure, based on any of the above embodiments, such as Figure 3 As shown, the cache reading module 31 includes a third cache area 32 , an unpacking module 33 and a reading state control module 34 .

[0079] The unpacking module 33 is in communication connection with the third buffer area 32 , the read state control module 34 and the second buffer area 35 respectively.

[0080] The read state control module 34 is used to determine the target data to be read in the preset buffer area in a first-in-first-out manner when the read condition is met, and perform a read operation on the target data from the second buffer area 35 .

[0081] The unpacking module 33 is used to unpack the target data and read valid data in the target data into the third buffer area 32 .

[0082] In this embodiment, the cache reading module 31 includes a third cache area 32 , an unpacking module 33 and a reading state control module 34 .

[0083] The unpacking module 33 is in communication connection with the third buffer area 32 , the read state control module 34 and the second buffer area 35 respectively.

[0084] The read state control module 34 is used to detect in real time whether the preset data reading condition is currently met based on the storage state of the second buffer area and the third buffer area. When the reading condition is met, the target data to be read is determined based on the first-in-first-out queue, and the target data is read from the second buffer area 35.

[0085] Since the data to be cached is packaged before being written into the second cache area, a data unpacking operation is required during the data reading process. Therefore, the unpacking module 33 is used to unpack the target data and read the valid data in the target data into the third cache area 32.

[0086] Furthermore, after the valid data is read into the third buffer area, the valid data may be subjected to data fusion, data preprocessing and other operations through a preset processing module. The present disclosure does not limit this.

[0087] The data cache system provided in this embodiment is capable of determining whether a preset data reading condition is currently met based on the read state control module by respectively setting a third cache area, an unpacking module, and a read state control module in the cache reading module. When the data reading condition is met, the target data to be read is automatically determined based on the first-in first-out queue, and the target data is read from the second cache area. The target data is unpacked based on the unpacking module, and valid data in the target data is read into the third cache area. Thus, the read and write operations of the data to be cached can be flexibly performed on the basis of storing the data to be cached in the DDR memory off-chip after the FPGA is initialized.

[0088] Figure 4 A flow chart of a sensor data caching method provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the method includes:

[0089] Step 401: Acquire data to be cached collected by any preset sensor, and store the data to be cached in a first cache area associated with the preset sensor in a field programmable logic gate array.

[0090] Step 402: In response to satisfying a preset data writing condition, write the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory communicatively connected to the field programmable logic gate array.

[0091] Step 403: Write the update status of the data to be cached into the preset cache area in a first-in-first-out manner, wherein the update status includes the data types and operation lengths of the multiple data packets corresponding to the current write operation.

[0092] The execution subject of this embodiment is a sensor data cache device, which can be coupled to a field programmable logic gate array. The field programmable logic gate array can be connected to a preset target memory, so after obtaining the data to be cached collected by the sensor, the data to be cached can be stored in the target memory before data preprocessing and data fusion, avoiding the use of the CPU for data cache operations.

[0093] It should be noted that the target memory can be a double rate synchronous dynamic random access memory. The storage space of the double rate synchronous dynamic random access memory is relatively large, and the cache speed of the double rate synchronous dynamic random access memory is faster than that of other memories. Therefore, for sensors with large data collection such as cameras, using double rate synchronous dynamic random access memory to cache sensor data can improve cache efficiency and realize effective storage of sensor data with large data volume.

[0094] In the present embodiment, there are multiple data cache units in the field programmable logic gate array, and the data cache units correspond one-to-one to multiple preset sensors. The data cache units include a cache write module, a cache read module, and a first-in-first-out queue. The cache write module and the cache read module are respectively communicated and connected with a preset cache area that uses a first-in-first-out method to store data. The cache write module is used to temporarily store the data to be cached transmitted by the sensor, and when the preset data write condition is met, the data to be cached is written to the second cache area in the target memory. After the data is written, the data status can be updated, and the updated status can be written to the preset cache area in a FIFO manner. Therefore, when the cache read module determines that the preset data reading condition is currently met, the target data can be determined in the preset cache area based on the FIFO method, and the target data in the second cache area is read into the third cache area preset in the cache read module.

[0095] Based on the above system architecture, the data to be cached collected by any preset sensor can be obtained, and the data to be cached can be stored in the first cache area associated with the preset sensor in the FPGA.

[0096] Furthermore, it is possible to determine in real time whether a preset data writing condition is met based on the current storage status of the first cache area and the second cache area. In response to meeting the preset data writing condition, the data to be cached in the first cache area is written into a second cache area associated with a preset sensor in a target memory that is communicatively connected to the field programmable logic gate array.

[0097] Optionally, in order to facilitate subsequent data reading operations, the update status of the data to be cached can also be written into the preset cache area in a first-in-first-out manner. The update status includes the data type and operation length of multiple data packets corresponding to this write operation. The preset cache area includes the update status corresponding to all data cached in the second cache area.

[0098] The sensor data caching method provided in this embodiment temporarily stores the data to be cached in the first cache area after acquiring the data to be cached. When the preset data writing condition is met, the data to be cached is written into the second cache area in the target memory that matches the sensor. Therefore, there is no need to cache the sensor data in the CPU, thus avoiding the technical problems of reduced system performance and fluctuation of data processing link delay.

[0099] In addition, by writing the update data into the preset cache area in a first-in-first-out manner, the sensor data cached in the second cache area can be automatically read into the third cache area in the preset cache area based on the FIFO method when the preset reading condition is met. This can more flexibly implement the read and write operations of the data to be cached collected by the sensor.

[0100] Figure 5 A flow chart of a sensor data caching method provided by another embodiment of the present disclosure is provided. Based on any of the above embodiments, Figure 5 As shown, step 402 includes:

[0101] Step 501: In response to the to-be-cached data in the first cache area satisfying a preset trigger condition, determine a first storage state, wherein the first storage state includes a cache state associated with the first cache area and a cache state associated with the second cache area.

[0102] Step 502: In response to the first storage state satisfying a preset condition, write the to-be-cached data into the second cache area.

[0103] In this embodiment, a trigger condition can be pre-set, and when the trigger condition is met, the monitoring of the storage status associated with the first cache area and the second cache area is triggered, so the first cache status can be obtained, and the first storage status includes the cache status associated with the first cache area and the cache status associated with the second cache area. For example, the first storage status includes information such as the amount of data stored in the first cache area and the second cache area, whether there is storage space, etc.

[0104] Optionally, the trigger condition may be that the amount of data in the first cache area reaches a preset data amount threshold. Alternatively, since the size of the data to be cached collected by different sensors is different, different trigger conditions may be set for different sensors, and the present disclosure does not limit this. For example, when the data to be cached is small, if it is detected that the sensor has not transmitted the next round of data for more than a preset time, the monitoring of the first storage state associated with the first cache area and the second cache area may be triggered.

[0105] Furthermore, it can be determined whether a preset condition is currently satisfied based on the first storage state, and in response to the first storage state satisfying the preset condition, the data to be cached is written into the second cache area.

[0106] Optionally, in order to ensure the accuracy of subsequent write operations, after the write operation is completed, the first storage states of the first cache area and the second cache area may be updated.

[0107] The sensor data caching method provided in this embodiment can further determine the first storage state associated with the first cache area and the second cache area by presetting the trigger condition when the trigger condition is met, so as to determine whether the preset condition is currently met based on the first storage state. Then, a flexible write operation on the cached data can be implemented based on the processing result.

[0108] Further, based on any of the above embodiments, step 502 includes:

[0109] If it is determined based on the first storage state that the first cache area and the second cache area are both full and have overflow data, the data to be cached is discarded.

[0110] If it is determined based on the first storage state that the first cache area and the second cache area are both full but there is no overflow data, return to execute the step of determining the first storage state until there is storage space in the second cache area, and write the data to be cached into the second cache area.

[0111] If it is determined based on the first storage state that storage space exists in the second cache area, the data to be cached is written into the second cache area.

[0112] In this embodiment, when there is cache space in the second cache area, it indicates that data can be written into the second cache area. On the contrary, if the second cache area is in a full state, data cannot be written into the second cache area. At this time, if the first cache area is also in a full state but there is no overflow data, or the first cache area is not full, at this time, the monitoring operation of the first storage state can be continued, and the data writing operation can be performed when it is determined that there is storage space in the second cache area. If it is determined based on the first storage state that the first cache area and the second cache area are both full and there is overflow data, a channel reset operation can be performed at this time.

[0113] Therefore, if it is determined based on the first storage state that both the first cache area and the second cache area are full and there is overflow data, the data to be cached is discarded. If it is determined based on the first storage state that both the first cache area and the second cache area are full but there is no overflow data, return to the step of determining the first storage state associated with the first cache area and the second cache area until there is storage space in the second cache area, and write the data to be cached into the second cache area. If it is determined based on the first storage state that there is storage space in the second cache area, the data to be cached is written into the second cache area.

[0114] The sensor data caching method provided in this embodiment discards the data to be cached when the first cache area and the second cache area are full and there is overflow data; when the first storage state determines that the first cache area and the second cache area are both full but there is no overflow data, the state monitoring operation continues; when there is storage space in the second cache area, the data to be cached is written into the second cache area. Thus, the writing process of the data to be cached can be flexibly performed based on the first storage state, which is applicable to more data writing scenarios.

[0115] Further, based on any of the above embodiments, step 501 includes:

[0116] Determine whether the amount of data to be cached in the first cache area reaches a preset data amount threshold.

[0117] If so, determine the first storage states corresponding to the first cache area and the second cache area.

[0118] In this embodiment, the preset trigger condition may be to monitor the first storage state when the amount of data to be cached in the first cache area reaches a preset data amount threshold. For example, the data amount threshold may be 256 bytes.

[0119] Therefore, it is possible to detect in real time whether the amount of data to be cached in the first cache area reaches a preset data amount threshold. If so, the first storage state associated with the first cache area and the second cache area is determined.

[0120] The sensor data caching method provided in this embodiment can further determine the first storage state associated with the first cache area and the second cache area by presetting the trigger condition, so that subsequent data writing operations can be flexibly performed based on the amount of data to be cached currently stored.

[0121] Figure 6 A flow chart of a sensor data caching method provided by another embodiment of the present disclosure is provided. Based on any of the above embodiments, Figure 6 As shown, step 402 includes:

[0122] Step 601: Determine the data volume corresponding to the data to be cached, and determine the transmission parameters preset by the user, wherein the transmission parameters include the number of bytes transmitted per clock beat.

[0123] Step 602: perform a packetization operation on the data to be cached based on the data volume and the transmission parameters to obtain a plurality of data packets to be transmitted.

[0124] Step 603: Write the multiple data packets to be transmitted into the second buffer area.

[0125] In this embodiment, before data is written, a data packaging operation may be performed on the cached data.

[0126] Optionally, the amount of data corresponding to the data to be cached can be determined, and the transmission parameters preset by the user can be determined, wherein the transmission parameters include the number of bytes transmitted per clock tick. The user can set the number of bytes transmitted per clock tick to 16, 8, or 4, etc. according to actual needs, and the present disclosure does not limit this.

[0127] Furthermore, the data to be buffered may be grouped based on the data volume and the transmission parameter to obtain a plurality of data packets to be transmitted, and the plurality of data packets to be transmitted may be written into the second buffer area.

[0128] The sensor data caching method provided in this embodiment can improve the success rate of data writing and avoid the problem of data loss during data transmission by performing a package operation on the cached data before writing the data.

[0129] Further, based on any of the above embodiments, step 602 includes:

[0130] Valid data matching the transmission parameters is acquired from the data to be cached, and the data packet to be transmitted is constructed based on the valid data.

[0131] In response to the data amount of the remaining valid data in the data to be cached being less than the transmission parameter, a byte quantity difference between the remaining valid data and the transmission parameter is determined.

[0132] A padding code matching the byte quantity difference is inserted into the remaining data to be cached to obtain the data packet to be transmitted.

[0133] In this embodiment, the data to be cached can be written into the DDR according to preset transmission parameters. The transmission parameters may include the number written in each clock beat. In the process of data transmission according to a fixed clock beat, if the amount of data actually transmitted is less than the number written in each clock beat in the transmission parameters, it may cause an incomplete frame structure, so that after the DDR obtains the data to be transmitted, it may not be able to correctly identify the beginning and end of the frame. In addition, since the transmission parameters are set in advance, when the amount of data actually transmitted is less than the number written in each clock beat in the transmission parameters, there are irregular gaps or inconsistent beats in the data stream, and the receiving DDR may be a channel part, resulting in data parsing errors.

[0134] In the process of solving the above problems, the inventors discovered through research that when the actual amount of data transmitted is less than the number written in each clock beat in the transmission parameters, data filling operations can be performed using filling characters so that the actual amount of data transmitted matches the number written in each clock beat in the transmission parameters, thereby ensuring the effectiveness and accuracy of data transmission.

[0135] Therefore, valid data matching the transmission parameters can be obtained from the data to be cached, and a data packet to be transmitted can be constructed based on the valid data. The data packet to be transmitted is written sequentially, and it is determined whether the current remaining valid fields are less than the transmission parameters. In response to the data amount of the remaining valid data in the data to be cached being less than the transmission parameters, the byte quantity difference between the remaining valid data and the transmission parameters is determined. A padding code matching the byte quantity difference is inserted into the remaining data to be cached to obtain a data packet to be transmitted.

[0136] Taking practical application as an example, the data written to DDR in a burst is 64 bytes, but the actual valid data is 62 bytes, and 16 bytes are written in each clock beat. The first clock beat is sop (the first data of the valid packet data), and 16 bytes are written. The second clock beat is data (the transmitted data signal), and 16 bytes are written. The third clock beat is data, and 16 bytes are written. The fourth beat is eop (the last data of the valid packet data), and 16 bytes are written, but the actual valid data of the last beat is 14 bytes, so the remaining 2 bytes are filled with pad, and pad is the unique code in the data.

[0137] Figure 7 A schematic diagram of data packet writing into DDR provided by an embodiment of the present disclosure, such as Figure 7 As shown, when the remaining valid data in the to-be-buffered data 71 does not match the number of bytes transmitted per clock beat, a padding operation can be performed through a padding code (pad) 72 to obtain a packet assembly result.

[0138] The sensor data caching method provided in this embodiment uses padding coding to perform data padding operations when the amount of remaining valid data is less than the transmission parameter, thereby ensuring the effectiveness and accuracy of data transmission.

[0139] Further, based on any of the above embodiments, step 403 includes:

[0140] The update status is encoded according to a preset encoding method to obtain encoded data, wherein the encoded data is used to indicate the data types and operation lengths of multiple data packets corresponding to this write operation.

[0141] The encoded data is added to the first-in-first-out queue.

[0142] In this embodiment, the encoding method can be preset. In this encoding method, the width of the encoded data is four bits, and the encoding method is used to indicate that the 2-3 bits in the encoded data represent the data type of the data packet, and the 0-1 bits represent the operation length corresponding to this write operation. Among them, bit [3: 2] is used to represent the data type, where sop = 01, eop = 10, D = 00, seop = 11. Bit [1: 0] represents the operation length of this burst. sop represents the frame header, eop represents the frame tail, seop represents sop and eop occur in the same beat, and D represents a normal data packet. For example, 00 represents a length of 256, 01 represents a length of 128, 10 represents a length of 64, and 11 represents a length of 32.

[0143] Therefore, the update state can be encoded according to the preset encoding method to obtain the encoded data. Therefore, the encoded data can indicate the data types and operation lengths of the multiple data packets corresponding to the current write operation. The encoded data can be added to the preset buffer area in a first-in-first-out manner.

[0144] The FIFO is set in the FPGA chip. The FIFO has a small width and a long depth, and consumes very few resources. For example, if the width of the FIFO is 4 bits and the depth is 8192, the resources occupied by the FIFO in the FPGA = 32Kbits.

[0145] The sensor data caching method provided in this embodiment encodes the update state according to a preset encoding method to obtain encoded data, and adds the encoded data to the preset cache area in a FIFO manner. Therefore, in the subsequent process of reading the data to be cached, the data type and operation length of each data packet can be accurately determined based on the update state stored in the FIFO, so the target data to be read can be located and read more accurately.

[0146] Figure 8 A flow chart of a sensor data caching method provided by another embodiment of the present disclosure is provided. Based on any of the above embodiments, Figure 8 As shown, after step 403, the following steps are also included:

[0147] Step 801 : In response to a preset data reading condition being met, target data to be read is determined in a preset buffer area based on a first-in-first-out method.

[0148] Step 802: Read the target data from the second buffer area into a third buffer area in the field programmable logic gate array associated with the preset sensor.

[0149] In this embodiment, since the update status is written into the preset buffer area in FIFO mode after the data is written, the target data can be read in the preset buffer area based on the FIFO mode when the data reading condition is met. Since the update status associated with all sensor data in the second buffer area is stored in the preset buffer area in a first-in-first-out mode, the target data can be read in sequence in a first-in-first-out mode.

[0150] Optionally, when it is detected that the data reading condition is currently met, the target data to be read can be determined in the preset cache area based on a first-in-first-out method. The field programmable logic gate array also includes a cache reading module, which can determine whether the data reading condition is currently met. In addition, the cache reading module also includes a third cache area, so the target data can be read from the second cache area to the third cache area associated with the preset sensor in the field programmable logic gate array.

[0151] Optionally, the first cache area and the third cache area may be the same cache area, so that the data to be written and the currently read data can be temporarily stored in the same cache area at the same time.

[0152] The sensor data caching method provided in this embodiment determines the target data to be read in a preset cache area based on a first-in-first-out manner when the data reading condition is met, thereby accurately performing data reading operations in the order in which the data are written.

[0153] Further, based on any of the above embodiments, step 801 includes:

[0154] In response to the existence of cache space in the third cache area, a second cache state is determined, wherein the second cache state includes a cache state associated with the second cache area and a cache state associated with the third cache area.

[0155] If it is determined based on the second cache state that there is cache space in the third cache area and there is cache data in the second cache area, the target data to be read currently is determined in the preset cache area based on a first-in-first-out method.

[0156] In this embodiment, in the idle state, it is possible to continuously detect whether there is still cache space in the third cache area. In response to the presence of cache space in the third cache area, the second cache state associated with the second cache area and the third cache area is determined. For example, the cache depth of the third cache area may be 1k bytes. When it is determined that there are still 256 bytes in the third cache area, the second cache state associated with the second cache area and the third cache area may be determined. The second cache state includes information such as the current data storage amount in the second cache area and the third cache area, and whether there is storage space.

[0157] Further, after the second cache state is acquired, there may be cache space in the third cache area, and the target data to be read currently is determined based on the first-in-first-out queue.

[0158] Optionally, if there is no cache space in both the third cache area and the second cache area, and there is data overflow, a channel reset operation can be performed. If there is no cache space in both the third cache area and the second cache area, but there is no data overflow, the second cache state can be continuously detected, and when there is cache space in the third cache area, there is cache data in the second cache area, and no data overflow occurs, a data write operation can be performed.

[0159] In order to ensure the accuracy of subsequent data reading operations, after each data reading operation is completed, the second cache state may be updated based on the data reading operation.

[0160] The sensor data caching method provided in this embodiment pre-sets the data reading conditions, so that the data reading operation can be performed more flexibly based on the data reading conditions after the data to be cached is written into the FPGA initialization off-chip DDR memory.

[0161] Further, based on any of the above embodiments, step 801 includes:

[0162] A plurality of data packets to be read are determined in a preset buffer area in a first-in-first-out manner.

[0163] For each data packet, a decoding operation is performed on the update status associated with the data packet in the preset buffer area based on a preset decoding method to obtain a data type and an operation length corresponding to the data packet.

[0164] Determine the memory space and memory address of the data type, operation length and transmission parameters set by the user corresponding to the data packet in the second buffer area.

[0165] Step 802 includes:

[0166] The target data is read from the second cache area to the third cache area based on the memory space and the memory address.

[0167] In this embodiment, since the FIFO stores the update status associated with all sensor data in the second buffer area in a first-in-first-out manner, the reading operation of the target data can be sequentially implemented in a first-in-first-out manner.

[0168] Optionally, multiple data packets to be read are determined in a preset buffer area in a FIFO manner. Since the update state in the preset buffer area is an encoded state, for each data packet, a decoding operation is performed on the update state associated with the data packet in the first-in-first-out queue based on a preset decoding method to obtain the data type and operation length corresponding to the data packet.

[0169] Determine the data type, operation length and user-set transmission parameters corresponding to the data packet, the memory space and memory address in the second buffer area, and read the target data from the second buffer area to the third buffer area based on the memory space and memory address.

[0170] Optionally, based on any of the above embodiments, after step 401, the method further includes:

[0171] Determining the data volume corresponding to the data to be cached and preset transmission parameters;

[0172] According to the data volume and the transmission parameters, a configuration operation is performed on the cache control of the second cache area through a preset configuration interface.

[0173] In this embodiment, the user may dynamically configure the second cache area in the target memory according to actual data cache requirements.

[0174] Optionally, the amount of data to be cached and the preset transmission parameters of the data currently transmitted by the sensor can be determined. The transmission parameters can be the number of bytes written for each clock beat. The transmission parameters can be set by the user according to actual needs, and the present disclosure does not limit this. Therefore, the cache space of the second cache area can be configured through a preset configuration interface.

[0175] Taking practical application as an example, the memory space mapped from FIFO to DDR is configurable. For example, the number of bytes per clock beat can be configured to 16 or 8 bytes or 4 bytes. At the same time, the maximum length of each transmission initiated is 256. The user can set the transmission parameters according to actual needs. For example, for different sensors, since the amount of sensor data collected is different, different transmission parameters can be set for different sensors, and the present disclosure does not limit this.

[0176] Optionally, when the number of bytes per clock is configured as 16, the memory range of the mapping with a FIFO depth of 8192 is [512B, 32MB]. Similarly, when the number of bytes per clock is configured as 8, the memory range of the mapping with a FIFO depth of 8192 is [256B, 16MB]. When the number of bytes per clock is configured as 4, the memory range of the mapping with a FIFO depth of 8192 is [128B, 8MB].

[0177] The specific second buffer write address memory mapping process is as follows: assuming that the number of bytes in each clock beat is configured as 16, according to the preset encoding method, if bit[1:0] of FIFO=00, then the memory address is increased by 256*16B on the original basis, if bit[1:0] of FIFO=01, then the memory address is increased by 128*16B on the original basis, if bit[1:0] of FIFO=10, then the memory address is increased by 64*16B on the original basis, if bit[1:0] of FIFO=11, then the memory address is increased by 32*16B on the original basis. The second buffer can be a circular address, for example, the entire depth is 1024 bytes, then the starting relative address starts counting from 0, and when 1024 bytes are written, the address will return to 0 and start counting again.

[0178] Assuming that the number of bytes in each clock beat is configured as 8, if bit[1:0] of FIFO=00, then the memory address is increased by 256*8B on the original basis; if bit[1:0] of FIFO=01, then the memory address is increased by 128*8B on the original basis; if bit[1:0] of FIFO=10, then the memory address is increased by 64*8B on the original basis; if bit[1:0] of FIFO=11, then the memory address is increased by 32*8B on the original basis.

[0179] The sensor data caching method provided in this embodiment determines the memory space and memory address mapped to DDR based on FIFO, thereby being able to accurately implement data reading operations in the order in which data are written.

[0180] Further, based on any of the above embodiments, step 802 includes:

[0181] An unpacking operation is performed on the target data to obtain valid data corresponding to the target data.

[0182] The valid data is read into the third buffer area.

[0183] In this embodiment, since it is necessary to perform a packaging operation on the cached data during the writing process of the cached data, it is necessary to perform a data unpacking operation accordingly during the data reading process.

[0184] Optionally, the target data may be unpacked to obtain valid data corresponding to the target data, so that the valid data may be read into the third buffer area.

[0185] The sensor data caching method provided in this embodiment can extract valid data from the target data and implement a read operation on the valid data by performing an unpacking operation on the target data.

[0186] Further, based on any of the above embodiments, the unpacking operation on the target data to obtain valid data corresponding to the target data includes:

[0187] The first data packet, the last data packet and at least one middle data packet in the target data are extracted.

[0188] The first data packet and at least one middle segment data packet are determined as the valid data.

[0189] For the last data packet, determine whether the last data packet includes padding code.

[0190] If it exists, the padding code is deleted and the remaining fields in the last data packet are determined as the valid data.

[0191] In this embodiment, since during the process of writing the data to be cached, the remaining valid data does not match the preset byte amount sent per clock beat, a padding code is inserted into the valid data to perform a packet assembly operation. Therefore, during the unpacking process, it can be first determined whether there is a padding code in the data packet, and if there is a padding code, the padding code is deleted.

[0192] Optionally, the first data packet (sop), the last data packet (eop) and at least one intermediate data packet (data) in the target data may be extracted.

[0193] Furthermore, since the padding code is generally filled in the eop, the first data packet and at least one intermediate data packet can be directly determined as valid data. Determine whether the eop includes the padding code. If so, delete the padding code and determine the remaining fields in the last data packet as valid data. On the contrary, if the eop does not contain the padding code, the eop can be directly determined as valid data.

[0194] The sensor data caching method provided in this embodiment can accurately acquire valid data and further implement a reading operation on the valid data by discarding the padding code during the unpacking process.

[0195] Fig. 9 A schematic diagram of the structure of a sensor data cache device provided in an embodiment of the present disclosure, such as Fig. 9As shown, the device includes: an acquisition module 91, a writing module 92 and an updating module 93. Among them, the acquisition module 91 is used to acquire the data to be cached collected by any preset sensor, and store the data to be cached in a first cache area associated with the preset sensor in the field programmable logic gate array. The writing module 92 is used to write the data to be cached in the first cache area to a second cache area associated with the preset sensor in a target memory connected to the field programmable logic gate array in communication in response to satisfying a preset data writing condition. The updating module 93 is used to write the update status of the data to be cached into the preset cache area in a first-in-first-out manner, and the update status includes the data type and operation length of multiple data packets corresponding to this write operation.

[0196] Further, based on any of the above embodiments, the write module includes: a determination unit, configured to determine a first storage state in response to the data to be cached in the first cache area satisfying a preset trigger condition, wherein the first storage state includes a cache state associated with the first cache area and a cache state associated with the second cache area. A write unit, configured to write the data to be cached into the second cache area in response to the first storage state satisfying a preset condition.

[0197] Further, based on any of the above embodiments, the write unit includes: a first processing subunit, which is used to discard the data to be cached if it is determined based on the first storage state that the first cache area and the second cache area are both full and there is overflow data. A second processing subunit, which is used to return to the step of determining the first storage state until there is storage space in the second cache area, and write the data to be cached into the second cache area if it is determined based on the first storage state that the first cache area and the second cache area are both full but there is no overflow data. A write subunit, which is used to write the data to be cached into the second cache area if it is determined based on the first storage state that there is storage space in the second cache area.

[0198] Further, based on any of the above embodiments, the determining unit includes: a determining subunit, configured to determine whether the amount of data to be cached in the first cache area reaches a preset data amount threshold. A determining subunit, configured to determine the first storage state if so.

[0199] Further, based on any of the above embodiments, the writing module includes: a determining unit, used to determine the data volume corresponding to the data to be cached, and to determine the transmission parameters preset by the user, wherein the transmission parameters include the number of bytes transmitted per clock tick. A packetizing unit, used to perform packetizing operations on the data to be cached based on the data volume and the transmission parameters to obtain multiple data packets to be transmitted. A writing unit, used to write the multiple data packets to be transmitted into the second buffer area.

[0200] Further, based on any of the above embodiments, the packet assembly unit includes: an acquisition subunit, configured to acquire valid data matching the transmission parameter from the data to be cached, and construct the data packet to be transmitted based on the valid data; a determination subunit, configured to determine the byte quantity difference between the remaining valid data and the transmission parameter in response to the amount of data remaining in the data to be cached being less than the transmission parameter; and a padding subunit, configured to insert a padding code matching the byte quantity difference into the remaining data to be cached, and obtain the data packet to be transmitted.

[0201] Further, based on any of the above embodiments, the update module includes: an encoding unit, configured to perform an encoding operation on the update state according to a preset encoding method to obtain encoded data, wherein the encoded data is used to indicate the data type and operation length of multiple data packets corresponding to this write operation. An update unit, configured to write the encoded data into the preset cache area in a first-in-first-out manner.

[0202] Further, based on any of the above embodiments, the device further includes: a determination module, configured to determine the target data to be read in the preset buffer area based on a first-in-first-out manner in response to satisfying a preset data reading condition; and a reading module, configured to read the target data from the second buffer area into a third buffer area in the field programmable logic gate array associated with the preset sensor.

[0203] Further, based on any of the above embodiments, the third cache area and the first cache area are the same cache area.

[0204] Further, based on any of the above embodiments, the determination module includes: a determination unit, configured to determine a second cache state in response to the existence of cache space in the third cache area, wherein the second cache state includes a cache state associated with the second cache area and a cache state associated with the third cache area. A reading unit, configured to determine the target data to be read in the preset cache area based on a first-in-first-out manner if it is determined based on the second cache state that there is cache space in the third cache area and there is cache data in the second cache area.

[0205] Further, on the basis of any of the above embodiments, the determination unit includes: a determination subunit, used to determine multiple data packets to be read in the preset cache area according to the first-in-first-out method. A decoding subunit, used to decode the update status associated with the data packet in the preset cache area based on a preset decoding method for each data packet, and obtain the data type and operation length corresponding to the data packet. A mapping subunit, used to determine the data type, operation length and user-set transmission parameters corresponding to the data packet in the second cache area. The reading unit includes: a reading subunit, used to read the target data from the second cache area to the third cache area based on the memory space and the memory address.

[0206] Further, based on any of the above embodiments, the reading module includes: an unpacking unit, configured to unpack the target data to obtain valid data corresponding to the target data; and a reading unit, configured to read the valid data into the third buffer area.

[0207] Further, based on any of the above embodiments, the unpacking unit includes: an extraction subunit, which is used to extract the first data packet, the last data packet and at least one intermediate data packet in the target data; a determination subunit, which is used to determine the first data packet and at least one intermediate data packet as the valid data; an identification subunit, which is used to determine whether the last data packet includes padding code for the last data packet; and a deletion subunit, which is used to delete the padding code if it exists, and determine the remaining fields in the last data packet as the valid data.

[0208] Furthermore, based on any of the above embodiments, the target memory includes a double rate synchronous dynamic random access memory.

[0209] Further, based on any of the above embodiments, the device further includes: a determination module, used to determine the data volume corresponding to the data to be cached and preset transmission parameters; and a configuration module, used to configure the cache control of the second cache area through a preset configuration interface according to the data volume and transmission parameters.

[0210] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0211] According to an embodiment of the present disclosure, the present disclosure further provides an electronic device, including:

[0212] at least one processor; and

[0213] a memory communicatively connected to the at least one processor; wherein,

[0214] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in any one of the above embodiments.

[0215] According to an embodiment of the present disclosure, the present disclosure further provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the method described in any one of the above embodiments.

[0216] According to an embodiment of the present disclosure, the present disclosure also provides a computer program product, which includes: a computer program, the computer program is stored in a readable storage medium, at least one processor of an electronic device can read the computer program from the readable storage medium, and at least one processor executes the computer program so that the electronic device executes the solution provided by any of the above embodiments.

[0217] Fig.10 A schematic diagram of the structure of an electronic device provided for an embodiment of the present disclosure. The electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0218] like Fig.10 As shown, the device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the device 1000 can also be stored. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0219] A number of components in the device 1000 are connected to the I / O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a disk, an optical disk, etc.; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0220] The computing unit 1001 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1001 performs the various methods and processes described above, such as the sensor data caching method. For example, in some embodiments, the sensor data caching method may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 1008. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, one or more steps of the sensor data caching method described above may be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the sensor data caching method in any other appropriate manner (eg, by means of firmware).

[0221] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0222] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0223] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0224] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0225] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0226] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services ("Virtual Private Server", or "VPS" for short). The server may also be a server of a distributed system, or a server combined with a blockchain.

[0227] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0228] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A sensor data caching method, comprising: Acquire the data to be cached collected by any preset sensor, and store the data to be cached in a first cache area associated with the preset sensor in a field programmable logic gate array; In response to satisfying a preset data writing condition, writing the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory communicatively connected to the field programmable logic gate array; The update status of the data to be cached is written into a preset cache area in a first-in-first-out manner, wherein the update status includes data types and operation lengths of multiple data packets corresponding to the current write operation.

2. The method according to claim 1, wherein: In response to satisfying a preset data writing condition, writing the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory communicatively connected to the field programmable logic gate array comprises: In response to the to-be-cached data in the first cache area satisfying a preset trigger condition, determining a first storage state, wherein the first storage state includes a cache state associated with the first cache area and a cache state associated with the second cache area; In response to the first storage state satisfying a preset condition, the to-be-cached data is written into the second cache area.

3. The method according to claim 2, wherein: In response to the first storage state satisfying a preset condition, writing the to-be-cached data into the second cache area comprises: If it is determined based on the first storage state that both the first cache area and the second cache area are full and there is overflow data, discarding the data to be cached; If it is determined based on the first storage state that both the first cache area and the second cache area are full but there is no overflow data, returning to the step of determining the first storage state until there is storage space in the second cache area, and writing the to-be-cached data into the second cache area; If it is determined based on the first storage state that storage space exists in the second cache area, the data to be cached is written into the second cache area.

4. The method according to claim 2, wherein: In response to the to-be-cached data in the first cache area satisfying a preset trigger condition, determining a first storage state includes: Determining whether the amount of data to be cached in the first cache area reaches a preset data amount threshold; If so, the first storage state is determined.

5. The method according to claim 1, wherein: In response to satisfying a preset data writing condition, writing the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory communicatively connected to the field programmable logic gate array comprises: Determine the data volume corresponding to the data to be cached, and determine the transmission parameters preset by the user, wherein the transmission parameters include the number of bytes transmitted per clock beat; Performing a packetization operation on the data to be cached based on the data volume and the transmission parameters to obtain a plurality of data packets to be transmitted; The multiple data packets to be transmitted are written into the second buffer area.

6. The method according to claim 5, wherein: The step of performing a packetization operation on the data to be cached based on the data volume and the transmission parameter to obtain a plurality of data packets to be transmitted includes: Acquire valid data matching the transmission parameters from the data to be cached, and construct the data packet to be transmitted based on the valid data; In response to the amount of remaining valid data in the data to be cached being less than the transmission parameter, determining a byte quantity difference between the remaining valid data and the transmission parameter; A padding code matching the byte quantity difference is inserted into the remaining data to be cached to obtain the data packet to be transmitted.

7. The method according to claim 1, wherein: The step of writing the update status of the data to be cached into a preset cache area in a first-in-first-out manner includes: Performing an encoding operation on the update status according to a preset encoding method to obtain encoded data, wherein the encoded data is used to indicate the data types and operation lengths of multiple data packets corresponding to this write operation; The encoded data is written into the preset buffer area in a first-in-first-out manner.

8. The method according to any one of claims 1 to 7, after writing the update status of the data to be cached into the preset cache area in a first-in-first-out manner, the method further comprises: In response to satisfying a preset data reading condition, determining the target data to be read currently in the preset buffer area based on a first-in-first-out manner; The target data is read from the second buffer area to a third buffer area in the field programmable logic gate array associated with the preset sensor. 9 . The method according to claim 8 , wherein the third cache area and the first cache area are the same cache area.

10. The method according to claim 8, wherein: In response to satisfying a preset data reading condition, determining the target data to be read in a preset buffer area based on a first-in-first-out manner includes: In response to the third cache area having cache space, determining a second cache state, wherein the second cache state includes a cache state associated with the second cache area and a cache state associated with the third cache area; If it is determined based on the second cache state that there is cache space in the third cache area and there is cache data in the second cache area, the target data to be read currently is determined in the preset cache area based on a first-in-first-out method.

11. The method according to claim 8, wherein: The step of determining the target data to be read in the preset buffer area based on the first-in-first-out method includes: Determining multiple data packets to be read in a preset buffer area according to the first-in-first-out method; For each data packet, a decoding operation is performed on the update status associated with the data packet in the preset buffer area based on a preset decoding method to obtain a data type and an operation length corresponding to the data packet; Determine the data type, operation length and user-set transmission parameters corresponding to the data packet, and the memory space and memory address in the second buffer area; The step of reading the target data from the second buffer area to a third buffer area in the field programmable logic gate array associated with the preset sensor comprises: The target data is read from the second cache area to the third cache area based on the memory space and the memory address.

12. The method according to claim 8, wherein: The step of reading the target data from the second buffer area to a third buffer area in the field programmable logic gate array associated with the preset sensor comprises: Unpacking the target data to obtain valid data corresponding to the target data; The valid data is read into the third buffer area.

13. The method according to claim 12, wherein: The unpacking operation on the target data to obtain valid data corresponding to the target data includes: Extracting the first data packet, the last data packet and at least one intermediate data packet from the target data; Determine the first data packet and at least one intermediate data packet as the valid data; For the last data packet, determining whether the last data packet includes padding code; If it exists, the padding code is deleted and the remaining fields in the last data packet are determined as the valid data.

14. The method according to any one of claims 1 to 7, wherein the target memory comprises a double data rate synchronous dynamic random access memory.

15. The method according to any one of claims 1 to 7, after obtaining the data to be cached collected by any preset sensor, further comprising: Determining the data volume corresponding to the data to be cached and preset transmission parameters; According to the data volume and the transmission parameters, a configuration operation is performed on the cache control of the second cache area through a preset configuration interface.

16. A data cache system, comprising a field programmable logic gate array and a preset target memory; the field programmable logic gate array is respectively connected to a plurality of sensors for communication; The field programmable logic gate array includes a plurality of data cache units, and the data cache units correspond one-to-one to a plurality of preset sensors; The double rate synchronous dynamic random access memory includes a plurality of second buffer areas, and the second buffer areas correspond to the sensors one by one; The data cache unit is used to write the to-be-cached data sent by the sensor into a second cache area corresponding to the sensor in the target memory when a preset writing condition is met, wherein: The cache control of the second cache area is dynamically configured based on the data volume of the data to be cached and preset transmission parameters; The data cache unit includes a preset cache area for storing data in a first-in-first-out manner, and the preset cache area is used to store the update status associated with the current write operation; The data cache unit is also used to determine the target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when a preset reading condition is met, and read the target data into the data cache unit.

17. The data cache system according to claim 16, wherein the data cache unit further comprises a cache write module and a cache read module; The cache writing module and the cache reading module are respectively connected to the preset cache area for communication; The cache writing module is used to cache the to-be-cached data sent by the sensor into a preset first cache area, and when a preset writing condition is met, write the to-be-cached data into a second cache area corresponding to the sensor in the target memory; The cache reading module is used to determine the target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when the preset reading condition is met, and read the target data into the third cache area in the cache reading module.

18. The data cache system according to claim 17, wherein: The cache writing module includes a first cache area, a packet assembly module and a write state control module, and the packet assembly module is respectively connected to the first cache area, the write state control module and the second cache area in communication; The first buffer area is used to perform a buffering operation on the data to be buffered collected by the sensor; The write state control module is used to control the packet assembly module to perform a packet assembly operation on the data to be cached when a preset data writing condition is met, and write the packetized data to be cached into the second cache area.

19. The data cache system according to claim 17, wherein: The cache reading module includes a third cache area, an unpacking module and a reading state control module; The unpacking module is respectively connected to the third buffer area, the read state control module and the second buffer area in communication; The read state control module is used to determine the target data to be read in the preset buffer area in a first-in-first-out manner when the read condition is met, and perform a read operation on the target data from the second buffer area; The unpacking module is used to unpack the target data and read valid data in the target data into the third buffer area.

20. The data cache system according to any one of claims 17 to 19, wherein: The storage space of the first cache area and the third cache area is smaller than the storage space of the second cache area.

21. The data cache system according to any one of claims 17 to 19, wherein: The first cache area and the third cache area are a unified cache area.

22. The data cache system according to any one of claims 16 to 19, wherein: The target memory includes a double data rate synchronous dynamic random access memory.

23. A sensor data caching device, comprising: An acquisition module, used for acquiring data to be cached collected by any preset sensor, and storing the data to be cached in a first cache area associated with the preset sensor in a field programmable logic gate array; a writing module, configured to write the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory communicatively connected to the field programmable logic gate array in response to satisfying a preset data writing condition; The update module is used to write the update status of the data to be cached into the preset cache area in a first-in-first-out manner, and the update status includes the data types and operation lengths of multiple data packets corresponding to the current write operation.

24. The device according to claim 23, wherein: The writing module comprises: a determining unit, configured to determine a first storage state in response to the to-be-cached data in the first cache area satisfying a preset trigger condition, wherein the first storage state includes a cache state associated with the first cache area and a cache state associated with the second cache area; A writing unit is used to write the to-be-cached data into the second cache area in response to the first storage state satisfying a preset condition.

25. The device according to claim 24, wherein: The writing unit comprises: a first processing sub-unit, configured to discard the data to be cached if it is determined based on the first storage state that both the first cache area and the second cache area are full and there is overflow data; a second processing sub-unit, configured to return to the step of determining the first storage state until storage space exists in the second cache area, and write the to-be-cached data into the second cache area if it is determined based on the first storage state that both the first cache area and the second cache area are in a full state but there is no overflow data; A writing subunit is used to write the to-be-cached data into the second cache area if it is determined that there is storage space in the second cache area based on the first storage state.

26. The device according to claim 24, wherein: The determining unit comprises: A determination subunit, configured to determine whether the amount of data to be cached in the first cache area reaches a preset data amount threshold; A determining subunit is configured to determine the first storage state if yes.

27. The device according to claim 23, wherein: The writing module comprises: A determination unit, configured to determine the amount of data corresponding to the data to be cached, and to determine a transmission parameter preset by a user, wherein the transmission parameter includes the number of bytes transmitted per clock tick; A packetizing unit, configured to perform a packetizing operation on the data to be cached based on the data volume and the transmission parameters to obtain a plurality of data packets to be transmitted; A writing unit is used to write the multiple data packets to be transmitted into the second buffer area.

28. The device according to claim 27, wherein The packaging unit comprises: An acquisition subunit, configured to acquire valid data matching the transmission parameters from the data to be cached, and construct the data packet to be transmitted based on the valid data; a determination subunit, configured to determine a byte quantity difference between the remaining valid data and the transmission parameter in response to the amount of data of the remaining valid data in the data to be cached being less than the transmission parameter; The padding subunit is used to insert a padding code matching the byte quantity difference into the remaining data to be cached to obtain the data packet to be transmitted.

29. The device according to claim 23, wherein: The update module includes: An encoding unit, used for performing an encoding operation on the update status according to a preset encoding method to obtain encoded data, wherein the encoded data is used to indicate the data types and operation lengths of multiple data packets corresponding to this write operation; The updating unit is used to write the encoded data into the preset buffer area in a first-in-first-out manner.

30. The device according to any one of claims 23 to 29, further comprising: A determination module, configured to determine the target data to be read in a preset buffer area based on a first-in-first-out manner in response to satisfying a preset data reading condition; A reading module is used to read the target data from the second buffer area into a third buffer area in the field programmable logic gate array associated with the preset sensor.

31. The device according to claim 30, wherein the third cache area and the first cache area are the same cache area.

32. The device according to claim 30, wherein: The determination module comprises: a determining unit, configured to determine a second cache state in response to the existence of cache space in the third cache area, wherein the second cache state includes a cache state associated with the second cache area and a cache state associated with the third cache area; The reading unit is used to determine the target data to be read in the preset cache area based on a first-in-first-out manner if it is determined based on the second cache state that there is cache space in the third cache area and there is cache data in the second cache area.

33. The device according to claim 30, wherein: The determining unit comprises: A determination subunit, used to determine a plurality of data packets to be read currently in a preset buffer area according to the first-in-first-out method; A decoding subunit, configured to perform a decoding operation on the update status associated with the data packet in the preset buffer area based on a preset decoding method for each data packet, and obtain a data type and an operation length corresponding to the data packet; A mapping subunit, used to determine the data type, operation length and user-set transmission parameters corresponding to the data packet, and the memory space and memory address in the second buffer area; The reading unit comprises: A reading subunit is used to read the target data from the second cache area to the third cache area based on the memory space and the memory address.

34. The device according to claim 30, wherein: The reading module comprises: An unpacking unit, used to unpack the target data to obtain valid data corresponding to the target data; A reading unit is used to read the valid data into the third buffer area.

35. The device according to claim 34, wherein The unpacking unit comprises: An extraction subunit, used to extract the first data packet, the last data packet and at least one intermediate data packet from the target data; A determination subunit, configured to determine the first data packet and at least one intermediate data packet as the valid data; an identification subunit, configured to determine, for the last data packet, whether the last data packet includes a padding code; The deletion subunit is used to delete the padding code if it exists, and determine the remaining fields in the last data packet as the valid data.

36. The apparatus according to any one of claims 23 to 29, wherein the target memory comprises a double data rate synchronous dynamic random access memory.

37. The device according to any one of claims 23 to 29, further comprising: A determination module, used to determine the data volume corresponding to the data to be cached and preset transmission parameters; A configuration module is used to configure the cache control of the second cache area through a preset configuration interface according to the data volume and transmission parameters.

38. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 15.

39. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-15.

40. A computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 15.

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