Decoding module digital-analog hybrid simulation method and simulation system based on V-am language

Abstract

The invention discloses a digital-analog hybrid simulation method and simulation system for a decoding module based on a V-am language. The simulation method comprises the following steps: electrifying an analog circuit, and carrying out signal initialization on a decoding circuit of a tested chip; driving an advanced peripheral bus to perform register configuration; exciting by using the data file, and extracting data; performing data conversion on each channel signal to convert into two differential signals of which the phase difference is 180 degrees; the differential signal is input into the register transmission stage of the analog circuit for processing, and the register transmission stage of the analog circuit processes data and then outputs the data to the register transmission stage of the digital circuit for decoding operation; data acquisition and transmission to the system control module; and performing data comparison and displaying a result. According to the invention, the joint simulation of the digital circuit and the analog circuit is realized, and the consistency of the analog circuit and the digital circuit in the working time sequence is ensured.

Description

Technical Field

[0001] The invention relates to a decoding module digital-analog hybrid simulation method based on V-ams language, and also relates to a corresponding decoding module digital-analog hybrid simulation system, belonging to the technical field of integrated circuit testing. Background Art

[0002] SoC (System on Chip) chip design integrates digital circuits, analog circuits, microprocessors, etc. on a single silicon chip to build a complex system to achieve advanced functions. With the widespread application of SoC chips, the interaction between digital and analog parts has become increasingly prominent, especially in the simulation verification stage. The verification of the digital-analog interaction level has become a key and under-resolved area in SoC chip verification, which poses a challenge to the overall performance and reliability of the chip.

[0003] Faced with the increasing complexity of chip design, the task of hardware verification has become more arduous, and the verification time has also been extended. According to authoritative research reports in the industry, only 39% of designs can pass the first silicon verification without defects, while 60% of designs have logical or functional defects, and more than 20% of designs require three or more silicon verifications. In addition, verification work occupies about 50% of the entire engineering time. Therefore, when evaluating and verifying mixed-analog SoC chips, traditional separate digital simulators and analog simulators are no longer sufficient to meet the needs, and analog and digital mixed simulation technology must be used to solve the challenges of mixed signal synchronous simulation. To this end, many EDA vendors provide a method of co-simulation, that is, connecting an analog simulator and a digital simulator through a "platform". The digital part is simulated by a digital simulator, the analog part is simulated by an analog simulator, and the interface signals of the digital part and the analog part are synchronized through the "platform". This verification method improves the simulation efficiency and realizes the simulation of the entire SoC system.

[0004] On the other hand, the single digital simulator is generally Synopsys's VCS, while the analog circuit is generally Cadence's XRun (or Finsim). The two are incompatible and cannot achieve simultaneous simulation of digital + analog circuits. However, simulating any independent circuit alone cannot check whether the logical relationship and timing of the two are correct. Figure 1 In a typical mixed-analog simulation system shown in the figure, the digital circuit simulator uses ncsim and the analog circuit uses xrun. Both tools belong to cadence to solve compatibility issues. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a mixed digital-analog simulation method for a decoding module based on the V-ams language.

[0006] Another technical problem to be solved by the present invention is to provide a mixed digital-analog simulation system of a decoding module based on the V-ams language.

[0007] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, a method for mixed analog-digital simulation of a decoding module based on V-ams language is provided, comprising the following steps:

[0009] Step 1: Power on the simulation circuit and initialize the signal of the decoding circuit of the chip under test;

[0010] Step 2: Drive the high-level peripheral bus to configure registers;

[0011] Step 3: Use data files for stimulation and extract data;

[0012] Step 4: Perform data conversion on each channel signal to convert it into two differential signals with a phase difference of 180°;

[0013] Step 5: Input the differential signal to the register transfer stage of the analog circuit for processing. After the register transfer stage of the analog circuit processes the data, it is output to the register transfer stage of the digital circuit for decoding operation;

[0014] Step 6: Data collection and transmission to the system control module;

[0015] Step 7: Compare data and display the results.

[0016] Preferably, the stimulus is a hexadecimal or decimal data file, which is shared by the register transfer stage of the digital circuit and the register transfer stage of the analog circuit.

[0017] Preferably, the signal initialization operation generates a stimulus input timing of a control signal required by an analog circuit, and controls data extraction to drive a register transfer stage of a digital circuit and a register transfer stage of an analog circuit using the same test vector.

[0018] Preferably, the register transfer stage of the analog circuit is implemented through an operational amplifier based on a Verilog-A model.

[0019] Preferably, the operation of performing data conversion on the signals of each channel includes offsetting the common-mode signal in the signal to serve as the first differential signal in the channel; and then flipping the first differential signal with the common-mode signal as the central axis to serve as the second differential signal in the channel, so as to convert the signal of the same channel into two differential signals as a group of differential signals of the channel.

[0020] Preferably, each group of differential signals of each channel is de-jittered and the direct current is blocked, and then input into the register transfer stage of the analog circuit.

[0021] According to a second aspect of an embodiment of the present invention, a decoding module digital-analog hybrid simulation system based on V-ams language is provided, comprising:

[0022] A system control module is communicatively connected with the adapter;

[0023] The adapter is communicatively connected with the bus function module and the test agent module respectively;

[0024] The bus function module is connected to the register transfer stage of the analog circuit, and the test agent module is connected to the register transfer stage of the digital circuit;

[0025] The register transfer stage of the digital circuit receives a signal of a test case, and the register transfer stage of the analog circuit receives a data signal of a data extraction circuit.

[0026] The data extraction circuit includes a data extraction module including a channel data processing module, a signal conversion module and a common-mode signal adjustment module, wherein the channel data processing module collects the aforementioned multi-channel analog signals and splits them into signals of each channel, and the signal conversion module converts the signals of each channel into digital signals; the common-mode signal adjustment module offsets the common-mode signal of the signal as the first differential signal in the channel; and then flips the first differential signal with the common-mode signal as the central axis as the second differential signal in the channel, so as to convert the signal of the same channel into two differential signals, which are output as a group of differential signals of the channel to the register transfer stage of the analog circuit.

[0027] Preferably, the register transfer stage of the analog circuit is responsible for processing analog signals; the register transfer stage of the digital circuit is responsible for processing digital signals;

[0028] During the simulation process, the register transfer stage of the analog circuit receives a control signal from the register transfer stage of the digital circuit to ensure that the behavior of the analog part meets the requirements of the digital control logic.

[0029] Preferably, the data extraction module extracts data from multiple channels by putting the hexadecimal or decimal data file into the simulation environment;

[0030] The data conversion module converts the extracted data of multiple channels into two differential signals with a phase difference of 180°, and sends them to the register transfer stage of the analog circuit.

[0031] Preferably, in the register transfer stage of the analog circuit, each group of differential signal inputs of each channel is used as the control timing, the bus driver generates an excitation signal according to the test case for processing, and outputs it to the register transfer stage of the digital circuit for decoding.

[0032] Compared with the prior art, the present invention has significant advantages in the simulation of digital plus analog logic functions of differential signal type encrypted data. By using the ncsim and xrun tools of Cadence, the present invention realizes the joint simulation of digital circuits and analog circuits, ensuring the consistency of the working timing of analog circuits and digital circuits. In addition, the present invention can convert multi-bit data into two differential signals for input, and collect the data of the analog circuit through the digital circuit to evaluate the analog parameter indicators such as the working power consumption and performance of the analog circuit, thereby ensuring the correctness and performance matching of the two-end interaction. At the same time, the present invention also provides a joint simulation environment of digital Verilog and analog nc_verilog, which supports the simulation of various ideal waveform files, randomly generated waveform files, and real card waveform files, etc., and enhances the flexibility and practicality of the simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the logical structure of an analog and digital hybrid simulation platform in the first embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of real data collected in an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of a differential signal obtained by data conversion in an embodiment of the present invention;

[0036] Figure 4 Schematic diagram of a data extraction circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The technical concept in the embodiment of the present invention is to jointly simulate the digital module and the analog module to ensure that the interface definition, working timing, state jump, etc. at both ends are consistent, and the working performance index of the analog circuit is confirmed so that the analog circuit and the digital circuit interact correctly and the performance is matched. In addition, differential signals are used to ensure the security of confidential data.

[0039] First embodiment

[0040] Figure 1The present invention provides a first embodiment of a V-ams language based decoding module digital-analog hybrid simulation system (hereinafter referred to as "simulation system"), which is used to perform analog and digital hybrid simulation on differential signal input decoding SoC chips.

[0041] The ports of this type of SoC chip are capable of receiving differential input signals. Differential signaling is a common signal transmission method in which the two signals are the same but have opposite polarities. In the SoC chip, these differential input signals are first received and processed by the analog circuit part. Then, the received analog signals are converted into digital signals after preliminary processing by the analog circuit inside the SoC chip. These digital signals are then digitally decoded by the digital logic circuit to extract useful information or perform specific digital processing tasks. For example, digital logic decoding may include operations such as signal amplification, filtering, comparison, and counting. The information decoded by the digital logic may need to be fed back to the analog circuit to control the behavior of the analog circuit, such as adjusting the amplitude, frequency, or other characteristics of the analog signal to meet specific application requirements.

[0042] In differential signal input decoding SoC chips, the common mode feedback (CMFB) mechanism is very important. Because the common mode feedback mechanism can achieve a stable output common mode level, ensuring that the chip is not affected by device characteristics and mismatch, thereby ensuring signal integrity and circuit performance. For this reason, the analog common mode feedback mechanism becomes the key point of this type of SoC chip, and the corresponding processing of differential signals also becomes the focus.

[0043] Combination Figure 1 and Figure 4 The simulation system includes a system control module (SCB) and an adapter that are in communication connection; the adapter is in communication connection with a bus function module (bus) and a test agent module (agent) respectively; the bus function module is connected to a register transfer level (Register Transfer Level) of an analog circuit, and the test agent module is connected to a register transfer level of a digital circuit; the register transfer level of the digital circuit receives a signal of a test case (test-case), and the register transfer level of the analog circuit receives a data signal of a data extraction circuit.

[0044] The register transfer stage of the analog circuit is responsible for processing analog signals, such as voltage and current, which are usually generated by analog circuits. The register transfer stage of the digital circuit processes digital signals, such as logic levels and clock signals, which are generated by digital circuits. During the simulation process, the register transfer stage of the analog circuit receives control signals from the register transfer stage of the digital circuit to ensure that the behavior of the analog part meets the requirements of the digital control logic.

[0045] The register transfer level of the digital circuit collects chip signals generated by the test cases. These signals simulate various input conditions that the actual chip may encounter during operation, and are used to verify the correctness and robustness of the chip design.

[0046] The register transfer stage of the analog circuit receives the data signal from the data extraction circuit. The data extraction circuit includes a data extraction module and a data conversion module. The data extraction module extracts the data of three channels from the hexadecimal or decimal data file put into the simulation environment; the data conversion module converts the data of the three channels extracted into two differential signals with a phase difference of 180° and sends them to the register transfer stage of the analog circuit.

[0047] In mixed-analog simulation, the cooperation between the bus function module (BFM) and the register transfer level of the digital circuit is key. The register transfer level of the digital circuit is responsible for processing the digital logic part, while the BFM is responsible for the interface between analog and digital logic. This cooperation ensures that the analog signal can be correctly converted into a digital signal.

[0048] BFM includes bus driver (bus-drv) and bus monitor (bus-monitor), which are used to encapsulate the timing of the low-level bus and provide a calling interface for the high-level.

[0049] Among them, the bus driver (bus-drv) is responsible for generating stimulus signals according to the test case and sending them to the register transfer level of the analog circuit. It simulates the external signals that the chip may receive during actual operation, such as input data, control signals, etc. By accurately simulating these signals, the bus driver ensures that the register transfer level of the analog circuit can respond to the expected stimulus, thereby verifying its function and performance.

[0050] The bus monitor is responsible for monitoring the output signals of the register transfer level of the analog circuit. It captures the response generated by the RTL and compares it with the expected results. If any inconsistencies are found, the bus monitor will record these differences for subsequent analysis and debugging. This real-time monitoring helps to discover and locate problems in a timely manner, thereby improving the accuracy and reliability of the simulation. The bus monitor monitors the data of multiple (for example, three) channels, and transmits the collected information to the adapter after packaging and sorting, and then transmits it to the system control module. The data of the three channels corresponds to three channel monitors, and each channel monitor is only responsible for monitoring one set of buses.

[0051] The test agent module (Agent) includes an agent driver (Agent-drv) and an agent monitor (Agent-monitor), wherein the agent driver is responsible for generating stimulus, while the agent monitor is responsible for monitoring the action of the digital circuit and collecting the data decoded by the digital decoding circuit.

[0052] In conventional digital verification platforms, an agent driver (Agent-drv) is required to generate stimulus signals according to test cases, and transparent transmission is used to transparently transmit the signals generated by the register transfer level of the analog circuit to the register transfer level of the digital circuit. In the simulation platform (Testbench), the output signal of the analog circuit is directly connected to the input port of the digital circuit, or the output signal of the digital circuit is directly connected to the input port of the analog circuit. In this way, by defining the connection between the analog and digital circuits, the transparent transmission of the signal is realized, so the agent driver (Agent-drv) can be omitted.

[0053] During the simulation process, the agent monitor is responsible for monitoring the output signals and decoded data of the register transfer stage of the digital circuit. The agent monitor captures the response generated by the register transfer stage of the digital circuit, collects the decoded data and puts it into the data queue, and then transmits the data packet to the system control module through the pipeline to compare it with the expected result. The agent monitor also performs timing judgment on some control signals in real time. If any inconsistency is found, the agent monitor will record these differences for subsequent analysis and debugging. This real-time monitoring helps to detect and locate problems in a timely manner, thereby improving the accuracy and reliability of the simulation.

[0054] Therefore, the test agent module (Agent) simulates a specific communication protocol to ensure that the signal strictly complies with the protocol regulations when it is transmitted between the register transfer level of the analog circuit and the register transfer level of the digital circuit. This means that whether it is data format, timing requirements or error handling mechanism, the Agent can ensure that the behavior of the register transfer level of the digital circuit meets the predetermined protocol standards. This strict protocol compliance check helps prevent problems caused by protocol misunderstandings or errors and ensures the accuracy of the simulation results.

[0055] The bus monitoring and agent monitoring transmit the signal to the system control module through the adapter. The system control module compares the data of multiple (for example, three) channels (from the bus monitoring) with the decoded data (from the agent monitoring) and displays the comparison result.

[0056] The system control module is responsible for managing and controlling various operations during the simulation process. It communicates with the adapter and passes simulation control signals or test vectors to the adapter. The adapter acts as a bridge between the simulation platform and the chip under test (DUT), ensuring that signals can be correctly converted between different interfaces and protocols.

[0057] Second embodiment

[0058] Next, in conjunction with the above-mentioned decoding module digital-analog hybrid simulation system based on the V-ams language, a decoding module digital-analog hybrid simulation method based on the V-ams language provided by the second embodiment of the present invention is introduced.

[0059] As mentioned before, the V-ams language-based decoding module digital-analog hybrid simulation system uses nc_verilog to build a platform, which can perform interactive simulation of digital verilog and analog nc_verilog. Use the compiler provided by nc_verilog, such as ncvlog, to compile the Verilog source file, generate the intermediate file required for simulation, describe the compiled design through the ncelab tool, generate the simulation snapshot, and use ncsim to simulate the snapshot. During the simulation process, you can use tools such as SimVision to view and debug the waveform.

[0060] The embodiment of the present invention uses Cadence's VAMS and Verilog-A to create an analog and digital hybrid simulation environment that can process digital and analog circuits at the same time. In this way, the interaction between digital and analog circuits can be verified on the same simulation platform without setting up different test platforms for the two.

[0061] In Cadence, create Verilog-A models of analog circuits and Verilog codes of digital circuits, define the electrical characteristics and behaviors of the circuits for the analog circuit models, describe the behavioral models of the analog circuits, and define input / output ports for the digital circuit codes.

[0062] The simulation platform (Testbench) is the top-level module for the interaction between analog and digital circuits. The Verilog module of the digital circuit and the Verilog-A model of the analog circuit are instantiated in the Testbench. The aforementioned simulation system is used to generate test stimulus signals, drive the DUT, and collect response data. The Testbench provides code for signal initialization, test sequence, monitoring, and analysis of circuit responses.

[0063] To perform mixed-analog simulation, you need to define the interface between digital and analog circuits and create Connect Modules, which define the correspondence between digital logic levels and analog voltage levels. Defining interfaces and connection rules involves the conversion of voltage and logic levels. In Cadence, you can use Connect Rules to define these conversions.

[0064] refer to Figure 2 In order to accurately simulate the SoC chip controlled by the voltage source, the embodiment of the present invention is based on the Verilog-A language and uses Cadence for software coding to build a simulation environment. The VAMS tool realizes the seamless connection between the analog circuit and the digital circuit, and transmits the key interface signals to the Testbench layer for effective signal driving and data collection. In terms of power consumption and performance analysis, the $cgav function in Verilog-A is used to collect current values ​​from the power supply VDD interface, and the power consumption and performance parameters of the module are calculated accordingly. In addition, other analog parameters such as voltage and flip time can also be obtained through monitoring means.

[0065] In order to ensure the accuracy of the simulation data, the actual collected waveform files were specially processed: through the conversion model written in VAMS, these waveform files were converted into differential signals of the ADC for simulation. Therefore, the consistency of the simulation results and the actual chip test results was ensured. In the pursuit of simulation efficiency, the clock module was also optimized and replaced with an ideal source using the VAMS model, which simplified the simulation process and improved efficiency.

[0066] More importantly, the embodiment of the present invention converts the encrypted multi-bit data into a differential signal, which can improve the anti-interference ability of the signal, thereby avoiding the risk of eavesdropping or leakage of encrypted data to a certain extent. A differential signal refers to a signal transmitted on two transmission lines, and the two signals have the same amplitude but opposite phases. When external interference affects the two lines, since the interference is usually the same on the two lines, the receiving end determines the logical state of the transmission by comparing the voltage difference on the two lines, which can effectively offset the influence of the external interference and maintain the integrity and accuracy of the signal. In the scenario of encrypted data transmission, by using differential signal transmission, even if the data is intercepted during the transmission process, due to the anti-interference characteristics of the differential signal, it is difficult for an illegal receiver to recover valid data from the interference, thereby protecting the security of the data. In addition, the characteristics of the differential signal at the physical level also help prevent signal leakage. Since the voltage difference of the differential signal is small, its electromagnetic radiation in space is also relatively small, which makes it more difficult to steal the signal in a non-contact manner. Therefore, the present invention is particularly suitable for application fields that require high security, such as the military and financial industries. In these fields, the security performance of the chip is extremely important, and the present invention can ensure the security and reliability of the chips used in these security-sensitive applications during the design and verification stages.

[0067] The second embodiment of the present invention provides a mixed digital-analog simulation method for a decoding module based on the V-ams language, which includes at least the following steps.

[0068] Step 1: Power on the simulation circuit and initialize the signal of the decoding circuit of the chip under test.

[0069] In this step, the analog circuit is powered on, and the signal initialization operation is completed for the digital DUT (ie, the SoC chip model under test) through the driver in the digital environment.

[0070] By completing the signal initialization operation on the digital decoding circuit controller, the stimulus input timing of the control signal required for the register transfer level of the analog circuit is generated to control the extraction of data (such as the signal generated by the bus driver according to the test case). Therefore, the same test vector can be used to drive the digital circuit and the analog circuit to ensure that the interface definition, working timing, state jump, etc. at both ends are consistent, thereby ensuring the consistency of the test.

[0071] Table 1: Test function point decomposition table (test vector example)

[0072]

[0073] Step 2: Drive the high-level peripheral bus to configure registers.

[0074] TEST_CASE drives the Advanced PeripheralBus through the bus driver (bus_drv) to read and write registers, configure the digital circuit controller, initialize parameters, and generate analog circuit control signal input stimulus. This can be achieved by adding corresponding control logic in the Testbench.

[0075] Step 3: Use the data file for stimulation and extract data.

[0076] The data file (txt format file) of hexadecimal or decimal data as stimulus is placed in the simulation environment to drive analog circuits and digital logic circuits. The hexadecimal or decimal data file can be shared by the register transfer level of the digital circuit and the register transfer level of the analog circuit. This reuse of data files reduces the repeated development of test vectors and ensures the consistency of test data.

[0077] In the Testbench, the data of the hexadecimal or decimal data file is read into the fscanf function (a function in C language used to format and read data from the file and store the data in appropriate variables), then converted into an analog signal through a DAC and given to the differential signal (see Figure 3 ) and use it as a test stimulus. In this way, the data extraction circuit can extract the required data from the file during the simulation and provide it to the digital DUT. Here, the data extraction circuit extracts data from multiple (for example, three) channels to prevent data serialization. Figure 2 An example of actually extracting data is provided in .

[0078] Specifically, if Figure 4 As shown, the data extraction module includes a channel data processing module, a signal conversion module and a common mode signal adjustment module connected in sequence. Among them, the channel data processing module collects the aforementioned multi-channel analog signals, splits the multi-channel analog signals into data, and obtains each channel signal (channel 1 split data, channel 2 split data and channel 3 split data). In this way, the multi-channel signal is split into individual channel signals for separate processing.

[0079] Step 4: Perform data conversion on the signals of each channel and convert them into two differential signals with a phase difference of 180°.

[0080] like Figure 3As shown, the signal conversion module includes analog-to-digital conversion channel 1, analog-to-digital conversion channel 2, and analog-to-digital conversion channel 3. Based on the connection rules (connrules), the signal conversion module converts the signals of each channel into digital signals. Select the most appropriate connrule mode according to the specific simulation requirements and circuit characteristics. For example, if the circuit is very sensitive to the analog load effect, you may need to select the full mode for more accurate simulation; if you have high requirements for simulation speed and the circuit is not sensitive to the load effect, you can select the basic mode to speed up the simulation process.

[0081] In the common-mode signal adjustment module, the common-mode part of the signal (common-mode signal) is offset to serve as the first differential signal in the channel; the first differential signal is then flipped around the common-mode signal as the center axis to serve as the second differential signal in the channel. Therefore, after the common-mode signal adjustment, the signal of the same channel is converted into two differential signals (see Figure 3 ), that is, each channel has a set of differential signals. Common-mode signals refer to the signal parts that exist in both channels of the differential signal. Adjusting the common-mode signal can improve the signal's anti-interference ability.

[0082] More preferably, each group of differential signals of each channel is de-jittered and DC is blocked before being input into the register transfer stage of the analog circuit.

[0083] Through the above steps, the present invention can convert the analog signals of each channel into differential signals for simulation. In this way, the signal processing process is not affected by the quantization range or interference, so the accuracy of the simulation result is guaranteed.

[0084] Step 5: Input the differential signal to the register transfer stage of the analog circuit for processing. After the register transfer stage of the analog circuit processes the data, it is output to the register transfer stage of the digital circuit for decoding operation.

[0085] In the register transfer stage of the analog circuit, each group of differential signals of each channel is input into the register transfer stage of the circuit to be simulated as the control timing, and the bus driver generates an excitation signal according to the test case for processing. After the register transfer stage of the circuit to be simulated is processed, the register transfer stage of the digital circuit is started. The register transfer stage of the digital circuit collects the data output by the register transfer stage of the analog circuit and performs subsequent decoding processing.

[0086] Usually, when performing analog simulation, it can only be performed according to the quantization range of the internal analog-to-digital converter (ADC). Therefore, due to this limitation, it is impossible to input actual encrypted data. However, in the embodiment of the present invention, an operational amplifier is used to split, convert and adjust the amplitude of the collected multi-channel data based on the Verilog-A model (see Figure 4 ), is not affected by the quantization range and can convert the encrypted data into differential signals for simulation, thus ensuring the correctness of the simulation results.

[0087] Step 6: Data collection and transmission to the system control module.

[0088] Use Agent-monitor to monitor the digital demodulated data and transmit the collected data to the system control module. In Testbench, you can write code to write the processed data to the monitoring tool.

[0089] The register transfer stage of the digital circuit collects the data output by the register transfer stage of the analog circuit and decodes it for testing and verification. This collection mechanism ensures that the output of the analog circuit can be analyzed on the digital test platform, thereby ensuring the consistency of the test indicators.

[0090] Step 7: Compare data and display the results.

[0091] Use tools provided by Cadence, such as SimVision, to view and analyze simulation results and check whether the interaction between digital and analog circuits is as expected.

[0092] Specifically, the system control module compares the known decoded data (provided by the algorithm model) with the decoded data received from the Agent-monitor detection. If they are the same, it is judged that the comparison is passed and the simulation screen will display the pass; if they are different, the comparison information will be prompted. This can be achieved by adding corresponding inspection logic in the Testbench.

[0093] In summary, in the above steps, a mixed-signal simulation environment is created through VAMS and Verilog-A provided by Cadence. This simulation environment can process digital and analog circuits at the same time. Because VAMS is an extension of Verilog, it allows simulation of continuous-time physical systems such as analog circuits and mixed-signal systems to support the modeling and simulation of analog circuits, and can be co-simulated with digital logic circuits, allowing analog and digital signals to be processed simultaneously in the same simulation environment.

[0094] These steps achieve consistency in test metrics by integrating the testing of digital and analog circuits on the same simulation platform, allowing the use of the same test vectors and test tools. This approach not only improves test efficiency, but also reduces design issues caused by inconsistent test environments.

[0095] Moreover, the present invention can compile analog schematics and digital verliog at the same time, and perform interactive simulation of both parties at the digital and analog levels to obtain real simulation data, and can reuse the verification platform of the digital module, reduce the amount of code writing, be compatible with analog design test vectors, ensure the consistency of test indicators and the graphical interface simulation parameters of the Cadence tool, and facilitate problem reproduction.

[0096] It should be noted that Figure 1 The Bus_monitor and Agent_drv in the embodiment are used in the digital circuit verification, and are not needed in the simulation process of each embodiment of the present invention, so they can be omitted. However, because the digital platform is directly reused in each embodiment, the digital platform can have the same structure as the digital-analog hybrid simulation system in each embodiment of the present invention, which can reduce costs (compared to the case of using a structure different from the digital platform).

[0097] The present invention is aimed at emulating a specific type of Soc chip, that is, a mixed digital-analog simulation of the Soc chip with analog differential input of the port, digital logic decoding and feedback analog circuit. The early data processing includes processing the differential signal, which can support the simulation of the actual card waveform data. The test vector can be shared with the digital simulation platform, and the product problem can be reproduced and simulated.

[0098] It should be noted that the above multiple embodiments are only examples. The technical solutions of various embodiments can be combined, and the order of various steps can be changed, all within the scope of protection of this patent.

[0099] The above is a detailed description of the decoding module digital-analog hybrid simulation method and simulation system based on the V-ams language provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear the corresponding legal liability.

Claims

1. A mixed analog-digital simulation method for a decoding module based on V-ams language, characterized in that The following steps are involved: Step 1: Power on the simulation circuit and initialize the signal of the decoding circuit of the chip under test; Step 2: Drive the high-level peripheral bus to configure registers; Step 3: Use data files for stimulation and extract data; Step 4: Perform data conversion on each channel signal to convert it into two differential signals with a phase difference of 180°; Step 5: Input the differential signal to the register transfer stage of the analog circuit for processing. After the register transfer stage of the analog circuit processes the data, it is output to the register transfer stage of the digital circuit for decoding operation; Step 6: Data collection and transmission to the system control module; Step 7: Compare data and display the results.

2. The decoding module digital-analog hybrid simulation method based on V-ams language as claimed in claim 1, characterized in that: The stimulus is a hexadecimal or decimal data file, which is shared by the register transfer stage of the digital circuit and the register transfer stage of the analog circuit.

3. The decoding module digital-analog hybrid simulation method based on V-ams language as claimed in claim 1 or 2, characterized in that: The signal initialization operation generates a stimulus input timing of a control signal required by an analog circuit and controls data extraction to drive a register transfer stage of a digital circuit and a register transfer stage of an analog circuit using the same test vector.

4. The V-ams language-based decoding module digital-analog hybrid simulation method as claimed in claim 3, characterized in that: The register transfer stage of the analog circuit is implemented through an operational amplifier based on a Verilog-A model.

5. The V-ams language-based decoding module digital-analog hybrid simulation method as claimed in claim 3, characterized in that The operations for data conversion of each channel signal include: The common mode signal in the signal is offset to serve as the first differential signal in the channel; the first differential signal is then flipped with the common mode signal as the center axis to serve as the second differential signal in the channel, so as to convert the signal of the same channel into two differential signals as a group of differential signals of the channel.

6. The V-ams language-based decoding module digital-analog hybrid simulation method according to claim 5, characterized in that: Each group of differential signals of each channel is de-jittered and the direct current is blocked, and then input into the register transfer stage of the analog circuit.

7. A hybrid digital-analog simulation system for decoding modules based on V-ams language, characterized in that include: A system control module is communicatively connected with the adapter; The adapter is communicatively connected with the bus function module and the test agent module respectively; The bus function module is connected to the register transfer stage of the analog circuit, and the test agent module is connected to the register transfer stage of the digital circuit; The register transfer stage of the digital circuit receives a signal of a test case, and the register transfer stage of the analog circuit receives a data signal of a data extraction circuit. The data extraction circuit includes a data extraction module including a channel data processing module, a signal conversion module and a common-mode signal adjustment module, wherein the channel data processing module collects the aforementioned multi-channel analog signals and splits them into signals of each channel, and the signal conversion module converts the signals of each channel into digital signals; the common-mode signal adjustment module offsets the common-mode signal of the signal as the first differential signal in the channel; and then flips the first differential signal with the common-mode signal as the central axis as the second differential signal in the channel, so as to convert the signal of the same channel into two differential signals, which are output as a group of differential signals of the channel to the register transfer stage of the analog circuit.

8. The V-ams language-based decoding module digital-analog hybrid simulation system as claimed in claim 7, characterized in that: The register transfer stage of the analog circuit is responsible for processing analog signals; the register transfer stage of the digital circuit processes digital signals; During the simulation process, the register transfer stage of the analog circuit receives a control signal from the register transfer stage of the digital circuit to ensure that the behavior of the analog part meets the requirements of the digital control logic.

9. The V-ams language-based decoding module digital-analog hybrid simulation system as claimed in claim 8, characterized in that: The data extraction module extracts data from multiple channels by putting the hexadecimal or decimal data file into the simulation environment; The data conversion module converts the extracted data of multiple channels into two differential signals with a phase difference of 180°, and sends them to the register transfer stage of the analog circuit.

10. The V-ams language-based decoding module digital-analog hybrid simulation system according to claim 9, characterized in that: In the register transfer stage of the analog circuit, each group of differential signal inputs of each channel is used as the control timing, and the bus driver generates a stimulus signal according to the test case for processing and output to the register transfer stage of the digital circuit for decoding.

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