Chip Design Index Generation Model Training Method, Device and Computer Equipment

Abstract

The present application relates to a method, apparatus, and computer device for training a chip design metric generation model. The method includes: obtaining a set of physical design parameter configurations; respectively inputting each physical design parameter configuration into a placement analysis tool, a clock tree analysis tool, and a routing analysis tool to obtain chip design metrics; generating a new physical design parameter configuration and a new set of physical design parameter configurations according to the chip design metrics; returning to execute the step of respectively inputting each physical design parameter configuration into the placement analysis tool, the clock tree analysis tool, and the routing analysis tool until the chip design metrics corresponding to any physical design parameter configuration meet the preset metric requirements to obtain target chip design metrics; determining training samples according to the target chip design metrics and the corresponding physical design parameter configurations, and training the chip design metric generation model using the training samples. Using this method can improve the efficiency of chip design.

Description

Technical Field

[0001] The present application relates to the technical field of chip design, and in particular, to a method, apparatus, computer device, computer-readable storage medium, and computer program product for training a chip design index generation model. Background Art

[0002] Electronic Design Automation (EDA) emerged along with the emergence of Integrated Circuits (ICs). In the early stage of EDA, the logic design and physical design in integrated circuits were mainly processed in parallel. Wired circuit boards were used to construct logic designs to imitate specific physical circuits in order to verify and simulate whether the designed functions were normal before starting mass production. With the development of circuit simulation and layout verification, it is no longer necessary to use wired circuit boards to construct logic modules, which has greatly accelerated the development of integrated circuits.

[0003] In the process of physical chip design for large circuits, traditional technologies require a lot of time for layout analysis, clock tree analysis, and routing analysis, resulting in an increase in the time spent on chip design and being unfavorable for improving the acquisition efficiency of chip design indicators. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for training a chip design index generation model that can improve the efficiency of chip design.

[0005] In a first aspect, the present application provides a method for training a chip design index generation model, including:

[0006] Obtain a set of physical design parameter configurations; the set of physical design parameter configurations includes at least two physical design parameter configurations; the physical design parameter configurations represent the configuration parameters of a layout analysis tool, the configuration parameters of a clock tree analysis tool, and the configuration parameters of a routing analysis tool;

[0007] Input each physical design parameter configuration in the set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively to obtain chip design indicators corresponding to each physical design parameter configuration in the set of physical design parameter configurations;

[0008] Configure the chip design indicators corresponding to each physical design parameter configuration in the set according to the physical design parameters, generate a new physical design parameter configuration, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set;

[0009] Return to execute the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively, until the chip design indicator corresponding to any physical design parameter configuration in the physical design parameter configuration set meets the preset indicator requirements, and use the chip design indicator that meets the preset indicator requirements as the target chip design indicator;

[0010] Determine a training sample according to the target chip design indicator and the physical design parameter configuration corresponding to the target chip design indicator, and use the training sample to train the chip design indicator generation model to be trained; the chip design indicator generation model is used to determine the chip design indicator according to the output result of the layout analysis tool.

[0011] In one embodiment, the generating a new physical design parameter configuration according to the chip design indicators corresponding to the physical design parameter configurations in the physical design parameter configuration set includes:

[0012] Determine a design indicator threshold according to the chip design indicators corresponding to the physical design parameter configurations in the physical design parameter configuration set;

[0013] Divide the physical design parameter configurations in the physical design parameter configuration set into a first set and a second set according to the design indicator threshold; the chip design indicators corresponding to the physical design parameter configurations in the first set are greater than or equal to the design indicator threshold; the chip design indicators corresponding to the physical design parameter configurations in the second set are less than the design indicator threshold;

[0014] Determine a parameter configuration search space according to the physical design parameter configurations in the physical design parameter configuration set; the parameter configuration search space represents the value range of the physical design parameter configuration;

[0015] Determine the expected improvement value of each physical design parameter configuration in the parameter configuration search space according to the first set and the second set, and screen out the maximum expected improvement value from the expected improvement values;

[0016] Use the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration.

[0017] In one embodiment, inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively to obtain the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set includes:

[0018] Determine the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the routing analysis tool according to each physical design parameter configuration in the physical design parameter configuration set;

[0019] Apply the configuration parameters of the layout analysis tool to the layout analysis tool to obtain the output result of the layout analysis tool;

[0020] Input the output result of the layout analysis tool into the clock tree analysis tool, and apply the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain the output result of the clock tree analysis tool;

[0021] Input the output result of the clock tree analysis tool into the routing analysis tool, and apply the configuration parameters of the routing analysis tool to the routing analysis tool to obtain the output result of the routing analysis tool;

[0022] Determine the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set according to the output result of the layout analysis tool, the output result of the clock tree analysis tool, and the output result of the routing analysis tool.

[0023] In one embodiment, determining the training samples according to the target chip design metrics and the physical design parameter configuration corresponding to the target chip design metrics includes:

[0024] Determine the chip layout parameters according to the physical design parameter configuration, parse the chip layout parameters to obtain a layout image, and convert the layout image into an embedding vector;

[0025] Determine the target vector according to the physical design parameter configuration corresponding to the target chip design metrics and the embedding vector;

[0026] Use the target vector and the target chip design metrics as the training samples.

[0027] In one embodiment, training the chip design metric generation model to be trained using the training samples includes:

[0028] Input the target vector in the training samples into the chip design metric generation model to be trained to obtain a predicted metric;

[0029] Determine the model loss function value according to the difference between the predicted index and the target chip design index in the training sample;

[0030] Adjust the chip design index generation model to be trained according to the model loss function value.

[0031] In one embodiment, the chip design index includes at least one of chip area, actual total wire length of routing, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin, and number of rule violations.

[0032] In a second aspect, the present application also provides a chip design index generation model training device, including:

[0033] An acquisition module, configured to acquire a set of physical design parameter configurations; the set of physical design parameter configurations includes at least two physical design parameter configurations; the physical design parameter configurations represent configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool;

[0034] An analysis module, configured to respectively input each physical design parameter configuration in the set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool, and obtain the chip design index corresponding to each physical design parameter configuration in the set of physical design parameter configurations;

[0035] A generation module, configured to generate a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the set of physical design parameter configurations, and add the new physical design parameter configuration to the set of physical design parameter configurations to obtain a new set of physical design parameter configurations;

[0036] An execution module, configured to return and execute the step of respectively inputting each physical design parameter configuration in the set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool, until the chip design index corresponding to any one of the physical design parameter configurations in the set of physical design parameter configurations meets the preset index requirement, and use the chip design index that meets the preset index requirement as the target chip design index;

[0037] A training module, configured to determine a training sample according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index, and use the training sample to train the chip design index generation model to be trained; the chip design index generation model is used to determine the chip design index according to the output result of the layout analysis tool.

[0038] In a third aspect, the present application also provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0039] In a fourth aspect, the present application also provides a computer-readable storage medium. On the computer-readable storage medium, a computer program is stored, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0040] In a fifth aspect, the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0041] The above-mentioned method, device, computer equipment, computer-readable storage medium and computer program product for training a chip design index generation model obtain a set of physical design parameter configurations; the set of physical design parameter configurations includes at least two physical design parameter configurations; the physical design parameter configuration represents the configuration parameters of a layout analysis tool, the configuration parameters of a clock tree analysis tool, and the configuration parameters of a routing analysis tool; input each physical design parameter configuration in the set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively to obtain the chip design indexes corresponding to each physical design parameter configuration in the set of physical design parameter configurations, so as to use the analysis tools to process the initial physical design parameter configurations and obtain the corresponding chip design indexes; generate new physical design parameter configurations according to the chip design indexes corresponding to each physical design parameter configuration in the set of physical design parameter configurations, and add the new physical design parameter configurations to the set of physical design parameter configurations to obtain a new set of physical design parameter configurations, so as to construct a new set of physical design parameter configurations in combination with the chip design indexes of the initial physical design parameter configurations; return to execute the step of inputting each physical design parameter configuration in the set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively until the chip design index corresponding to any one of the physical design parameter configurations in the set of physical design parameter configurations meets the preset index requirements, and use the chip design index that meets the preset index requirements as the target chip design index, so as to accurately determine the chip design index that meets the preset index requirements through iteration; determine training samples according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index, and use the training samples to train the chip design index generation model to be trained; the chip design index generation model is used to determine the chip design index according to the output result of the layout analysis tool, so as to accurately train the chip design index generation model by using physical design parameter configurations such as layout configuration, clock tree configuration, and routing configuration and chip design indexes, so that the chip design index generation model can quickly output information such as the chip design index of the chip, and efficiently and portably determine information such as the chip design index by the chip design index generation model, without manually configuring the parameters of the clock tree analysis tool and the routing analysis tool one by one in each iteration of the chip design process, but predicting the chip design index by the chip design index generation model based on the output result of the layout analysis tool, so as to reduce the generation time of the chip design index and further improve the efficiency of chip design. Brief Description of the Drawings

[0042] To more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the accompanying drawings required for the description of the embodiments of the present application or the related art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0043] Figure 1 It is an application environment diagram of a method for training a chip design index generation model in an embodiment;

[0044] Figure 2 It is a schematic flowchart of a method for training a chip design index generation model in an embodiment;

[0045] Figure 3 It is a schematic flowchart of a chip physical design in an embodiment;

[0046] Figure 4 It is a schematic diagram of a layout image in an embodiment;

[0047] Figure 5 It is a schematic architecture diagram of a layout engine adapter in an embodiment;

[0048] Figure 6 It is a structural block diagram of a device for training a chip design index generation model in an embodiment;

[0049] Figure 7 It is an internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0050] In order to make the objectives, technical solutions, and advantages of the present application clearer, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] The method for training a chip design index generation model provided by the embodiments of the present application can be applied to, for example Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or can be placed on the cloud or other network servers. The terminal 102 obtains a set of physical design parameter configurations; the set of physical design parameter configurations includes at least two physical design parameter configurations; the physical design parameter configurations represent the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the routing analysis tool; the terminal 102 inputs each physical design parameter configuration in the set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively, and obtains the chip design indicators corresponding to each physical design parameter configuration in the set of physical design parameter configurations; the terminal 102 generates a new physical design parameter configuration according to the chip design indicators corresponding to each physical design parameter configuration in the set of physical design parameter configurations, and adds the new physical design parameter configuration to the set of physical design parameter configurations to obtain a new set of physical design parameter configurations; the terminal 102 returns to execute the step of inputting each physical design parameter configuration in the set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively, until the chip design indicator corresponding to any one of the physical design parameter configurations in the set of physical design parameter configurations meets the preset indicator requirements, and uses the chip design indicator that meets the preset indicator requirements as the target chip design indicator; the terminal 102 determines a training sample according to the target chip design indicator and the physical design parameter configuration corresponding to the target chip design indicator, and uses the training sample to train the chip design indicator generation model to be trained; the chip design indicator generation model is used to determine the chip design indicator according to the output result of the layout analysis tool. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptop computers, etc. The server 104 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0052] In an exemplary embodiment, as Figure 2 shown, a method for training a chip design indicator generation model is provided. Taking the application of this method to a terminal as an example, it includes the following steps S202 to step S210. Among them:

[0053] Step S202, obtain a set of physical design parameter configurations; the set of physical design parameter configurations includes at least two physical design parameter configurations; the physical design parameter configurations represent the configuration parameters of the layout analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the routing analysis tool.

[0054] Among them, the set of physical design parameter configurations can include several physical design parameter configurations.

[0055] Among them, the physical design parameter configuration may refer to information characterizing the configuration parameters of a layout analysis tool, a clock tree analysis tool, and a routing analysis tool.

[0056] Among them, the layout analysis tool may refer to a tool used for operations such as physical verification of a chip, density analysis, routability prediction, and parameter extraction. The configuration parameters of the layout analysis tool may include information characterizing the position arrangement of each module or circuit unit (such as CPU cores, caches, memory controllers, etc.) inside the chip.

[0057] Among them, the clock tree analysis tool may refer to a tool used for operations such as clock network verification of a chip, load balancing, delay matching, and power consumption evaluation. The configuration parameters of the clock tree analysis tool may include information characterizing the structure of the clock tree and related parameters of the clock tree.

[0058] Among them, the routing analysis tool may refer to a tool used for operations such as connectivity verification of a chip, signal integrity analysis, power integrity analysis, and compliance analysis. The configuration parameters of the routing analysis tool may include information characterizing the setting methods of wires, metal layers, vias, etc. between various circuit elements.

[0059] As an example, when performing chip design, the terminal may first obtain several groups of physical design parameter configurations input by the user. The several groups of physical design parameter configurations may form a physical design parameter configuration set. In practical applications, each group of physical design parameter configurations may characterize the configuration parameters of a layout analysis tool, a clock tree analysis tool, and a routing analysis tool. For example: Physical design parameter configuration 1 may characterize configuration parameter A1 of the layout analysis tool, configuration parameter B1 of the clock tree analysis tool, and configuration parameter C1 of the routing analysis tool. Physical design parameter configuration 2 may characterize configuration parameter A2 of the layout analysis tool, configuration parameter B2 of the clock tree analysis tool, and configuration parameter C2 of the routing analysis tool.

[0060] Step S204: Input each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively to obtain the chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set.

[0061] Among them, the chip design indicators may refer to information characterizing indicators / parameters such as chip area, actual routing bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin, and number of rule violations.

[0062] As an example, the terminal can input each physical design parameter configuration in the physical design parameter configuration set into a placement analysis tool, a clock tree analysis tool, and a routing analysis tool respectively. The placement analysis tool can perform placement analysis based on the physical design parameter configuration, the clock tree analysis tool can perform clock tree analysis based on the physical design parameter configuration, and the routing analysis tool can perform routing analysis based on the physical design parameter configuration. The terminal can determine the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set according to the output results of the placement analysis tool, the clock tree analysis tool, and the routing analysis tool.

[0063] Step S206: Generate a new physical design parameter configuration according to the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set.

[0064] As an example, each physical design parameter configuration in the physical design parameter configuration set is pre-generated / configured. The chip design metrics obtained by the placement analysis tool, the clock tree analysis tool, and the routing analysis tool based on each physical design parameter in the physical design parameter configuration set usually cannot meet the chip design requirements. At this time, the terminal can generate a new physical design parameter configuration according to the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set. For example, the original physical design parameter configuration set includes 3 groups of physical design parameter configurations. The terminal can determine the chip design metrics of these 3 groups of physical design parameter configurations through the placement analysis tool, the clock tree analysis tool, and the routing analysis tool. Then, the terminal can generate a new physical design parameter configuration based on the chip design metrics of these 3 groups of physical design parameter configurations, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set. At this time, the new physical design parameter configuration set includes 4 groups of physical design parameter configurations.

[0065] Step S208: Return to execute the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the placement analysis tool, the clock tree analysis tool, and the routing analysis tool respectively, until the chip design metrics corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meet the preset metric requirements, and use the chip design metrics that meet the preset metric requirements as the target chip design metrics.

[0066] Among them, the preset index requirement can refer to the information that is preset and used to determine whether the chip design index meets the chip design requirements. In practical applications, the preset index requirement can include, but is not limited to, whether the difference between the chip design index and the design index threshold is less than the preset difference threshold, or whether the chip design index is greater than the design index threshold, etc. It can be understood that the preset chip design requirements can also include information such as the functions that the chip needs to possess.

[0067] As an example, after obtaining the new set of physical design parameter configurations, the terminal can input each physical design parameter configuration in the new set of physical design parameter configurations into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively to obtain the chip design indexes corresponding to each physical design parameter configuration in the new set of physical design parameter configurations. Then, the terminal can compare the chip design indexes corresponding to each physical design parameter configuration in the new set of physical design parameter configurations with the preset design index threshold (or the design index threshold determined based on the chip design indexes corresponding to each physical design parameter configuration in the new set of physical design parameter configurations) respectively to determine whether the chip design indexes meet the preset index requirements. If the chip design index corresponding to any physical design parameter configuration in the new set of physical design parameter configurations meets the preset index requirements, the terminal can use the chip design index that meets the preset index requirements as the target chip design index. If the chip design indexes corresponding to each physical design parameter configuration in the new set of physical design parameter configurations do not meet the preset index requirements, at this time, the terminal can generate a new physical design parameter configuration again according to the chip design indexes corresponding to each physical design parameter configuration in the new set of physical design parameter configurations, and add the new physical design parameter configuration to the set of physical design parameter configurations to realize the re-update / expansion of the set of physical design parameter configurations. After that, the terminal can input each physical design parameter configuration in the set of physical design parameter configurations at this time into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively to obtain the chip design indexes corresponding to each physical design parameter configuration in the set of physical design parameter configurations at this time, and determine whether the chip design indexes meet the preset index requirements until the target chip design index is obtained.

[0068] Step S210: Determine a training sample according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index, and use the training sample to train the chip design index generation model to be trained; the chip design index generation model is used to determine the chip design index according to the output result of the layout analysis tool.

[0069] Among them, the training sample can refer to the information used to train the chip design index generation model to be trained.

[0070] Among them, the chip design index generation model can refer to a model used to determine chip design indexes based on the output results of the layout analysis tool. In practical applications, the chip design index generation model can replace the clock tree analysis tool and the routing tool to quickly generate information such as chip design indexes based on the output results of the layout analysis tool.

[0071] As an example, the terminal can determine / generate training samples according to the target chip design indexes and the physical design parameter configurations corresponding to the target chip design indexes, and use the training samples to train the chip design index generation model to be trained. In practical applications, the chip design index generation model to be trained can be used as a pre-trained chip design index generation model after training. When determining the chip design indexes, the terminal can first obtain several groups of physical design parameter configurations input by the user, then the terminal can input the several groups of physical design parameter configurations input by the user into the layout analysis tool, and then the terminal can input the output results of the layout analysis tool into the pre-trained chip design index generation model, and the pre-trained chip design index generation model can output the chip design indexes.

[0072] In the above chip design index generation model training method, a physical design parameter configuration set is obtained; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents the configuration parameters of a layout analysis tool, the configuration parameters of a clock tree analysis tool, and the configuration parameters of a routing analysis tool; each physical design parameter configuration in the physical design parameter configuration set is respectively input into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool to obtain the chip design indexes corresponding to each physical design parameter configuration in the physical design parameter configuration set, so as to use the analysis tools to process the initial physical design parameter configurations and obtain the corresponding chip design indexes; according to the chip design indexes corresponding to each physical design parameter configuration in the physical design parameter configuration set, new physical design parameter configurations are generated, and the new physical design parameter configurations are added to the physical design parameter configuration set to obtain a new physical design parameter configuration set, so as to construct a new physical design parameter configuration set in combination with the chip design indexes of the initial physical design parameter configurations; return to execute the step of respectively inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool until the chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets the preset index requirements, and use the chip design index that meets the preset index requirements as the target chip design index, so as to accurately determine the chip design index that meets the preset index requirements through iteration; according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index, training samples are determined, and the chip design index generation model to be trained is trained using the training samples; the chip design index generation model is used to determine the chip design index according to the output result of the layout analysis tool, so as to accurately train the chip design index generation model using physical design parameter configurations such as layout configuration, clock tree configuration, and routing configuration and the chip design index, so that the chip design index generation model can quickly output information such as the chip design index of the chip, and efficiently and portably determine information such as the chip design index by the chip design index generation model, without manually configuring the parameters of the clock tree analysis tool and the routing analysis tool one by one in each iteration of the chip design process, but the chip design index generation model predicts the chip design index based on the output result of the layout analysis tool, thereby reducing the generation time of the chip design index and further improving the efficiency of chip design.

[0073] In an exemplary embodiment, chip design metrics corresponding to each physical design parameter configuration in a set of physical design parameter configurations are configured to generate a new physical design parameter configuration, including: determining a design metric threshold according to the chip design metrics corresponding to each physical design parameter configuration in the set of physical design parameter configurations; dividing each physical design parameter configuration in the set of physical design parameter configurations into a first set and a second set according to the design metric threshold; the chip design metrics corresponding to the physical design parameter configurations in the first set are greater than or equal to the design metric threshold; the chip design metrics corresponding to the physical design parameter configurations in the second set are less than the design metric threshold; determining a parameter configuration search space according to each physical design parameter configuration in the set of physical design parameter configurations; the parameter configuration search space represents the value range of the physical design parameter configuration; determining the expected improvement value of each physical design parameter configuration in the parameter configuration search space according to the first set and the second set, and screening out the maximum expected improvement value from the expected improvement values; using the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration.

[0074] Among them, the design metric threshold may refer to information used to determine whether the chip design metrics meet the chip design requirements. In practical applications, the design metric threshold may include, but is not limited to, the average value or median of the chip design metrics corresponding to each physical design parameter configuration in the set of physical design parameter configurations, etc. The design metric threshold may also be a preset value.

[0075] As an example, the terminal can configure the corresponding chip design metrics for each physical design parameter configuration in the physical design parameter configuration set, calculate information such as the median / average value of the chip design metrics to obtain the design metric threshold. Then, the terminal can divide each physical design parameter configuration in the physical design parameter configuration set into a first set and a second set according to the design metric threshold. Among them, the chip design metrics corresponding to the physical design parameter configurations in the first set are greater than or equal to the design metric threshold, and the chip design metrics corresponding to the physical design parameter configurations in the second set are less than the design metric threshold. The terminal can also analyze the value range of the physical design parameter configurations based on each physical design parameter configuration in the physical design parameter configuration set, and determine the parameter configuration search space according to the value range of the physical design parameter configurations. Then, the terminal can use the preset expected improvement value calculation expression to determine the expected improvement value of each physical design parameter configuration in the parameter configuration search space based on the physical design parameter configurations in the first set and the corresponding chip design metrics, and the physical design parameter configurations in the second set and the corresponding chip design metrics. The terminal can also screen out the expected improvement value with the largest value from the calculated expected improvement values as the maximum expected improvement value. Then, the terminal can use the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration. In specific implementation, each physical design parameter configuration in the physical design parameter configuration set can be understood as several isolated data points, and each physical design parameter configuration in the parameter configuration search space can be understood as a data interval containing the above data points. The terminal can calculate the expected improvement value corresponding to each data in the above data interval respectively by combining the physical design parameter configurations in the first set and the corresponding chip design metrics, and the physical design parameter configurations in the second set and the corresponding chip design metrics. The physical design parameter configuration corresponding to the expected improvement value with the largest value can be used as the new physical design parameter configuration.

[0076] In practical applications, the terminal can calculate the expected improvement value of each physical design parameter configuration in the parameter configuration search space based on the TPE (Tree-structured Parzen Estimator) algorithm (an algorithm for Bayesian optimization). Then, the terminal can select the maximum value from the expected improvement values as the maximum expected improvement value. In practical applications, the maximum expected improvement value is related to the chip design metrics. For example, when the chip design metric is the chip area, the maximum expected improvement value can be the maximum value of the chip area reduction; when the chip design metric is the actual total wire length of the routing, the maximum expected improvement value can be the maximum value of the reduction in the actual total wire length of the routing; when the chip design metric is the chip power consumption, the maximum expected improvement value can be the maximum value of the chip power consumption reduction; when the chip design metric is the clock frequency, the maximum expected improvement value can be the maximum value of the increase in the clock frequency; when the chip design metric is the worst negative timing margin, the maximum expected improvement value can be the minimum value of the difference between the negative timing margin and 0; when the chip design metric is the total negative timing margin, the maximum expected improvement value can be the minimum value of the difference between the total negative timing margin and 0; when the layout metric value is the number of rule violations, the maximum expected improvement value can be the minimum value of the number of rule violations.

[0077] In this embodiment, by determining the design metric threshold according to the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set; dividing each physical design parameter configuration in the physical design parameter configuration set into a first set and a second set according to the design metric threshold; the chip design metrics corresponding to the physical design parameter configurations in the first set are greater than or equal to the design metric threshold; the chip design metrics corresponding to the physical design parameter configurations in the second set are less than the design metric threshold; determining the parameter configuration search space according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents the value range of the physical design parameter configuration; determining the expected improvement value of each physical design parameter configuration in the parameter configuration search space according to the first set and the second set, and selecting the maximum expected improvement value from the expected improvement values; using the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration, it is possible to determine the threshold based on the chip design metrics, use the threshold to divide each physical design parameter configuration into two different sets, calculate the expected improvement value of each physical design parameter configuration in the parameter configuration search space determined by each physical design parameter configuration in the physical design parameter configuration set in combination with different sets, and use the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration, determine the accurate physical design parameter configuration, so as to accurately update the physical design parameter configuration set, improve the accuracy of the physical design parameter configuration set, and thus improve the accuracy of chip design.

[0078] In some embodiments, each physical design parameter configuration in the set of physical design parameter configurations is input into a placement analysis tool, a clock tree analysis tool, and a routing analysis tool respectively, to obtain the chip design metrics corresponding to each physical design parameter configuration in the set of physical design parameter configurations, including: determining the configuration parameters of the placement analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the routing analysis tool according to each physical design parameter configuration in the set of physical design parameter configurations; applying the configuration parameters of the placement analysis tool to the placement analysis tool to obtain the output result of the placement analysis tool; inputting the output result of the placement analysis tool into the clock tree analysis tool, and applying the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain the output result of the clock tree analysis tool; inputting the output result of the clock tree analysis tool into the routing analysis tool, and applying the configuration parameters of the routing analysis tool to the routing analysis tool to obtain the output result of the routing analysis tool; and determining the chip design metrics corresponding to each physical design parameter configuration in the set of physical design parameter configurations according to the output result of the placement analysis tool, the output result of the clock tree analysis tool, and the output result of the routing analysis tool.

[0079] As an example, the terminal can determine the configuration parameters of the placement analysis tool, the configuration parameters of the clock tree analysis tool, and the configuration parameters of the routing analysis tool according to each physical design parameter configuration in the set of physical design parameter configurations. Then, the terminal can apply the configuration parameters of the placement analysis tool to the placement analysis tool. The placement analysis tool can perform operations such as physical verification, density analysis, routability prediction, and parameter extraction based on the configuration parameters of the placement analysis tool to obtain the output result of the placement analysis tool. Then, the terminal can input the output result of the placement analysis tool into the clock tree analysis tool, and apply the configuration parameters of the clock tree analysis tool to the clock tree analysis tool. The clock tree analysis tool can perform operations such as clock network verification, load balancing, delay matching, and power consumption evaluation by combining the output result of the placement analysis tool and the configuration parameters of the clock tree analysis tool to obtain the output result of the clock tree analysis tool. Then, the terminal can input the output result of the clock tree analysis tool into the routing analysis tool, and apply the configuration parameters of the routing analysis tool to the routing analysis tool. The routing analysis tool can perform operations such as connectivity verification, signal integrity analysis, power integrity analysis, and compliance analysis by combining the output result of the clock tree analysis tool and the configuration parameters of the routing analysis tool to obtain the output result of the routing analysis tool. In practical applications, the terminal can determine the chip design metrics corresponding to each physical design parameter configuration in the set of physical design parameter configurations according to the output result of the placement analysis tool, the output result of the clock tree analysis tool, and the output result of the routing analysis tool.

[0080] In this embodiment, the configuration parameters of the placement analysis tool, the clock tree analysis tool, and the routing analysis tool are determined according to each physical design parameter configuration in the physical design parameter configuration set; the configuration parameters of the placement analysis tool are applied to the placement analysis tool to obtain the output result of the placement analysis tool; the output result of the placement analysis tool is input into the clock tree analysis tool, and the configuration parameters of the clock tree analysis tool are applied to the clock tree analysis tool to obtain the output result of the clock tree analysis tool; the output result of the clock tree analysis tool is input into the routing analysis tool, and the configuration parameters of the routing analysis tool are applied to the routing analysis tool to obtain the output result of the routing analysis tool; according to the output results of the placement analysis tool, the clock tree analysis tool, and the routing analysis tool, the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set are determined, so that the chip design and analysis can be accurately and orderly performed using the placement analysis tool, the clock tree analysis tool, and the routing analysis tool, accurate chip design metrics can be obtained, and the accuracy of the chip design metrics can be improved.

[0081] In some embodiments, the training samples are determined according to the target chip design metrics and the physical design parameter configurations corresponding to the target chip design metrics, including: determining the chip placement parameters according to the physical design parameter configurations, parsing the chip placement parameters to obtain a placement image, and converting the placement image into an embedding vector; determining a target vector according to the physical design parameter configuration corresponding to the target chip design metrics and the embedding vector; using the target vector and the target chip design metrics as the training samples.

[0082] Among them, the chip placement parameters may refer to the information characterizing the layout and connection relationship of circuit elements on the chip.

[0083] Among them, the placement image can display the layout and connection relationship of circuit elements on the chip in the form of an image.

[0084] Among them, the embedding vector may refer to the information obtained after converting the placement image into a preset vector space.

[0085] As an example, the physical design parameter configuration may include chip layout parameters. The terminal can analyze the physical design parameter configuration to determine the chip layout parameters. The chip layout parameters can be a design netlist file that can characterize the layout and connection relationship of circuit elements on the chip. The terminal can parse the chip layout parameters / the design netlist file obtained from the chip layout parameters to determine the layout image. Then, the terminal can convert the layout image into a preset space to obtain an embedding vector. Then, the terminal can determine the target vector according to the physical design parameter configuration corresponding to the target chip design index and the embedding vector. Taking the target vector and the target chip design index as training samples, in practical applications, the physical design parameter configuration can be represented as X, the chip design index can be represented as Y, and the embedding vector can be represented as V. Then, the training sample can be represented as ([X, V], Y).

[0086] In this embodiment, by determining the chip layout parameters according to the physical design parameter configuration, parsing the chip layout parameters to obtain the layout image, and converting the layout image into an embedding vector; determining the target vector according to the physical design parameter configuration corresponding to the target chip design index and the embedding vector; taking the target vector and the target chip design index as training samples, it is possible to convert the layout image determined based on the chip layout parameters into an embedding vector, and combine the target chip design index and the physical design parameter configuration corresponding to the target chip design index to generate accurate training samples, so as to subsequently use the training samples to train the chip design index generation model to be trained, and further optimize the performance of the chip design index generation model to be trained.

[0087] In some embodiments, training the chip design index generation model to be trained using the training samples includes: inputting the target vector in the training samples into the chip design index generation model to be trained to obtain a predicted index; determining the model loss function value according to the difference between the predicted index and the target chip design index in the training samples; adjusting the chip design index generation model to be trained according to the model loss function value.

[0088] Among them, the predicted index can refer to the chip design index output by the chip design index generation model based on the physical design parameter configuration characterized by the target vector. In practical applications, the chip design index output by the chip design index generation model can be used as a predicted value of the chip design index corresponding to the physical design parameter configuration characterized by the target vector input into the chip design index generation model. It can be understood that the chip design index generation model can be used to simplify / replace the steps of clock tree analysis and routing analysis, and speed up the determination of the chip design index.

[0089] Among them, the model loss function value may refer to information characterizing the degree of difference between the predicted value and the true value output by the chip design index generation model. In practical applications, the model loss function value can be used to adjust the model parameters of the chip design index generation model.

[0090] As an example, the terminal can input the target vector in the training sample into the chip design index generation model to be trained. The chip design index generation model to be trained can analyze the physical design parameter configuration represented by the target vector to obtain a predicted index. Then, the terminal can determine the model loss function value according to the difference between the predicted index and the target chip design index in the training sample. If the model loss function value meets the preset loss function value requirement, the terminal can determine that the training of the chip design index generation model is completed. If the model loss function value does not meet the preset loss function value requirement, the terminal can adjust the model parameters of the chip design index generation model to be trained according to the model loss function value. Then, the terminal can input the target vector in the training sample into the chip design index generation model again. The chip design index generation model can generate a new predicted index. Then, the terminal can determine the model loss function value again according to the difference between the new predicted index and the target chip design index in the training sample. If the model loss function value still does not meet the preset loss function value requirement, the terminal can adjust the model parameters of the chip design index generation model again based on the current model loss function value. Then, repeat the above steps until the training of the chip design index generation model is completed to obtain a trained chip design index generation model. The trained chip design index generation model can be used as a pre-trained chip design index generation model.

[0091] In this embodiment, by inputting the target vector in the training sample into the chip design index generation model to be trained, a predicted index is obtained; according to the difference between the predicted index and the target chip design index in the training sample, the model loss function value is determined; according to the model loss function value, the chip design index generation model to be trained is adjusted, so that the model loss function value can be accurately calculated based on the training sample, and the chip design index generation model can be accurately adjusted, optimizing the model performance of the chip design index generation model and improving the accuracy of the chip design index output by the chip design index generation model.

[0092] In some embodiments, the chip design index includes at least one of chip area, actual total wire length of routing, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin, and number of rule violations.

[0093] Among them, the chip area (Area) can refer to the product of the maximum dimensions from one edge of the chip to the other opposite edge, that is, length times width. The chip area can include all active and passive components, interconnects, power networks, and all other parts that make up the chip. In practical applications, the chip area can characterize the actual physical space occupied by the integrated circuit on the silicon wafer.

[0094] Among them, the actual wirelength can refer to the sum of the lengths of all the wires connecting two endpoints (such as the input and output pins between logic units).

[0095] Among them, the chip power consumption (Power) can refer to the electrical energy consumed by the integrated circuit in the working state.

[0096] Among them, the clock frequency (Frequency) can refer to the number of times the clock signal switches per second in a digital circuit.

[0097] Among them, the worst negative slack (WNS) can refer to the timing slack of the most severely timing-constraint-violating path among all paths. The actual arrival time of this path exceeds the specified time limit. The timing slack refers to the difference between the specified setup time or hold time and the actual arrival time. A positive timing slack indicates that the path meets the timing requirements; a negative timing slack means there is a timing violation.

[0098] Among them, the total negative slack (TNS) can refer to the sum of the absolute values of the timing slacks on all negative-timing-slack paths.

[0099] Among them, the number of rule violations can refer to the total number of errors detected by verification tools such as design rule check (DRC) or electrical rule check (ERC), where the design does not meet specific process requirements or circuit specifications.

[0100] As an example, the terminal can analyze information such as chip layout parameters, determine the maximum dimensions from one edge of the chip to another opposite edge (such as the length and width of the chip), and calculate the product of the maximum dimensions to obtain the chip area. The terminal can analyze information such as chip layout parameters, determine the length of each wire connecting two endpoints (such as input and output pins between logic units), and calculate the sum of the above wire lengths to obtain the actual bus length of the wiring. The terminal can simulate the behavior of the circuit in the chip based on information such as chip layout parameters and monitor the electrical energy consumed by the circuit in the working state to obtain the chip power consumption. The terminal can perform static timing analysis based on information such as chip layout parameters to determine the clock frequency. The terminal can perform static timing analysis based on information such as chip layout parameters, determine the difference between the specified setup time (SetupTime) or hold time (Hold Time) of each path in the chip and the actual arrival time of the path, obtain the timing margin, and take the timing margin with the largest absolute value in the negative timing margins as the worst negative timing margin. The terminal can also calculate the sum of the absolute values of the negative timing margins to obtain the total negative timing margin. The terminal can also perform rule checks on information such as chip layout parameters based on design rule check (DRC) or electrical rule check (ERC), etc., determine whether the information such as chip layout parameters violates the rules, and determine the number of design rules violated by the information such as chip layout parameters as the number of rule violations.

[0101] In this embodiment, by analyzing design metrics such as chip area, actual bus length of the wiring, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin, and number of rule violations, the accuracy of the design metric information can be improved, so as to obtain accurate training samples, thereby improving the accuracy of the output results of the chip design metric generation model trained using the training samples.

[0102] In some embodiments, such as Figure 3As shown, a flowchart of the physical design of a chip is provided. To perform multi-objective optimization on the physical design of the chip, the terminal can establish a sample set of (physical design parameter configuration X, chip design metrics Y). Initially, both X and Y are empty (i.e., the sample set is initialized). The terminal can define the parameter configuration space, which includes the configuration parameters of the layout analysis tool, the clock tree analysis tool, and the routing analysis tool. During chip design, the terminal can obtain the configuration parameters of the layout analysis tool, the clock tree analysis tool, and the routing analysis tool from the parameter configuration space, thereby determining the set of physical design parameter configurations. The terminal can determine the configuration parameters of the layout analysis tool, the clock tree analysis tool, and the routing analysis tool according to each physical design parameter configuration in the set of physical design parameter configurations. Then, the terminal can apply the configuration parameters of the layout analysis tool to the layout analysis tool to implement parameter configuration in the layout stage and obtain the output result of the layout analysis tool. The output result of the layout analysis tool is input to the clock tree analysis tool, and the configuration parameters of the clock tree analysis tool are applied to the clock tree analysis tool to implement parameter configuration in the clock tree analysis stage and obtain the output result of the clock tree analysis tool. The output result of the clock tree analysis tool is input to the routing analysis tool, and the configuration parameters of the routing analysis tool are applied to the routing analysis tool to implement parameter configuration in the routing stage and obtain the output result of the routing analysis tool. The terminal can use a preset layout engine adapter to determine the chip area (Area), actual routing bus length (Wirelength), chip power consumption (Power), clock frequency (Frequency), worst negative timing slack (WNS), total negative timing slack (TNS), and design rule violation count (DRC) and other chip design metrics corresponding to each physical design parameter configuration in the set of physical design parameter configurations in combination with the output results of the layout analysis tool, the clock tree analysis tool, and the routing analysis tool. The chip design metrics can be used as the final output of the physical design.

[0103] The terminal can use the expected improvement algorithm based on the chip design metrics to generate a physical design parameter configuration that maximizes the current expected improvement value to update the set of physical design parameter configurations. In practical applications, the terminal can determine the parameter configuration search space according to each physical design parameter configuration in the set of physical design parameter configurations and use a preset calculation expression to determine the layout metric value (such as chip design metrics) y of each physical design parameter configuration x in the parameter configuration search space. At the same time, the terminal can also set a threshold (such as a design metric threshold) y * and based on the threshold y * to divide the two layout density functions l(x) and g(x). At this time, a conditional probability p(x|y) can be defined, and the conditional probability p(x|y) can be expressed as:

[0104] ,

[0105] Among them, l(x) can refer to the layout density function of the physical design parameter configurations x in which the layout metric value y is less than the threshold y * , and g(x) can refer to the layout density function of the physical design parameter configurations x in which the layout metric value y is greater than or equal to the threshold y * . Assuming that the layout metric value y corresponding to a certain physical design parameter configuration x is less than the threshold y * denoted as p(y < y * ) = , then the expected improvement value EI y* (x) of using the TPE algorithm can be expressed as:

[0106] ,

[0107] Among them, Y(X) can refer to the set of observations under the existing samples X (such as physical design parameter configurations), which refers to Y. p(x) can refer to the distribution of parameters (such as physical design parameter configurations), and p(y) can refer to the distribution of observed values.

[0108] Based on the above calculation expressions, the expected improvement value of each physical design parameter configuration can be determined. The physical design parameter configuration corresponding to the maximum expected improvement value in the expected improvement values can be used as the new physical design parameter configuration to update the physical design parameter configuration set. If the chip design index corresponding to any physical design parameter configuration in the physical design parameter configurations in the physical design parameter configuration set meets the preset index requirements, the terminal can determine that the optimization can be ended at this time.

[0109] In a specific implementation, the terminal can analyze the physical design parameter configuration, determine the chip layout parameters, convert the chip layout parameters into a design netlist file, and parse the design netlist file to obtain a layout image. As Figure 4 shown, a schematic diagram of a layout image is provided. The terminal can also use a Transformer network to convert the layout image into a preset vector space to obtain the embedded vector information v.

[0110] The terminal can also analyze chip design metrics such as chip area (Area), actual wire length of the routing (Wirelength), chip power consumption (Power), clock frequency (Frequency), worst negative timing slack (WNS), total negative timing slack (TNS), and design rule violation count (DRC) based on the final output of the physical design. After that, the terminal can add the final output of the physical design (such as physical design parameter configuration) to X, add the chip design metrics to Y, to obtain training samples. The training samples can form a sample set. At the same time, the terminal can also save the embedding vector v to V, and splice V together with X as additional encoded information. It can be understood that the terminal can expand the sample set by updating the physical design parameter configuration set, and the sample set can contain several training samples. The terminal can establish a regression model for ([X, V], Y). The terminal can also use the final output of the physical design, chip design metrics, and embedding vector corresponding to each training sample to train the chip design metric generation model to be trained. The trained chip design metric generation model can output information such as the layout positions of circuit elements on the chip, the connection relationships between circuit elements, and chip design metrics such as chip area, actual wire length of the routing, chip power consumption, clock frequency, worst negative timing slack, total negative timing slack, and rule violation count based on the output results of the layout analysis tool, without the need for complex clock tree analysis and routing analysis, thereby accelerating the generation speed of chip design metrics and the chip design process, and reducing the chip design time.

[0111] As Figure 5 shown, an architecture schematic diagram of a layout engine adapter is provided. The layout engine adapter can integrate the operations of Python and C++ to achieve layout configuration in chip design. Specifically, the layout engine adapter can be used as a top-level module, responsible for coordinating operations at different levels. The layout engine adapter can be used as an interface-level architecture, and the organizational level of the layout engine adapter can include Python processes and subsystems. The operation level of the layout engine adapter includes PythonPlacement API, Python WL, Python Density, C++ Density, C++ WL, parameter configuration, and layout engine execution. Python is mainly used for high-level operations and API calls, while C++ is responsible for specific underlying calculations and optimizations.

[0112] In this embodiment, by comprehensively considering wiring, clock tree analysis, and layout tasks, optimization is carried out starting from the entire physical design stage, considering more comprehensive metrics, especially the metrics after wiring. In this way, the overall metrics are more referenceable and practical. At the same time, design rule violations (DRC) are considered in the metrics, which is a particularly critical metric. If this metric is not 0, the subsequent processes are not considered, which can solve the problem of slow evaluation in the physical design stage of large chips. The metrics are approximately solved using a machine learning model, thereby improving the efficiency of chip design.

[0113] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps do not necessarily have to be executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these steps or stages does not necessarily have to be sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0114] Based on the same inventive concept, an embodiment of the present application further provides a chip design metric generation model training device for implementing the above-mentioned chip design metric generation model training method. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the chip design metric generation model training device provided below can refer to the limitations on the chip design metric generation model training method in the above text, and will not be repeated here.

[0115] In an exemplary embodiment, as Figure 6 shown, a chip design metric generation model training device is provided, including: an acquisition module 602, an analysis module 604, a generation module 606, an execution module 608, and a training module 610, where:

[0116] The acquisition module 602 is configured to acquire a set of physical design parameter configurations; the set of physical design parameter configurations includes at least two physical design parameter configurations; the physical design parameter configurations represent the configuration parameters of a layout analysis tool, the configuration parameters of a clock tree analysis tool, and the configuration parameters of a wiring analysis tool.

[0117] An analysis module 604, configured to input each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively, to obtain chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set.

[0118] A generation module 606, configured to generate a new physical design parameter configuration according to the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set.

[0119] An execution module 608, configured to return and execute the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the routing analysis tool respectively, until the chip design metrics corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meet the preset metric requirements, and use the chip design metrics that meet the preset metric requirements as the target chip design metrics.

[0120] A training module 610, configured to determine training samples according to the target chip design metrics and the physical design parameter configuration corresponding to the target chip design metrics, and use the training samples to train a chip design metric generation model to be trained; the chip design metric generation model is configured to determine chip design metrics according to the output result of the layout analysis tool.

[0121] In one exemplary embodiment, the generation module 606 is further specifically configured to determine a design metric threshold according to the chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set; divide the physical design parameter configurations in the physical design parameter configuration set into a first set and a second set according to the design metric threshold; the chip design metrics corresponding to the physical design parameter configurations in the first set are greater than or equal to the design metric threshold; the chip design metrics corresponding to the physical design parameter configurations in the second set are less than the design metric threshold; determine a parameter configuration search space according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents the value range of the physical design parameter configuration; determine the expected improvement value of each physical design parameter configuration in the parameter configuration search space according to the first set and the second set, and screen out the maximum expected improvement value from the expected improvement values; use the physical design parameter configuration corresponding to the maximum expected improvement value as the new physical design parameter configuration.

[0122] In one exemplary embodiment, the analysis module 604 is further specifically configured to determine configuration parameters of the layout analysis tool, configuration parameters of the clock tree analysis tool, and configuration parameters of the routing analysis tool according to each physical design parameter configuration in the physical design parameter configuration set; apply the configuration parameters of the layout analysis tool to the layout analysis tool to obtain an output result of the layout analysis tool; input the output result of the layout analysis tool into the clock tree analysis tool, and apply the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain an output result of the clock tree analysis tool; input the output result of the clock tree analysis tool into the routing analysis tool, and apply the configuration parameters of the routing analysis tool to the routing analysis tool to obtain an output result of the routing analysis tool; and determine chip design metrics corresponding to each physical design parameter configuration in the physical design parameter configuration set according to the output result of the layout analysis tool, the output result of the clock tree analysis tool, and the output result of the routing analysis tool.

[0123] In one exemplary embodiment, the training module 610 is further specifically configured to determine chip layout parameters according to the physical design parameter configuration, parse the chip layout parameters to obtain a layout image, and convert the layout image into an embedding vector; determine a target vector according to the physical design parameter configuration corresponding to the target chip design metric and the embedding vector; and use the target vector and the target chip design metric as the training sample.

[0124] In one exemplary embodiment, the training module 610 is further specifically configured to input the target vector in the training sample into the chip design metric generation model to be trained to obtain a predicted metric; determine a model loss function value according to the difference between the predicted metric and the target chip design metric in the training sample; and adjust the chip design metric generation model to be trained according to the model loss function value.

[0125] In one exemplary embodiment, the chip design metrics include at least one of chip area, actual routed bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin, and number of rule violations.

[0126] Each module in the above chip design metric generation model training apparatus can be implemented in whole or in part by software, hardware, and combinations thereof. The above modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in a computer device in software form, so that the processor can call and execute operations corresponding to the above modules.

[0127] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structural diagram may be as shown in Figure 7 . The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a method for training a chip design index generation model. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad provided on the shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0128] Those skilled in the art can understand that Figure 7 the structure shown in is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0129] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, it implements the steps in the above method embodiments.

[0130] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, it implements the steps in the above method embodiments.

[0131] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by the processor, it implements the steps in the above method embodiments.

[0132] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data that have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0133] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0134] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0135] The above-described embodiments merely represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application shall be subject to the appended claims.

Claims

1. A chip design index generation model training method, characterized in that: The method comprises: Acquire a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool; Inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool respectively, to obtain chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set; Generate a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set; Return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool, respectively, until a chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets a preset index requirement, and use the chip design index that meets the preset index requirement as a target chip design index; According to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, training samples are determined, and the chip design indicator generation model to be trained is trained using the training samples; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

2. The method according to claim 1, characterized in that The generating a new physical design parameter configuration according to the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set includes: Determining a design indicator threshold according to a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set; The physical design parameter configurations in the physical design parameter configuration set are divided into a first set and a second set according to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the first set is greater than or equal to the design indicator threshold; the chip design indicator corresponding to the physical design parameter configuration in the second set is less than the design indicator threshold; Determine a parameter configuration search space according to each physical design parameter configuration in the physical design parameter configuration set; the parameter configuration search space represents a value range of the physical design parameter configuration; Determine, according to the first set and the second set, an expected improvement value of each physical design parameter configuration in the parameter configuration search space, and screen out a maximum expected improvement value from the expected improvement values; The physical design parameter configuration corresponding to the maximum expected improvement value is used as the new physical design parameter configuration.

3. The method according to claim 1, characterized in that: The step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool to obtain a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set includes: Determining configuration parameters of the layout analysis tool, configuration parameters of the clock tree analysis tool, and configuration parameters of the routing analysis tool according to each physical design parameter configuration in the physical design parameter configuration set; Applying the configuration parameters of the layout analysis tool to the layout analysis tool to obtain an output result of the layout analysis tool; Inputting the output result of the layout analysis tool into the clock tree analysis tool, and applying the configuration parameters of the clock tree analysis tool to the clock tree analysis tool to obtain the output result of the clock tree analysis tool; Inputting the output result of the clock tree analysis tool into the wiring analysis tool, and applying the configuration parameters of the wiring analysis tool to the wiring analysis tool to obtain the output result of the wiring analysis tool; According to the output results of the layout analysis tool, the output results of the clock tree analysis tool and the output results of the wiring analysis tool, the chip design index corresponding to each physical design parameter configuration in the physical design parameter configuration set is determined.

4. The method according to claim 1, characterized in that The determining of the training sample according to the target chip design index and the physical design parameter configuration corresponding to the target chip design index includes: Determining chip layout parameters according to the physical design parameter configuration, parsing the chip layout parameters to obtain a layout image, and converting the layout image into an embedding vector; Determining a target vector according to the physical design parameter configuration corresponding to the target chip design indicator and the embedded vector; The target vector and the target chip design index are used as the training samples.

5. The method according to claim 4, characterized in that The step of using the training samples to train a chip design indicator generation model to be trained includes: Inputting the target vector in the training sample into the chip design index generation model to be trained to obtain a prediction index; Determining a model loss function value according to a difference between the prediction index and a target chip design index in the training sample; According to the model loss function value, the chip design indicator generation model to be trained is adjusted.

6. The method according to claim 1, characterized in that The chip design index includes at least one of chip area, actual wiring bus length, chip power consumption, clock frequency, worst negative timing margin, total negative timing margin and number of rule violations.

7. A chip design index generation model training device, characterized in that: The device comprises: An acquisition module, used to acquire a physical design parameter configuration set; the physical design parameter configuration set includes at least two physical design parameter configurations; the physical design parameter configuration represents configuration parameters of a layout analysis tool, configuration parameters of a clock tree analysis tool, and configuration parameters of a routing analysis tool; An analysis module, used to input each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool and the wiring analysis tool respectively, to obtain a chip design indicator corresponding to each physical design parameter configuration in the physical design parameter configuration set; A generating module, configured to generate a new physical design parameter configuration according to chip design indicators corresponding to each physical design parameter configuration in the physical design parameter configuration set, and add the new physical design parameter configuration to the physical design parameter configuration set to obtain a new physical design parameter configuration set; an execution module, configured to return to the step of inputting each physical design parameter configuration in the physical design parameter configuration set into the layout analysis tool, the clock tree analysis tool, and the wiring analysis tool, respectively, until a chip design index corresponding to any one of the physical design parameter configurations in the physical design parameter configuration set meets a preset index requirement, and the chip design index that meets the preset index requirement is used as a target chip design index; A training module is used to determine training samples according to the target chip design indicators and the physical design parameter configuration corresponding to the target chip design indicators, and use the training samples to train the chip design indicator generation model to be trained; the chip design indicator generation model is used to determine the chip design indicators according to the output results of the layout analysis tool.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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