Memory circuit and operating method thereof

Abstract

A memory circuit includes an array of memory cells configured to store a set of stored data, a multiply-accumulate (MAC) circuit, and an input-output (IO) circuit. The storage data set is one of the first weight signal set or the inverted weight signal set. The MAC circuit is configured to generate the first data set in response to the second data set and the stored data set. The IO circuit includes a first circuit and a second circuit. The first circuit is configured to transmit a first set of weight signals in response to at least the set of enable signals; or generates a set of inverting weight signals in response to at least the set of inverting enable signals. The second circuit is configured to output a first set of output signals in response to at least the first set of data and the set of enable signals. The embodiment of the invention also discloses a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to memory circuits and methods of operating the same. Background Art

[0002] Recent developments in the field of artificial intelligence have generated a variety of products and / or applications, including but not limited to speech recognition, image processing, machine learning, natural language processing, etc. Such products and / or applications usually use neural networks to process large amounts of data for learning, training, cognitive computing, etc. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory cell array, configured to store a storage data group, the storage data group being one of a first weight signal group or an inverted weight signal group, the inverted weight signal group being inverted to the first weight signal group; a multiplication-accumulation (MAC) circuit, coupled to the memory cell array, and configured to generate a first data group in response to a second data group and a storage data group; and an input-output (IO) circuit, coupled to the MAC circuit, the IO circuit comprising: a first circuit, coupled to the memory cell array, and configured to: send a first weight signal group in response to at least an enable signal group; or generate an inverted weight signal group in response to at least an inverted enable signal group; and a second circuit, coupled to the MAC circuit, and configured to output a first output signal group in response to at least the first data group and the enable signal group.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a computation in memory (CIM) macro circuit, the CIM macro circuit comprising: a memory cell array, comprising rows and columns, and configured to store a storage data group, the storage data group being one of a first weight signal group or an inverted weight signal group, the inverted weight signal group being inverted to the first weight signal group; and a multiplication-accumulation (MAC) circuit, coupled to the memory cell array, and configured to generate a first data group in response to a second data group and a storage data group; and an input-output (IO) circuit, coupled to the CIM macro circuit, and configured to output a first output signal group, the IO circuit comprising: a write circuit, coupled to the memory cell array, and configured to: send the first weight signal group in response to at least an enable signal group; or generate an inverted weight signal group in response to at least an inverted enable signal group; and a read circuit, coupled to the MAC circuit, and configured to output the first output signal group in response to at least the first data group and the enable signal group.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, the method comprising: receiving a first weight signal group by a first write circuit; generating an enable signal group by a second write circuit in response to at least a count signal, the count signal corresponding to the number of active word lines coupled to a memory cell array; generating an inverted enable signal group by the first circuit in response to the enable signal group, the inverted weight signal group being inverted to the first weight signal group; performing a write operation on the memory cell array, performing a write operation on the memory circuit comprising: at least one of the following: outputting the first weight signal group by the first write circuit in response to at least the enable signal group; or outputting the first weight signal group by the first write circuit in response to at least the inverted enable signal group. to generate an inverted weight signal group; and storing a storage data group in a memory cell array, the storage data group being one of the first weight signal group or the inverted weight signal group; performing a calculation in memory (CIM) operation between the storage data group and the first group of input signal groups by a multiplication-accumulation (MAC) circuit, thereby generating a first data group, the MAC circuit being coupled to the memory cell array; performing a read operation on a memory cell column in the memory cell array by a read circuit, performing a read operation on a memory cell column in the memory cell array includes: generating a first output signal group by a read circuit coupled to the MAC circuit and the memory cell array in response to at least the first data group, the enable signal group or the count signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of a memory device according to some embodiments.

[0008] Figure 2 is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 3 is a circuit diagram of a memory circuit according to some embodiments.

[0010] Figure 4 is a block diagram of a memory circuit according to some embodiments.

[0011] Figure 5A-Figure 5B is a corresponding circuit diagram of a corresponding write circuit according to some embodiments.

[0012] Figure 6 is a circuit diagram of a circuit according to some embodiments.

[0013] Figure 7A-7Bis a corresponding circuit diagram of a corresponding memory circuit according to some embodiments.

[0014] Figure 8 is a circuit diagram of a write circuit according to some embodiments.

[0015] Fig. 9 is a circuit diagram of a read circuit according to some embodiments.

[0016] Figure 10A-10B is a corresponding graph of corresponding waveforms according to some embodiments.

[0017] Fig.11A is a schematic diagram of a memory device according to some embodiments.

[0018] Fig. 11B is a schematic diagram of a neural network according to some embodiments.

[0019] Fig. 11C is a schematic diagram of an integrated circuit (IC) device according to some embodiments.

[0020] Figure 12A-12B is a flow chart of a method of operating a circuit according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0023] According to some embodiments, a memory circuit includes a memory cell array configured to store a set of storage data.

[0024] In some embodiments, the stored data set is one of the first weight signal set or the inverted weight signal set. In some embodiments, the inverted weight signal set is inverted with the first weight signal set. In some embodiments, the inverted weight signal set is generated from the first weight signal set.

[0025] In some embodiments, the memory cell array includes memory cells that store a logic 0 or a logic 1. In some embodiments, memory cells in the memory cell array that store a corresponding logic 1 consume more energy than corresponding memory cells in the memory cell array that store a logic 0. In some embodiments, the memory cell array is configured to store fewer logic 1s than logic 0s, thereby causing the memory cell array to consume less energy than otherwise.

[0026] In some embodiments, the memory circuit further comprises a multiply-accumulate (MAC) circuit coupled to the memory cell array. In some embodiments, the MAC circuit is configured to generate the first data set in response to the second data set and the stored data set.

[0027] In some embodiments, the memory circuit also includes input / output (IO) circuitry coupled to the MAC circuitry.

[0028] In some embodiments, the IO circuit includes a first circuit coupled to the memory cell array. In some embodiments, the first circuit is configured to send a first weight signal group in response to at least one enable signal group, or to generate an inverted weight signal group in response to at least another inverted enable signal group.

[0029] In some embodiments, the IO circuit further comprises a second circuit coupled to the MAC circuit. In some embodiments, the second circuit is configured to output a first output signal group in response to at least the first data group and an enable signal.

[0030] In some embodiments, the memory circuit is part of a compute-in-memory (CIM) macro and is configured to perform CIM operations that can be used in neural network applications, among other applications. In some embodiments, by configuring the memory circuit to store fewer logic ones than logic zeros, the power consumption of the CIM macro is reduced compared to other approaches.

[0031] Figure 1 1 is a block diagram of a memory device 100 according to some embodiments. The memory device is an integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuits for other functions in addition to the memory device.

[0032] The memory device 100 includes a memory circuit 102 and a memory controller 120 .

[0033] The memory circuit 102 includes a memory macro 110. The memory macro 110 includes a memory array 112, one or more weight buffers 114a, a multiply-accumulate (MAC) circuit 115, and an input / output (IO) circuit 114b. The memory controller 120 includes a word line driver 122, a bit line driver 124, an inverted bit line driver 125, a control circuit 126, and an input buffer 128. In some embodiments, one or more elements of the memory controller 120 are included in the memory macro 110, and / or one or more elements of the memory macro 110 (except the memory array 112) are included in the memory controller 120. In some embodiments, one or more elements of the memory macro 110 are not included in the memory macro 110. In some embodiments, at least one of the one or more weight buffers 114a or the IO circuit 114b is not included in the memory macro 110.

[0034] Macros have reusable configurations that can be used for IC devices of various types or designs. In some embodiments, macros are understood to be similar to the architectural hierarchy of modular programming, where subprocesses / programs are called by a main program (or other subprograms) to perform a given computing function. In this case, the IC device uses macros to perform one or more given functions. Therefore, in this case, the IC device is similar to the main program and the macro is similar to the subprocess / program in terms of the architectural hierarchy. In some embodiments, the macro is a soft macro. In some embodiments, the macro is a hard macro. In some embodiments, the macro is a soft macro described digitally in register transfer level (RTL) code. In some embodiments, synthesis, placement, and routing have not yet been performed on the macro, so the soft macro can be synthesized, placed, and routed for various process nodes. In some embodiments, the macro is a hard macro digitally described in a binary file format (e.g., a graphic database system II (GDSII) stream format), wherein the binary file format represents the plane geometry of one or more layout diagrams of the macro in a hierarchical form, text labels, other information, etc. In some embodiments, the macro is synthesized, placed, and routed so that the hard macro is specific to a specific process node.

[0035] A memory macro is a macro that includes addressable memory cells to allow data to be written to or read from the memory cells. In some embodiments, the memory macro also includes circuits configured to provide access to the memory cells and / or perform further functions associated with the memory cells. For example, as described herein, the memory macro 110 includes memory cells MC that form a circuit configured to provide a computing-in-memory (CIM) function associated with the memory cells MC. The described macro configuration is an example. Other configurations are within the scope of various embodiments. In some embodiments, the memory cells MC and the MAC circuit 115 are referred to as "CIM macros".

[0036] The memory cells MC of the memory macro 110 are arranged in a plurality of columns and rows of the memory array 112. The memory controller 120 is electrically coupled to the memory cells MC and configured to control operations of the memory cells MC, including but not limited to read operations, write operations, and the like.

[0037] The memory array 112 further includes a plurality of word lines (also referred to as “address lines”) WL1 to WLr extending along the rows, a plurality of bit lines (also referred to as “data lines”) BL1 to BL2 extending along the columns of the memory cells MC, and a plurality of bit lines (also referred to as “data lines”) BL2 to BL3 extending along the columns of the memory cells MC. t , and a plurality of inverted bit lines (also referred to as “inverted data lines”) BLB1 to BLB2 extending along the columns of the memory cells MC. t , where r and t are natural numbers. In some embodiments, the memory array 112 does not include a plurality of inverted bit lines BLB1 to BLB t , but also includes a plurality of source lines SL1 to SLt (not shown) extending along the columns of memory cells MC. Other variations of the memory array 112 are also within the scope of the present disclosure. Each memory cell MC is electrically coupled to the storage controller 120 via at least one word line, at least one bit line, and at least one inverted bit line. In some example operations, the word line is configured to transmit the address of the memory cell MC to be read therefrom, or to transmit the address of the memory cell MC to be written, etc. In at least one embodiment, a word line group is configured to perform reading word lines and writing word lines at the same time. In some embodiments, the bit line and the inverted bit line are used to transmit data read from or written to the memory cell MC indicated by the corresponding word line, etc.

[0038] In some embodiments, the read bit line and / or the read inverted bit line are configured to transmit data read from the memory cell MC indicated by the corresponding word line, and the write bit line and / or the write inverted bit line are configured to transmit data to be written to the memory cell MC indicated by the corresponding word line, etc.

[0039] Word lines are generally referred to herein as WL, bit lines are also generally referred to herein as BL, and inverted bit lines are referred to herein as BLB. Various numbers of word lines, bit lines, and / or inverted bit lines in the memory array 112 are within the scope of various embodiments. In some embodiments, the memory cell MC is a non-volatile memory (NVM). Example memory types of the memory cell MC include, but are not limited to, static random access memory (SRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), phase change RAM (PCRAM), spin transfer torque RAM (STTRAM), floating gate metal oxide semiconductor field effect transistor (FGMOS), spin electronics, etc. In one or more example embodiments described herein, the memory cell MC comprises an SRAM memory cell.

[0040] exist Figure 1 In the example configuration, the memory cell MC is a single-port memory cell. In some embodiments, the port of the memory cell is represented by a word line group WL and a bit line BL / inverted bit line BLB (referred to herein as a WL / BL / BLB group), which are configured to provide access to the memory cell in a read operation (i.e., read access) and / or a write operation (i.e., write access). A single-port memory cell has one WL / BL / BLB group that is configured for read access and write access, but not at the same time. A multi-port memory cell has several WL / BL / BLB groups, each of which is configured for read access only, or for write access only, or for read access and write access. About Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A-Figure 5B , Figure 6 , Figure 7A-7B , Figure 8 , Fig. 9 , Figure 10A-10B and Figures 11A-11C An example of a single-port memory cell is described. Other configurations or other numbers of ports of memory cells in the memory array 112 are within the scope of the present disclosure. For example, in some embodiments, reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A-Figure 5B , Figure 6 , Figure 7A-7B , Figure 8 , Fig. 9 , Figure 10A-10B and Figures 11A-11C One or more of the single-port memory cells described may be replaced with a corresponding multi-port memory cell.

[0041] The memory array 112 includes a plurality of memory segments. In some embodiments, the memory segments include memory rows, memory columns, memory bodies, and the like. A memory row includes a plurality of memory cells coupled to the same word line WL. A memory column (also referred to as a "memory string") includes a plurality of memory cells coupled to the same bit line BL and the same inverted bit line BLB. A memory body includes a plurality of memory rows and / or a plurality of memory columns. In at least one embodiment, a memory body includes a portion of a memory array 112 having a plurality of memory rows and a plurality of memory columns. In some embodiments, a memory segment includes a plurality of memory bodies. In one example, a first memory segment 105 includes a memory column of memory cells MC coupled to a bit line BL1 and an inverted bit line BLB1, a second memory segment 107 includes a memory column of memory cells MC coupled to a bit line BL2 and an inverted bit line BLB2, and the like. Other ways of dividing the memory array 112 into a plurality of memory segments are within the scope of various embodiments.

[0042] In some embodiments, memory array 112 includes memory cells that store either logic 0 or logic 1. In some embodiments, memory cells in memory array 112 that store corresponding logic 1 consume more energy than corresponding memory cells in memory array 112 that store logic 0. In some embodiments, memory array 112 is configured to store fewer logic 1s than logic 0s, thereby causing memory array 112 to consume less energy than otherwise.

[0043] Each memory cell MC includes a storage portion 117a (for ease of explanation, only the memory cell 117 is shown). Each memory cell MC is configured to store weight data W (also referred to as "weight signal group W") or inverted weight data WB (also referred to as inverted weight signal group WB). In some embodiments, the inverted weight signal group WB is inverted with the weight signal group W. Each storage portion 117a corresponds to each calculation portion 115a.

[0044] In one or more example embodiments described herein, the memory cell MC is a unit memory cell, that is, each memory cell is configured to store one bit of weight data W or inverted weight data WB. This is an example, and each multi-bit memory cell configured to store more than one bit of weight data W or inverted weight data WB is within the scope of various embodiments. In some embodiments, the unit memory cell is also referred to as a bit cell. For example, a memory cell 113 coupled to a word line WL1, a bit line BLt, and an inverted bit line BLBt is configured to store weight data W1, t or inverted weight data WB. In some embodiments, Figure 1 The weight data W1,t in the embodiment also includes the inverted weight data WB. For the sake of convenience, WB1,t is Figure 1The combination of the plurality of weight data W (or inverted weight data WB) stored in the plurality of memory cells constitutes the weight value used by the MAC circuit 115 in the CIM operation. For simplicity, one weight data stored in the memory cell MC of the memory array 112, a plurality of weight data stored in the plurality of memory cells MC, or all weight data stored in all memory cells MC are referred to herein as weight data W.

[0045] The MAC circuit 115 includes MAC units (shown only in the first column of the MAC circuit 115 for ease of illustration / coupled to the first memory segment 105 for ease of illustration). In some embodiments, each of the MAC units is a corresponding computational portion 115a of the plurality of computational portions 115a. In some embodiments, each of the computational portions 115a of the plurality of computational portions 115a is a corresponding MAC unit.

[0046] Each memory cell MC includes a storage part 117a (for ease of illustration, only shown in the memory cell 117) and a calculation part 115a (for ease of illustration, only shown in the memory cell 117). Each memory cell MC is configured to store a weight data W, and is configured to perform a CIM operation on the weight data W and the received data D_IN. Each storage part 117a corresponds to each calculation part 115a.

[0047] Each storage part 117 a of the memory cell MC is configured to store weight data W, and each calculation part 115 a in the memory cell MC is configured to perform a CIM operation on the weight data W and the reception data D_IN.

[0048] Each MAC unit of the MAC circuit 115 includes a calculation part 115a (shown only in the first column of the MAC circuit 115 for ease of explanation, / coupled to the first memory segment 105 for ease of explanation). Each MAC unit of the MAC circuit 115 is configured to perform a CIM operation on one of the weight data W or the inverted weight data WB and the received data D_IN. Each calculation part 115a in the MAC circuit 115 is configured to perform a CIM operation on the weight data W or the inverted weight data WB and the received data D_IN, and each calculation part 115a corresponds to each storage part 117a.

[0049] In some embodiments, each computation portion 115a of the MAC circuit 115 is coupled to each corresponding memory cell of the memory cells MC through a corresponding bit line BL and an inverted bit line BLB, and is configured to receive one of the weight data W or the inverted weight data WB.

[0050] Each computational portion 115a of the MAC circuit 115 is also coupled to an output of an input buffer 128 and is configured to receive input data D_IN. Figure 1 In the example configuration of FIG. 1 , input data D_IN is provided from input buffer 128 in memory controller 120. In one or more embodiments, as Fig.11A As shown, input data D_IN is output data (eg, output data D_OUT) provided from another memory macro (not shown) of memory device 100. In some embodiments, input data D_IN is serially provided to computing portion 115a in the form of a bit stream as described herein.

[0051] The calculation part 115a of the MAC circuit 115 is configured to generate output data OUT or OUTB corresponding to a CIM operation performed on the input data D_IN and one of the weight data W or inverted weight data WB read from one or more memory cells MC based on the input data D_IN from the input buffer 128. Examples of CIM operations include, but are not limited to, mathematical operations, logical operations, combinations thereof, and the like. In at least one embodiment, the calculation part 115a is a MAC circuit, and the CIM operation includes multiplying one or more multi-bit weight values ​​with one or more multi-bit input data values. Other calculation parts or circuits configured to perform CIM operations other than multiplication are within the scope of various embodiments. The output data OUT or OUTB is provided to the IO circuit 114b as input data.

[0052] In one or more exemplary embodiments described herein, each calculation part 115a is configured to calculate the corresponding bit of the output signal OUT or OUTB based on the CIM operation of one of the bits of the weight data W or the inverted weight data WB and the bit of the received data D_IN. This is an example, when the memory cell MC is a multi-bit memory cell, each memory cell is configured to store more than one bit of weight data W or inverted weight data WB, and each calculation part 115a is configured to perform a corresponding CIM operation on the corresponding multi-bit weight data W and the inverted weight data WB, thereby generating a corresponding bit of the output signal OUT or OUTB (also referred to as "data signal OUT or OUTB group" or "data OUT or OUTB group"), and within the scope of various embodiments.

[0053] The weight buffer 114 a is configured to receive new weight data (e.g., weight data W) or new inverted weight data (e.g., inverted weight data WB). The weight buffer 114 a is configured to forward the new weight data (e.g., weight data W) or new inverted weight data (e.g., inverted weight data WB) to the corresponding memory cells in the memory array 112.

[0054] The weight buffer 114a is coupled to the memory array 112 and the IO circuit 114b, and is configured to temporarily store new weight data or new inverted weight data to be updated in the memory array 112. In some embodiments, the weight buffer 114a is located outside the memory macro 110. In some embodiments, the weight buffer 114a is part of the IO circuit 114b. In some embodiments, the weight buffer 114a is not part of the IO circuit 114b. In some embodiments as described herein, each memory segment is coupled to a corresponding weight buffer. In one or more embodiments described herein, a common weight buffer is coupled to multiple memory segments. The weight buffer 114a is coupled to the memory cells MC in the memory array 112 via the bit line BL and the inverted bit line BLB. In a weight data update operation, new weight data (weight data W or inverted weight data WB) is written from the weight buffer 114a and into one or more memory cells MC via the corresponding bit line BL and the corresponding inverted bit line BLB. As Figure 1 As schematically shown, the weight buffer 114a is coupled to the memory controller 120 to receive new weight data and / or control signals specifying when and / or at which memory cell MC to update the new weight data. In at least one embodiment, the new weight data is received from an external circuit (e.g., a processor as described herein) outside the memory device 100. The new weight data is received by one or more input / output circuits (e.g., IO circuit 114b) and forwarded to the weight buffer 114a. Example weight buffers include, but are not limited to, registers, memory cells, or other circuit elements configured for data storage.

[0055] IO circuit 114b has an input coupled to bit line BL / inverted bit line BLB to receive output data OUT / OUTB from one or more memory cells MC through MAC circuit 115. In some embodiments, IO circuit 114b is configured to receive output data OUT / OUTB received from bit line BL / inverted bit line BLB from memory array 112 and generate output signal D_OUT (also referred to as "output signal group D_OUTB") at the output of IO circuit 114b. Examples of IO circuit 114b include registers, flip-flops, latches, etc. In some embodiments, one or more non-limiting examples of IO circuit 114b are Figure 4 , Figure 5A-Figure 5B , Figure 6 , Figure 7A-7B , Figure 8 or Fig. 9 At least one of the embodiments is shown in the drawings, and thus similar detailed description is omitted.

[0056] In some embodiments, the output data D_OUT is provided as input data to another memory macro (not shown) of the memory device 100 (eg, Fig.11A In one or more embodiments, the output data D_OUT is output to an external circuit outside the memory device 100, such as a processor as described herein, through one or more I / O circuits (not shown) of the memory controller 120.

[0057] exist Figure 1 In an example configuration, the controller 120 includes a word line driver 122, a bit line driver 124, an inverted bit line driver 125, a control circuit 126, and an input buffer 128. In at least one embodiment, the controller 120 also includes one or more clock generators for providing clock signals to various components of the memory device 100, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations in the memory device 100.

[0058] The word line driver 122 is coupled to the memory array 112 via the word lines WL. The word line driver 122 is configured to decode a row address of a memory cell MC to be accessed in a read operation or a write operation. The word line driver 122 is configured to provide a voltage to the selected word line WL corresponding to the decoded row address, and to supply a different voltage to other unselected word lines WL. In some embodiments, each word line WL1, WL2, ..., WLr of the word lines WL has a corresponding input signal XIN0, XIN1, ..., XIN2 of the input signal XIN. r .

[0059] The bit line driver 124 is coupled to the memory array 112 via the bit lines BL. The bit line driver 124 is configured to decode a column address of a memory cell MC selected to be accessed in a read operation or a write operation. The bit line driver 124 is configured to provide a voltage to a selected bit line BL corresponding to the decoded column address and to provide a different voltage to other unselected bit lines BL.

[0060] The inversion bit line driver 125 is coupled to the memory array 112 via the inversion bit line BLB. The inversion bit line driver 125 is configured to decode the column address of the memory cell MC selected to be accessed in the read operation or the write operation. The inversion bit line driver 125 is configured to provide a voltage to the selected inversion bit line BLB corresponding to the decoded column address, and provide a different voltage to other unselected inversion bit lines BLB.

[0061] The control circuit 126 is coupled to one or more of the memory cell MC, the weight buffer 114a, the MAC circuit 115, the IO circuit 114b, the word line driver 122, the bit line driver 124, the inverted bit line driver 125, and the input buffer 128 to coordinate the operation of these circuits, drivers, and / or buffers in the overall operation of the memory device 100. For example, the control circuit 126 is configured to generate various control signals for controlling the operation of one or more of the memory cell MC, the weight buffer 114a, the MAC circuit 115, the IO circuit 114b, the word line driver 122, the bit line driver 124, the inverted bit line driver 125, and the input buffer 128.

[0062] Input buffer 128 is configured to receive input data from an external circuit (e.g., a processor as described herein) external to memory device 100. Input data is received through one or more I / O circuits (e.g., IO circuit 114b) and forwarded to memory array 112 by input buffer 128. Example input buffers include, but are not limited to, registers, memory cells, or other circuit elements configured for data storage.

[0063] In at least one embodiment, a CIM memory device (such as memory device 100) is superior to other methods in which data is moved back and forth between the memory and the processor because such back and forth data movement is a bottleneck for performance and energy efficiency and can be avoided. Examples of CIM applications include, but are not limited to, artificial intelligence, image recognition, neural networks for machine learning, etc. In some embodiments, memory device 100 enables weight data updates and CIM operations to be performed simultaneously in one or more embodiments.

[0064] As a result, in at least one embodiment, one or more advantages can be achieved, including but not limited to reduced processing time, reduced power consumption, reduced chip area, reduced manufacturing costs, improved performance, etc.

[0065] Other configurations or numbers of elements in memory device 100 are within the scope of the present disclosure.

[0066] Figure 2 is a circuit diagram of a memory circuit 200 according to some embodiments.

[0067] The memory circuit 200 is Figure 1 The present invention is only an embodiment of a portion of the memory device 100 , and thus similar detailed description is omitted.

[0068] and Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A-Figure 5B , Figure 6 , Figure 7A-7B , Figure 8 , Fig. 9 , Figure 10A-10B and Figures 11A-11C The same or similar components in one or more of the embodiments (as shown below) are given the same reference numerals, and thus their detailed description is omitted. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A-Figure 5B , Figure 6 , Figure 7A-7B , Figure 8 , Fig. 9 , Figure 10A-10B and Figures 11A-11C Some of the markup elements in Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A-Figure 5B , Figure 6 , Figure 7A-7B , Figure 8 , Fig. 9 , Figure 10A-10B and Figures 11A-11C In some embodiments, Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A-Figure 5B , Figure 6 , Figure 7A-7B , Figure 8 , Fig. 9 , Figure 10A-10B and Figures 11A-11C include Figure 1 , Figure 2 Additional elements not shown.

[0069] The memory circuit 200 includes an input driver group 202 , a memory macro 204 , a control circuit 206 , and an IO circuit 208 .

[0070] In some embodiments, the input driver group 202 is a word line driver 122, Figure 2 The controller 206 is Figure 1 The memory controller 120, Figure 2 The IO circuit 208 is Figure 1 IO circuit 114b in, so similar detailed description is omitted. In some embodiments, Figure 2 The memory macro 204 is Figure 1 The memory array 112 and the MAC circuit 115 are described in detail, and thus similar detailed descriptions are omitted.

[0071] The input driver group 202 is coupled to the memory macro 204 and the controller 206. In some embodiments, the input driver group 202 is configured to generate an input signal XIN and generate a count signal ACT_XIN. In some embodiments, the count signal ACT_XIN corresponds to the number of word lines WL in the memory macro 204. In some embodiments, the memory macro 204 is a CIM macro.

[0072] Memory macro 204 is coupled to input driver group 202 and IO circuit 208 .

[0073] The controller 206 is coupled to the input driver group 202 and the IO circuit 208. In some embodiments, the controller 206 includes one or more clock generators for providing a control signal group CTRL, such as a clock signal, to the input driver group 202 and the IO circuit 208 for data exchange with an external device, and / or one or more controllers for controlling various operations in the memory circuit 200.

[0074] IO circuit 208 is coupled to input driver group 202 and controller 206 .

[0075] In some embodiments, the IO circuit 208 is configured to perform at least one read or write operation of the memory macro 204. In some embodiments, the IO circuit 208 is configured to perform at least one of the read or write operations of the memory macro 204 in response to at least one of the count signal ACT_XIN, the control signal group CTRL, or the data signal group OUT or OUTB. In some embodiments, the IO circuit 208 is configured to generate the output signal group D_OUT in response to at least one of the count signal ACT_XIN, the control signal group CTRL, or the data signal group OUT or OUTB.

[0076] exist Figure 1 In the embodiment, the word line WL corresponds to one or more word lines WL1, WL2, ..., WLr, and the bit line BL corresponds to one or more bit lines BL1, BL2, ..., BL t , the reverse bit line BLB corresponds to one or more reverse bit lines BLB1, BLB2, ..., BLB t , and thus similar detailed description is omitted.

[0077] Other configurations or numbers of elements in memory circuit 200 are within the scope of the present disclosure.

[0078] Figure 3 is a circuit diagram of a memory circuit 300 according to some embodiments.

[0079] The memory circuit 300 is Figure 1For example, the word line driver group 302 and the counter 304 are Figure 2 The embodiment of the input driver group 202 is described above, and thus similar detailed description is omitted.

[0080] The memory circuit 300 includes a word line driver group 302 , a counter 304 , and a memory macro 204 .

[0081] The word line driver group 302 is coupled to the memory macro 204 and the counter 304. In some embodiments, the word line driver group 302 is configured to generate a word line signal group XIN. The word line driver group includes at least one of word line drivers 302a, 302b, ..., 302N, where N is an integer. In some embodiments, each word line driver 302a, 302b, ..., 302N is configured to generate a corresponding word line signal XIN0, XIN1, ..., XIN2. N .

[0082] In some embodiments, the word line signal group XIN includes word line signals XIN0, XIN1, . . . , XIN N One or more of, where N is an integer. In some embodiments, the word line signal group XIN includes N+1 word line signals. In some embodiments, each word line WL0, WL1, ..., WLN of the word line group WL has a corresponding word line signal XIN0, XIN1, ..., XINN of the word line signal group XIN. N .

[0083] In some embodiments, each word line driver 302a, 302b, ..., 302N of the word line driver group 302 is configured to output a corresponding word line signal XIN0, XIN1, ..., XIN2 of the word line signal group XIN on a corresponding word line WL0, WL1, ..., WLN of the word line group WL. N .

[0084] In some embodiments, counter 306 is coupled to word line driver group 302. In some embodiments, counter 306 is configured to receive word line signal group XIN on word line group WL. In some embodiments, counter 306 is configured to count the number of active inputs (e.g., active word lines WL) receiving active word line signals XIN from word line driver group 302, thereby generating count signal ACT_XIN. In other words, in some embodiments, counter 306 is configured to generate count signal ACT_XIN by counting the number of active inputs (e.g., active word lines WL) receiving active word line signals XIN by word line driver group 302. In some embodiments, active input is an input of a word line signal having a logic high (e.g., logic 1). In some embodiments, active input is an input of a word line signal having a logic low (e.g., logic 0).

[0085] In some embodiments, the counter 306 is configured to generate the count signal ACT_XIN by counting the number of active word line signals XIN received from the word line driver group 302. In some embodiments, the signals of the active word lines in the number of active word line signals XIN are word line signals equal to logic high (e.g., logic 1). In some embodiments, the signals of the active word lines in the number of active word line signals XIN are word line signals equal to logic low (e.g., logic 0).

[0086] In some embodiments, the counter is further configured to send a count signal ACT_XIN to the IO circuit 208. In some embodiments, the count signal ACT_XIN is the number of active word line signals in the word line signal group XIN. In other words, in some embodiments, the count signal ACT_XIN is the number of active word lines in the word line group WL. For example, in some embodiments, if the number of word lines WL is 8, the number of word line signals XIN having logic 1 is 7, the number of active word line signals XIN is 7, and the counter 306 is configured to count 7 active word line signals XIN, so the counter 306 generates a count signal ACT_XIN of 7.

[0087] In some embodiments, a counting signal ACT_XIN is generated for each corresponding column of memory cells in the memory macro 204. In some embodiments, the counting signal ACT_XIN includes counting signals ACT_XIN1, ACT_XIN2, ..., ACT_XIN N In some embodiments, the counting signals ACT_XIN1, ACT_XIN2, ..., ACT_XIN N is the corresponding count signal of the corresponding column of memory cells in the memory macro 204.

[0088] In some embodiments, the counting signal ACT_XIN may be used by at least one of the circuits 400 , 800 , or 900 .

[0089] Other configurations or numbers of elements in memory circuit 300 are within the scope of the present disclosure.

[0090] Figure 4 is a block diagram of a memory circuit 400 according to some embodiments.

[0091] The memory circuit 400 includes the weight buffer 114 a , the memory macro 204 , a write circuit 402 , a circuit 404 , a write circuit 406 , and a read circuit 408 .

[0092] In some embodiments, write circuit 402 , circuit 404 , write circuit 406 , and read circuit 408 are embodiments of IO circuit 114 b , and thus similar detailed descriptions are omitted.

[0093] The write circuit 402 is coupled to the circuit 404 , the write circuit 406 , and the read circuit 408 .

[0094] An input of write circuit 402 is coupled to an output of write circuit 406. In some embodiments, an input of write circuit 402 is coupled to an output of counter 306.

[0095] An output of write circuit 402 is coupled to an input of circuit 404 , an input of write circuit 406 , and an input of read circuit 408 .

[0096] The write circuit 402 is configured to at least receive the count signal ACT_XIN or store the data set DO. In some embodiments, the count signal ACT_XIN is Figure 3 In some embodiments, the storage data group DO is received from the write circuit 406. In some embodiments, the storage data group DO includes a weight signal group W (at least Figure 1 discussed in the following) or the inverted weight signal group WB (at least in the attached Figure 1 discussed in ).

[0097] The write circuit 402 is configured to generate at least an enable signal group INV_EN in response to at least the storage data group DO or the counting signal ACT_XIN. In some embodiments, the enable signal group INV_EN includes enable signals INV_EN0, INV_EN1, ..., INV_EN N One or more of , where N is an integer.

[0098] The write circuit 402 is configured to output at least an enable signal group INV_EN to at least one of the circuit 404 , the write circuit 406 , or the read circuit 408 .

[0099] The circuit 404 is coupled to the write circuit 402 and the write circuit 406 .

[0100] An input of circuit 404 is coupled to an output of write circuit 402 .

[0101] The output of circuit 404 is coupled to the input of write circuit 406 .

[0102] The write circuit 402 is configured to receive at least an enable signal group INV_EN.

[0103] The write circuit 402 is configured to generate at least an inverted enable signal group INV_ENB in ​​response to at least the enable signal group INV_EN. In some embodiments, the inverted enable signal group INV_ENB includes inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB N One or more of , where N is an integer.

[0104] In some embodiments, the inverted enable signal group INV_ENB is inverted with the enable signal group INV_EN. In some embodiments, at least the inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB N At least corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN N Invert.

[0105] The circuit 404 is configured to output at least an inverted enable signal group INV_ENB to the write circuit 406 .

[0106] Write circuit 406 is coupled to write circuit 402, circuit 404, and weight buffer 114a.

[0107] The input of write circuit 406 is coupled to the output of write circuit 402, the output of circuit 404, and the source of weight signal group W. In some embodiments, weight signal group W is composed of Figure 1 In some embodiments, the weight signal group W is composed of a circuit external to the memory device 100. Figure 1 In some embodiments, the weight signal group W is composed of Figure 1 In some embodiments, the weight signal group W is composed of a circuit external to the IO circuit 114b. Figure 1 The IO circuit 114b is a part of the circuit that sends or generates.

[0108] The output of write circuit 406 is connected to the input of write circuit 402 and the input of weight buffer 114a.

[0109] The write circuit 406 is configured to receive at least the weight signal group W, the enable signal group INV_EN or the inverted enable signal group INV_ENB. In some embodiments, the enable signal group INV_EN is received from the write circuit 402. In some embodiments, the inverted enable signal group INV_ENB is received from the circuit 404.

[0110] The write circuit 406 is configured to generate at least the storage data group DO in response to at least the weight signal group W, the enable signal group INV_EN or the inverted enable signal group INV_ENB. In some embodiments, the write circuit 406 is configured to output at least the storage data group DO in response to at least the weight signal group W, the enable signal group INV_EN or the inverted enable signal group INV_ENB.

[0111] In some embodiments, the stored data set DO includes a weight signal set W (at least Figure 1 discussed in the following) or the inverted weight signal group WB (at least in the attached Figure 1 discussed in ).

[0112] In some embodiments, the weight signal group W includes weight signals W0, W1, ..., W N One or more of .

[0113] In some embodiments, the inverted weight signal group WB includes corresponding inverted weight signals WB0, WB1, . . . , WB N One or more of .

[0114] In some embodiments, the write circuit 406 generates the inverted weight signal group WB in response to at least the weight signal group W, the enable signal group INV_EN, or the inverted enable signal group INV_ENB. In some embodiments, the write circuit 406 generates the inverted weight signal group WB in response to at least the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN. N or the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB of the inverted enable signal group INV_ENB N , from the corresponding weight signals W0, W1, ..., W of the weight signal group W N Generates the inverted weight signals WB0, WB1, ..., WB N .

[0115] In some embodiments, the inverted weight signals WB0, WB1, . . . , WB NThe corresponding weight signals W0, W1, ..., W N Invert.

[0116] In some embodiments, storing the data group DO includes storing data signals DO0, DO1, . . . , DO N One or more of , where N is an integer.

[0117] In some embodiments, the stored data set DO is equal to one or more members of the weight signal set W or the inverted weight signal set WB.

[0118] In some embodiments, based on the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN N Or the corresponding inverted enable signal INV_ENB0, INV_ENB1, ..., INV_ENB N , store data signals DO0, DO1, ..., DO N Equal to the corresponding weight signals W0, W1, ..., W N Or inverted weight signals WB0, WB1, ..., WB N .

[0119] In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, . . . , INV_EN1 of the enable signal group INV_EN are N When the storage data signals DO0, DO1, . . . , DO N is equal to the corresponding weight signals W0, W1, ..., W of the weight signal group W N In some embodiments, when the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB N When the logic is high, the storage data signals DO0, DO1, ..., DO N is equal to the corresponding weight signals W0, W1, ..., W of the weight signal group W N .

[0120] In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, . . . , INV_EN1 of the enable signal group INV_EN are N When the stored data signals DO0, DO1, ..., DO N =WB0, WB1, ..., WB1 of the inverted weight signal group WB NIn some embodiments, when the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB N When the storage data signals DO0, DO1, ..., DO N =WB0, WB1, ..., WB1 of the inverted weight signal group WB N .

[0121] In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, . . . , INV_EN N When the storage data signals DO0, DO1, . . . , DO N =WB0, WB1, ..., WB1 of the inverted weight signal group WB N In some embodiments, when the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB N When the stored data signals DO0, DO1, ..., DO N =WB0, WB1, ..., WB1 of the inverted weight signal group WB N .

[0122] In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, . . . , INV_EN1 of the enable signal group INV_EN are N When the stored data signals DO0, DO1, ..., DO N is equal to the corresponding weight signals W0, W1, ..., W of the weight signal group W N In some embodiments, when the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB N When the storage data signals DO0, DO1, ..., DO N equal to the corresponding weight signals W0, W1, ..., W of the weight signal group WB N .

[0123] The write circuit 406 is configured to output at least the storage data group DO to at least one of the write circuit 402 or the weight buffer 114a.

[0124] The weight buffer 114 a is coupled to the write circuit 406 and the memory macro 204 .

[0125] An input of the weight buffer 114 a is coupled to an output of the write circuit 406 .

[0126] The output of the weight buffer 114a is coupled to the input of the memory macro 204. In some embodiments, the output of the weight buffer 114a is also coupled to the input of the write circuit 402, and the weight buffer 114a is also configured to output the storage data group DO' to the write circuit 402. In these embodiments, the input of the write circuit 402 is not coupled to the output of the write circuit 406.

[0127] The weight buffer 114 a is configured to at least receive and store the data set DO.

[0128] The weight buffer 114a is configured to generate at least a stored data set DO' in response to at least the stored data set DO. In some embodiments, the stored data set DO' is equal to the stored data set DO. In some embodiments, the stored data set DO' is a delayed version of the stored data set DO.

[0129] In some embodiments, the stored data set DO' includes stored data signals DO0', DO1', . . . , DO N ', where N is an integer. In some embodiments, the stored data signals DO0', DO1', ..., DO N ' is equal to the corresponding storage data signals DO0, DO1, ..., DO N In some embodiments, the stored data signals DO0', DO1', ..., DO N ' is the corresponding storage data signal DO0, DO1, ..., DO N A delayed version of .

[0130] The weight buffer 114 a is configured to output at least the storage data group DO′ to the memory macro 204 .

[0131] Memory macro 204 is coupled to weight buffer 114 a and read circuit 408 .

[0132] The input of memory macro 204 is coupled to the output of weight buffer 114a. In some embodiments, the input of memory macro 204 is coupled to the output of weight buffer 114a and Figure 2 The output end of the input driver group 202.

[0133] An output of the memory macro 204 is coupled to an input of the read circuit 408 .

[0134] The memory macro 204 is configured to receive and store at least a storage data set DO.

[0135] In some embodiments, during a read operation of the memory macro 204 , the memory macro 204 is configured to output at least the output signal group OU in response to at least the storage data group DO′ or the input signal group XIN.

[0136] In some embodiments, the output signal group OU includes output signals OU0, OU1, . . . , OU N One or more of , where N is an integer.

[0137] In some embodiments, the output signal group OU includes an output signal group OUT (at least Figure 1 ) or the output signal group OUTB (at least Figure 1 discussed in ).

[0138] In some embodiments, the output signal group OUT includes output signals OUT0, OUT1, . . . , OUT N One or more of, where N is an integer. In some embodiments, when the stored data set DO includes a weight signal set W, the output signal set OUT corresponds thereto.

[0139] In some embodiments, the output signal group OUTB includes output signals OUTB0, OUTB1, . . . , OUTB N One or more of, wherein N is an integer. In some embodiments, when the stored data group DO includes the inverted weight signal group WB, the output signal group OUTB corresponds thereto.

[0140] In some embodiments, the output signal group OU is equal to one or more members of the output signal group OUT or the output signal group OUTB. In some embodiments, the output signals OU0, OU1, ..., OU N Equal to the corresponding output signal OUT0, OUT1, ..., OUT N Or the corresponding output signals OUTB0, OUTB1, ..., OUTB N .

[0141] The memory macro 204 is configured to output at least the output signal group OU to the read circuit 408. In some embodiments, the memory macro 204 is configured to output at least the output signal group OUT or OUTB to the read circuit 408.

[0142] Read circuit 408 is coupled to write circuit 402 and memory macro 204 .

[0143] The input of the read circuit 408 is connected to the output of the write circuit 402 , the memory macro 204 , and the output of the counter 306 .

[0144] In some embodiments, the output of the read circuit 408 is coupled to other circuits (not shown).

[0145] Read circuit 408 is configured to receive at least enable signal group INV_EN, output signal group OU or count signal ACT_XIN. In some embodiments, read circuit 408 is configured to receive at least enable signal group INV_EN, count signal ACT_XIN and one of output signal group OUT or output voltage group OUTB.

[0146] In some embodiments, the enable signal group INV_EN is received from the write circuit 402. In some embodiments, the count signal ACT_XIN is received from the counter 306. In some embodiments, during a read operation of the memory macro 204, the output signal group OU is read from the memory macro 204 in response to at least one of the enable signal group INV_EN or the count signal ACT_XIN.

[0147] The read circuit 408 is configured to output at least the output signal group D_OUT in response to at least the enable signal group INV_EN, the output signal group OU or the count signal ACT_XIN. In some embodiments, the read circuit 408 is configured to generate at least the output signal group D_OUT in response to at least the enable signal group INV_EN, the output signal group OU or the count signal ACT_XIN.

[0148] In some embodiments, the output signal group D_OUT includes output signals D_OUT0, D_OUT1, . . . , D_OUT N One or more of , where N is an integer.

[0149] The read circuit 408 is configured to output at least an output signal group D_OUT.

[0150] Other configurations or numbers of elements in memory circuit 400 are within the scope of the present disclosure.

[0151] Figure 5A-Figure 5B is a corresponding circuit diagram of a corresponding write circuit 500A- 500B according to some embodiments.

[0152] The write circuit 500A is Figure 4 This is an embodiment of the write circuit 406, and thus similar detailed description is omitted.

[0153] The write circuit 500A is configured to generate at least the storage data group DO in response to at least the weight signal group DIN, the enable signal group INV_EN or the inverted enable signal group INV_ENB. In some embodiments, the weight signal group DIN is equal to the weight signal group W.

[0154] In some embodiments, the storage data set DO may be used by at least one of the weight buffer 114 a , the memory circuit 400 , the write circuit 402 , or the write circuit 800 .

[0155] In some embodiments, the weight signal group W may be used by at least one of the weight buffer 114 a , the memory circuit 400 , the write circuit 402 , or the write circuit 800 .

[0156] In some embodiments, the inverted weight signal group WB may be used by at least one of the weight buffer 114 a , the memory circuit 400 , the write circuit 402 , or the write circuit 800 .

[0157] In some embodiments, the write circuit 500A is configured to generate at least the storage data group DO in response to at least the weight signal group W, the enable signal group INV_EN, or the inverted enable signal group INV_ENB.

[0158] The write circuit 500A includes a path group 520 and a path group 522 .

[0159] In some embodiments, path group 520 includes one or more of paths 520a, 520b, ..., 520N.

[0160] In some embodiments, path group 522 includes one or more of paths 522a, 522b, ..., 522N.

[0161] In some embodiments, the paths in the path group 520 and the paths in the path group 522 are selected / deselected based on the inverted enable signal group INV_ENB or the enable signal group INV_EN. In some embodiments, the selected paths in the path group 520 or the path group 522 are configured to generate the corresponding inverted weight signal group WB or the corresponding weight signal group W as the storage data signal group DO.

[0162] In some embodiments, the paths in the path group 520 are selected by corresponding inverted enable signals in the inverted enable signal group INV_ENB. Similarly, in some embodiments, the paths in the path group 520 are deselected by corresponding inverted enable signals in the inverted enable signal INV_ENB.

[0163] In some embodiments, the paths in the path group 522 are selected by corresponding enable signals in the enable signal group INV_EN. Similarly, in some embodiments, the paths in the path group 522 are deselected by corresponding enable signals in the enable signal group INV_EN.

[0164] In some embodiments, each path in path group 520 and each corresponding path in path group 522 are coupled together.

[0165] Each path in the path group 520 is configured to receive a corresponding weight signal in the weight signal group DIN and a corresponding inverted enable signal in the inverted enable signal group INV_ENB.

[0166] Each path in path group 520 is configured to generate a corresponding inverted weight signal of inverted weight signal WB in response to being selected. In some embodiments, unselected paths in path group 520 do not output or generate corresponding inverted weight signals in inverted weight signal WB group.

[0167] Based on the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB of the inverted enable signal group INV_ENB N To select each path in path group 520.

[0168] In some embodiments, the path group 520 further includes an inverter group 502 .

[0169] In some embodiments, inverter group 502 includes one or more of inverters 502a, 502b, ..., 502N.

[0170] Each path in the path group 520 includes a corresponding inverter 502 a , 502 b , . . . , 502N in the inverter group 502 .

[0171] In some embodiments, when selected, the inverters 502a, 502b, ..., 502N of the inverter group 502 are configured to respond to the corresponding weight signals DIN0, DIN1, ...DIN of the weight signal group DIN. N and the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB of the inverted enable signal group INV_ENB N , generating corresponding inverted weight signals WB0, WB1, ...WB of the inverted weight signal group WB N .

[0172] For brevity, path 520a will be described, but the remaining paths in path group 520 are similar to path 520a. For brevity, inverter 502a will be described, but the remaining inverters in inverter group 502 are similar to inverter 502a.

[0173] In some embodiments, the inverter 502a is enabled or selected by a logic low signal (logic 0). In some embodiments, when the inversion enable signal INV_ENB0 in the inversion enable signal group INV_ENB is a logic low signal (logic 0), the inverter 502a is enabled or selected.

[0174] In some embodiments, inverter 502a is coupled to circuit 404 and weight buffer circuit 114a. In some embodiments, inverter 502a is a tri-state inverter. In some embodiments, in response to the inverting enable signal INV_ENB0 in the inverting enable signal group INV_ENB, inverter 502a is selected or deselected. In some embodiments, when inverter 502a is selected, inverter 502a is configured to generate an inverted output signal (e.g., weight signal WB0). In some embodiments, when inverter 502a is deselected, inverter 502a is configured to have a high impedance state at the output terminal. In some embodiments, when inverter 502a is deselected, weight signal WB0 is logic 0.

[0175] In some embodiments, the inverter 502a is configured to receive the corresponding weight signal DIN0 in the weight signal group DIN and the corresponding inverted enable signal INV_ENB0 in the inverted enable signal group INV_ENB. In some embodiments, the inverter 502a is selected by the corresponding inverted enable signal INV_ENB0 in the inverted enable signal group INV_ENB.

[0176] In some embodiments, when selected, the inverter 502a is configured to generate a corresponding inverted weight signal WB0 in the inverted weight signal group WB in response to the corresponding weight signal DIN0 of the weight signal group DIN. In some embodiments, when the inverter 502a is selected, the corresponding data signal DO0 in the stored data signal group DO is equal to the corresponding inverted weight signal WB0 in the inverted weight signal group WB.

[0177] In some embodiments, when deselected, the inverter 502a is not configured to generate a corresponding inverted weight signal WB0 in the inverted weight signal group WB in response to the corresponding weight signal DIN0 of the weight signal group DIN. In some embodiments, when the inverter 502a is deselected, the corresponding data signal DO0 in the stored data signal group DO is equal to the corresponding inverted weight signal W0 in the weight signal group W generated by the inverter 506a.

[0178] Each path in the path group 522 is configured to receive a corresponding weight signal in the weight signal group DIN and a corresponding enable signal in the enable signal group INV_EN.

[0179] Each path in path group 522 is configured to generate a corresponding weight signal in weight signal group W in response to being selected. In some embodiments, unselected paths in path group 522 do not output or generate corresponding weight signals in weight signal group W.

[0180] Based on the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN N To select each path in the path group 522.

[0181] In some embodiments, path group 522 further includes inverter group 504 and inverter group 506 .

[0182] In some embodiments, inverter group 504 includes one or more of inverters 504a, 504b, ..., 504N. In some embodiments, inverter group 506 includes one or more of inverters 506a, 506b, ..., 506N.

[0183] Each path of the path group 522 includes a corresponding inverter 504 a , 504 b , . . . , 504N of the inverter group 504 and a corresponding inverter 506 a , 506 b , . . . , 506N of the inverter group 506 .

[0184] The inverters 504a, 504b, ..., 504N of the inverter group 504 are configured to respond to the corresponding weight signals DIN0, DIN1, ...DIN of the weight signal group DIN. N , generating corresponding inverted weight signals DINB0, DINB1, ...DINB of the inverted weight signal group DINB N .

[0185] In some embodiments, when selected, the inverters 506a, 506b, ..., 506N of the inverter group 506 are configured to respond to the corresponding inverted weight signals DINB0, DINB1, ...DINB of the inverted weight signal group DINB. N and the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN N , generating corresponding weight signals W0, W1, ...W of weight signal group W N .

[0186] In some embodiments, the order of the inverters 506a, 506b, ..., 506N of the inverter group 506 and the order of the corresponding inverters 504a, 504b, ..., 504N of the inverter group 504 are changed. For example, in some embodiments, the outputs of the corresponding inverters 506a, 506b, ..., 506N of the inverter group 506 are coupled to the corresponding inputs of the corresponding inverters 504a, 504b, ..., 504N of the inverter group 504.

[0187] For brevity, path 522a will be described, but the remaining paths in path group 522 are similar to path 522a. For brevity, inverters 504a and 506a will be described, but the remaining inverters in inverter groups 504 and 506 are similar to inverters 504a, 506a.

[0188] In some embodiments, the inverter 506a is enabled or selected by a logic low signal (logic 0). In some embodiments, when the enable signal INV_EN0 of the enable signal group INV_EN is a logic low signal (logic 0), the inverter 506a is enabled or selected.

[0189] In some embodiments, inverter 504a is coupled between circuit 404 and inverter 506a. In some embodiments, inverter 506a is coupled to inverter 504a and weight buffer circuit 114a.

[0190] Inverter 504a is configured to receive weight signal DIN0 in weight signal group DIN. Inverter 504a is configured to generate inverted weight signal DINB0 in inverted weight signal group DINB in ​​response to corresponding weight signal DIN0 in weight signal group DIN. Output terminal of inverter 504b is connected to input terminal of inverter 506a.

[0191] In some embodiments, inverter 506a is a tri-state inverter. In some embodiments, in response to the enable signal INV_EN0 in the enable signal group INV_EN, inverter 506a is selected or deselected. In some embodiments, when inverter 506a is selected, inverter 506a is configured to generate an output signal (e.g., weight signal W0). In some embodiments, when inverter 506a is deselected, inverter 506a is configured to have a high impedance state at the output terminal. In some embodiments, when inverter 506a is deselected, weight signal W0 is logic 0.

[0192] In some embodiments, the inverter 506a is configured to receive the corresponding inverted weight signal DINB0 of the weight signal group DIN and the corresponding enable signal INV_EN0 of the enable signal group INV_EN. In some embodiments, the inverter 506a is selected by the corresponding enable signal INV_EN0 in the enable signal group INV_EN.

[0193] In some embodiments, when selected, the inverter 506a is configured to generate a corresponding weight signal W0 in the weight signal group W0 in response to the corresponding inverted weight signal DINB0 of the inverted weight signal group DINB. In some embodiments, when the inverter 506a is selected, the corresponding data signal DO0 of the stored data signal group DO is equal to the corresponding weight signal W0 of the weight signal group W.

[0194] In some embodiments, when deselected, the inverter 506a is not configured to generate a corresponding weight signal W0 in the weight signal group W in response to the corresponding inverted weight signal DINB0 of the inverted weight signal group DINB. In some embodiments, when the inverter 506a is deselected, the corresponding data signal DO0 of the stored data signal group DO is equal to the corresponding inverted weight signal WB0 of the inverted weight signal group WB generated by the inverter 502a.

[0195] Other configurations or numbers of elements in write circuit 500A are within the scope of the present disclosure.

[0196] Figure 5B is a corresponding circuit diagram of a corresponding write circuit 500B according to some embodiments.

[0197] The write circuit 500B is Figure 4 The embodiments of the write circuit 406 are described above, and thus similar detailed description is omitted.

[0198] The write circuit 500B is Figure 5A The writing circuit 500A is a variation of the writing circuit 500A, and thus similar detailed description is omitted. Figure 5A Compared with the write circuit 500A, Figure 5B The inverter group 512 replaces the Figure 5A The inverter group 502, Figure 5B The inverter group 514 in the Figure 5A Inverter set 504, Figure 5B The inverter bank 516 shown replaces Figure 5A The inverter group 506 is thus omitted from similar detailed description.

[0199] and Figure 5A Compared with the write circuit 500A, Figure 5B The enable signal group INV_EN replaces Figure 5A The inverted enable signal group INV_ENB, and Figure 5B Another inverting enable signal group INV_ENB replaces Figure 5A The enable signal group INV_EN is used, so similar detailed description is omitted.

[0200] The write circuit 500B includes a path group 520 and a path group 522 .

[0201] In some embodiments, Figure 5B , the paths in path group 520 are selected by corresponding enable signals in enable signal group INV_EN. Similarly, in some embodiments, Figure 5B In the example, the paths in the path group 520 are deselected by the corresponding enable signals in the enable signal group INV_EN.

[0202] In some embodiments, Figure 5B , the paths in path group 522 are selected by the corresponding inverted enable signals in inverted enable signal group INV_ENB. Similarly, in some embodiments, Figure 5B , the paths in the path group 522 are deselected by the corresponding inverted enable signals in the inverted enable signal INV_ENB.

[0203] exist Figure 5B In the example, the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN are N To select each path in path group 520.

[0204] In some embodiments, the path group 520 further includes an inverter group 512 .

[0205] In some embodiments, inverter group 512 includes one or more of inverters 512a, 512b, ..., 512N. In some embodiments, inverters 512a, 512b, ..., 512N in inverter group 512 are similar to corresponding inverters 502a, 502b, ..., 502N in inverter group 502.

[0206] exist Figure 5B , each path of the path group 520 includes a corresponding inverter 512 a , 512 b , . . . , 512N of the inverter group 512 .

[0207] In some embodiments, when selected, the inverters 512a, 512b, ..., 512N of the inverter group 512 are configured to respond to the corresponding weight signals DIN0, DIN1, ...DIN of the weight signal group DIN. N and the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN N , generating corresponding inverted weight signals WB0, WB1, ...WB of the inverted weight signal group WB N .

[0208] For brevity, path 520a will be described, but the remaining paths in path group 520 are similar to path 520a. For brevity, inverter 512a will be described, but the remaining inverters in inverter group 512 are similar to inverter 512a.

[0209] In some embodiments, the inverter 512a is enabled or selected by a logic high signal (logic 1). In some embodiments, when the enable signal INV_EN0 of the enable signal group INV_EN is a logic high signal (logic 1), the inverter 512a is enabled or selected.

[0210] In some embodiments, inverter 512a is coupled to circuit 404 and weight buffer circuit 114a. In some embodiments, inverter 512a is a tri-state inverter. In some embodiments, in response to the enable signal INV_EN0 in the enable signal group INV_EN, inverter 512a is selected or deselected. In some embodiments, when inverter 512a is selected, inverter 512a is configured to generate an inverted output signal (e.g., weight signal WB0). In some embodiments, when inverter 512a is deselected, inverter 512a is configured to have a high impedance state at the output terminal. In some embodiments, when inverter 512a is deselected, weight signal WB0 is logic 0.

[0211] In some embodiments, the inverter 512a is configured to receive a corresponding weight signal DIN0 in the weight signal group DIN and a corresponding enable signal INV_EN0 in the enable signal group INV_EN. In some embodiments, the inverter 512a is selected by a corresponding enable signal INV_EN0 in the enable signal group INV_EN.

[0212] In some embodiments, when selected, the inverter 512a is configured to generate a corresponding inverted weight signal WB0 in the inverted weight signal group WB in response to the corresponding weight signal DIN0 of the weight signal group DIN. In some embodiments, when the inverter 512a is selected, the data signal DO0 corresponding to the stored data signal group DO is equal to the inverted weight signal WB0 corresponding to the inverted weight signal group WB.

[0213] In some embodiments, when deselected, the inverter 512a is not configured to generate a corresponding inverted weight signal WB0 in the inverted weight signal group WB in response to the corresponding weight signal DIN0 of the weight signal group DIN. In some embodiments, when the inverter 512a is deselected, the data signal DO0 corresponding to the stored data signal group DO is equal to the weight signal W0 corresponding to the weight signal group W generated by the inverter 516a.

[0214] exist Figure 5B In the embodiment, each path in the path group 522 is configured to receive a corresponding weight signal in the weight signal group DIN and a corresponding inverted enable signal in the inverted enable signal group INV_ENB.

[0215] exist Figure 5B In the embodiment, each path of the path group 522 is configured to generate a corresponding weight signal of the weight signal group W in response to being selected. In some embodiments, the unselected paths in the path group 522 do not output or generate corresponding weight signals in the weight signal group W.

[0216] exist Figure 5BIn the embodiment, the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB of the inverted enable signal group INV_ENB are used. N To select each path in path group 522.

[0217] In some embodiments, path group 522 further includes inverter group 514 and inverter group 516 .

[0218] In some embodiments, inverter group 514 includes one or more of inverters 514a, 514b, ..., 514N. In some embodiments, inverters 514a, 514b, ..., 514N of inverter group 514 are similar to corresponding inverters 504a, 504b, ..., 504N of inverter group 504.

[0219] In some embodiments, inverter group 516 includes one or more of inverters 516a, 516b, ..., 516N. In some embodiments, inverters 516a, 516b, ..., 516N of inverter group 516 are similar to corresponding inverters 506a, 506b, ..., 506N of inverter group 506.

[0220] exist Figure 5B , each path of the path group 522 includes a corresponding inverter 514a, 514b, ..., 514N of the inverter group 514 and a corresponding inverter 516a, 516b, ..., 516N of the inverter group 516.

[0221] The inverters 514a, 514b, ..., 514N of the inverter group 514 are configured to respond to the corresponding weight signals DIN0, DIN1, ...DIN of the weight signal group DIN. N , generating corresponding inverted weight signals DINB0, DINB1, ...DINB of the inverted weight signal group DINB N .

[0222] In some embodiments, when selected, the inverters 516a, 516b, ..., 516N of the inverter group 516 are configured to respond to the corresponding inverted weight signals DINB0, DINB1, ...DINB of the inverted weight signal group DINB. N and the corresponding inverted enable signals INV_ENB0, INV_ENB1, ..., INV_ENB of the inverted enable signal group INV_ENB N , generating corresponding weight signals W0, W1, ...W of weight signal group W N .

[0223] In some embodiments, the order of the inverters 516a, 516b, ..., 516N of the inverter group 516 and the order of the corresponding inverters 514a, 514b, ..., 514N of the inverter group 514 are changed. For example, in some embodiments, the outputs of the corresponding inverters 516a, 516b, ..., 516N of the inverter group 516 are coupled to the corresponding inputs of the corresponding inverters 514a, 514b, ..., 514N of the inverter group 514.

[0224] For brevity, path 522a will be described, but the remaining paths in path group 522 are similar to path 522a. For brevity, inverters 514a and 516a will be described, but the remaining inverters in inverter groups 514 and 516 are similar to inverters 514a and 516a.

[0225] In some embodiments, the inverter 516a is enabled or selected by a logic high signal (logic 1). In some embodiments, when the inversion enable signal INV_ENB0 in the inversion enable signal group INV_ENB is a logic high signal (logic 1), the inverter 516a is enabled or selected.

[0226] In some embodiments, inverter 514a is coupled between circuit 404 and inverter 516a. In some embodiments, inverter 516a is coupled to inverter 514a and weight buffer circuit 114a.

[0227] Inverter 514a is configured to receive weight signal DIN0 in weight signal group DIN. Inverter 514a is configured to generate inverted weight signal DINB0 in inverted weight signal group DINB in ​​response to corresponding weight signal DIN0 in weight signal group DIN. Output terminal of inverter 514b is connected to input terminal of inverter 516a.

[0228] In some embodiments, inverter 516a is a tri-state inverter. In some embodiments, in response to the inverting enable signal INV_ENB0 in the inverting enable signal group INV_ENB, inverter 516a is selected or deselected. In some embodiments, when inverter 516a is selected, inverter 516a is configured to generate an output signal (e.g., weight signal W0). In some embodiments, when inverter 516a is deselected, inverter 516a is configured to have a high impedance state at the output terminal. In some embodiments, when inverter 516a is deselected, weight signal W0 is logic 0.

[0229] In some embodiments, the inverter 516a is configured to receive the corresponding inverted weight signal DINB0 of the weight signal group DIN and the corresponding inverted enable signal INV_ENB0 of the inverted enable signal group INV_ENB. In some embodiments, the inverter 516a is selected by the corresponding inverted enable signal INV_ENB0 in the inverted enable signal group INV_ENB.

[0230] In some embodiments, when selected, the inverter 516a is configured to generate a corresponding weight signal W0 in the weight signal group W in response to the corresponding inverted weight signal DINB0 of the inverted weight signal group DINB. In some embodiments, when the inverter 516a is selected, the corresponding data signal DO0 of the stored data signal group DO is equal to the corresponding weight signal W0 of the weight signal group W.

[0231] In some embodiments, when deselected, the inverter 516a is not configured to generate a corresponding weight signal W0 in the weight signal group W in response to the corresponding inverted weight signal DINB0 of the inverted weight signal group DINB. In some embodiments, when the inverter 516a is deselected, the corresponding data signal DO0 of the stored data signal group DO is equal to the corresponding inverted weight signal WB0 of the inverted weight signal group WB generated by the inverter 512a.

[0232] Other configurations or numbers of elements in write circuit 500B are within the scope of the present disclosure.

[0233] Figure 6 is a circuit diagram of circuit 600 according to some embodiments.

[0234] Circuit 600 is Figure 4 The embodiments of the circuit 404 are described above, and thus similar detailed description is omitted.

[0235] The circuit 600 is configured to generate at least an inverted enable signal group INV_ENB in ​​response to at least an enable signal group INV_EN. In some embodiments, the inverted enable signal group INV_ENB is inverted to the enable signal group INV_EN.

[0236] In some embodiments, the inverted enable signal group INV_ENB may be used by at least one of the memory circuit 400 , the write circuit 406 , the write circuit 500A, or the write circuit 500B.

[0237] The circuit 600 includes an inverter bank 602 .

[0238] In some embodiments, inverter group 602 includes one or more of inverters 602a, 602b, ..., 602N.

[0239] The inverters 602a, 602b, ..., 602N of the inverter group 602 are configured to respond to the corresponding enable signals INV_EN0, INV_EN1, ... INV_EN of the enable signal group INV_EN. N , generating corresponding inverted enable signals INV_ENB0, INV_ENB1, ... INV_ENB of the inverted enable signal group INV_ENB N .

[0240] Each inverter 602 a , 602 b , . . . , 602N in the inverter group 602 is coupled between the write circuit 402 and the circuit 406 .

[0241] In some embodiments, the inverters 602 a , 602 b , . . . , 602N of the inverter group 602 are coupled between the write circuit 402 and the corresponding inverters 502 a , 502 b , . . . , 502N of the inverter group 502 .

[0242] In some embodiments, the inverters 602 a , 602 b , . . . , 602N of the inverter group 602 are coupled between the write circuit 402 and the corresponding inverters 516 a , 516 b , . . . , 516N of the inverter group 516 .

[0243] Other configurations or numbers of elements in circuit 600 are within the scope of the present disclosure.

[0244] Figure 7A-7B is a respective circuit diagram of respective memory circuits 700A-700B according to some embodiments.

[0245] The memory circuit 700A is Figure 1 Memory macro 110 or Figure 2 The present invention relates to an embodiment of the memory macro 204, and thus similar detailed description is omitted.

[0246] The memory circuit 700A is Figure 1 The present invention relates to an embodiment of the memory array 112, and thus similar detailed description is omitted.

[0247] In some embodiments, the memory circuit 700A depicts a non-limiting example in which the inverted data 714 stored in a column of memory cells 704 consumes less energy than the data 712 stored in a column of memory cells 702, and thus similar detailed description is omitted.

[0248] Memory circuit 700A includes a column of memory cells 702 and a column of memory cells 704 .

[0249] In some embodiments, at least one of the memory cell columns 702 or the memory cell columns 704 corresponds to Figure 1 The memory array 112 or Figure 2 The memory macro 204 is a column of memory cells, and thus similar detailed description is omitted.

[0250] The column of memory cells 702 includes memory cells 702a, 702b, 702c, and 702d. In some embodiments, each of the memory cells 702a, 702b, 702c, and 702d is a nonvolatile memory cell. Each of the memory cells 702a, 702b, 702c, and 702d is coupled together by a bit line (not labeled). The bit line has a current I BL-A .

[0251] Each of memory cells 702a, 702b, and 702c stores a logic 1. Memory cell 702d stores a logic 0. In some embodiments, a logic 1 consumes more energy than a logic 0, so the current I BL-A The peak value of is greater than that of fewer memory cells storing logical 1s (eg, column of memory cells 704).

[0252] In some embodiments, since the number of logic 1s is greater than the number of logic 0s in column 702 of memory cells, if the data stored in column 702 of memory cells is inverted (e.g., as shown in column 704 of memory cells), column 702 of memory cells will consume less energy because logic 1s consume more energy than logic 0s.

[0253] The memory cell 704 column includes memory cells 704a, 704b, 704c, and 704d. In some embodiments, each of the memory cells 704a, 704b, 704c, and 704d is a nonvolatile memory cell. Each of the memory cells 704a, 704b, 704c, and 704d is coupled together by a bit line (not labeled). The bit line has a current I BL-B .

[0254] Each of memory cells 704a, 704b, and 704c stores a logic 0. Memory cell 704d stores a logic 1.

[0255] The data 714 stored in the memory cell column 704 is opposite to the data 712 stored in the memory cell column 702. In some embodiments, the number of logical 0s in the memory cell column 704 is greater than the number of logical 1s in the memory cell column 704, so the memory cell column 704 consumes less energy than the memory cell column 702, and thus the current I BL-B The peak value is less than the current I BL-A peak value.

[0256] Other configurations or numbers of elements in memory circuit 700A are within the scope of the present disclosure.

[0257] The memory circuit 700B is Fig. 7A The memory circuit 700A is a variation of the memory circuit 700A, and thus similar detailed description is omitted. Fig. 7A Compared to the memory circuit 700A, the memory cell columns 706 and 708 are SRAM cells, and thus similar detailed description is omitted.

[0258] The memory circuit 700B is Figure 1 Memory macro 110 or Figure 2 The present invention relates to an embodiment of the memory macro 204, and thus similar detailed description is omitted.

[0259] The memory circuit 700B is Figure 1 The present invention relates to an embodiment of the memory array 112, and thus similar detailed description is omitted.

[0260] In some embodiments, the memory circuit 700B depicts a non-limiting example in which the inverted data 718 stored in a column of memory cells 708 consumes less energy than the data 716 stored in a column of memory cells 706, and thus similar detailed description is omitted.

[0261] Memory circuit 700B includes a column of memory cells 706 and a column of memory cells 708 .

[0262] In some embodiments, at least one of memory cell columns 706 or memory cell columns 708 corresponds to Figure 1 The memory array 112 or Figure 2 The memory macro 204 is a column of memory cells, and thus similar detailed description is omitted.

[0263] Memory cell column 706 includes memory cells 706a, 706b, 706c, and 706d. In some embodiments, each of memory cells 706a, 706b, 706c, and 706d is an SRAM memory cell. Each of memory cells 706a, 706b, 706c, and 706d is coupled together by a bit line (not labeled). The bit line has a current I BL-C .

[0264] Each of memory cells 706a, 706b, and 706c stores a logic 1. Memory cell 706d stores a logic 0. In some embodiments, a logic 1 consumes more energy than a logic 0, so the current I BL-C The peak value of is greater than that of fewer memory cells storing logical 1s (eg, column of memory cells 708).

[0265] In some embodiments, since the number of logic 1s in column 706 of memory cells is greater than the number of logic 0s, if the data stored in column 706 is inverted (e.g., as shown in column 708 of memory cells), column 706 of memory cells will consume less energy because a logic 1 consumes more energy than a logic 0.

[0266] Memory cell column 708 includes memory cells 708a, 708b, 708c, and 708d. In some embodiments, each of memory cells 708a, 708b, 708c, and 708d is an SRAM memory cell. Each memory cell 708a, 708b, 708c, and 708d is coupled together by a bit line (not labeled). The bit line has a current I BL-D .

[0267] Each of memory cells 708a, 708b, and 708c stores a logic 0. Memory cell 708d stores a logic 1.

[0268] The data 718 stored in the memory cell column 708 is the opposite of the data 716 stored in the memory cell column 706. In some embodiments, the number of logical 0s in the memory cell column 708 is greater than the number of logical 1s in the memory cell column 708, so the memory cell column 708 consumes less energy than the memory cell column 706, so the current I BL-D The peak value is less than the current I BL-A peak value.

[0269] In some embodiments, the data 714 stored in the memory cell 704 column or the data 718 stored in the memory cell 708 column is the storage data of the storage data DO′ group.

[0270] Other configurations or numbers of elements in memory circuit 700B are within the scope of the present disclosure.

[0271] Figure 8 is a circuit diagram of a write circuit 800 according to some embodiments.

[0272] The write circuit 800 is Figure 4 This is an embodiment of the write circuit 402, and thus similar detailed description is omitted.

[0273] The write circuit 800 is configured to receive at least a count signal ACT_XIN / 2 or a storage data group DO. In some embodiments, the count signal ACT_XIN is Figure 3 In some embodiments, the count signal ACT_XIN / 2 is received from a divider circuit (not shown), and the divider circuit (not shown) is coupled to Figure 3 Counter 306 in.

[0274] In some embodiments, the storage data set DO is received from the write circuit 406. In some embodiments, the storage data set DO includes a weight signal set W or an inverted weight signal set WB.

[0275] The write circuit 800 is configured to generate at least an enable signal group INV_EN in response to at least a storage data group DO and a count signal ACT_XIN / 2. In some embodiments, the count signal ACT_XIN / 2 is equal to Figure 3 The counter 306 in generates the counting signal ACT_XIN / 2.

[0276] In some embodiments, the enable signal group INV_EN may be used by at least one of the memory circuit 400 , the circuit 404 , the write circuit 406 , the read circuit 408 , the write circuit 500A, the write circuit 500 k , or the circuit 600 .

[0277] The write circuit 800 includes an accumulator 802 and a comparator 804 .

[0278] An input terminal of the accumulator 802 is coupled to the write circuit 406. An input terminal of the accumulator 802 is coupled to a first input terminal of the comparator 804.

[0279] In some embodiments, each row and each column data entry of the weight signal group W or the inverted weight signal group WB of the weight write circuit 406 is coupled to the accumulator 802 .

[0280] The accumulator 802 is configured to generate the accumulation signal group ACC in response to the storage data group DO. In some embodiments, the accumulator 802 is configured to generate the accumulation signal group ACC in response to the weight signal group W or the inverted weight signal group WB.

[0281] In some embodiments, the accumulation signal group ACC includes one or more of the accumulation signals ACCa, ACCb, . . . , ACCN.

[0282] In some embodiments, the accumulator 802 is configured to determine the number of rows of a single column in the storage data group DO having a value equal to a logic high (e.g., logic 1). In some embodiments, each accumulation signal ACCa, ACCb, ..., ACCN of the accumulation signal group ACC is the number of rows of the corresponding column in the storage data group DO whose value is equal to a logic high (e.g., logic 1).

[0283] Other variations of the accumulator 802 are within the scope of the present disclosure. In some embodiments, the accumulator 802 is configured to determine the number of rows of a single column in the storage data set DO having a value equal to a logic low (e.g., a logic 0). In some embodiments, each accumulation signal ACCa, ACCb, ..., ACCN of the accumulation signal set ACC is the number of rows of the corresponding column in the storage data set DO whose value is equal to a logic low (e.g., a logic 0).

[0284] In some embodiments, the accumulator 802 is configured to accumulate each value of a column of storage data in the storage data group DO. In some embodiments, the accumulator 802 is configured to add each value of a column of storage data in the storage data group DO. For example, in some embodiments, for column 1 of storage data in the storage data group DO, if the number of values ​​equal to logic high (e.g., logic 1) is 7, the accumulator 802 is configured to determine that the accumulation signal ACC0 of the accumulation signal group ACC is equal to 7.

[0285] In some embodiments, the accumulator 802 includes an adder that can be used to perform addition operations or other arithmetic / logical operations. In some embodiments, the accumulator 802 also includes a register or memory location that can be used to store the results of the addition operations or other arithmetic / logical operations.

[0286] Comparator 804 is connected to accumulator 802 and the source of counter signal ACT_XIN / 2. In some embodiments, the source of counter signal ACT_XIN / 2 is Figure 3 The counter 306 in is coupled to a divider (not shown).

[0287] The comparator 804 is configured to receive the accumulation signal group ACC and the counter signal ACT_XIN / 2. The comparator 804 is configured to compare the accumulation signal group ACC and the counter signal ACT_XIN / 2. The comparator 804 is configured to generate the enable signal group INV_EN based on the comparison of the accumulation signal group ACC and the counter signal ACT_XIN / 2.

[0288] In some embodiments, the comparator 804 is configured to generate the enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN based on the comparison of the corresponding accumulation signals ACCa, ACCb, ..., ACCN of the accumulation signal group ACC with the counter signal ACT_XIN / 2. N .

[0289] For example, according to some embodiments, if the number of rows of a single column having a value equal to a logic high (e.g., logic 1) in the storage data group DO is greater than 1 / 2 of the number of active word line signals XIN (e.g., control signal ACT_XIN / 2) received from the word line driver group 302, the enable signal group INV_EN is logically high (e.g., logic 1). For example, according to some embodiments, if the number of rows of column 1 having a value equal to a logic high (e.g., logic 1) in the storage data D0 of the storage data group DO is greater than 1 / 2 of the number of active word line signals XIN received from the word line driver group 302 (e.g., control signal ACT_XIN / 2), the enable signal INV_EN0 of the enable signal group INV_EN is logically high (e.g., logic 1).

[0290] For example, according to some embodiments, if the number of rows of a single column having a value equal to a logic high (e.g., logic 1) in the storage data group DO is less than 1 / 2 of the number of active word line signals XIN received from the word line driver group 302 (e.g., control signal ACT_XIN / 2), the enable signal group INV_EN is logically low (e.g., logic 0). For example, according to some embodiments, if the number of rows of column 1 having a value equal to a logic high (e.g., logic 1) in the storage data D0 of the storage data group DO is less than 1 / 2 of the number of active word line signals XIN received from the word line driver group 302 (e.g., control signal ACT_XIN / 2), the enable signal INV_EN0 of the enable signal group INV_EN is logically low (e.g., logic 0).

[0291] Other variations of the comparator 804 are within the scope of the present disclosure. For example, according to some embodiments, if the number of rows of a single column having a value equal to a logic high (e.g., logic 1) in the storage data group DO is greater than 1 / 2 of the number of active word line signals XIN received from the word line driver group 302 (e.g., control signal ACT_XIN / 2), the enable signal group INV_EN is logically low (e.g., logic 0). For example, according to some embodiments, if the number of rows of column 1 having a value equal to a logic high (e.g., logic 1) in the storage data D0 of the storage data group DO is greater than 1 / 2 of the number of active word line signals XIN received from the word line driver group 302 (e.g., control signal ACT_XIN / 2), the enable signal INV_EN0 of the enable signal group INV_EN is logically low (e.g., logic 0).

[0292] For example, according to some embodiments, if the number of rows of a single column having a value equal to a logic high (e.g., logic 1) in the storage data group DO is less than 1 / 2 of the number of active word line signals XIN received from the word line driver group 302 (e.g., control signal ACT_XIN / 2), the enable signal group INV_EN is logically high (e.g., logic 1). For example, according to some embodiments, if the number of rows of column 1 having a value equal to a logic high (e.g., logic 1) in the storage data D0 of the storage data group DO is less than 1 / 2 of the number of active word line signals XIN received from the word line driver group 302 (e.g., control signal ACT_XIN / 2), the enable signal INV_EN0 of the enable signal group INV_EN is logically high (e.g., logic 1).

[0293] In some embodiments, the enable signal group INV_EN corresponds to a digital signal having a binary value.

[0294] Other configurations or numbers of elements in write circuit 800 are within the scope of the present disclosure.

[0295] Fig. 9 is a circuit diagram of a read circuit 900 according to some embodiments.

[0296] The read circuit 900 is Figure 4 The read circuit 408 is an embodiment of the present invention, and thus similar detailed description is omitted.

[0297] Read circuit 900 is coupled to write circuit 402 and memory macro 204 .

[0298] The read circuit 900 is configured to receive at least an enable signal group INV_EN, an output signal group OU or a count signal ACT_XIN. In some embodiments, the read circuit 900 is configured to receive at least an enable signal group INV_EN, a count signal ACT_XIN and at least one of an output signal OUT or an output signal OUTB.

[0299] In some embodiments, the enable signal group INV_EN is received from the write circuit 800. In some embodiments, the count signal ACT_XIN is received from the counter 306. In some embodiments, during a read operation of the memory macro 204, the output signal group OU is read from the memory macro 204 in response to at least one of the enable signal group INV_EN or the count signal ACT_XIN.

[0300] The read circuit 900 is configured to output at least the output signal group D_OUT in response to at least the enable signal group INV_EN, the output signal group OU or the count signal ACT_XIN. In some embodiments, the read circuit 900 is configured to generate at least the output signal group D_OUT in response to at least the enable signal group INV_EN, the output signal group OU or the count signal ACT_XIN. In some embodiments, if one or more weight signals of the weight signal group W are not inverted by the write circuit 406, the output signal group D_OUT corresponds to the output signal group generated by the CIM macro (e.g., similar to the memory macro 204).

[0301] The read circuit 900 includes an analog-to-digital converter group (ADC) 902 and a subtractor group 904 .

[0302] The ADC group 902 is configured to convert analog signals into corresponding digital signals. In some embodiments, the ADC group 902 is configured to generate a digital signal group MAC_tmp in response to the output signal group OU.

[0303] In some embodiments, the output signal group OU is a bit line current value group I BL In some embodiments, the bit line current value group I BL is the corresponding analog signal group.

[0304] In some embodiments, the bit line current value set IBL is Figure 7B The current I BL-B At least one of the bit line current value group I is omitted, and thus similar detailed description is omitted. BL One or more bit line current values ​​I BL0 ,I BL1 ,…,I BLN yes Figure 7B The current I BL-B , and thus similar detailed description is omitted.

[0305] In some embodiments, the bit line current value group I BL yes Figure 7B The current I BL-D At least one of the bit line current value group I is omitted, and thus similar detailed description is omitted. BL One or more bit line current values ​​I BL0 ,I BL1 ,…,I BLN yes Figure 7B The current I BL-D , and thus similar detailed description is omitted.

[0306] In some embodiments, the ADC group 902 includes one or more of ADCs 902a, 902b, ..., 902N. In some embodiments, the digital signal group MAC_tmp includes digital signals MAC_tmp0, MAC_tmp1, ..., MAC_tmp N In some embodiments, the digital signal group MAC_tmp is an intermediate MAC signal group.

[0307] In some embodiments, each ADC 902a, 902b, ..., 902N of the ADC group 902 is configured to respond to a corresponding output signal OU0, OU1, ..., OU N , generating corresponding digital signals MAC_tmp0, MAC_tmp1, ..., MAC_tmp of the digital signal group MAC_tmp N .

[0308] In some embodiments, each ADC 902a, 902b, ..., 902N in ADC group 902 is coupled to a corresponding column of memory cells in memory array 112. In some embodiments, each ADC 902a, 902b, ..., 902N in ADC group 902 is coupled to a corresponding column of memory cells in memory macro 204.

[0309] In some embodiments, each ADC 902 a , 902 b , . . . , 902N in the ADC group 902 is coupled between a corresponding memory cell column in the memory macro 204 and a corresponding subtractor 904 a , 904 b , . . . , 904N in the subtractor group 904 .

[0310] The subtractor group 904 is configured to generate an output signal group D_OUT in response to at least the digital signal group MAC_tmp, the enable signal group INV_EN, or the counting signal ACT_XIN.

[0311] In some embodiments, subtractor group 904 includes one or more of subtractors 904a, 904b, ..., 904N.

[0312] In some embodiments, each subtractor 904a, 904b, ..., 904N of the subtractor group 904 is configured to respond to at least a corresponding digital signal MAC_tmp0, MAC_tmp1, ..., MAC_tmp N , the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN Nor counting signal ACT_XIN, generating corresponding output signals D_OUT0, D_OUT1, ..., D_OUT of the output signal group D_OUT N .

[0313] Other variations of the group of subtractors 904 are within the scope of the present disclosure. In some embodiments, each subtractor 904a, 904b, ..., 904N of the group of subtractors 904 is configured to respond to at least a corresponding digital signal MAC_tmp0, MAC_tmp1, ..., MAC_tmp of the digital signal group MAC_tmp. N , the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN N or the corresponding counting signals ACT_XIN1, ACT_XIN2, ..., ACT_XIN of the counting signals ACT_XIN of the corresponding memory cell columns in the memory macro 204. N , to generate the corresponding output signals D_OUT0, D_OUT1, ..., D_OUT of the output signal group D_OUT N .

[0314] In some embodiments, the subtractors 904a, 904b, ..., 904N of the subtractor group 904 are coupled to corresponding columns of memory cells in the memory array 112 through corresponding ADCs 902a, 902b, ..., 902N of the ADC group 902. In some embodiments, the subtractors 904a, 904b, ..., 904N of the subtractor group 904 are coupled to corresponding columns of memory cells in the memory macro 204 through corresponding ADCs 902a, 902b, ..., 902N of the ADC group 902.

[0315] In some embodiments, each ADC 902a, 902b, ..., 902N in the ADC group 902 and each subtractor 904a, 904b, ..., 904N in the subtractor group 904 are coupled to a corresponding column of memory cells in the memory cell array.

[0316] In some embodiments, the output signals D_OUT0, D_OUT1, . . . , D_OUT1 of the output signal group D_OUT N At least one of is set to logic low (eg, logic 0) or logic high (eg, logic 1) by a corresponding subtractor 904a, 904b, . . . , 904N of the subtractor group 904.

[0317] In some embodiments, if the corresponding enable signals INV_EN0, INV_EN1, . . . , INV_EN1 of the enable signal group INV_EN are Nis equal to a logic high signal (eg, logic 1), then the corresponding output signals D_OUT0, D_OUT1, . . . , D_OUT N The corresponding subtractors 904a, 904b, ..., 904N of the subtractor group 904 are determined according to Formula 1 (as shown below). Formulas 1 and 2 are written with reference to the output signal group D_OUT and the output signal group MAC_TMP, but are applicable to each corresponding output signal D_OUT0, D_OUT1, ..., D_OUT N and each corresponding digital signal MAC_tmp0, MAC_tmp1, ..., MAC_tmp N . (as described in the example below).

[0318] D_OUT=ACT_XIN–MAC_TMP(1)

[0319] In some embodiments, if the corresponding enable signals INV_EN0, INV_EN1, . . . , INV_EN1 of the enable signal group INV_EN are N is equal to a logic low signal (eg, logic 0), then the corresponding output signals D_OUT0, D_OUT1, . . . , D_OUT N The corresponding subtractors 904a, 904b, ..., 904N of the subtractor group 904 are determined according to Formula 2 (as shown below).

[0320] D_OUT=MAC_TMP(2)

[0321] For example, in some embodiments, if the enable signal INV_EN0 is equal to a logic high signal (e.g., logic 1), the subtractor 904a determines the output signal D_OUT0 according to Formula 1 (as shown below). In this non-limiting example, if the count signal ACT_XIN is equal to 7 and the digital signal MAC_tmp0 is equal to 6, then applying Formula 1 results in the output signal D_OUT0 being equal to 1.

[0322] For example, in some embodiments, if the enable signal INV_EN0 is equal to a logic low signal (e.g., logic 0), the subtractor 904a determines the output signal D_OUT0 according to Formula 1 (as shown below). In this non-limiting example, if the count signal ACT_XIN is equal to 7 and the digital signal MAC_tmp0 is equal to 6, applying Formula 1 results in the output signal D_OUT0 being equal to 6.

[0323] In some embodiments, each corresponding enable signal INV_EN0, INV_EN1, . . . , INV_EN1 of the enable signal group INV_EN Nis a corresponding enable signal that can be used to enable or disable the corresponding subtractor 904a, 904b, ..., 904N of the subtractor group 904. In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN N is a logic high signal (eg, logic 1), the subtractors 904a, 904b, ..., 904N of the subtractor group 904 are enabled. In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN are enabled, N When φ is a logic low signal (eg, logic 0), the subtractors 904a, 904b, ..., 904N of the subtractor group 904 are disabled.

[0324] In some embodiments, if the subtractors 904a, 904b, ..., 904N in the subtractor group 904 are enabled, the corresponding subtractors 904a, 904b, ..., 904N in the subtractor group 904 will perform a subtraction operation according to Formula 1 to determine the corresponding output signals D_OUT0, D_OUT1, ..., D_OUT in the output signal D_OUT group. N .

[0325] In some embodiments, if the subtractors 904a, 904b, ..., 904N in the subtractor group 904 are disabled, the corresponding subtractors 904a, 904b, ..., 904N in the subtractor group 904 will determine the corresponding output signals D_OUT0, D_OUT1, ..., D_OUT in the output signal D_OUT group according to Formula 2. N In these embodiments, the corresponding subtractors 904a, 904b, ..., 904N of the subtractor group 904 will pass the corresponding input signals (eg, the corresponding digital signals MAC_tmp0, MAC_tmp1, ..., MAC_tmp of the digital signal group MAC_tmp). N ) as the corresponding output signals D_OUT0, D_OUT1, ..., D_OUT N .

[0326] Other variations of the subtractor group 904 are within the scope of the present disclosure. In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN are enabled, N When is a logic low signal (eg, logic 0), the subtractors 904a, 904b, ..., 904N of the subtractor group 904 are enabled. In some embodiments, when the corresponding enable signals INV_EN0, INV_EN1, ..., INV_EN of the enable signal group INV_EN are enabled, NWhen is a logic high signal (e.g., logic 1), the subtractors 904a, 904b, ..., 904N of the subtractor group 904 are disabled. In some embodiments, when disabled, Formula 1 can be used by the corresponding subtractors 904a, 904b, ..., 904N of the subtractor group 904. In some embodiments, when enabled, Formula 2 can be used by the corresponding subtractors 904a, 904b, ..., 904N of the subtractor group 904.

[0327] Further operation of the read circuit 900 is performed in the corresponding Figure 10A-10B The waveforms 1000A-1000B are further described.

[0328] Other configurations or numbers of elements in read circuit 900 are within the scope of the present disclosure.

[0329] Figure 10A-10B are corresponding graphs of corresponding waveforms 1000A-1000B according to some embodiments.

[0330] In some embodiments, waveform 1000A is Figure 5A The operation example of the write circuit 500A is described above, and thus similar detailed description is omitted.

[0331] In some embodiments, waveform 1000B is Fig. 9 This is an example of the operation of the read circuit 900, and thus similar detailed description is omitted.

[0332] In some embodiments, from Figure 10A-10B Starting from time T1-T3, the address signal ADDR corresponds to the address A1 of the memory macro 204, and Figure 10A-10B Starting from time T3-T6, the address information ADDR corresponds to address A2 in the memory macro 204.

[0333] In some embodiments, the bit line signals BL0, BL1, . . . BL N is at least Figure 5A-Figure 5B The corresponding storage data signals DO0, DO1, ..., DO N , and thus similar detailed description is omitted.

[0334] In some embodiments, waveforms 1000A- 100B are described for column 0 and column N of memory macro 204 for simplicity, but are applicable to every column of memory cells in memory macro 204 .

[0335] At time T0, the clock signal CLK of the memory macro 204 is equal to logic 0, the address signal ADDR of the address A1 of the memory macro 204 is equal to logic 0, the address signal DDR of the address A2 of the memory macro 204 is equal to logic 1, and the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is equal to logic 0. The corresponding weight signal DIN0 is equal to logic zero, the corresponding bit line signal BL0 is equal to logic 1, the enable signal INV_ENN of the corresponding column N of the memory macro 204 is equal to logic 1, and the corresponding weight signal DIN N Equal to logic 0, the corresponding bit line signal BL N Equal to logical 0.

[0336] At time T1, the clock signal CLK of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A1 of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A2 of the memory macro 204 is converted to logic 0, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is converted to logic 1, the corresponding weight signal DIN0 is converted to logic 1, the corresponding bit line signal BL0 is converted to logic 0, and the enable signal INV_EN0 of the corresponding column N of the memory macro 204 is converted to logic 1. N Converted to logic 0, the corresponding weight signal DIN N Converted to logic 1, and the corresponding bit line signal BL N Converted to logic 1.

[0337] In response to the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 transitioning to logic 1, the inverter 506a is turned off and the inverter 502a is turned on (because the inverted enable signal INV_ENB0 transitions to logic 0 ( Fig. 10A In response to the inverter 502a being turned on, the inverter 502a inverts the weight signal DIN0 (which is changing to logic 1), thereby changing the corresponding bit line signal BL0 to logic 0.

[0338] In response to the enable signal INV_EN of the corresponding column N of the memory macro 204 N changes to logic 0, turning on inverter 506a and turning off inverter 502a (because the inverted enable signal INV_ENB N Transformed to logic 1 ( Fig. 10A In response to the conduction of the inverter 506a, the inverter 506a is made to invert the weight signal DINB which is being converted to logic 0. N ( Fig. 10A DIN is inverted by inverter 504a, thereby converting the corresponding bit line signal BL0 to logic 1. In some embodiments, since inverter 504a inverts the weight signal DIN NInverting, thus inverting the weight signal DINB N ( Fig. 10A (not shown) in response to the weight signal DIN N A transition to a logic 1 and a transition to a logic 0.

[0339] At time T2, the clock signal CLK of the memory macro 204 is equal to logic 1, the address signal ADDR of the address A1 of the memory macro 204 is equal to logic 1, the address signal ADD of the address A2 of the memory macro 204 is equal to logic 0, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is equal to logic 1, the corresponding weight signal DIN0 is equal to logic 1, the corresponding bit line signal BL0 is equal to logic 0, and the enable signal INV_EN0 of the corresponding column N of the memory macro 204 is equal to logic 1. N Equal to logic 0, the corresponding weight signal DIN N Equal to logic 1, the corresponding bit line signal BL N Equal to logical 1.

[0340] In response to the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 being logic 1, the inverter 506a is turned off and the inverter 502a is turned on (because the inverted enable signal INV_ENB0 is logic 0 ( Fig. 10A In response to the inverter 502a being turned on, the inverter 502a inverts the weight signal DIN0 (which is logic 1), thereby making the corresponding bit line signal BL0 logic 0.

[0341] In response to the enable signal INV_EN of the corresponding column N of the memory macro 204 N is logic 0, turning on the inverter 506a and turning off the inverter 502a (because the inverted enable signal INV_ENB N is logic 1 ( Fig. 10A In response to the conduction of the inverter 506a, the inverter 506a inverts the weight signal DINB. N ( Fig. 10A DIN is inverted, so that the corresponding bit line signal BL0 is logic 1. In some embodiments, because the inverter 504a is N Inverting, in response to the weight signal DIN N For logic 1, the inverted weight signal DINB N ( Fig. 10A ) is logic 0.

[0342] At time T3, the clock signal CLK of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A1 of the memory macro 204 is converted to logic 0, the address signal ADD of the address A2 of the memory macro 204 is converted to logic 1, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is converted to logic 0, the corresponding weight signal DIN0 is converted to logic 0, the corresponding bit line signal BL0 is converted to logic 1, and the enable signal INV_EN0 of the corresponding column N of the memory macro 204 is converted to logic 0. N Converted to logic 1, the corresponding weight signal DIN N Converts to logic 0, and the corresponding bit line signal BL N Converts to logic 0.

[0343] In response to the enable signal INV_EN0 of the corresponding column N of the memory macro 204 turning to logic 0, the inverter 506a is turned on and the inverter 502a is turned off (because the inverted enable signal INV_ENB0 turns to logic 1 ( Fig. 10A In response to the conduction of the inverter 506a, the inverter 506a is made to respond to the inverted weight signal DINB0 ( Fig. 10A (not shown) is inverted, thereby converting the corresponding bit line signal BL0 to logic 0. In some embodiments, since the inverter 504a inverts the weight signal DIN0, the inverted weight signal DINB0 ( Fig. 10A ) changes to logic 1 in response to the transition of the weight signal DIN0 to logic 0.

[0344] In response to the enable signal INV_EN of the corresponding column N of the memory macro 204 N changes to logic 1, turning off inverter 506a and turning on inverter 502a (because the inverted enable signal INV_ENB N changes to logic 0 ( Fig. 10A In response to the conduction of the inverter 502a, the inverter 502a is made to respond to the weight signal DIN. N (which is transitioning to logic 0) is inverted, thereby causing the corresponding bit line signal BL N Transformed to logic 1.

[0345] At time T4, the clock signal CLK of the memory macro 204 is equal to logic 1, the address signal ADDR of the address A1 of the memory macro 204 is equal to logic 0, the address signal ADDR of the address A2 of the memory macro 204 is equal to logic 1, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is equal to logic 0, the corresponding weight signal DIN0 is equal to logic 0, the corresponding bit line signal BL0 is equal to logic 1, the enable signal INV_ENN of the corresponding column N of the memory macro 204 is equal to logic 1, and the corresponding weight signal DIN N Equal to logic 0, the corresponding bit line signal BL N Equal to logical 0.

[0346] In response to the enable signal INV_EN0 of the corresponding column N of the memory macro 204 being logic 0, the inverter 506a is turned on and the inverter 502a is turned off (because the inverted enable signal INV_ENB0 is logic 1 ( Fig. 10A In response to the conduction of the inverter 506a, the inverter 506a inverts the weight signal DINB0 ( Fig. 10A (not shown) is inverted to logic 1, thereby making the corresponding bit line signal BL0 logic 0. In some embodiments, because the inverter 504a inverts the weight signal DIN0, in response to the weight signal DIN0 being logic 0, the inverted weight signal DINB0 ( Fig. 10A ) is logic 1.

[0347] In response to the enable signal INV_EN of the corresponding column N of the memory macro 204 N is logic 1, turning off the inverter 506a and turning on the inverter 502a (because the inverting enable signal INV_ENB N is logic 0 ( Fig. 10A In response to the conduction of the inverter 502a, the inverter 502a is made to respond to the weight signal DIN. N (which is changing to logic 0) is inverted, thereby making the corresponding bit line signal BL N is logic 1.

[0348] At time T5, the clock signal CLK of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A1 of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A2 of the memory macro 204 is converted to logic 0, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is converted to logic 1, the corresponding weight signal DIN0 is converted to logic 1, the corresponding bit line signal BL0 is converted to logic 0, and the enable signal INV_EN0 of the corresponding column N of the memory macro 204 is converted to logic 1. N Converted to logic 0, the corresponding weight signal DIN NConverted to logic 1, and the corresponding bit line signal BL N Converts to logic 1.

[0349] Other configurations of waveform 1000A are also within the scope of the present disclosure.

[0350] Fig. 10B is a corresponding graph of a corresponding waveform 1000B according to some embodiments.

[0351] At time T0, the clock signal CLK of the memory macro 204 is equal to logic 0, the address signal ADDR of the address A1 of the memory macro 204 is equal to logic 0, the address signal ADDR of the address A2 of the memory macro 204 is equal to logic 1, the input signal XIN0 is equal to logic 0, the input signal XIN1 is equal to logic 0, and the input signal XIN M = logic 1, the count signal ACT_XIN is equal to value 0, the enable signal INV_EN0 of column 0 corresponding to the memory macro 204 is equal to logic 0, the digital signal MAC_tmp0 is equal to value 0, the output signal D_OUT0 is equal to value 0, and the enable signal INV_EN0 of column N corresponding to the memory macro 204 is equal to logic 0. N Equal to logic 1, digital signal MAC_tmp N Equal to the value 0, the output signal D_OUT N Equal to the value 0.

[0352] At time T1, the clock signal CLK of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A1 of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A2 of the memory macro 204 is converted to logic 0, the input signal XIN0 is converted to logic 1, the input signal XIN1 is converted to logic 1, and the input signal XIN M The count signal ACT_XIN is converted to a value of 7, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is converted to 1, the digital signal MAC_tmp0 is converted to a value of 6, the output signal D_OUT0 is converted to a value of 1, and the enable signal INV_EN0 of the corresponding column N is converted to 1. N Converted to value 7, output signal D_OUT N Converts to the numeric value 7.

[0353] In response to the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 transitioning to logic 1, the subtractor 904a is enabled. In response to the subtractor 904a being enabled, the subtractor 904a is caused to apply Formula 1 when determining the output signal D_OUT0 based on the digital signal MAC_tmp0 and the count signal ACT_XIN. When the count signal ACT_XIN is equal to the value 7 and the digital signal MAC_tmp0 transitions to the value 6, the subtractor 904a determines that the output signal D_OUT0 transitions to the value 1 according to Formula 1. For example, 7-6 is equal to 1.

[0354] In response to the enable signal INV_EN of the corresponding column N of the memory macro 204 N is converted to logic 0, resulting in the subtractor 904N being disabled. In response to disabling the subtractor 904N, the subtractor 904N is caused to operate based on the digital signal MAC_tmp N Formula 2 is applied when determining the output signal D_OUTN. When the digital signal MAC_tmp N When the value changes to 7, the subtractor 904N determines the output signal D_OUT according to formula 2 N Transforms to a value of 7.

[0355] At time T2, the clock signal CLK of the memory macro 204 is equal to logic 1, the address signal ADDR of the address A1 of the memory macro 304 is equal to logic 1, the input signal XIN1 is equal to logic 1, and the input signal XIN M = logic 0, the count signal ACT_XIN is equal to the value 7, the enable signal INV_EN0 of column 0 corresponding to the memory macro 204 is equal to logic 1, the digital signal MAC_tmp0 is equal to the value 6, the output signal D_OUT0 is equal to the value 1, and the enable signal INV_EN0 of row N corresponding to the memory macro 204 is equal to logic 1. N Equal to logic 0, digital signal MAC_tmp N Equal to the value 7, the output signal D_OUT N Equals the value 7.

[0356] At time T3, the clock signal CLK of the memory macro 204 is converted to logic 1, the address signal ADDR of the address A1 of the memory macro 204 is converted to logic 0, the address signal ADDR of the address A2 of the memory macro 204 is converted to logic 1, the input signal XIN0 is converted to logic 0, the input signal XIN1 is converted to logic 0, and the input signal XIN MThe count signal ACT_XIN is converted to a value of 15, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 is converted to a logic 0, the digital signal MAC_tmp0 is converted to a value of 11, the output signal D_OUT0 is converted to a value of 11, and the enable signal INV_EN0 of the corresponding column N of the memory macro 204 is converted to a logic 0. N N is converted to logic 1, the digital signal MAC_tmp N Converted to value 9, output signal D_OUT N Converts to the value 6.

[0357] In response to the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 transitioning to logic 0, the subtractor 904a is disabled. In response to disabling the subtractor 904a, the subtractor 904a is caused to apply Formula 2 when determining the output signal D_OUT0 based on the digital signal MAC_tmp0. When the digital signal MAC_tmp0 transitions to a value of 11, the subtractor 904a determines that the output signal D_OUT0 transitions to a value of 11 according to Formula 2.

[0358] In response to the enable signal INV_EN of the corresponding column N of the memory macro 204 N tmp_tmp is converted to logic 1, so that the subtractor 904N is enabled. In response to enabling the subtractor 904N, the subtractor 904N is caused to perform a power-on operation based on the digital signal MAC_tmp_tmp. N The count signal ACT_XIN determines the output signal D_OUT N Formula 1 applies when the count signal ACT_XIN is equal to the value 15 and the digital signal MAC_tmp N When the value changes to 9, the subtractor 904N determines the output signal D_OUT according to formula 1 N Converts to the value 6. For example, 15-9 equals 6.

[0359] At time T4, the clock signal CLK of the memory macro 204 is equal to logic 1, the address signal ADDR of the address A1 of the memory macro command 204 is equal to logic 0, the address signal DDRR of the address A2 of the memory macro program 204 is equal to logic 1, the input signal XIN0 is equal to logic 0, the input signal XIN1 is equal to logic 0, and the input signal XIN M Equal to logic 1, counting signal ACT_XI N =15, the enable signal INV_EN0 of column 0 corresponding to the memory macro 204 is equal to logic 0, the digital signal MAC_tmp0 is equal to the value 11, the output signal D_OUT0 is equal to the value 11, the enable signal INV_ENN of column N corresponding to the memory macro 204 is equal to logic 1, the digital signal MAC_tmp N Equal to value 9, output signal D_OUTN Equals the value 6.

[0360] At time T5, the clock signal CLK of the memory macro 204 changes to logic 1, the address signal ADDR of the address A1 of the memory macro 204 changes to logic 1, the address signal ADDR of the address A2 of the memory macro 204 changes to logic 0, the input signal XIN0 changes to logic 1, the input signal XIN1 changes to logic 1, and the input signal XIN M = changes to logic 0, the count signal ACT_XIN changes to value 0, the enable signal INV_EN0 of the corresponding column 0 of the memory macro 204 changes to logic 1, the digital signal MAC_tmp0 changes to value 0, the output signal D_OUT0 changes to value 0, and the enable signal INV_EN0 of the corresponding column N of the memory macro 204 changes to logic 1. N Converted to logic 0, the digital signal MAC_tmp N Converted to value 0, output signal D_OUT N Converts to the value 0.

[0361] In some embodiments, the write circuit 500A or 500B achieves one or more advantages discussed in this application.

[0362] Other configurations of waveform 1000B are also within the scope of the present disclosure.

[0363] Fig.11A is a schematic diagram of a memory device 1100A according to some embodiments.

[0364] Memory device 1100A includes memory macros 1102, 1104, 1106, 1108 and memory controller 1120. In some embodiments, one or more of memory macros 1102, 1104, 1106, 1108 correspond to memory macro 110, and / or memory controller 1120 corresponds to memory controller 120. In some embodiments, one or more of memory macros 1102, 1104, 1106, 1108 correspond to memory circuit 102, and / or memory controller 1120 corresponds to memory controller 120.

[0365] exist Fig.11A In the example configuration in FIG. 1 , memory controller 1120 is a common memory controller for memory macros 1102, 1104, 1106, 1108. In at least one embodiment, at least one of memory macros 1102, 1104, 1106, 1108 has its own memory controller. The number of four memory macros in memory device 1100A is an example. Other configurations are within the scope of various embodiments.

[0366] The memory macros 1102, 1104, 1106, and 1108 are coupled to each other in sequence, and the output data of the previous memory macro is the input data of the subsequent memory macro. For example, the input data DIN is input to the memory macro 1102. The memory macro 1102 generates a weight data W or an inverted weight data WB (such as WB) stored in the memory macro 1102 based on the input data DIN and the weight data W or the inverted weight data WB (such as WB) stored in the memory macro 1102. Figure 1 1104) performs one or more CIM operations, and generates output data DOUT2 as a result of the CIM operation. Output data DOUT2 is provided as input data DIN4 of memory macro 1104. Memory macro 1104 performs one or more CIM operations based on input data DIN4 and one of weight data W or inverted weight data WB stored in memory macro 1104, and generates output data DOUT4 as a result of the CIM operation. Output data DOUT4 is provided as input data DIN6 of memory macro 1106. Memory macro 1106 performs one or more CIM operations based on input data DIN6 and one of weight data W or inverted weight data WB stored in memory macro 1106, and generates output data DOUT6 as a result of the CIM operation. Output data DOUT6 is provided as input data DIN8 of memory macro 1108. Memory macro 1108 performs one or more CIM operations based on input data DIN8 and one of weight data W or inverted weight data WB stored in memory macro 1108, and generates output data DOUT as a result of the CIM operation.

[0367] One or more of the input data DIN, DIN4, DIN6, DIN8 corresponds to Figure 1 The input data D_IN and / or one or more of the output data DOUT2, DOUT4, DOUT6, DOUT described above correspond to the attached Figure 1 The output data D_OUT described above is not described, and thus similar detailed description is omitted. In at least one embodiment, the configuration of the memory macros 1102, 1104, 1106, 1108 implements a neural network.

[0368] Other configurations or numbers of elements in the memory device 1100A are within the scope of the present disclosure.

[0369] Fig. 11B is a schematic diagram of a neural network 1100B according to some embodiments.

[0370] The neural network 1100B includes a plurality of layers AE, each layer including a plurality of nodes (or neurons). The nodes in the consecutive layers of the neural network 1100B are connected to each other through a matrix or connection array. For example, the nodes in layers A and B are connected to each other through the connections in the matrix 1112, the nodes in layers B and C are connected to each other according to the connections in the matrix 1114, the nodes in layers C and D are connected to each other according to the connections in the matrix 1116, and the nodes in layers D and E are connected to each other according to the connections in the matrix 1118. Layer A is an input layer configured to receive input data 1111. The input data 1111 is propagated from one layer to the next layer through the neural network 1100B via the corresponding connection matrix between the layers. When the data propagates through the neural network 1100B, the data undergoes one or more calculations and is output as output data 1119 from layer E, which is the output layer of the neural network 1100B. Layers B, C, and D between the input layer A and the output layer E are sometimes referred to as hidden layers or intermediate layers. Fig. 11B The number of layers, the number of connection matrices, and the number of nodes in each layer are examples. Other configurations are within the scope of various embodiments. For example, in at least one embodiment, neural network 1100B does not include hidden layers and has an input layer connected to an output layer via a connection matrix. In one or more embodiments, neural network 1100B has one, two, or more than three hidden layers.

[0371] In some embodiments, matrices 1112, 1114, 1116, 1118 are implemented by memory macro instructions 1102, 1104, 1106, 1108 accordingly, input data 1111 corresponds to input data DIN, and output data 1119 corresponds to output data DOUT, so similar detailed descriptions are omitted. Specifically, in matrix 1112, the connection between a node in layer A and another node in layer B has a corresponding weight. For example, the connection between node A1 and node B1 has a weight W (A1, B1), which corresponds to a weight value or an inverted weight value stored in the memory array of memory macro 1102. Memory macros 1104, 1106, 1108 are configured in a similar manner. When machine learning is performed using neural network 1100B, weight data W or inverted weight data WB in one or more of memory macros 1102, 1104, 1106, 1108 is updated, for example, by a processor and through memory controller 1120. According to some embodiments, one or more advantages described herein may be realized in a neural network 1100B that is implemented in whole or in part by one or more memory macros and / or memory devices.

[0372] Other configurations or numbers of elements in neural network 1100B are within the scope of the present disclosure.

[0373] Fig. 11Cis a schematic diagram of an integrated circuit (IC) device 1100C according to some embodiments.

[0374] IC device 1100C is Figure 1 The memory device 100 or Fig.11A The present invention is not limited to embodiments of the memory device 1100A, and thus similar detailed description is omitted.

[0375] IC device 1100C includes one or more hardware processors 1132, one or more memory devices 1134 coupled to processors 1132 via one or more buses 1136. In some embodiments, one or more hardware processors 1132 may be used as Figure 1 The controller 120 or Fig.11A One or more components of the memory controller 1120 are omitted, and thus similar detailed description is omitted. In some embodiments, one or more memory devices 1134 may be used as Figure 1 The memory circuit 102, Figure 1 Memory macro 110 or Fig.11A One or more components in one or more of the memory macros 1102, 1104, 1106, or 1108 in the embodiment of the present invention are described above, and thus similar detailed description is omitted.

[0376] In some embodiments, the IC device 1100C includes one or more other circuits, including but not limited to a cellular transceiver, a global positioning system (GPS) receiver, a network interface circuit for one or more of Wi-Fi, USB, Bluetooth, etc. Examples of processors 1132 include but are not limited to a central processing unit (CPU), a multi-core CPU, a neural processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other programmable logic devices, a multimedia processor, an image signal processor (ISP), etc. Examples of memory devices 1134 include one or more memory devices and / or memory macros herein. In at least one embodiment, each processor 1132 is coupled to a corresponding memory device in the memory device 1134.

[0377] Because one or more memory devices 1134 are CIM memory devices, various calculations are performed in the memory devices, which reduces the computational workload of the corresponding processor, reduces memory access time, and improves performance. In at least one embodiment, the IC device 1100C is a system on chip (SOC). In at least one embodiment, the IC device 1100C can achieve one or more advantages of the present invention.

[0378] Other configurations or numbers of elements in IC device 1100C are within the scope of the present disclosure.

[0379] Figure 12A-12B is a flow chart of a method 1200 of operating a circuit according to some embodiments.

[0380] In some embodiments, Figure 12A-12B is a flow chart of a method 1200 of operating a memory circuit, such as Figure 1 A memory device 100, Figure 2 The memory circuit 200, Figure 3 The memory circuit 300, Figure 4 The memory circuit 400, corresponding Figure 5A-Figure 5B Write circuits 500A-500B, Figure 6 The circuit 600, corresponding Figure 7A-7B Memory circuits 700A-700B, Figure 8 The writing circuit 800, Fig. 9 The read circuit 900, Fig.11A The memory device 1100A of Fig. 11B Neural Network 1100B, Fig. 11C IC device 1100C.

[0381] In some embodiments, method 1200 uses corresponding Figure 10A-10B One or more aspects of waveforms 1000A-1000B.

[0382] It should be understood that Figure 12A-12B Additional operations may be performed before, during, and / or after the method 1200 shown, and some other processes may only be briefly described herein. In some embodiments, other operation sequences of the method 1200 are within the scope of the present disclosure. The method 1200 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, replaced, reordered, and / or eliminated, according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of the method 1200 are not performed.

[0383] In operation 1202 of method 1200 , a first write circuit receives a first weight signal group.

[0384] In some embodiments, the first write circuit of method 1200 includes at least one of write circuits 406 or 500 .

[0385] In some embodiments, the first weight signal group of method 1200 includes weight signal group W.

[0386] In operation 1204 of method 1200 , an enable signal group INV_EN is generated in response to at least one counting signal.

[0387] In some embodiments, the counting signal of method 1200 includes a counting signal ACT_XIN. In some embodiments, the counting signal corresponds to the number of active word lines WL coupled to the memory cell array. In some embodiments, the memory cell array of method 1200 includes memory array 112.

[0388] In some embodiments, operation 1204 is performed by a second write circuit. In some embodiments, the second write circuit of method 1200 includes at least one of write circuits 402 or 800 .

[0389] In operation 1206 of method 1200 , in response to the enable signal group INV_EN, an inverted enable signal group INV_ENB is generated.

[0390] In some embodiments, operation 1206 is performed by a first circuit. In some embodiments, the first circuit of method 1200 includes at least one of circuits 404 or 600 .

[0391] In some embodiments, the inverted weight signal group is opposite to the first weight signal group.

[0392] In operation 1208 of method 1200 , a write operation of the memory cell array is performed.

[0393] In some embodiments, operation 1208 includes at least one of operations 1210 or 1212 .

[0394] In some embodiments, operation 1208 also includes operation 1214 .

[0395] In operation 1210 of method 1200 , in response to at least the enable signal group INV_EN, a first weight signal group is output.

[0396] In some embodiments, operation 1210 is performed by a first write circuit.

[0397] In operation 1212 of method 1200 , in response to at least the inverted enable signal group INV_ENB, an inverted weight signal group WB is output.

[0398] In some embodiments, operation 1212 is performed by a first write circuit.

[0399] In operation 1214 of method 1200 , the storage data set is stored in the memory cell array.

[0400] In some embodiments, the stored data set of method 1200 includes at least one of the first weight signal set or the inverted weight signal set WB. In some embodiments, the stored data set of method 1200 includes one or more instances of at least one of the first weight signal set or the inverted weight signal set WB.

[0401] In some embodiments, operation 1214 is performed by a first write circuit.

[0402] In operation 1216 of method 1200 , a computation-in-memory (CIM) operation is performed between the stored data set and the first input signal set to generate a first data set.

[0403] In some embodiments, the first input signal group of method 1200 includes received data D_In.

[0404] In some embodiments, operation 1216 is performed by a multiply-accumulate (MAC) circuit 115. In some embodiments, the MAC circuit is coupled to an array of memory cells.

[0405] In some embodiments, operation 1216 of method 1200 is repeated for each column of memory cells in the memory cell array.

[0406] In some embodiments, the first data group of method 1200 includes the output signal group OUT or OUTB.

[0407] In operation 1218 of method 1200, a read operation of a column of memory cells in the memory cell array is performed.

[0408] In some embodiments, operation 1218 is performed by a read circuit. In some embodiments, the read circuit of method 1200 includes at least one of read circuits 408 or 900 .

[0409] In some embodiments, a column of memory cells in a memory cell array includes one or more columns of memory cells within the memory cell array.

[0410] In some embodiments, operation 1218 of method 1200 is repeated for each column of memory cells in the memory cell array.

[0411] In some embodiments, operation 1218 includes operation 1220 .

[0412] In operation 1220 of method 1200 , a first output signal group is generated in response to at least a first data group, an enable signal group INV_EN, or a counting signal.

[0413] In some embodiments, the first output signal group of method 1200 includes the output signal group D_OUT.

[0414] In some embodiments, operation 1220 is performed by a read circuit. In some embodiments, the read circuit of method 1200 includes at least one of read circuits 408 or 900 .

[0415] In some embodiments, a read circuit is coupled to the MAC circuit and the memory cell array.

[0416] By using the method 1200, the memory circuit operates to achieve one or more of the benefits discussed in this disclosure.

[0417] Although the method 1200 is described above with reference to a single column of memory cells in the memory array 112 , it should be understood that in some embodiments, the method 1200 is applicable to each column of the memory device 100 .

[0418] Other operations of method 1200 are within the scope of the present disclosure.

[0419] In addition, the low or high logic values ​​of the various signals used in the above description are also used for illustration. The embodiments of the present disclosure are not limited to specific logic values ​​when the signals are activated and / or deactivated. It is within the scope of various embodiments to select different logic values. Figure 1-11C It is within the scope of various embodiments to select different numbers of elements.

[0420] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the above description, those skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the attached claims and their equivalents.

[0421] One aspect of the specification relates to a memory circuit. The memory circuit includes a memory cell array configured to store a storage data group, the storage data group is one of a first weight signal group or an inverted weight signal group, and the inverted weight signal group is inverted with the first weight signal group. In some embodiments, the memory circuit also includes a multiplication-accumulation (MAC) circuit coupled to the memory cell array, and is configured to generate a first data group in response to a second data group and a storage data group. In some embodiments, the memory circuit also includes an input-output (IO) circuit coupled to the MAC circuit. In some embodiments, the IO circuit includes a first circuit coupled to the memory cell array and configured to send a first weight signal group in response to at least an enable signal group, or to generate an inverted weight signal group in response to at least an inverted enable signal group. In some embodiments, the IO circuit also includes a second circuit coupled to the MAC circuit and configured to output a first output signal group in response to at least the first data group and the enable signal group.

[0422] In some embodiments, the IO circuit further includes: a third circuit coupled to the first circuit and the second circuit and configured to generate an enable signal group in response to at least a storage data group in the memory cell array.

[0423] In some embodiments, the IO circuit further includes: a fourth circuit coupled to the first circuit and the third circuit and configured to generate an inverted enable signal group in response to the enable signal group.

[0424] In some embodiments, the memory circuit further includes a weight buffer circuit coupled to the memory cell array and the first circuit and configured to send the first weight signal group to the memory cell array.

[0425] In some embodiments, the first circuit includes: a first path group, each path in the first path group includes: a first inverter, coupled to the fourth circuit and the weight buffer circuit, and configured to generate a corresponding first inverted weight signal in the inverted weight signal group in response to a corresponding first weight signal in the second weight signal group and a corresponding first inverted enable signal in the inverted enable signal group; and a second path group, each path in the second path group includes: a second inverter, configured to generate a corresponding first intermediate weight signal in the intermediate inverted weight signal group in response to a corresponding first weight signal in the second weight signal group; and a third inverter, coupled to the second inverter, the third circuit and the weight buffer circuit, and configured to generate a corresponding first weight signal in the first weight signal group in response to a corresponding first intermediate weight signal in the intermediate inverted weight signal group and a corresponding first enable signal in the inverted enable signal group, wherein each path in the first path group and each corresponding path in the second path group are coupled together.

[0426] In some embodiments, the fourth circuit includes: a first inverter group, each inverter in the first inverter group being configured to generate a corresponding inverted signal in the inverted enable signal in response to a corresponding enable signal in the enable signal group.

[0427] In some embodiments, the third circuit includes: an accumulator, coupled to the first circuit and the fourth circuit, and configured to generate an accumulation signal group in response to a stored data group; and a comparator, coupled to the accumulator, and configured to generate an output comparison signal group in response to the accumulation signal group and a first count signal, the output comparison signal group being an enable signal group, and the first count signal corresponding to half the number of word lines coupled to the memory cell array.

[0428] In some embodiments, the second circuit includes: an analog-to-digital converter (ADC) group, each ADC in the ADC group being configured to generate a corresponding digital signal in the digital signal group in response to corresponding data in the storage data group; and a subtractor group, each subtractor in the subtractor group being configured to generate a corresponding output signal in the first output signal group in response to at least a corresponding enable signal in the enable signal group or a first count signal on the word line group, wherein each ADC in the ADC group and each subtractor in the subtractor group are coupled to corresponding memory cell columns in the memory cell array.

[0429] In some embodiments, the memory circuit further includes: a word line group coupled to the memory cell array; and an input driver circuit coupled to the memory cell array through the word line group and configured to send a word line signal group on the word line group to generate a count signal and send the count signal to the IO circuit.

[0430] In some embodiments, the input driver circuit includes: an input driver circuit group, each input driver circuit of the input driver circuit group is configured to generate a corresponding word line signal in the word line group signal in response to a corresponding input signal in the input signal group; and a counter, coupled to the input driver circuit group, and the counter is configured to count the number of inputs coupled to the input driver circuit group, thereby generating a counting signal, and the counter is also configured to send the counting signal to the IO circuit, the counting signal being the number of word lines of the word line group.

[0431] Another aspect of the present specification relates to a memory circuit. The memory circuit includes a computation in memory (CIM) macro circuit. In some embodiments, the CIM macro circuit includes a memory cell array, the memory cell array includes rows and columns, and is configured to store a storage data group, the storage data group is one of a first weight signal group or an inverted weight signal group, and the inverted weight signal group is inverted with the first weight signal group. In some embodiments, the CIM macro circuit also includes a multiply-accumulate (MAC) circuit coupled to the memory cell array, and is configured to generate a first data group in response to a second data group and a storage data group. In some embodiments, the memory circuit also includes an input-output (IO) circuit, which is coupled to the CIM macro circuit and configured to output a first output signal group. In some embodiments, the IO circuit includes a write circuit, which is coupled to the memory cell array and is configured to send a first weight signal group in response to at least an enable signal group; or generate an inverted weight signal group in response to at least an inverted enable signal group. In some embodiments, the IO circuit also includes a read circuit, which is coupled to the MAC circuit, and is configured to output a first output signal group in response to at least a first data group and an enable signal group.

[0432] In some embodiments, the IO circuit further includes: a first circuit coupled to the write circuit and the read circuit and configured to generate an enable signal group in response to at least a storage data group in the memory cell array.

[0433] In some embodiments, the IO circuit further includes: a second circuit coupled to the write circuit and the first circuit and configured to generate an inverted enable signal group in response to the enable signal group.

[0434] In some embodiments, the second circuit includes: a first inverter group, each inverter in the first inverter group being configured to generate a corresponding inverted signal in the inverted enable signal in response to a corresponding enable signal in the enable signal group.

[0435] In some embodiments, the first circuit includes: an accumulator, coupled to the write circuit and the second circuit, and configured to generate an accumulation signal group in response to a stored data group; and a comparator, coupled to the accumulator, and configured to generate an output comparison signal group in response to the accumulation signal group and a first count signal, the output comparison signal group being an enable signal group, and the first count signal corresponding to half the number of word lines coupled to the memory cell array.

[0436] In some embodiments, the read circuit includes: an analog-to-digital converter (ADC) group, each ADC in the ADC group is configured to generate a corresponding digital signal in the digital signal group in response to corresponding data in the storage data group; and a subtractor group, each subtractor in the subtractor group is configured to generate a corresponding output signal in the first output signal group in response to at least a corresponding enable signal in the enable signal group or a first count signal on the word line group, wherein each ADC in the ADC group and each subtractor in the subtractor group are coupled to a corresponding memory cell column in the memory cell array.

[0437] In some embodiments, the memory circuit further includes: a word line group coupled to the memory cell array; and an input driver circuit coupled to the memory cell array through the word line group and configured to generate a count signal by sending a word line signal group on the word line group, and send the count signal to the IO circuit.

[0438] In some embodiments, the input driver circuit includes: an input driver circuit group, each input driver circuit in the input driver circuit group is configured to generate a corresponding word line signal in the word line group signal in response to a corresponding input signal in the input signal group; and a counter, coupled to the input driver circuit group, and the counter is configured to count the number of inputs coupled to the input driver circuit group, thereby generating a counting signal, and the counter is also configured to send the counting signal to the IO circuit, the counting signal being the number of word lines of the word line group.

[0439] In some embodiments, the write circuit includes: a first path group, each path in the first path group includes: a first inverter, which is coupled to the second circuit and configured to generate a corresponding first inverted weight signal in the inverted weight signal group in response to a corresponding first weight signal in the second weight signal group and a corresponding first inverted enable signal in the inverted enable signal group; and a second path group, each path in the second path group includes: a second inverter, which is configured to generate a corresponding first intermediate weight signal in the intermediate inverted weight signal group in response to a corresponding first weight signal in the second weight signal group; and a third inverter, coupled to the second inverter and the first circuit, and configured to generate a corresponding first weight signal in the first weight signal group in response to a corresponding first intermediate weight signal in the intermediate inverted weight signal group and a corresponding first enable signal in the inverted enable signal group, wherein each path in the first path group and each corresponding path in the second path group are coupled together.

[0440] Another aspect of the present specification relates to a method of operating a memory circuit. The method includes receiving a first weight signal group by a first write circuit. In some embodiments, the method also includes generating an enable signal group by a second write circuit in response to at least a count signal, the count signal corresponding to the number of active word lines coupled to the memory cell array. In some embodiments, the method also includes generating an inverted enable signal group by the first circuit in response to the enable signal group, the inverted weight signal group being inverted to the first weight signal group. In some embodiments, the method also includes performing a write operation of the memory cell array. In some embodiments, performing a write operation of the memory circuit includes: outputting the first weight signal group by the first write circuit in response to at least the enable signal group; or generating an inverted weight signal group by the first write circuit in response to at least the inverted enable signal group. In some embodiments, performing a write operation of the memory circuit also includes storing a storage data group in the memory cell array, the storage data group being one of the first weight signal group or the inverted weight signal group. In some embodiments, the method also includes performing a calculation in memory (CIM) operation between the storage data group and the first group of input signal groups by a multiply-accumulate (MAC) circuit, thereby generating the first data group, the MAC circuit being coupled to the memory cell array. In some embodiments, the method further comprises performing, by a read circuit, a read operation on a column of memory cells in the memory cell array. In some embodiments, performing a read operation on a column of memory cells in the memory cell array comprises: generating, by a read circuit coupled to the MAC circuit and the memory cell array, a first output signal group in response to at least a first data group, an enable signal group, or a count signal.

[0441] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory circuit, comprising: A memory cell array configured to store a storage data group, wherein the storage data group is one of a first weight signal group or an inverted weight signal group, wherein the inverted weight signal group is inverted with respect to the first weight signal group; a multiply-accumulate circuit coupled to the memory cell array and configured to generate a first data set in response to a second data set and the stored data set; as well as An input-output circuit is coupled to the multiplication-accumulation circuit, and the input-output circuit includes: A first circuit is coupled to the memory cell array and is configured to: In response to at least an enable signal group, sending the first weight signal group; or generating the set of inverted weight signals in response to at least the set of inverted enable signals; and A second circuit is coupled to the multiplication-accumulation circuit and is configured to output a first output signal group in response to at least the first data group and the enable signal group.

2. The memory circuit according to claim 1, wherein: The input-output circuit also includes: A third circuit is coupled to the first circuit and the second circuit and is configured to generate the enable signal group in response to at least the storage data group in the memory cell array.

3. The memory circuit according to claim 2, wherein: The input-output circuit also includes: A fourth circuit is coupled to the first circuit and the third circuit and is configured to generate the inverted enable signal group in response to the enable signal group.

4. The memory circuit according to claim 3, further comprising: A weight buffer circuit is coupled to the memory cell array and the first circuit and is configured to send the first weight signal group to the memory cell array.

5. The memory circuit according to claim 4, wherein: The first circuit comprises: A first path group, each path in the first path group comprises: a first inverter coupled to the fourth circuit and the weight buffer circuit and configured to generate a corresponding first inverted weight signal in the inverted weight signal group in response to a corresponding first weight signal in the second weight signal group and a corresponding first inverted enable signal in the inverted enable signal group; and A second path group, each path in the second path group comprises: a second inverter configured to generate a corresponding first intermediate weight signal in an intermediate inverted weight signal group in response to a corresponding first weight signal in the second weight signal group; and a third inverter coupled to the second inverter, the third circuit and the weight buffer circuit and configured to generate a corresponding first weight signal in the first weight signal group in response to a corresponding first intermediate weight signal in the intermediate inverted weight signal group and a corresponding first enable signal in the inverted enable signal group, Each path in the first path group and each corresponding path in the second path group are coupled together.

6. The memory circuit according to claim 3, wherein: The second circuit comprises: an analog-to-digital converter group, each analog-to-digital converter in the analog-to-digital converter group being configured to generate a corresponding digital signal of a digital signal group in response to corresponding data of the stored data group; and a subtractor group, each subtractor in the subtractor group being configured to generate a corresponding output signal in the first output signal group in response to at least a corresponding enable signal in the enable signal group or a first count signal on a word line group, Each analog-to-digital converter in the analog-to-digital converter group and each subtractor in the subtractor group are coupled to a corresponding memory cell column in the memory cell array.

7. A memory circuit comprising: A computing macro circuit in a memory, wherein the computing macro circuit in the memory comprises: a memory cell array including rows and columns and configured to store a storage data group, the storage data group being one of a first weight signal group or an inverted weight signal group, the inverted weight signal group being inverted with respect to the first weight signal group; and a multiply-accumulate circuit coupled to the memory cell array and configured to generate a first data set in response to a second data set and the stored data set; and An input-output circuit is coupled to the computing macro circuit in the memory and is configured to output a first output signal group, the input-output circuit comprising: A write circuit is coupled to the memory cell array and is configured to: sending a first set of weight signals in response to at least the set of enable signals; or generating the set of inverted weight signals in response to at least a set of inverted enable signals; and A read circuit is coupled to the multiplication-accumulation circuit and is configured to output the first output signal group in response to at least the first data group and the enable signal group.

8. The memory circuit according to claim 7, wherein: The input-output circuit also includes: A first circuit is coupled to the write circuit and the read circuit and is configured to generate the enable signal group in response to at least the storage data group in the memory cell array.

9. The memory circuit according to claim 8, wherein: The input-output circuit also includes: A second circuit is coupled to the write circuit and the first circuit and is configured to generate the inverted enable signal group in response to the enable signal group.

10. A method of operating a memory circuit, the method comprising: Receiving a first weight signal group by a first writing circuit; generating, by a second write circuit, a set of enable signals in response to at least a count signal corresponding to a number of active word lines coupled to the memory cell array; generating, by the first circuit in response to the enable signal group, an inverted enable signal group, wherein the inverted weight signal group is inverted with respect to the first weight signal group; Executing a write operation of the memory cell array, wherein executing the write operation of the memory circuit comprises: At least one of the following: The first write circuit outputs the first weight signal group in response to at least the enable signal group; or generating, by the first write circuit, the inverted weight signal group in response to at least the inverted enable signal group; and storing a storage data group in the memory cell array, the storage data group being one of the first weight signal group or the inverted weight signal group; performing an in-memory computation operation between the stored data set and a first set of input signals by a multiplication-accumulation circuit, the multiplication-accumulation circuit being coupled to the memory cell array; generating a first data set; The read circuit performs a read operation on a memory cell column in the memory cell array, and the read operation on the memory cell column in the memory cell array includes: The first output signal group is generated by the read circuit coupled to the multiplication-accumulation circuit and the memory cell array in response to at least a first data group, the enable signal group, or the count signal.

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