Test scheme capable of checking data retention performance of NOR type Flash memory

Abstract

According to the test scheme capable of examining the data retention performance of the NOR type Flash memory, the influence of erasing and writing circulation on the data retention performance is focused on, the erasing and writing circulation times of the Flash memory test are unified, a clear temperature selection criterion is stipulated, a reference is provided for related tests of the Flash memory, and the data retention performance of the NOR type Flash memory is evaluated. The method comprises the following steps of: 1, determining a basic test algorithm of the NOR type Flash memory as a Checkerboard algorithm from two aspects of algorithm design complexity and fault coverage rate; 2, improving the process of the Checkerboard algorithm, and determining a judgment step of a data retention fault; 3, carrying out a pre-experiment to determine the test temperature, the erasing frequency and the number of samples of the data retention performance of the NOR type Flash memory; 4, determining the number of erasing times of the data retention test at normal temperature and the number of samples under each number of erasing times; 5, determining a test pattern, a failure criterion, test duration and a test period; step 6, based on the non-replacement timing truncation test, performing a data retention test combined with an erasing cycle; and step 7, test data processing: carrying out data fitting on the calculated average failure time under different erasing times and the erasing times to obtain a corresponding relationship between the average failure time and the erasing times.

Description

Technical field:

[0001] The present invention relates to the field of integrated circuit quality and reliability testing, and in particular to a test scheme for assessing the data retention performance of a NOR type Flash memory, and belongs to the use reliability evaluation of the memory. Background technology:

[0002] Memory is almost everywhere in electronic devices. However, the floating gate structure design also brings unavoidable problems in memory reliability. The most prominent one is that before writing new data to the memory, an erase operation must be performed to restore each storage unit to an unprogrammed state before new data can be written, which seriously affects the writing speed. In addition, multiple erases and writes will also cause the memory data retention performance to deteriorate.

[0003] For memory, reliability refers to the accuracy and integrity of the data it stores, which mainly includes two aspects: erase and write endurance and data retention. During the use of memory, the main working scenarios that cause reliability problems are erase and write cycles and data retention, in addition to write interference and read interference.

[0004] When writing data to the memory, the erase operation must be performed first before the new data can be written, and new data cannot be written directly on the basis of the original data. During the memory erase and write process, whether using the hot electron injection principle or the tunneling principle, electrons need to pass through the oxide layer barrier, which will cause certain damage to the oxide layer. As the number of erase and write cycles increases, the damage to the oxide layer material continues to accumulate, eventually resulting in large fluctuations in the amount of charge entering the storage unit when storing data, making the threshold voltage value distribution dispersed, thereby increasing the possibility of errors in data retention and reading.

[0005] During the memory data retention process, a reliability problem that is prone to occur is that as the data retention time increases, the charge in the memory cell gradually loses and diffuses, eventually leading to errors when reading data. The more data stored in the memory and the longer it is stored, the more likely this problem will occur. In this process, as the charge in the memory cell is lost, the threshold voltage will show a trend of gradually decreasing.

[0006] The main impact of read interference and write interference on the data stored in the memory is that when the read and write voltages are applied, a weak electric field will also appear in the oxide layer, causing a small amount of channel electrons to enter the storage medium, ultimately leading to data errors. In addition, the storage layer of the floating gate structure may also have coupled crosstalk, resulting in erroneous writing.

[0007] Due to the existence of the above reliability issues, the reliability indicators for measuring memory are mainly erasure endurance and data retention. Erasure endurance refers to the ability of the memory to still have a certain storage window after multiple erase and write cycles, that is, the threshold voltage distribution after writing data cannot be too dispersed. It is usually required that the memory has 100,000 erasable times at room temperature. Data retention refers to the ability of the memory to keep the data reading result unchanged after a period of time under certain environmental conditions. It is usually required to store data at room temperature for 10 years without reading errors. Some high-reliability devices require storage time at 55°C.

[0008] According to different internal architectures, memories can be divided into different types such as NAND, NOR, AND and Ni-NOR. The NOR structure first proposed by Intel in 1988 and the NAND structure proposed by Toshiba in 1989 are the two most important memories on the market. According to the different characteristics of the two memories, their application scenarios are also different. NOR Flash memory should be used in situations where a smaller capacity, fast reading speed, and code access are required, and NAND Flash memory should be selected for situations that require large-capacity external data storage, low storage cost, and fast erasing. Therefore, the reliability requirements of NOR Flash memory are usually more stringent than those of NAND Flash memory, while NAND Flash memory is superior to NOR Flash memory in terms of capacity and cost.

[0009] The memory-related test standards currently used at home and abroad require the use of high temperature to accelerate the data retention test, but do not specify exact temperature selection criteria. In addition, there are no uniform regulations on whether to perform erase and write cycles and the number of erase and write cycles. Therefore, it is necessary to propose a memory test scheme with exact temperature selection criteria and uniform regulations on whether to perform erase and write cycles and the number of erase and write cycles.

[0010] The present invention mainly targets NOR-type Flash memory, focuses on the influence of erase-write cycles on data retention performance, unifies the number of erase-write cycles in memory tests, stipulates clear temperature selection criteria, provides a reference for memory-related tests, and is a test scheme that can assess the data retention performance of NOR-type Flash memory. Summary of the invention:

[0011] 1. Purpose: To address the deficiencies of the prior art, the present invention proposes a test scheme for the data retention performance of a testable memory.

[0012] 2. Technical solution:

[0013] The present invention mainly targets NOR Flash memory, focuses on the influence of erase-write cycles on data retention performance, unifies the erase-write cycle times of memory tests, stipulates clear temperature selection criteria, and provides a reference for memory-related tests.

[0014] The present invention proposes a test scheme for evaluating the data retention performance of a NOR type Flash memory, which comprises the following steps:

[0015] Step 1: From the aspects of algorithm design complexity and fault coverage, the basic test algorithm of deterministic memory is algorithm;

[0016] Step 2: Improve the algorithm flow and determine the steps for distinguishing data retention failures; during the erase and write process, select to write all data "0" and the erase and write times can be selected as needed. Data writing and verification must be performed after the erase and write cycle is completed.

[0017] After writing the test pattern, the first data read is to verify whether the data is written normally. If a data error occurs in this step of verification, it may be one of the following faults: fixed fault, flip fault, write disturbance fault and coupling fault, rather than data retention fault.

[0018] The second data read after the data retention test is to verify whether the normally written data has any faults. If a data error occurs in this step of verification, the detected fault can be considered a data retention fault.

[0019] Step 3: Conduct preliminary tests to determine the data retention performance test temperatures of NOR Flash memory at 85°, 125°, and 150°, and the erase and write times are 10 and 500 respectively; each group of samples has 3 samples, and the total number of samples is 18; during the preliminary test, read the data stored in each device every 100 hours and compare it with the initially written data. If at a certain test temperature, the device has a data retention failure for the first time and the rest of the functions are normal, then select this temperature as the data retention test temperature.

[0020] Step 4: Determine that the erase and write times of the data retention test at room temperature are 10, 1000, 10000, 30000 and 50000 times respectively, the number of samples under each erase and write number is 4, and the number of samples is 20 in total;

[0021] Step 5: Determine the test pattern, failure criteria, test duration and test cycle; during the erase and write cycle, a full "0" pattern should be used for writing, and a pattern should be written to stimulate data retention failure. Set the test duration to 1000 hours, and choose to test every 20 hours.

[0022] Step 6: Based on the non-replacement timed truncation test, a data retention test combined with an erase-write cycle is performed; according to the improved algorithm flow, a test pattern is written to the memory after the erase and write, and the written data is saved for subsequent data read verification. After writing the test pattern and before the data retention test, a data read verification is required to confirm whether the memory is in normal working condition. If a single failure of some units occurs, the fault address should be recorded and eliminated in the subsequent data retention failure record. If the entire memory cannot write data, the device will no longer be subjected to a data retention test. After completing the erase-write cycle, all devices are placed in a 150° temperature box for data retention testing.

[0023] For devices that have completed the previous step of verification and can be subjected to data retention testing, place them in a 150°C environment for 1000 hours, take them out every 20 hours, read the data for verification, and record the unit addresses where data retention failures occur. Addresses that have already been recorded are not recorded repeatedly.

[0024] Step 7: Experimental data processing: data fitting is performed on the average failure time and the number of erase and write times calculated under different erase and write times to obtain the corresponding relationship between the average failure time and the number of erase and write times.

[0025] 3. Advantages and effects:

[0026] The present invention proposes a test scheme for evaluating the data retention performance of a NOR-type Flash memory, which has the following advantages:

[0027] (1) The data retention test is accelerated using high temperature and the exact temperature selection criteria are specified;

[0028] (2) Before the data retention test, an erase and write cycle must be performed, and the number of erase and write cycles is specified to examine the impact of the erase and write cycles on data retention performance;

[0029] (3) The data retention performance test scheme of NOR Flash memory combined with erase and write cycles disclosed in the present invention includes determining the fault test algorithm, test flow, test temperature, test pattern and test data processing method, which can be used to test the memory and make up for the shortcomings of the existing test methods. Description of the drawings:

[0030] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0031] Figure 1 This is a flow chart of a test scheme for assessing the data retention performance of NOR-type Flash memory;

[0032] Figure 2 It is the improved algorithm test flow chart;

[0033] Figure 3 This is a flow chart of a data retention test combined with erase and write cycles. Implementation method:

[0035] The present invention is further described below in conjunction with specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0036] The present invention provides a test scheme for evaluating the data retention performance of a NOR type Flash memory, and its flow chart is as follows: Figure 1 As shown, the specific implementation steps are as follows:

[0037] A test scheme for evaluating the data retention performance of a NOR type Flash memory includes the following steps:

[0038] Step 1: Determine the basic test algorithm for the memory. Analyze the memory failure mode, determine the selection principle of the memory test algorithm from the two aspects of algorithm design complexity and fault coverage, and determine the memory data retention fault test algorithm as the algorithm.

[0039] Starting from the common faults of memory, analyze the manifestations of each fault. During the use of memory, the common faults of its storage array mainly include data retention fault, fixed fault, flip fault, write interference fault and coupling fault. Analyze the commonly used memory test algorithms such as algorithm, algorithm, algorithm and algorithm.

[0040] The algorithm, namely the memory scanning algorithm, is also called the all-0 / all-1 method, which performs detection by performing full-scan programming and data verification on the memory.

[0041] The algorithm is also called a roaming algorithm. During the test, only one storage unit is written with "1", and the address where "1" is written increases continuously. The data "1" will roam every storage unit.

[0042] The algorithm writes opposite data to all adjacent storage cells during the test, so it is also called the chessboard algorithm. The specific test process is to first erase the entire chip data, then write the opposite data of the adjacent cells to each cell, and finally read and verify the data. If there is a difference between the data, it indicates that the memory has a functional failure.

[0043] The advantage of the algorithm is that it can detect multiple unit faults and partial coupling faults with less time and design cost, but the disadvantage is that it is powerless against more complex coupling faults. The algorithm can be used to detect data retention faults, fixed faults, conversion faults, and coupling faults of some adjacent storage cells.

[0044] The algorithm is an algorithm that uses a finite state machine to implement read, write and erase operations on cells of all addresses of the memory. By arranging, combining and repeating the read, write and erase operations, it can cover almost all coupling faults.

[0045] The advantage of the algorithm is that it has a high coverage of coupling faults and the time complexity of the algorithm is lower than that of the algorithm. However, the disadvantage is that there are many types of algorithms and the design complexity is high. In addition, since the original algorithm was proposed for memory testing, some operations, such as writing 1 to a certain unit, are not applicable to memory. In addition, since there are multiple erases and writes to the memory unit during the execution of the algorithm, the internal charge of the memory unit will be refreshed, so it is not suitable for detecting data retention faults. The algorithm can be used to detect fixed faults, conversion faults and most coupling faults.

[0046] The time complexity comparison of the above four algorithms is shown in Table 2, where represents the number of loops in the algorithm. It can be seen that under the same tested memory capacity, the time cost required by algorithm and algorithm is the lowest, algorithm is in the middle, and algorithm requires the most time.

[0047] Table 2 Comparison of time complexity of each algorithm

[0048]

[0049] The fault coverage of the above four algorithms is shown in Table 3. It can be seen that the main advantages of the algorithms are concentrated on the testing of coupled faults, while the algorithms are applicable to all faults except coupled faults.

[0050] Table 3 Fault coverage of each algorithm

[0051]

[0052] Taking into account the time complexity and fault coverage, the algorithm is selected as the basic test algorithm and improved for the data retention performance test of NOR Flash memory considering the number of erase and write times.

[0053] Step 2: Improve the algorithm flow and determine the steps for distinguishing data retention failures. During the erase process, select to write all data "0" and the number of erases can be selected as needed. Data writing and verification must be performed after the erase cycle is completed. Write the test pattern and read the data for the first time to verify whether the data is written normally. If a data error occurs in this step of verification, it may be one of the fixed faults, flip faults, write interference faults and coupling faults, rather than a data retention fault.

[0054] The second reading of data after the data retention test is to verify whether the normally written data has any faults. If a data error occurs in this step of verification, the detected fault can be considered as a data retention fault.

[0055] The improved test algorithm process is as follows Figure 2 As shown in the figure, the erase and write times are manually set, and different times can be selected according to the test needs.

[0056] During the erase process, all data "0" is written because the state of the memory after erasure is the state of data "1". Only by writing all 0 can the erase and write cycle stress be applied to each unit.

[0057] After the erase and write cycle is completed, the test pattern is written and the first data read is to verify whether the data is written normally. If a data error occurs in this step of verification, it may be one of the fixed faults, flip faults, write disturbance faults and coupling faults, rather than the data retention faults that the research mainly focuses on.

[0058] The second data read after the data retention test is to verify whether the normally written data has any faults. If a data error occurs in this step of verification, the detected fault can be considered a data retention fault.

[0059] Step 3: Determine the test temperature of the memory data retention performance through preliminary tests. In order to determine the required retention temperature for the data retention test, and to save as much time as possible without changing the failure mechanism of the memory data retention, preliminary tests are carried out. The test temperatures are 85°, 125°, and 150°, respectively. At each test temperature, the test samples are divided into two groups according to the number of erase and write times, which are 10 and 500 times, respectively. The number of samples in each test group is 3, for a total of 18 test samples.

[0060] The pre-test conditions are set as shown in Table 2.

[0061] Table 2 Pre-test condition settings

[0062]

[0063] During the pre-test, the data stored in each device is read every 100 hours and compared with the data initially written. If a device has a data retention failure for the first time at a certain test temperature and the rest of the functions are normal, then this temperature is selected as the data retention test temperature.

[0064] The memory 2516 selected in this embodiment, specifically, after 500 hours of data retention, only had a data retention failure at 150° C., and the other functions were normal, so 150° C. was selected as the data retention test temperature.

[0065] Step 4: Determine the number of erase and write times for the data retention test and the number of samples at each erase and write time. According to the different erase and write times at room temperature, the samples are grouped into 10, 1000, 10000, 30000 and 50000 times. Select 4 samples at each erase and write time. The erase and write times are the main factors affecting data retention performance. The more levels are selected, the more accurate the final result will be. Generally, no less than 4 levels are required.

[0066] Currently, the maximum number of times a memory can be erased and written is generally 100,000 times. However, considering the actual use process, such a large number of erases and writes are usually not performed.

[0067] At the same time, when conducting a preliminary test on the erase and write performance of the memory, it is found that there are few memories that can still work normally after the erase and write times exceed 50,000 times, so the maximum erase and write times are selected as 50,000 times.

[0068] The memory 2516 selected in this embodiment is specifically divided into 10, 1000, 10000, 30000 and 50000 times of erasure. Usually, the number of accelerated test devices under a single stress should not be less than 3. The memory 2516 selected in this embodiment is specifically selected 4 samples under each erasure number.

[0069] Step 5: Determine the test pattern, failure criteria, test duration and test cycle. During the erase and write cycle, a full "0" pattern should be used for writing, and a pattern should be written to stimulate data retention failure.

[0070] The test duration is set to 1000 hours, and the test is performed every 20 hours. In order to make all storage cells affected by the erase and write cycles, a full "0" pattern should be used for writing during the erase and write cycles; during the data retention process, a pattern should be written to better stimulate data retention failures.

[0071] During the test process, if the read data is inconsistent with the written data, it can be considered a failure. The specific failure cause analysis and test data processing should be carried out after the entire test is completed and when entering the evaluation process.

[0072] With reference to the data retention requirements in various standards and the pre-test results, the test duration is set to 1000 hours. Because it is impossible to accurately measure the time of memory failure, a periodic test method is used. Considering that the temperature acceleration stress at 150°C is large, data verification should be performed at a shorter time interval to ensure the accuracy of the measured data. The test is performed every 20 hours.

[0073] Step 6: Perform a data retention test combined with erase and write cycles. Randomly select 20 devices and divide them into five groups, with four devices in each group. The five groups of devices are subjected to 10, 1000, 10,000, 30,000 and 50,000 erase and write cycles respectively. The erase and write cycle refers to the data retention test based on the improved algorithm flow ( Figure 2 )conduct.

[0074] Data writing and verification means: according to the algorithm process ( Figure 2 ), write a test pattern to the memory after erasing and writing, and save the written data for subsequent data read verification. After writing the test pattern and before performing the data retention test, a data read verification is required to confirm whether the memory is in normal working condition. If a single failure of some units occurs, the failure address should be recorded and eliminated in the subsequent data retention failure record. If the entire memory cannot write data, the data retention test will no longer be performed on the device.

[0075] The data retention test means: for devices that have completed the previous step of verification and can be subjected to the data retention test, they are placed in a 150°C environment for 1000 hours, taken out every 20 hours, the data therein is read for verification, and the unit address where the data retention failure occurs is recorded. The address that has already been recorded is not recorded repeatedly.

[0076] After the erase and write cycles are completed, all devices are placed in a temperature box for data retention testing. The memory 2516 selected in this embodiment is specifically set at a test temperature of 150° C. The performance retention test conditions are shown in Table 3.

[0077] Table 3 Summary of performance retention test conditions

[0078]

[0079] During the data retention test, all devices are verified once every 20 hours, and the addresses where data changes are fed back are recorded. During the data recording process, data errors occurring at the same address of the same memory are not recorded repeatedly. If a certain address of the memory fails data verification three times, and the error does not disappear during the subsequent data verification process, it is considered that the memory has a data retention failure.

[0080] The memory 2516 selected in this embodiment is specifically formed into a data retention test process combined with erase and write cycles as follows: Figure 3 shown.

[0081] Step 7: Test data processing. Select the test truncation type as the non-replacement timed truncation test, and perform data fitting on the average failure time under different erase and write times to obtain the relationship between the two.

[0082] The test data of each group are processed separately. Since the storage unit with data retention failure will no longer write data, it can be regarded as a non-replacement timing truncation test, and the average failure time under different erase and write times is calculated. Then, the average failure time and erase and write times are fitted to obtain the relationship between the two.

Claims

1. A test scheme for evaluating the data retention performance of a NOR Flash memory comprises the following steps: Step S1: From the aspects of algorithm design complexity and fault coverage, it is determined that the basic test algorithm of NOR Flash memory is the Checkerboard algorithm; Step S2: improving the Checkerboard algorithm process and determining the steps for distinguishing data retention failures; Step S3: Conduct a preliminary test to determine that the test temperatures for the data retention performance of the NOR Flash memory are 85°, 125°, and 150°, respectively, and the number of erase and write times is 10 times and 500 times, respectively; each group of samples has 3 samples, and the total number of samples is 18; Step S4: determining that the number of erase and write times of the data retention test at room temperature is 10, 1000, 10000, 30000 and 50000 times respectively, the number of samples under each erase and write number is 4, and the number of samples is 20 in total; Step S5: Determine the test pattern, failure criteria, test duration and test cycle; Step S6: Based on the non-replacement timing truncation test, a data retention test combined with erase and write cycles is performed; Step S7: test data processing, performing data fitting on the average failure time and the number of erase / write times calculated under different erase / write times, and obtaining the corresponding relationship between the average failure time and the number of erase / write times.

2. A test scheme for evaluating the data retention performance of a NOR Flash memory according to claim 1, characterized in that: In step S2, during the erase process, select to write all data "0", and the erase times can be selected as needed. Checkerboard data writing and verification must be performed after the erase cycle is completed. When writing the Checkerboard test pattern, the first data read is to verify whether the data is written normally. If a data error occurs in this step of verification, it is likely to be one of the following faults: fixed fault, flip fault, write disturbance fault, and coupling fault, rather than a data retention fault. The second data read after the data retention test is to verify whether the normally written data has any faults. If a data error occurs in this step of verification, the detected fault can be considered a data retention fault.

3. The test scheme for evaluating the data retention performance of a NOR Flash memory according to claim 1, characterized in that: During the pre-test, the data stored in each device is read every 100 hours and compared with the data initially written. If a device has a data retention failure for the first time at a certain test temperature and the rest of the functions are normal, then this temperature is selected as the data retention test temperature. In step S5, the full "0" pattern should be used for writing during the erase and write cycle, and the Checkerboard pattern should be written to trigger data retention failure. Set the test time to 1000 hours, and choose to test once every 20 hours.

4. The test scheme for evaluating the data retention performance of a NOR Flash memory according to claim 1, characterized in that: In step S6, according to the improved Checkerboard algorithm process, the Checkerboard test pattern is written to the Flash memory after erasure and the written data is saved for subsequent data read verification. After writing the test pattern and before performing the data retention test, a data read verification is required to confirm whether the Flash memory is in normal working condition. If a single failure of some units occurs, the fault address should be recorded and removed from the subsequent data retention failure record. If the entire memory cannot write data, the device will no longer be tested for data retention. After completing the erase and write cycle, all devices are placed in a 150° temperature box for data retention test. For devices that have completed the previous step of verification and can be subjected to data retention testing, place them in a 150°C environment for 1000 hours, take them out every 20 hours, read the data for verification, and record the unit addresses where data retention failures occur. Addresses that have already been recorded are not recorded repeatedly.

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