Built-in computing macro-cell-oriented built-in self-test architecture, system and method

Abstract

The invention relates to a built-in self-test method, architecture and system oriented to an in-memory computing macro-cell, and the method comprises the steps: executing a first test mode: inserting a computing activation vector and a computing enabling instruction in an MBIST test algorithm, and carrying out a computing test after a read operation to detect a coupling fault between a storage array and bit multiplication logic; and judging whether the storage reading result and the calculation result are correct or not, if so, entering a second test mode or judging that the self-test is correct and completing the detection, and otherwise, diagnosing the fault position based on the detection result. According to the test method provided by the invention, the calculation enabling and the calculation activation vector are inserted in the traditional MBIST algorithm, and the additionally executed multiply-accumulate calculation operation is verified after the read operation, so that the test efficiency is greatly improved on the premise of covering the fault type of the traditional memory. The specific fault of data coupling between the storage unit and the calculation unit can be further effectively detected, and the fault coverage rate is increased.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a built-in self-test architecture, system and method for in-memory computing macro units. Background Art

[0002] With the rapid development of artificial intelligence algorithms and deep neural networks (DNNs), the "memory wall" problem in traditional computing hardware has become increasingly prominent. Computing-in-memory (CIM) technology has become a key technology for addressing this problem by bringing computing power directly into memory, effectively reducing data movement costs and power consumption.

[0003] In-memory compute macros are widely deployed in AI chips as computing IP, providing computing power and some storage. However, these large numbers of on-chip in-memory compute macros require robustness and self-testing capabilities to ensure system-level reliability and testability. Furthermore, as technology scales down and design complexity continues to grow, the probability of chip failure increases. Therefore, the reliability and testability of DCIM should be carefully ensured before mass production.

[0004] For traditional memory IP, built-in self-test (BIST) is an effective and fast method for verifying its functionality and enhancing its reliability in chip designs. On-chip BIST enables autonomous and efficient self-testing, reducing reliance on expensive automatic test equipment (ATE). BIST has been widely used in SRAM memories, and dedicated memory BIST (MBIST) algorithms have been developed, such as MSCAN and Checkerboard.

[0005] However, DCIM's tight integration of memory cells and computational logic presents new challenges for chip testing. Because DCIM couples SRAM memory and logic, coupled faults between the SRAM and computational logic can cause circuit failures, in addition to existing faults inherent in the SRAM and computational logic. This is a unique fault characteristic of DCIM. Furthermore, in traditional memory BIST, since the read and write data are consistent—that is, the test vector (write data) and the result to be verified (read data) are identical—the result comparison circuit can simply use an XOR structure. However, in DCIM, the calculation result is the multiplication-and-accumulation (MAC) result of the weight data read from multiple rows of SRAM and the input data. This MAC result is completely different from the input data. For a set of test vectors, the ideal calculation result is called a golden reference. Generating the golden reference for DCIM's MAC result requires either additional memory (ROM) or an additional set of equivalent computational circuits, both of which incur significant area overhead. Furthermore, after the MAC operation, the fault location is difficult to pinpoint directly. Because the mapping relationship between input and computational output is many-to-one (i.e., different inputs may produce the same output), traditional memory BIST (MBIST) solutions, such as the March algorithm, are no longer sufficient to meet DCIM testing requirements. They fail to cover coupled faults related to computation, resulting in low test coverage and impacting the system reliability and productivity of AI chips.

[0006] Currently, most CIM tests use FPGAs to apply stress. This testing method is only suitable for testing a small number of chips or a single chip. It is difficult to automate and cannot be applied to mass production scenarios (large quantities of chips must be quickly screened, and testing each chip individually consumes enormous time and manpower). Furthermore, this method can only apply stress to the top layer of the AI ​​chip. For chips that integrate multiple CIMs, it is difficult to test and locate faults in each CIM individually.

[0007] There are also existing technologies that design self-test circuits for CIM, but their test vectors / instructions are all randomly generated and do not analyze and cover the fault types unique to in-memory calculations, resulting in low test fault coverage.

[0008] Therefore, it is necessary to improve the existing testing architecture and method of in-memory computing macro units. Summary of the Invention

[0009] To solve the above technical problems, the present invention provides a built-in self-test (BIST) architecture for in-memory computing macrocells that is efficient, low-overhead, and capable of achieving high fault coverage, including: a BIST method for in-memory computing macrocells, characterized by comprising executing a first test mode: Inserting a calculation activation vector and a calculation enable instruction in the MBIST test algorithm to perform a calculation test after the read operation to detect coupling faults between the storage array and the bit multiplication logic; and Determine whether the stored read result and the calculation result are correct. If so, enter the second test mode or determine that the self-test is correct and complete the test. Otherwise, diagnose the fault location based on the test result.

[0010] The test method provided in the present application inserts calculation enable and calculation activation vectors in the traditional MBIST algorithm, and verifies the additional multiplication and accumulation calculation operations performed after the read operation. On the premise of covering the traditional memory fault types, it can further effectively detect the unique fault of data coupling between storage units and calculation units, thereby improving the fault coverage.

[0011] Optionally, the built-in self-test method for an in-memory computing macro unit provided by the present application further includes executing a second test mode: Generating a set of automatic test vectors using ATPG, traversing the set of automatic test vectors and corresponding activation vectors to perform multiplication and accumulation operations respectively for testing computing logic; and Determine whether the calculation result is correct. If not, diagnose the fault location. If so, determine that the self-test is correct and complete the test.

[0012] The second test mode complements the first test mode, forming a multi-mode joint test system to improve the integrity, robustness, and reliability of the overall test of the in-memory computing unit. The second test mode automatically generates input patterns with high fault coverage through ATPG, improving test efficiency and coverage.

[0013] Optionally, the built-in self-test method for in-memory computing macro units provided in the present application further includes the steps of: A mode selection step, selecting a corresponding test mode based on the test requirements, wherein the test modes include a first test mode, a second test mode, and a sequential test mode; If only a storage test is required, the first test mode is executed; If only calculation test is required, the second test mode is executed; and If storage test and calculation test are required at the same time, execute the sequential test mode: execute the first test mode first, then execute the second test mode.

[0014] This implementation method achieves flexible adaptation to different testing needs and enhances the versatility and configuration capabilities of the test solution by supporting multiple test modes of storage, computing, and their combination. In addition, the configuration logic of its mode selection mechanism improves the intelligence and automation of the test process and simplifies the test control process. Finally, on-demand calling can avoid redundant testing, improve test efficiency, shorten test time, and reduce resource consumption.

[0015] Optionally, in the built-in self-test method for the in-memory computing macro unit provided in the present application, the first test mode includes: Weight writing step: outputting ascending addresses to the test address channel in sequence, and writing test data into each row of the memory array through the test weight channel during each address corresponding cycle. This write operation is synchronously controlled by controlling the "CIM write enable" signal to ensure that all physical addresses of the memory array are loaded with uniform known data, providing a known weight benchmark for subsequent tests; Computation activation step: re-traverse the address range of the weight writing step, load the test input channel as the activation vector, pull high the "CIM calculation enable" signal and the "CIM read enable" signal to trigger the storage array read and the multiplication and accumulation calculation path to start in conjunction. In each cycle, the storage array reads the weight of the corresponding row and performs parallel bitwise multiplication with the input activation value, then completes the accumulation through the addition tree and outputs the calculation result; Result judgment and error detection steps: If the calculation result is consistent with the expected value, the system enters the next test mode or outputs "BIST correct" as high to complete the test; otherwise, the system will output "BIST correct" as low and enter the diagnosis process.

[0016] First, a unified known weight writing mechanism can ensure the predictability of subsequent calculation outputs, provide ideal reference values ​​for fault detection, and improve test controllability and accuracy.

[0017] Secondly, the synchronous control mechanism of CIM write enable and calculation / read enable signals can achieve precisely controlled write and calculation processes, avoid timing misalignment or test distortion, and enhance test stability.

[0018] Optionally, in the built-in self-test method for the in-memory computing macro unit provided in the present application, the second test mode includes: Test vector weight loading step: Write the automatic test vector generated by ATPG into the corresponding memory array address line, and control the write timing through the "CIM write enable" signal to ensure that the automatic test vector data is correctly configured; Activation vector loading and calculation triggering steps: After the automatic test vector is written, the system synchronously loads the corresponding activation vector to the calculation path and simultaneously pulls up the "CIM calculation enable" to start the multiplication and accumulation operation; Result judgment step: compare the test results with the adjacent columns. If all automatic test vectors pass the test, pull up the "BIST test passed" signal and issue the "BIST end" instruction; if any automatic test vector fails the test, record the error location information and output it.

[0019] The main technical effects of this design include: Improved computational path testing accuracy: Diverse test vectors generated by ATPG can accurately cover corner errors and interconnect anomalies in complex computational paths.

[0020] Reduced test dependencies: The self-comparison mechanism eliminates the need for a golden reference value, reducing test storage costs and external control complexity.

[0021] Improve timing control stability: Ensure the synchronization and consistency of the test process through precise control signals such as "CIM write enable" and "CIM calculate enable".

[0022] Automatic diagnosis and feedback mechanism: Once a fault is detected, the system can automatically record the error location and output it, enhancing the efficiency of fault location and debugging.

[0023] Strong scalability: Supports expansion to multiple vector tests or different activation combination tests, improving overall BIST flexibility.

[0024] To achieve the above-mentioned object of the invention, the present application provides a built-in self-test architecture for in-memory computing macro units, comprising: An MBIST module is configured to generate a test address and a test weight for testing the storage array of the in-memory computing macro unit in a first test mode; The LBIST module is configured to generate test inputs for detecting coupling faults between the memory array and the bit multiplication logic in a first test mode, and to provide automatic test vectors for testing the computation logic of the in-memory computation macrocell in a second test mode; A BIST controller is connected with the MBIST module and the LBIST module, and is used to control the operation of the MBIST module and the LBIST module; a multiplexer network connected between the BIST controller, the MBIST module, the LBIST module, and the in-memory computation macrocell, for switching inputs corresponding to the modes between a functional mode and a test mode; and The diagnosis unit is connected to the BIST controller and is used to analyze and output the fault location according to the test feedback information.

[0025] Optionally, the MBIST module includes: Storing decoders for generating test weights; and A storage counter is connected to the storage decoder and is used to generate a test address.

[0026] Optionally, the LBIST module includes: Logic decoders for generating test inputs and automatic test vectors; and A logic counter is connected to the logic decoder and is used to control the timing of the automatic test vector.

[0027] To achieve the above-mentioned object of the invention, the present application provides a built-in self-test system for an in-memory computing macro unit, comprising the built-in self-test architecture for an in-memory computing macro unit described above, and further comprising: an in-memory computing macro unit connected to the built-in self-test architecture; and A comparison unit is connected to the in-memory computing macro unit and the diagnostic unit, and can compare the storage test results and / or calculation test results of the in-memory computing macro unit with preset values, and send storage error information and / or logic error information to the diagnostic unit.

[0028] Optionally, the comparison unit includes a logic comparator and a storage comparator, which are respectively used for comparing calculation test results and storing test results. The logic comparator determines whether the calculation result is correct based on the consistency of the calculation results of two adjacent columns. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of a typical fault model for an in-memory computing array.

[0030] Figure 2 It is a schematic structural diagram of a built-in self-test system for in-memory computing macro units provided by an embodiment of the present invention.

[0031] Figure 3 yes Figure 2 Schematic diagram of the structure of the logic comparator.

[0032] Figure 4 It is a flowchart of the first test mode in the built-in self-test method for in-memory computing macro units provided by an embodiment of the present invention.

[0033] Figure 5 It is a flow chart of the second test mode in the built-in self-test method for in-memory computing macro units provided by an embodiment of the present invention.

[0034] Figure 6 It is a timing diagram of a built-in self-test method for an in-memory computing macro unit provided by an embodiment of the present invention.

[0035] Figure 7 It is a schematic diagram of the steps of a built-in self-test method for an in-memory computing macro unit provided by an embodiment of the present invention.

[0036] Figure 8 It is a schematic diagram of the steps of a built-in self-test method for an in-memory computing macro unit provided by an embodiment of the present invention.

[0037] Figure 9 It is a schematic diagram of the steps of a built-in self-test method for an in-memory computing macro unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] Figure 1 The in-memory computing array and two typical failure models are shown. The in-memory computing array is used to perform the following operations: Vector-matrix multiplication (VMM) or matrix-matrix multiplication (MMM), i.e. Y = W × A; Among them, A is the input vector or input matrix, which is input through address lines A0, A1, ..., AM; W is the weight matrix, which is stored in the form of storage units; Y is the output vector or matrix, which represents the result of weighted calculation.

[0040] Continue to refer Figure 1 The weight storage unit W{i,j} is responsible for storing the weight value of the i-th row and j-th column, and is generally implemented using technologies such as SRAM, RRAM and FeRAM.

[0041] The bitwise multiplication calculation unit, also known as the multiplier ×, receives the corresponding input Ai in each row and performs parallel multiplication with the weights of each column: W{i,j}*Ai.

[0042] The adder array accumulates the multiplication results of all rows in the same column to implement the vector dot product.

[0043] The multi-column calculation structure selects different columns of results and outputs them to Y{0,0} to Y{0,N}.

[0044] Among the two typical fault models, the first is the weight-input coupling fault. The fault is located between the input signal and the weight storage unit. There is electrical coupling between the input and the weight, which may cause voltage disturbances, thereby causing instability when reading the stored weight. The input signal may also affect the stability of the storage unit, causing errors in the read weight, and ultimately leading to incorrect weight values ​​in the multiplication calculation. Even if the input is correct, it may lead to erroneous results.

[0045] The second type is the weight-bit multiplication result coupling fault, which is located between the weight storage unit and the multiplication result output terminal. The stored weight value affects the multiplier result output line during the output process, which may cause the weight to change and cause the output multiplication result to be contaminated. It may also cause the original result to be interfered with by the bypass signal in the output stage. Ultimately, even if the input and weight are correct, the final result may be wrong because the weight affects the output path.

[0046] Because DCIM couples SRAM storage and logic together, in addition to the inherent faults of the SRAM and computing logic, coupled faults between the two can also cause circuit failures. This is a unique fault caused by the characteristics of DCIM. After discovering the unique faults caused by the characteristics of in-memory computing, the applicant has specifically proposed a built-in self-test architecture 100 for in-memory computing macrocells that is efficient, low-overhead, and achieves high fault coverage. Figure 2 Shown, including: The MBIST module 10 is configured to generate a test stimulus for a storage path in the in-memory computing macrocell 200. Specifically, the MBIST module is configured to generate a test address and a test weight for testing a storage array of the in-memory computing macrocell in a first test mode. The MBIST module 10 includes: a storage decoder 11 for generating a test weight and decoding it into a control signal; a storage counter 12 connected to the storage decoder 11 for generating a test address; The LBIST module 20 is configured to generate test stimuli for the computation paths in the in-memory computation macrocell 200. Specifically, the LBIST module 20 is configured to generate test inputs for detecting coupling faults between the memory array and the memory array and the bit multiplication logic in a first test mode, and to provide automatic test vectors for testing the computation logic of the in-memory computation macrocell 200 in a second test mode. The LBIST module 20 includes: a logic decoder 21 for generating test inputs and automatic test vectors for logic function units; a logic counter 22 connected to the logic decoder 21 for controlling the timing of the automatic test vectors; A BIST controller 30 is connected to the MBIST module 10 and the LBIST module 20 and is used to control the operation of the MBIST module 10 and the LBIST module 20; a multiplexer network 40 connected between the BIST controller 30, the MBIST module 10, the LBIST module 20, and the in-memory computation macro unit 200, capable of switching between a functional mode and a test mode and gating inputs corresponding to the mode; and The diagnosis unit 50 is connected to the BIST controller 30 and is used to analyze and output the fault location and / or fault type according to the test feedback information.

[0047] Specifically, the multiplexer network 40 includes: a weight selector 41 for selectively inputting test weights or functional weights, an input selector 42 for selectively inputting test inputs or functional inputs (matrix or vector), an address selector 43 for selectively inputting test addresses or outputs of logic counters, and a control signal selector 44 for selectively inputting test control signals or control signals. The input of each selector is determined by the output instruction of the BIST controller 30. In other words, each selector selectively operates in test mode or functional mode under the control of the BIST controller 30.

[0048] Specifically, the logic decoder 21 is configured to be integrated with ATPG for generating test vectors. ATPG is an automated tool for generating test vectors for digital circuits. Its goal is to detect specific types of faults (such as open circuits, short circuits, coupling, delays, etc.) to verify whether the chip has manufacturing defects or functional failures. In some embodiments, ATPG can be set separately from the logic decoder 21 and connected to the logic decoder.

[0049] Continue to refer Figure 2 This embodiment also provides a built-in self-test system for an in-memory computing macro unit, including a built-in self-test architecture 100 for an in-memory computing macro unit, an in-memory computing macro unit 200 and a comparison unit 300.

[0050] Optionally, the comparison unit 300 includes a logic comparator 310 and a storage comparator 320, which are respectively used for comparing the calculation test results and the storage test results. More specifically, the logic comparator 310 determines whether the calculation result is correct based on the consistency of the calculation results of two adjacent columns, such as Figure 3 As shown, in this embodiment, due to the use of a self-comparison method, there is no need to generate an additional ideal reference calculation result. The same activation and weight can be input into each column, and the consistency of the calculation results between two adjacent columns can be compared to determine whether the calculation is correct, which greatly reduces the additional hardware overhead.

[0051] The in-memory computing macro unit 200 is connected to the built-in self-test architecture 100, and the comparison unit 300 is connected to the in-memory computing macro unit 200 and the diagnostic unit 50. It can compare the storage test results and / or calculation test results of the in-memory computing macro unit 200 with preset values, and send storage error information and / or logic error information to the diagnostic unit 50.

[0052] This embodiment also provides a built-in self-test method for an in-memory computing macro unit, which includes a first test mode and a second test mode. Figure 4 This is a flow chart of the first test mode. After the first test mode starts, a basic storage test algorithm is first selected, the test algorithm is executed, and the calculation enable and calculation activation vectors are inserted to perform calculation testing after the read operation; it is determined whether the stored read results and calculation results are correct. If not, the error location is diagnosed; if so, it is further determined whether it is the last step of the algorithm. If so, the BIST output is correct. If not, it returns to the execution of the test algorithm, inserts the calculation enable and calculation activation vectors, and performs the calculation testing steps after the read operation.

[0053] Figure 5 This is a flow chart of the second test mode. After the second test mode starts, the ATPG test vector is traversed to determine whether the calculation result is correct. If not, the error location is diagnosed. If so, it is further determined whether it is the last test vector. If so, the BIST is output as correct. If not, it returns to traversing the ATPG test vector.

[0054] The following combination Figure 6 right Figure 2 The working principle of the built-in self-test architecture 100 of the in-memory computing macrocell shown in FIG is described. After receiving the BIST enable signal, the BIST controller 30 selects the test control signal, test weight, test input and test address through the multiplexer network 40. If the test instruction requires that both the storage function and the computing function be tested: First, the first test mode is executed, the MBIST (Memory Built-In Self-Test) module 10, which is the built-in memory self-test module, based on the traditional MBIST algorithm, such as March C - algorithm; then perform the address traversal and weight writing steps: the BIST controller 30 outputs ascending addresses (0~511) to the test address channel in sequence, and writes all-1 test data to each row of the SRAM through the test weight channel in the cycle corresponding to each address. The write operation is synchronized by controlling the "CIM write enable" signal to ensure that all physical addresses of the SRAM are loaded with unified known data, providing a known weight benchmark for subsequent tests.

[0055] After writing, the compute activation step begins: the BIST controller 30 retraverses the address range (0–511). This stage loads the test input (also known as input activation) channel with a 32-bit all-one activation vector (i.e., 32'hffffffff) and pulls high the "CIM compute enable" and "CIM read enable" signals to trigger the SRAM read and multiply-accumulate computation paths. In each cycle, the SRAM reads the all-one weights of the corresponding row and performs a parallel bitwise multiplication with the input activation value. The result is then accumulated through the adder tree and output.

[0056] After the calculation is complete, the result judgment and error detection steps begin. The system expects the output to be the product of the accumulation of 32-bit all-one weights and 32-bit all-one activations, a fixed value. This calculated output is fed into a logic comparator for result judgment. If the calculated value matches the expected value, the system proceeds to the next test mode. Otherwise, the system outputs "BIST Correct" low, entering the diagnostic process.

[0057] This test phase uses a logic comparator to check whether the final accumulated result is the expected value. Since the intermediate paths (read, calculate, and store) are all involved in data transmission, it effectively covers SRAM bitcell failures, read path errors, local failures of multipliers / adders, and coupling defects in the data path.

[0058] It should be noted that the test input being all 1s is only used as an example. In different basic MBIST algorithms and different steps of the same MBIST algorithm, different test inputs can be selected to match the corresponding algorithm for testing.

[0059] The test method provided in this embodiment inserts calculation enable and calculation activation vectors in the traditional MBIST algorithm, and verifies the additional multiplication and accumulation calculation operations performed after the read operation. On the premise of covering traditional memory fault types, it can further effectively detect the unique fault of data coupling between storage units and calculation units, thereby improving the fault coverage rate.

[0060] If the settlement value of the first test mode is consistent with the expected value, the second test mode is executed (also known as entering the second test phase). This phase mainly performs coverage testing on complex combinational logic structures such as multipliers and adder trees in the CIM structure, using stimulus and expectation pairs pre-generated by the automatic test pattern generation tool (ATPG).

[0061] The second test mode includes the steps of: Test vector weight loading: The BIST controller 30 writes the weight vectors (W0, W1, ..., W31) generated by ATPG (Automatic Test Pattern Generation) into the corresponding SRAM address lines in ascending address order. The weight data is 256 bits wide, and each set of weights corresponds to a specific activation vector for the combined test calculation path. During the loading process, the "CIM Write Enable" signal controls the write timing to ensure the correct configuration of the weight data.

[0062] Activation vector loading and calculation triggering steps: After the weights are written, the system synchronously loads the corresponding activation vectors (A0, A1, ...Ai) into the calculation path and simultaneously pulls "CIM calculation enable" high to initiate the multiplication and accumulation operation. During this process, the multiplier output is again compared and judged by the self-comparison module to verify its functional correctness.

[0063] Result judgment step: After all ATPG vector tests pass, the BIST controller pulls up BIST pass and issues a "BIST end" command to complete the entire BIST process. If any test fails, the BIST controller 30 records the error location information and outputs the error location information through the diagnostic unit.

[0064] It should be noted that the BIST test has passed only when both BIST Correct and BIST Complete are 1.

[0065] Optionally, if only the storage function needs to be tested, then only the relevant steps of the first test mode can be executed. Similarly, if only the logic function needs to be tested, then only the relevant steps of the second test mode can be executed. Figure 4 As shown, a built-in self-test method for an in-memory computing macro unit also includes a mode selection step. If only a storage test is required, the first test mode is entered; if only a calculation / logic test is required, the second test mode is entered; if both storage and calculation tests are required, a sequential test mode is executed, that is, the relevant steps of the first test mode are executed first, and then the relevant steps of the second test mode are executed.

[0066] Alternatively, as Figure 7 As shown, this embodiment provides a built-in self-test method for an in-memory computing macro unit, including the steps of: Inserting a calculation activation vector and a calculation enable instruction in the MBIST test algorithm to perform a calculation test after the read operation to detect coupling faults between the storage array and the bit multiplication logic; and Determine whether the stored read result and the calculation result are correct. If so, enter the second test mode or determine that the self-test is correct and complete the test. Otherwise, diagnose the fault location based on the test result.

[0067] Alternatively, as Figure 8 As shown, the built-in self-test method of the in-memory computing macro unit provided in this embodiment further includes executing the second test mode: Generating a set of automatic test vectors using ATPG, traversing the set of automatic test vectors and corresponding activation vectors to perform multiplication and accumulation operations respectively for testing computing logic; and Determine whether the stored read results and calculation results are correct. If not, diagnose the fault location. If so, determine that the self-test is correct and complete the test.

[0068] Alternatively, as Figure 9 As shown, the built-in self-test method for the in-memory computing macro unit provided in this embodiment further includes the steps of: A mode selection step, selecting a corresponding test mode based on the test requirements, the test modes including a first test mode, a second test mode and a sequential test mode; If only a storage test is required, the first test mode is executed; If only calculation test is required, the second test mode is executed; and If storage test and calculation test are required at the same time, execute the sequential test mode: execute the first test mode first, then execute the second test mode.

[0069] Optionally, the first test mode includes: Weight writing step: outputting ascending addresses to the test address channel in sequence, and writing test data into each row of the memory array through the test weight channel during each address corresponding cycle. This write operation is synchronously controlled by controlling the "CIM write enable" signal to ensure that all physical addresses of the memory array are loaded with uniform known data, providing a known weight benchmark for subsequent tests; Compute activation step: re-traverse the address range of the weight write step, load the test input channel as the activation vector, pull high the "CIM compute enable" signal and the "CIM read enable" signal to trigger the storage array read and the multiplication and accumulation calculation path to start in conjunction. In each cycle, the storage array reads the weight of the corresponding row and performs a parallel bitwise multiplication operation with the input activation value, then completes the accumulation through the adder tree and outputs the calculation result; Result judgment and error detection steps: If the calculation result is consistent with the expected value, it enters the next test mode or outputs "BIST correct" as high to complete the test; otherwise, the system will output "BIST correct" as low to perform error diagnosis.

[0070] Optionally, the second test mode includes: Test vector weight loading step: Write the automatic test vector generated by ATPG into the corresponding memory array address line, and control the write timing through the "CIM write enable" signal to ensure that the automatic test vector data is correctly configured; Activation vector loading and calculation triggering steps: After the automatic test vector is written, the system synchronously loads the corresponding activation vector to the calculation path, pulls up "CIM calculation enable", and starts the multiplication and accumulation operation; Result judgment step: Compare the test results with the adjacent columns. If all automatic test vectors pass the test, pull up the "BIST correct" signal and issue the "BIST end" instruction; if any automatic test vector fails the test, record the error location information and output it.

[0071] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A built-in self-test method for an in-memory computing macro unit, characterized in that: The first test mode is executed as follows: Inserting calculation activation vector and calculation enable instruction in MBIST test algorithm to perform calculation test after read operation to detect coupling fault between storage array and bit multiplication logic; as well as Determine whether the stored read result and the calculation result are correct. If so, enter the second test mode or determine that the self-test is correct and complete the test. Otherwise, diagnose the fault location based on the test result.

2. The built-in self-test method for in-memory computing macro units according to claim 1, characterized in that: Also included is the execution of a second test mode: Generating a set of automatic test vectors using ATPG, traversing the set of automatic test vectors and corresponding activation vectors to perform multiplication and accumulation operations respectively for testing computing logic; and Determine whether the calculation result is correct. If not, diagnose the fault location. If so, determine that the self-test is correct and complete the test.

3. The built-in self-test method for in-memory computing macro units according to claim 2, characterized in that: Also includes the steps: A mode selection step, selecting a corresponding test mode based on the test requirements, wherein the test modes include a first test mode, a second test mode, and a sequential test mode; If only a storage test is required, the first test mode is executed; If only calculation test is required, the second test mode is executed; as well as If storage test and calculation test are required at the same time, execute the sequential test mode: execute the first test mode first, then execute the second test mode.

4. The built-in self-test method for in-memory computing macro units according to claim 1, characterized in that: The first test mode includes: Weight writing step: output ascending addresses to the test address channel in sequence, and write test data into each row of the storage array through the test weight channel during each address corresponding cycle. This write operation is synchronized by controlling the "CIM write enable" signal to ensure that all physical addresses of the storage array are loaded with uniform known data, providing a known weight benchmark for subsequent testing; Compute activation step: retraverse the address range of the weight writing step, load the test input channel as the activation vector, and pull high the "CIM compute enable" signal and the "CIM read enable" signal to trigger the storage array read and the multiplication and accumulation calculation path to start in conjunction. In each cycle, the storage array reads the weight of the corresponding row and performs a parallel bitwise multiplication operation with the input activation value. The accumulation is then completed through the adder tree and the calculation result is output; Result judgment and error detection steps: If the calculation result is consistent with the expected value, the system enters the next test mode or outputs "BIST correct" as high to complete the test; otherwise, the system will output "BIST correct" as low and enter the diagnosis process.

5. The built-in self-test method for in-memory computing macro units according to claim 1, characterized in that: The second test mode includes: Test vector weight loading step: Write the automatic test vector generated by ATPG into the corresponding memory array address line and control the write timing through the "CIM write enable" signal to ensure that the automatic test vector data is correctly configured; Activation vector loading and calculation triggering steps: After the automatic test vector is written, the system synchronously loads the corresponding activation vector into the calculation path and simultaneously pulls up "CIM calculation enable" to start the multiplication and accumulation operation; Result judgment step: The test results are compared with the adjacent columns. If all automatic test vectors pass the test, the "BIST test passed" signal is pulled high and the "BIST end" instruction is issued; if any automatic test vector fails the test, the error location information is recorded and output.

6. A built-in self-test architecture for an in-memory computing macrocell, characterized in that: include: An MBIST module is configured to generate a test address and a test weight for testing the storage array of the in-memory computing macro unit in a first test mode; The LBIST module is configured to generate test inputs for detecting coupling faults between the memory array and the bit multiplication logic in a first test mode, and to provide automatic test vectors for testing the computation logic of the in-memory computation macrocell in a second test mode; A BIST controller is connected with the MBIST module and the LBIST module, and is used to control the operation of the MBIST module and the LBIST module; a multiplexer network connected between the BIST controller, the MBIST module, the LBIST module and the in-memory computation macro unit, for switching inputs corresponding to the modes between a functional mode and a test mode; as well as The diagnosis unit is connected to the BIST controller and is used to analyze and output the fault location according to the test feedback information.

7. The built-in self-test architecture for in-memory computing macro units according to claim 6, characterized in that: The MBIST module comprises: Storing decoders for generating test weights; and A storage counter is connected to the storage decoder and is used to generate a test address.

8. The built-in self-test architecture for in-memory computing macro units according to claim 6, wherein: The LBIST module includes: Logic decoders for generating test inputs and automatic test vectors; and A logic counter is connected to the logic decoder and is used to control the timing of the automatic test vector.

9. A built-in self-test system for an in-memory computing macro unit, comprising the built-in self-test architecture for an in-memory computing macro unit according to any one of claims 6 to 8, characterized in that: Also includes: an in-memory computing macro unit connected to the built-in self-test architecture; as well as A comparison unit is connected to the in-memory computing macro unit and the diagnostic unit, and can compare the storage test results and / or calculation test results of the in-memory computing macro unit with preset values, and send storage error information and / or logic error information to the diagnostic unit.

10. The built-in self-test system for in-memory computing macro units according to claim 9, characterized in that: The comparison unit includes a logic comparator and a storage comparator, which are respectively used for comparing calculation test results and storing test results. The logic comparator determines whether the calculation result is correct based on the consistency of the calculation results of two adjacent columns.

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