Dielectric contact etch

Abstract

A method for forming a semiconductor device in a plasma processing chamber is provided. The atomic layer etch selectively etches the SiO relative to the SiN and deposits a fluorinated polymer. Stripping the fluorinated polymer layer includes flowing a stripping gas comprising oxygen into a plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. The SiN layer is selectively etched with respect to SiO and SiGe and Si.

Description

This application is a divisional application of the invention patent application with application number 201880010344.7, application date January 9, 2018, applicant is Rum Research Company, and invention name is "Dielectric Contact Etching". CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Application No. 15 / 425,901, filed February 6, 2017, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0002] The present disclosure relates to a method for forming a semiconductor device on a semiconductor wafer, and more particularly, to a fin transistor. Background Art

[0003] In forming semiconductor devices, FinFET fabrication and epitaxial growth may be used to provide fin-shaped transistors. Summary of the invention

[0004] To achieve the foregoing and in accordance with the purposes of the present disclosure, a method for forming a semiconductor device in a plasma processing chamber is provided. Atomic layer etching selectively etches SiO relative to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, which includes flowing a stripping gas containing oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. The SiN layer is selectively etched relative to SiO and SiGe and Si.

[0005] These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example and not limitation in the accompanying figures and in which like reference numerals indicate similar elements and in which:

[0007] Figure 1 is a high-level flow chart of one implementation.

[0008] Figure 2 is a more detailed flow chart of the fluorinated polymer deposition stage.

[0009] Figure 3 is a more detailed flow chart of the activation phase.

[0010] Figure 4A -F is a schematic cross-sectional view of a structure processed according to an embodiment.

[0011] Figure 5 is a schematic diagram of a plasma processing chamber that can be used in embodiments.

[0012] Figure 6 is a schematic diagram of a computer system that can be used to practice embodiments.

[0013] Figure 7 is a more detailed flow chart of the oxygen stripping process.

[0014] Figure 8 is a more detailed flow chart of the SiN etching process. DETAILED DESCRIPTION

[0015] The present invention will now be described in detail with reference to several preferred embodiments shown in the accompanying drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without some or all of these specific details. In other cases, well-known process steps and / or structures are not described in detail to avoid making the present invention unclear unnecessarily.

[0016] Figure 1 1 is a high-level flow chart of an embodiment. In this embodiment, a substrate having a structure such as a FinFET structure having epitaxial growth is placed in a plasma processing chamber (step 104). Cyclic atomic layer etching of SiO is provided (step 108). Each cycle of the atomic layer etching process includes a fluorinated polymer deposition phase (step 112) and an activation phase (step 116). Unwanted fluorinated polymer is stripped using oxygen stripping (step 120). The SiN layer is selectively etched (step 124). The substrate having the structure is removed from the plasma processing chamber (step 128). Figure 2 1 is a more detailed flow chart of the fluorinated polymer deposition phase (step 112). Fluorinated polymer deposition gas is flowed into the plasma processing chamber (step 204). Fluorinated polymer deposition gas is formed into a plasma, thereby depositing fluorocarbon polymer on the structure (step 208). The flow of fluorinated polymer deposition gas is stopped (step 212). Figure 3 is a more detailed flow chart of the activation phase (step 116). An activation gas is flowed into the plasma processing chamber, wherein the activation gas includes an inert bombardment gas (step 304). The activation gas is formed into a plasma, which activates fluorine and carbon in the fluorinated polymer, thereby causing selective etching of SiO relative to SiN (step 308). The flow of the activation gas is stopped (step 312). Example

[0017] In one example, a substrate having a structure is placed in a plasma processing chamber (step 104). Figure 4A4 is a schematic cross-sectional view of a structure 400, wherein a substrate 404 is located below a silicon layer 408, which is below a dielectric layer 418 having a FinFET structure 420. The FinFET structure 420 is SiGe or Si or a combination thereof. In the specification and claims, SiGe or Si includes doped and undoped SiGe or Si. The top of the FinFET structure 420 is enlarged using epitaxial growth techniques. A coating etch stop SiN layer 424 has been conformally deposited around the enlarged top of the FinFET structure 420. A hard mask 428 is formed on the dielectric layer 418.

[0018] Figure 5 5 is a schematic diagram of a plasma processing chamber that can be used in one embodiment. In one or more embodiments, the plasma processing system 500 includes a gas distribution plate 506 that provides a gas inlet and an electrostatic chuck (ESC) 508 in a processing chamber 549, and the processing chamber 549 is surrounded by a chamber wall 550. In the processing chamber 549, the substrate 404 is located on the top of the ESC 508. The ESC 508 can provide a bias from the ESC source 548. The gas source 510 is connected to the plasma processing chamber 549 through the distribution plate 506. The gas source 510 includes a plurality of gas sources. The ESC temperature controller 551 is connected to the ESC 508 and provides temperature control of the ESC 508. In this example, the first connector 513 is used to provide power to the internal heater 511 to heat the internal area of ​​the ESC 508, and the second connector 514 provides power to the external heater 512 to heat the external area of ​​the ESC 508. The RF source 530 provides RF power to the lower electrode 534, in this embodiment, the upper electrode is the gas distribution plate 506 and is electrically grounded. In a preferred embodiment, 2 MHz, 60 MHz and 27 MHz power sources make up the RF source 530 and the ESC source 548. In this embodiment, a generator is provided for each frequency. In other embodiments, the generators can be in separate RF sources, or separate RF generators can be connected to different electrodes. For example, the upper electrode can have an inner electrode and an outer electrode connected to different RF sources. The controller 535 is controllably connected to the RF source 530, the ESC source 548, the exhaust pump 520 and the etching gas source 510. An example of such a plasma processing chamber is the Exelan Flex manufactured by Lam Research Corporation (Fremont, CA). TM Etching system. The processing chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0019] Figure 66 is a high-level block diagram showing a computer system 600, which is suitable for implementing the control circuit 535 used in the embodiment. The computer system can have a variety of physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to giant supercomputers. The computer system 600 includes one or more processors 602, and can further include an electronic display device 604 (for displaying graphics, text and other data), a main memory 606 (e.g., random access memory (RAM)), a storage device 608 (e.g., a hard disk drive), a removable storage device 610 (e.g., an optical drive), a user interface device 612 (e.g., a keyboard, a touch screen, a keypad, a mouse or other positioning device, etc.) and a communication interface 614 (e.g., a wireless network interface). The communication interface 614 enables software and data to be transmitted between the computer system 600 and an external device through a link. The system can also include a communication infrastructure 616 (e.g., a communication bus, a cross-over bar, or a network), and the aforementioned devices / modules are connected to the communication infrastructure 616.

[0020] The information transmitted via the communication interface 614 may be in the form of a signal that can be received by the communication interface 614 through a communication link, such as an electronic, electromagnetic, optical, or other signal, which carries the signal and can be a communication link implemented using wires or cables, optical fibers, telephone lines, cellular phone links, radio frequency links, and / or other communication channels. Using such a communication interface, it is expected that one or more processors 602 can receive information from a network or can output information to a network during the implementation of the above-mentioned method steps. In addition, the method implementation can be executed only on the processor or can be executed in conjunction with a remote processor on a network such as the Internet, and the remote processor shares part of the processing.

[0021] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, auxiliary memory, removable storage, and storage devices (such as hard disks, flash memory, hard drive memory, CD-ROMs, and other forms of permanent memory), and should not be interpreted as covering transient subject matter such as carrier waves or signals. Examples of computer code include machine code, such as that produced by a compiler, and files including higher-level code executed by a computer using an interpreter. Computer-readable media can also be computer code transmitted by a computer data signal embodied in a carrier wave and represented as a sequence of instructions executable by a processor.

[0022] After placing the structure 400 with the substrate 404 in the plasma processing chamber 549, a cyclic atomic layer etch is provided (step 108). Each cycle of the atomic layer etch process includes a fluorinated polymer deposition phase (step 112) and an activation phase (step 116). Figure 2 FIG. 1 is a more detailed flow chart of the fluorinated polymer deposition phase (step 112). The fluorinated polymer deposition gas is flowed into the plasma processing chamber (step 204). In this embodiment, the fluorinated polymer deposition gas is flowed at a C of between 1 and 20 sccm. 4 F 6 , O between 1 and 520 sccm 2 , CO between 10 and 300 sccm, and Ar between 100 and 1000 sccm. The fluorinated polymer deposition gas forms a plasma, thereby depositing a fluorocarbon polymer on the structure (step 208). RF power between 0-200 watts at 60 MHz and / or 27 MHz is provided to convert the deposition gas into a plasma. The flow of the fluorinated polymer deposition gas is stopped after 1 to 15 seconds (step 212). Other fluorocarbons may be used as deposition gases.

[0023] Figure 4B is a schematic cross-sectional view of structure 400 after the fluorinated polymer deposition stage is complete. A thin conformal layer or fluorinated polymer coating 432 is deposited on structure 400. Fluorinated polymer coating 432 is not drawn to scale but rather is drawn thicker for better understanding.

[0024] Figure 3 1 is a more detailed flow chart of the activation phase (step 116). An activation gas is flowed into the plasma processing chamber, wherein the activation gas includes an inert bombardment gas (step 304). In this example, the activation gas contains only 100-1000 sccm of Ar. In this example, the activation gas is hydrogen-free. The activation gas is formed into a plasma, which activates the fluorine and carbon in the fluorinated polymer, which results in selective etching of SiO relative to SiN, SiGe, Si and doped Si (step 308). In this example, 30-400 watts of RF power are provided at 60 MHz, and 30-300 watts of RF power are provided at 27 MHz. The flow of the activation gas is stopped after a few seconds (step 312).

[0025] Figure 4C is a schematic cross-sectional view of structure 400 after the activation stage is complete. The plasma generated by the inert bombardment gas activates the fluorine and carbon in the fluorinated polymer, resulting in etching of portions of dielectric layer 418 relative to SiN. A layer of dielectric layer 418 is shown as being etched away.

[0026] The cycle is repeated multiple times. In this example, the process is repeated 5-50 times. Figure 4D is a schematic cross-sectional view of structure 400 after 15 cycles of atomic layer etching have been performed. The atomic layer etching selectively etches the SiO layer relative to SiN, SiGe, Si, and doped Si. A fluorinated polymer layer 436 is deposited on the exposed portion of etch stop layer 424.

[0027] Oxygen stripping is provided to strip the fluorinated polymer layer (step 120). Figure 7 1 is a more detailed flow chart of oxygen stripping in this example (step 120). A stripping gas containing oxygen is flowed into the plasma processing chamber (step 704). In this example, the stripping gas is 200-2000 sccm. 2 . Stripping may include other gases such as CO 2 , CO and / or a noble gas. The stripping gas is formed into a plasma (step 708). In this example, RF power is provided at 200 Watts at 60 MHz. The flow of the stripping gas is stopped (step 712).

[0028] Figure 4E is a schematic cross-sectional view of structure 400 after oxygen stripping is complete. The fluorinated polymer layer has been stripped without removing etch stop layer 424.

[0029] The SiN is selectively etched (step 124). Figure 8 1 is a more detailed flow chart for selectively etching SiN (step 124). A SiN etching gas is flowed into the plasma processing chamber (step 804). In this example, the SiN etching gas is 10-200 sccm CH 3 F and 100-800sccm H 2 The SiN etch gas is formed into a plasma (step 808). In this example, the RF power is provided at a frequency of 60 MHz and a power between 50 and 250 W. The RF power is pulsed at a duty cycle of 50% and at a frequency between 50-500 Hz. The flow of the stripping gas is stopped (step 812). Other hydrofluorocarbons and hydrocarbons may be added.

[0030] Figure 4F is a schematic cross-sectional view of structure 400 after selectively etching etch stop SiN layer 424. Etch stop layer 424 is selectively etched such that dielectric layer 418 and SiO of FinFET structure 420 have minimal etching.

[0031] The substrate 404 with the structure 400 is removed from the plasma processing chamber (step 128). Prior to removing the structure 400 from the plasma processing chamber, additional steps may be performed.

[0032] It is found that the atomic layer etching has an etching selectivity ratio of SiO to SiN greater than 10:1. In some embodiments, the thickness of the etch stop layer 424 is less than 5nm. Without such a high etching selectivity ratio of SiO to SiN during etching of the SiO dielectric layer 418, the etch stop layer 424 can be etched away to expose the epitaxial portion of the FinFET structure 420, which may damage the device and cause defects. In order to selectively etch the etch stop layer 424 relative to SiO, SiGe and Si, the fluorinated polymer must be fully removed. It has been found that stripping the fluorinated polymer in the absence of oxygen does not fully remove the fluorinated polymer. The prior art avoids the use of oxygen in this process because oxygen damages the epitaxial portion of the FinFET structure 420. Due to the high selectivity of atomic layer etching, the etch stop layer 424 is not over-etched and provides sufficient protection for the FinFET structure 420 to prevent damage by oxygen. The use of oxygen in stripping fully removes the fluorinated polymer, so that SiN can be etched highly selectively. The etching selectivity ratio of SiN to SiO is at least 10:1 in the steady state. In addition, the etching selectivity of SiN to SiGe and Si is at least 10:1 in the steady state. In the absence of high selectivity for etching SiN relative to SiO, etching SiN will further etch and change the dielectric layer 418. In the absence of high etch selectivity for etching SiN relative to SiGe and Si, etching SiN may damage the FinFET structure 420, resulting in reduced device performance. In addition, it was unexpectedly discovered that the atomic layer etching of SiO has various embodiments that can provide a small CD etch wrap around, which enables etching around the structure and then through the structure. The etch wrap improves the resulting contact because the etch wrap provides a contact along the inclined surface of the epitaxial portion of the FinFET structure 420. In various embodiments, one or more layers can be between, above or below the various layers. In various embodiments, additional steps or stages can be added. In other embodiments, various steps can be performed in different processing chambers. For example, stripping can be performed in a different chamber from the atomic layer etching of SiO.

[0033] In addition to fluorocarbons, fluorinated polymer deposition gases may also contain CO, O 2 , CO 2 and / or Ar. CO provides more carbon deposition on regions with low aspect ratios than on regions with high aspect ratios, which further slows down the etching of SiN in the low aspect ratio regions. Preferably, the activation gas does not contain fluorine. Preferably, the activation gas does not contain hydrogen. Preferably, the bias voltage during the fluorinated polymer deposition phase and the activation phase has a magnitude of less than 200 volts.

[0034] The amount or thickness of the fluorinated polymer provides self-limitation of the amount of etching during the activation phase.In the specification and claims, atomic layer etching is defined as a self-limiting etching process, eg self-limitation of the activation process due to the limited presence of the fluorinated polymer.

[0035] Preferably, SiO is selectively etched at a ratio of at least 10:1 relative to SiGe and Si. More preferably, SiO is selectively etched at a ratio of at least 20:1 relative to SiGe and Si. Preferably, SiO is selectively etched at a ratio of at least 10:1 relative to SiN. More preferably, SiO is selectively etched at a ratio of at least 20:1 relative to SiN. Preferably, SiN is selectively etched at a ratio of at least 10:1 relative to SiGe and Si. More preferably, SiN is selectively etched at a ratio of at least 20:1 relative to SiGe and Si. Preferably, SiN is selectively etched at a ratio of at least 10:1 relative to SiO. More preferably, SiN is selectively etched at a ratio of at least 20:1 relative to SiO. In various embodiments, the doped Si can be silicon doped with carbon, phosphorus, or boron.

[0036] The embodiments provide a method to significantly improve device performance by strictly controlling key dielectric etch process set points and parameters. In particular, dielectric contact etching requires plasma exposure that results in long periods of time for transistor components. This can lead to irreversible damage to the source and drain epitaxial growth regions (epi) of fin transistors and, therefore, degrade device performance.

[0037] Although the design of the device provides some protection for the active area of ​​the transistor, typically a thin silicon nitride (SiN) layer separating the dielectric (typically silicon oxide or just oxide) and the active two-dimensional area of ​​the transistor, this SiN layer is removed non-selectively relative to the oxide in the same process step known as "overetch" (OE). If the SiN layer is too thin (<5nm), then in prior art it is certainly removed, resulting in undesirable exposure to the powerful OE plasma and, therefore, epi damage manifested in physical loss of epi material in the epitaxial growth areas that are most critical to device performance.

[0038] Various embodiments provide a method of stopping on a thin (about 4nm) SiN layer that protects epitaxial growth during an oxide OE recipe step, and then gently removing the SiN layer, thereby causing minimal or no damage to the epitaxial growth below. To achieve this, an atomic layer etch (ALE) technique is used on the oxide OE step to ensure high selectivity relative to the SiN layer (commonly referred to as a "stop layer"). Once the oxide is removed, a short stripping step is applied to remove unwanted polymers, followed by a very low power selective SiN removal step (referred to as LRM). This step shows excellent selectivity for oxides and epitaxial growth that are still exposed in some areas. The epitaxial growth remains virtually intact. Since the LRM step is able to selectively remove SiN relative to epi, the obvious benefit is an increase in the contact area between the contact metal and epi (good epitaxial wraparound). This results in a reduction in contact resistance, which further improves device performance.

[0039] In various embodiments, the traditional powerful non-selective oxide over-etch recipe step is replaced by a series of low-power high-selectivity steps to minimize or even eliminate epi loss of the transistor while keeping other key process specification parameters under control. The "all-in-one" oxide and SiN removal steps are replaced by a sequence of selected recipe steps to highly increase selectivity to the appropriate layers with the goal of minimizing undesirable material loss.

[0040] In various embodiments, in order to selectively remove the oxide relative to the underlying SiN, an ALE technique is applied that is designed to increase the oxide / SiN selectivity to 10 or higher. This enables the removal of oxide in the contacts while the SiN stop layer remains in place to protect the underlying epi. Once the oxide is removed with a certain amount of overetch, an oxygen strip is applied to remove any polymer left over from the ALE step to ensure that clean SiN is exposed for the subsequent dedicated SiN removal step. The remaining SiN layer protects the Si epitaxial growth from oxidation during the stripping. After the stripping step is completed, a SiN removal step (LRM) is applied. This step is developed to remove SiN with high selectivity (selectivity > 10) relative to oxide (e.g., the sidewalls of the newly etched contact) and epitaxial growth, where SiN should be removed. In other embodiments, the fluorocarbon gas can be C 3 F 6 , C 4 F 8 , C 5 F 8 or C 6 F 6 In addition, it is preferred that the fluorocarbon gas does not include hydrofluorocarbons. In other embodiments, the SiN etching gas may use O2 or CO 2 Replace H 2 or with H 2 combination.

[0041] Although the present invention has been described according to several preferred embodiments, there are changes, modifications, permutations and various alternative equivalents that fall within the scope of the present invention. It should also be noted that there are many alternatives to the method and apparatus of the present invention. Therefore, the following appended claims are intended to be interpreted as including all such changes, modifications, permutations and various alternative equivalents that fall within the true spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device in a plasma processing chamber, comprising: providing an atomic layer etch that selectively etches SiO relative to SiN and deposits a fluorinated polymer; Stripping the fluorinated polymer layer, comprising: flowing a stripping gas comprising oxygen into the plasma processing chamber; forming a plasma from the stripping gas; and stopping the flow of the stripping gas; and The SiN layer is selectively etched relative to SiO and SiGe and Si.

2. The method of claim 1, wherein the stripping gas consists essentially of oxygen.

3. The method according to claim 2, wherein: The selective etching of the SiN layer comprises: flowing an etching gas comprising at least one of H2, O2 or CO2 and CH3F into the plasma processing chamber; and The etching gas is formed into a plasma.

4. The method of claim 3, wherein providing the atomic layer etch comprises providing a plurality of cycles, wherein each cycle comprises: The fluorinated polymer deposition stage includes: flowing a fluorinated polymer deposition gas comprising a fluorocarbon gas into the plasma processing chamber; forming the fluorinated polymer deposition gas into a plasma to deposit a fluorocarbon polymer layer; and ceasing to flow the fluorinated polymer deposition gas into the plasma processing chamber; and an activation phase comprising: flowing an activated gas comprising an inert bombardment gas into the plasma processing chamber; forming the activated gas into a plasma, wherein the inert bombardment gas activates fluorine and carbon in the fluorinated polymer, thereby causing selective etching of SiO relative to SiN; and The flow of the activated gas into the plasma processing chamber is stopped. The method according to claim 4 , wherein the activation gas does not contain hydrogen. The method according to claim 5 , wherein the activation gas does not contain fluorine.

7. The method of claim 4, wherein the activation gas consists essentially of Ar.

8. The method of claim 4, wherein the fluorinated polymer deposition phase provides a bias voltage having a magnitude less than 200 volts and the activation phase provides a bias having a magnitude less than 200 volts.

9. The method of claim 4, wherein the fluorinated polymer deposition stage gas further comprises CO.

10. The method of claim 9, wherein the fluorinated polymer deposition stage gas further comprises O2 or Ar.

11. The method of claim 4, wherein the atomic layer etch selectively etches silicon oxide relative to silicon nitride at a ratio greater than 10:

1.

12. The method of claim 4, wherein the selectively etching the SiN layer selectively etches SiN relative to SiGe and Si at a ratio of at least 10:

1. 13 . The method of claim 4 , wherein the semiconductor device comprises a fin transistor having an epitaxial growth region protected by a SiN layer having a thickness less than 5 nm in a silicon oxide dielectric layer.

14. The method of claim 1, wherein the selective etching of the SiN layer comprises: flowing an etching gas comprising at least one of H2, O2 or CO2 and CH3F into the plasma processing chamber; as well as The etching gas is formed into a plasma.

15. The method of claim 1, wherein said providing said atomic layer etch comprises providing a plurality of cycles, wherein each cycle comprises: The fluorinated polymer deposition stage includes: flowing a fluorinated polymer deposition gas comprising a fluorocarbon into the plasma processing chamber; forming the fluorinated polymer deposition gas into a plasma to deposit a fluorocarbon polymer layer; and stopping the flow of the fluorinated polymer deposition gas into the plasma processing chamber; and an activation phase comprising: flowing an activated gas comprising an inert bombardment gas into the plasma processing chamber; forming the activated gas into a plasma, wherein the inert bombardment gas activates fluorine and carbon in the fluorinated polymer, thereby causing selective etching of SiO relative to SiN; and The flow of the activated gas into the plasma processing chamber is stopped.

16. The method of claim 15, wherein the activation gas consists essentially of Ar.

17. The method of claim 15, wherein the fluorinated polymer deposition stage gas further comprises CO, O2 or Ar. 18 . The method of claim 15 , wherein the semiconductor device comprises a fin transistor having an epitaxial growth region protected by a SiN layer having a thickness less than 5 nm in a silicon oxide dielectric layer.

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