Embedded packaging substrate structure and manufacturing method

Abstract

The invention discloses an embedded packaging substrate structure and a manufacturing method, and relates to the technical field of embedded packaging substrates. The method comprises the following steps: preparing a substrate main body; forming a first conduction column on the substrate main body; arranging a viscous first dielectric material on the surface of the substrate main body; placing a chip on the surface of the first dielectric material; pressing the chip into the first dielectric material through a vacuum film pressing machine; arranging a viscous second dielectric material on the surface of the first dielectric material; manufacturing a blind hole communicated with the first conduction column and the chip in the second dielectric material; and manufacturing a first circuit communicated with the blind hole on the surface of the second dielectric material to form an embedded packaging substrate structure. According to the manufacturing method of the embedded packaging substrate structure, the reliability problem caused by CTE mismatching due to different materials is solved, the depth of the via hole is reduced, and the blind hole can be filled up and filled up by subsequent electroplating.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded packaging substrates, and in particular to an embedded packaging substrate structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of the electronics industry, the multifunctionality and miniaturization of electronic products have become a development trend. In the field of packaging substrates, embedding components into the interior of the substrate can help electronic products achieve high integration, multifunctionality and miniaturization. At present, in order to embed components into the substrate, there are usually two methods: 1. Prefabricate a substrate with a cavity, and then bury the components into the cavity; 2. With the help of solder paste or DAF (die attach film, a kind of adhesive film) or adhesive resin material, the components are mounted on the substrate and then plastic-wrapped, and then laser drilling or sandblasting drilling is used to make electrical conduction between layers.

[0003] For the first method, the process is relatively long, which is not conducive to shortening the production cycle and reducing costs. For the second method, multiple materials are needed to achieve component mounting and fixing, such as solder paste or DAF or adhesive resin materials. The difference in the coefficient of thermal expansion (CTE) between different materials brings reliability risks. Moreover, the device packaging is completed first, and then the interlayer conductive blind vias are formed by laser burning or sandblasting. At this time, the depth of the hole is too large, and the existing electroplating filling capacity cannot meet the complete filling of the conductive blind vias, resulting in an increased risk of blind via filling depressions and voids, which is not conducive to product quality. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an embedded package substrate structure and a manufacturing method.

[0005] On the one hand, a method for manufacturing an embedded package substrate structure according to an embodiment of the present invention comprises the following steps:

[0006] preparing a substrate body;

[0007] forming a first conductive column on the substrate body;

[0008] A first dielectric material having viscosity is disposed on the surface of the substrate body; the first dielectric material covers the first conductive pillar;

[0009] placing a chip on the surface of the first dielectric material;

[0010] Pressing the chip into the first dielectric material by a vacuum laminator;

[0011] A second dielectric material having viscosity is arranged on the surface of the first dielectric material; the first dielectric material and the second dielectric material are the same material;

[0012] Making a blind hole in the second dielectric material that is conductive with the first conductive pillar and the chip;

[0013] A first circuit connected to the blind hole is manufactured on the surface of the second dielectric material to form an embedded package substrate structure.

[0014] According to some embodiments of the present invention, the step of preparing the substrate body includes:

[0015] Obtaining a substrate;

[0016] A second conductive column is arranged in the substrate, wherein the second conductive column passes through the upper surface and the lower surface of the substrate;

[0017] A second circuit that is in conduction with the second conducting pillar is fabricated on the upper surface and the lower surface of the substrate to form the substrate body.

[0018] According to some embodiments of the present invention, the step of forming a first conductive pillar on the substrate body includes:

[0019] Making a metal seed layer on the surface of the substrate body;

[0020] Attaching a photosensitive dry film on the surface of the metal seed layer;

[0021] exposing and developing the photosensitive dry film to form a first window corresponding to the first conductive pillar;

[0022] Electroplating the substrate body to form the first conducting column at the first window;

[0023] The photosensitive dry film is removed, and the metal seed layer on the surface of the substrate body is etched.

[0024] According to some embodiments of the present invention, the step of providing a first viscous dielectric material on the surface of the substrate body includes:

[0025] A first dielectric material having viscosity is pressed on the surface of the substrate body by a vacuum laminator, so that the first dielectric material covers the surface of the substrate body and the first conducting pillar.

[0026] According to some embodiments of the present invention, a connection terminal is provided at the bottom of the chip; and the step of pressing the chip into the first dielectric material by a vacuum laminator comprises:

[0027] The chip is placed upside down on the surface of the first dielectric material, with the connecting terminals facing upwards;

[0028] The chip is pressed into the first dielectric material by the vacuum laminator so that the surface of the chip is connected to the second circuit.

[0029] According to some embodiments of the present invention, the step of making a blind hole in the second dielectric material that is connected to the first conductive pillar and the chip includes:

[0030] Performing laser drilling on the second dielectric material to form a through hole penetrating the second dielectric material;

[0031] The blind hole is formed by electroplating in the through hole, and the blind hole is conductively connected to the first conductive pillar and the connecting terminal.

[0032] On the other hand, the embedded package substrate structure according to an embodiment of the present invention includes:

[0033] substrate body;

[0034] A first conductive column is disposed on the surface of the substrate body;

[0035] A first dielectric material with viscosity is disposed on the surface of the substrate body and covers the first conducting column;

[0036] A chip is disposed in the first dielectric material;

[0037] A second dielectric material having viscosity is disposed on the surface of the first dielectric material, and the first dielectric material and the second dielectric material are the same material;

[0038] A blind hole is disposed in the second dielectric material, and the blind hole is conductively connected to the first conductive pillar and the chip;

[0039] The first circuit is arranged on the surface of the second dielectric material, and the first circuit is connected to the blind hole.

[0040] According to some embodiments of the present invention, the substrate body includes a substrate, a second conductive column and a second circuit, the second conductive column is arranged in the substrate and passes through the upper surface and the lower surface of the substrate; the second circuit is arranged on the upper surface and the lower surface of the substrate and is conductive with the second conductive column.

[0041] According to some embodiments of the present invention, a connection terminal is provided at the bottom of the chip, the connection terminal is connected to the blind hole, and the surface of the chip is connected to the second circuit.

[0042] According to some embodiments of the present invention, the chip is pressed into the first dielectric material by a vacuum laminator.

[0043] The embedded package substrate structure and manufacturing method according to the embodiment of the present invention have at least the following beneficial effects: the first dielectric material and the second dielectric material of the same material are used to bond the chip and plastic-encapsulate the chip, thereby solving the reliability problem caused by CTE mismatch due to different materials of the embedded chip in the prior art; before installing the chip, a part of the interlayer conductive pillars (i.e., the first conductive pillars 200) can be made in advance to reduce the depth of the conductive hole, which is conducive to the blind hole being filled and leveled by subsequent electroplating.

[0044] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0046] Figure 1 A flowchart of the steps of a method for manufacturing an embedded package substrate structure according to an embodiment of the present invention;

[0047] Figure 2 is a structural schematic diagram of a substrate body according to an embodiment of the present invention;

[0048] Figure 3 It is a structural schematic diagram of an embodiment of the present invention after a first conductive pillar is formed on a substrate body;

[0049] Figure 4 This is a schematic structural diagram of an embodiment of the present invention after a first dielectric material is disposed on the surface of a substrate body;

[0050] Figure 5 It is a schematic diagram of the structure after a chip is placed on the surface of the first dielectric material according to an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the structure after the chip is pressed into the first dielectric material according to an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of a structure in which a second dielectric material is disposed on the surface of a first dielectric material according to an embodiment of the present invention;

[0053] Figure 8 It is a structural schematic diagram of an embedded package substrate structure according to an embodiment of the present invention;

[0054] Reference numerals:

[0055] The substrate body 100 , the substrate 110 , the second conductive pillar 120 , the second circuit 130 , the first conductive pillar 200 , the first dielectric material 300 , the chip 400 , the connecting terminal 410 , the second dielectric material 500 , the blind hole 600 , and the first circuit 700 . DETAILED DESCRIPTION

[0056] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0057] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0058] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0059] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0060] With the continuous development of the electronics industry, the multifunctionality and miniaturization of electronic products have become a development trend. In the field of packaging substrates, embedding components into the interior of the substrate can help electronic products achieve high integration, multifunctionality and miniaturization. At present, in order to embed components into the substrate, there are usually two methods: 1. Prefabricate a substrate with a cavity, and then bury the components into the cavity; 2. With the help of solder paste or DAF (die attach film, a kind of adhesive film) or adhesive resin material, the components are mounted on the substrate and then plastic-wrapped, and then laser drilling or sandblasting drilling is used to make electrical conduction between layers.

[0061] For the first method, the process is relatively long, which is not conducive to shortening the production cycle and reducing costs. For the second method, multiple materials are needed to achieve component mounting and fixing, such as solder paste or DAF or adhesive resin materials. The difference in the coefficient of thermal expansion (CTE) between different materials brings reliability risks. Moreover, the device packaging is completed first, and then the interlayer conductive blind vias are formed by laser burning or sandblasting. At this time, the depth of the hole is too large, and the existing electroplating filling capacity cannot meet the complete filling of the conductive blind vias, resulting in an increased risk of blind via filling depressions and voids, which is not conducive to product quality.

[0062] To this end, an embodiment of the present invention proposes an embedded packaging substrate structure and a manufacturing method thereof, which uses a first dielectric material and a second dielectric material of the same material to bond the chip and plastic-encapsulate the chip, thereby solving the reliability problem caused by CTE mismatch due to different materials of the embedded chip in the prior art; before installing the chip, a portion of interlayer conductive columns (i.e., the first conductive column 200) can be made in advance to reduce the depth of the conductive hole, which is conducive to the blind hole being filled and leveled by subsequent electroplating.

[0063] The following is combined with Figure 1 To Attachment Figure 8 , the embedded packaging substrate structure and manufacturing method of the embodiment of the present invention are described in detail.

[0064] On the one hand, if Figure 1 As shown, the method for manufacturing the embedded package substrate structure according to the embodiment of the present invention comprises the following steps:

[0065] Step S100: preparing a substrate main body 100;

[0066] Step S200: forming a first conductive pillar 200 on the substrate body 100;

[0067] Step S300: a first dielectric material 300 having viscosity is disposed on the surface of the substrate body 100; the first dielectric material 300 covers the first conductive pillar 200;

[0068] Step S400: placing a chip 400 on the surface of the first dielectric material 300;

[0069] Step S500: pressing the chip 400 into the first dielectric material 300 by a vacuum laminator;

[0070] Step S600: a second dielectric material 500 having viscosity is disposed on the surface of the first dielectric material 300; the first dielectric material 300 and the second dielectric material 500 are the same material;

[0071] Step S700: making a blind hole 600 in the second dielectric material 500 that is conductive with the first conductive pillar 200 and the chip 400;

[0072] Step S800: a first circuit 700 connected to the blind hole 600 is fabricated on the surface of the second dielectric material 500 to form an embedded package substrate structure.

[0073] Specifically, Figure 2 As shown, in this example, the substrate body 100 includes a substrate 110, a second conductive column 120 and a second circuit 130, wherein the substrate 110 can be made of FR4 or epoxy resin containing glass fiber with good strength and rigidity. The second conductive column 120 runs through the upper surface and the lower surface of the substrate 110, and the second circuit 130 is arranged on the upper surface and the lower surface of the substrate 110, and the second circuit 130 is connected to the second conductive column 120. The second circuit 130 on the upper surface of the substrate 110 is connected to the second circuit 130 on the lower surface by the first conductive column 120 arranged in the substrate 110. In this example, the above-mentioned step S100: preparing the substrate body 100 specifically includes the following three steps:

[0074] (1) Obtaining a substrate 110;

[0075] (2) a second conductive pillar 120 is disposed in the substrate 110, and the second conductive pillar 120 penetrates the upper surface and the lower surface of the substrate 110;

[0076] (3) The second circuits 130 that are in electrical communication with the second conductive pillars 120 are fabricated on the upper and lower surfaces of the substrate 110 to form the substrate body 100 .

[0077] It should be noted that, in order to set the second conductive pillar 120 in the substrate 110, the second conductive pillar 120 can be formed in the substrate 110 by drilling and electroplating. In order to make the second circuit 130 on the upper surface and the lower surface of the substrate 110, the dry film can be opened by a method of sticking a dry film-exposure-development to form a window corresponding to the second circuit 130, and then the whole board is electroplated to form the second circuit 130 at the window.

[0078] After the substrate body 100 is prepared, Figure 3 As shown, it is necessary to form a first conductive pillar 200 on the substrate body 100. It should be noted that the first conductive pillar 200 is located on the surface of the second circuit 130, so as to be connected with the second circuit 130. In this example, the above step S200: forming the first conductive pillar 200 on the substrate body 100 includes the following five steps:

[0079] (1) forming a metal seed layer on the surface of the substrate body 100;

[0080] (2) attaching a photosensitive dry film to the surface of the metal seed layer;

[0081] (3) exposing and developing the photosensitive dry film to form a first window corresponding to the first conductive pillar 200;

[0082] (4) electroplating the substrate body 100 to form a first conductive column 200 at the first window;

[0083] (5) The photosensitive dry film is removed, and the metal seed layer on the surface of the substrate body 100 is etched.

[0084] Specifically, a metal seed layer is formed on the surface of the substrate body 100 by magnetron sputtering or other methods, so as to facilitate subsequent electroplating on the substrate body 100. Then, a photosensitive dry film is attached to the surface of the metal seed layer to protect the area on the substrate body 100 that does not need electroplating, and then the photosensitive dry film is exposed and developed, and a window is opened at a position corresponding to the first conductive pillar 200 on the photosensitive dry film to form a first window; then the entire substrate body 100 is electroplated to form the first conductive pillar 200 at the first window.

[0085] like Figure 4 As shown, in some embodiments of the present invention, the above step S300: the step of providing a first viscous dielectric material 300 on the surface of the substrate body 100 includes:

[0086] A first dielectric material 300 having viscosity is disposed on the surface of the substrate body 100 by a vacuum laminator, so that the first dielectric material 300 covers the surface of the substrate body 100 and the first conductive pillar 200 .

[0087] It should be noted that the first dielectric material 300 can simultaneously play the role of bonding the chip 400 and plastic-encapsulating the chip 400 .

[0088] like Figure 5 As shown, in some embodiments of the present invention, a connection terminal 410 is provided at the bottom of the chip 400 , and the chip 400 is inverted on the surface of the first dielectric material 300 . Since the first dielectric material 300 is viscous, it can fix the chip 400 .

[0089] Then, if Figure 6 As shown, the chip 400 needs to be pressed into the first dielectric material 300 by a vacuum laminator, specifically:

[0090] The chip 400 is placed upside down on the surface of the first dielectric material 300, with the connecting terminal 410 facing upward;

[0091] The chip 400 is pressed into the first dielectric material 300 by a vacuum laminator, so that the surface of the chip 400 is connected to the second circuit 130 .

[0092] It should be noted that the chip 400 is directly pressed into the first dielectric material 300 by a vacuum laminator without presetting a cavity for placing the chip 400. Instead, the chip 400 is directly placed and sealed, thereby simplifying the process flow, shortening the product production cycle, and improving production efficiency. The surface of the chip 400 needs to be connected to the second circuit 130 to achieve electrical connection between the chip 400 and the circuit.

[0093] like Figure 7 As shown, after the chip 400 is pressed into the first dielectric material 300, the second dielectric material 500 needs to be pressed on the surface of the first dielectric material 300. It should be noted that the first dielectric material 300 and the second dielectric material 500 are made of the same material. By using packaging media of the same material, the reliability risk caused by the difference in the coefficient of thermal expansion (CTE) between different materials can be avoided.

[0094] Furthermore, if Figure 8 As shown, in some embodiments of the present invention, the above step S700: the step of making a blind hole 600 in the second dielectric material 500 that is connected to the first conductive pillar 200 and the chip 400, includes the following two steps:

[0095] (1) performing laser drilling on the second dielectric material 500 to form a through hole penetrating the second dielectric material 500;

[0096] (2) A blind via 600 is formed in the through hole by electroplating. The blind via 600 is electrically connected to the first conductive pillar 200 and the connecting terminal 410 .

[0097] By making a blind hole 600 in the second dielectric material 500 that is in conduction with the first conductive pillar 200 and the connection terminal 410 , the circuit on the surface of the second dielectric material 500 can be connected to the second circuit 130 and the chip 400 through the blind hole.

[0098] Finally, if Figure 8As shown, on the surface of the second dielectric material 500 , a first circuit 700 is manufactured by dry film pasting-exposure-development-electroplating-film stripping. The first circuit 700 is connected to the blind hole 600 and further connected to the chip 400 and the second circuit 130 .

[0099] According to the method for manufacturing an embedded package substrate structure of an embodiment of the present invention, the first dielectric material 300 and the second dielectric material 500 are used to bond the chip 400 and plastic-encapsulate the chip 400, thereby solving the reliability problem caused by CTE mismatch due to different materials of the embedded chip 400 in the prior art; before installing the chip 400, a portion of interlayer conductive pillars (i.e., the first conductive pillars 200) can be manufactured in advance to reduce the depth of the conductive hole, which is conducive to the blind hole 600 being filled and leveled by subsequent electroplating.

[0100] On the other hand, the embodiment of the present invention also provides an embedded package substrate structure, such as Figures 2 to 8 As shown, it includes:

[0101] substrate main body 100;

[0102] The first conductive pillar 200 is disposed on the surface of the substrate body 100;

[0103] A first dielectric material 300 having viscosity is disposed on the surface of the substrate body 100 and covers the first conductive pillar 200;

[0104] The chip 400 is disposed in the first dielectric material 300;

[0105] The second dielectric material 500 having viscosity is disposed on the surface of the first dielectric material 300, and the first dielectric material 300 and the second dielectric material 500 are the same material;

[0106] A blind hole 600 is disposed in the second dielectric material 500, and the blind hole 600 is electrically connected to the first conductive pillar 200 and the chip 400;

[0107] The first circuit 700 is disposed on the surface of the second dielectric material 500 , and the first circuit 700 is connected to the blind hole 600 .

[0108] Specifically, Figure 2As shown, in this example, the substrate body 100 includes a substrate 110, a second conductive column 120 and a second circuit 130, wherein the substrate 110 may be made of FR4 or epoxy resin containing glass fiber with good strength and rigidity. The second conductive column 120 passes through the upper surface and the lower surface of the substrate 110, and the second circuit 130 is arranged on the upper surface and the lower surface of the substrate 110, and the second circuit 130 is connected to the second conductive column 120. The second circuit 130 on the upper surface of the substrate 110 is connected to the second circuit 130 on the lower surface through the first conductive column 120 arranged in the substrate 110.

[0109] It should be noted that, in order to set the second conductive pillar 120 in the substrate 110, the second conductive pillar 120 can be formed in the substrate 110 by drilling and electroplating. In order to make the second circuit 130 on the upper surface and the lower surface of the substrate 110, the dry film can be opened by a method of sticking a dry film-exposure-development to form a window corresponding to the second circuit 130, and then the whole board is electroplated to form the second circuit 130 at the window.

[0110] After the substrate body 110 is prepared, Figure 3 As shown, it is necessary to form a first conductive column 200 on the substrate body 100. It should be noted that the first conductive column 200 is located on the surface of the second circuit 130, so as to be connected to the second circuit 130. In order to form the first conductive column 200, a metal seed layer is first formed on the surface of the substrate body 100 by magnetron sputtering or other methods, so as to facilitate subsequent electroplating on the substrate body 100. Then, a photosensitive dry film is attached to the surface of the metal seed layer to protect the area on the substrate body 100 that does not require electroplating, and then the photosensitive dry film is exposed and developed, and a window is opened at the position corresponding to the first conductive column 200 on the photosensitive dry film to form a first window; then the entire substrate body 100 is electroplated to form the first conductive column 200 at the first window.

[0111] Then, a first dielectric material 300 with viscosity is disposed on the surface of the substrate body 100 by a vacuum laminator, so that the first dielectric material 300 covers the surface of the substrate body 100 and the first conductive pillar 200. It should be noted that the first dielectric material 300 can simultaneously bond the chip 400 and plastic-encapsulate the chip 400.

[0112] like Figure 5 As shown, in some embodiments of the present invention, a connection terminal 410 is provided at the bottom of the chip 400, and the chip 400 is inverted on the surface of the first dielectric material 300. Since the first dielectric material 300 is viscous, it can fix the chip 400. Then, as shown in FIG. Figure 6As shown, the chip 400 needs to be pressed into the first dielectric material 300 by a vacuum laminator so that the surface of the chip 400 is connected to the second circuit 130 .

[0113] It should be noted that the chip 400 is directly pressed into the first dielectric material 300 by a vacuum laminator without presetting a cavity for placing the chip 400. Instead, the chip 400 is directly placed and sealed, thereby simplifying the process flow, shortening the product production cycle, and improving production efficiency. The surface of the chip 400 needs to be connected to the second circuit 130 to achieve electrical connection between the chip 400 and the circuit.

[0114] like Figure 7 As shown, after the chip 400 is pressed into the first dielectric material 300, the second dielectric material 500 needs to be pressed on the surface of the first dielectric material 300. It should be noted that the first dielectric material 300 and the second dielectric material 500 are made of the same material. By using packaging media of the same material, the reliability risk caused by the difference in the coefficient of thermal expansion (CTE) between different materials can be avoided.

[0115] like Figure 8 As shown, a blind hole 600 conducting with the first conductive pillar 200 and the connecting terminal 410 is made in the second dielectric material 500, so that the circuit on the surface of the second dielectric material 500 can be conducted with the second circuit 130 and the chip 400 through the blind hole.

[0116] Finally, if Figure 8 As shown, on the surface of the second dielectric material 500 , a first circuit 700 is manufactured by dry film pasting-exposure-development-electroplating-film stripping. The first circuit 700 is connected to the blind hole 600 and further connected to the chip 400 and the second circuit 130 .

[0117] According to the embedded package substrate structure of the embodiment of the present invention, the first dielectric material 300 and the second dielectric material 500 are used to bond the chip 400 and plastic-encapsulate the chip 400, thereby solving the reliability problem caused by CTE mismatch due to different materials of the embedded chip 400 in the prior art; before installing the chip 400, a part of the interlayer conductive pillars (i.e., the first conductive pillars 200) can be made in advance to reduce the depth of the conductive hole, which is conducive to the blind hole 600 being filled and leveled by subsequent electroplating.

[0118] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0119] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A method for manufacturing an embedded package substrate structure, characterized in that: The following steps are involved: preparing a substrate body; forming a first conductive column on the substrate body; A first viscous dielectric material is disposed on the surface of the substrate body; The first dielectric material covers the first conductive pillar; placing a chip on the surface of the first dielectric material; Pressing the chip into the first dielectric material by a vacuum laminator; Disposing a second medium material having viscosity on the surface of the first medium material; The first dielectric material and the second dielectric material are the same material; Making a blind hole in the second dielectric material that is conductive with the first conductive pillar and the chip; A first circuit connected to the blind hole is manufactured on the surface of the second dielectric material to form an embedded package substrate structure.

2. The method for manufacturing an embedded package substrate structure according to claim 1, characterized in that: The step of preparing the substrate body comprises: Obtaining a substrate; A second conductive column is arranged in the substrate, wherein the second conductive column passes through the upper surface and the lower surface of the substrate; A second circuit that is in conduction with the second conducting pillar is fabricated on the upper surface and the lower surface of the substrate to form the substrate body.

3. The method for manufacturing an embedded package substrate structure according to claim 1, characterized in that: The step of forming a first conductive column on the substrate body includes: Making a metal seed layer on the surface of the substrate body; Attaching a photosensitive dry film on the surface of the metal seed layer; exposing and developing the photosensitive dry film to form a first window corresponding to the first conductive pillar; Electroplating the substrate body to form the first conducting column at the first window; The photosensitive dry film is removed, and the metal seed layer on the surface of the substrate body is etched.

4. The method for manufacturing an embedded package substrate structure according to claim 1, characterized in that: The step of providing a first viscous dielectric material on the surface of the substrate body comprises: A first dielectric material having viscosity is pressed on the surface of the substrate body by a vacuum laminator, so that the first dielectric material covers the surface of the substrate body and the first conducting pillar.

5. The method for manufacturing an embedded package substrate structure according to claim 2, characterized in that: The bottom of the chip is provided with a connection terminal; the step of pressing the chip into the first dielectric material by a vacuum laminator comprises: The chip is placed upside down on the surface of the first dielectric material, with the connecting terminals facing upwards; The chip is pressed into the first dielectric material by the vacuum laminator so that the surface of the chip is connected to the second circuit.

6. The method for manufacturing an embedded package substrate structure according to claim 5, characterized in that: The step of making a blind hole in the second dielectric material connected to the first conductive pillar and the chip comprises: Performing laser drilling on the second dielectric material to form a through hole penetrating the second dielectric material; The blind hole is formed by electroplating in the through hole, and the blind hole is conductively connected to the first conductive pillar and the connecting terminal.

7. An embedded package substrate structure, characterized in that: include: substrate body; A first conductive column is disposed on the surface of the substrate body; A first dielectric material with viscosity is disposed on the surface of the substrate body and covers the first conducting column; A chip is disposed in the first dielectric material; A second dielectric material having viscosity is disposed on the surface of the first dielectric material, and the first dielectric material and the second dielectric material are the same material; A blind hole is disposed in the second dielectric material, and the blind hole is conductively connected to the first conductive pillar and the chip; The first circuit is arranged on the surface of the second dielectric material, and the first circuit is connected to the blind hole.

8. The embedded package substrate structure according to claim 7, characterized in that: The substrate body includes a substrate, a second conductive column and a second circuit. The second conductive column is arranged in the substrate and passes through the upper surface and the lower surface of the substrate. The second circuit is arranged on the upper surface and the lower surface of the substrate and is conductive with the second conductive column.

9. The embedded package substrate structure according to claim 8, characterized in that: A connecting terminal is disposed at the bottom of the chip, the connecting terminal is connected to the blind hole, and the surface of the chip is connected to the second circuit.

10. The embedded package substrate structure according to claim 7, characterized in that: The chip is pressed into the first dielectric material by a vacuum laminator.

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