Method and structure for packaging FC (Fiber Channel) chip by utilizing vertical routing

Abstract

The invention discloses a vertical routing and FC chip packaging method and structure, belongs to the technical field of chip packaging, removes the redundant design of an adapter plate, can reduce the thickness size of a package of a product, meets the light and thin requirements, and also can reduce the packaging cost due to the change of the size of the product. In addition, the FC chip is used for replacing the adapter plate, so that the product is additionally provided with the performance of one chip on the original basis, and the purpose of improving the performance of the whole product is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of chip packaging, and in particular relates to a chip packaging method and structure utilizing vertical bonding and FC. Background Art

[0002] At present, POP (Package on Package) products mainly rely on traditional WB (wire bonding) wire bonding and adapter board (substrate) to achieve packaging. In this process, the WB chip and adapter board are precisely pasted on the substrate, and bonding connections are established between the chip and the substrate, and between the adapter board and the substrate through welding wires. The adapter board plays the role of a transfer medium, which is mainly responsible for transmitting the signal of one IC to another IC to achieve an effective combination of the two ICs.

[0003] However, when the adapter plate only serves as a transfer medium for connectivity, some problems may be encountered, such as attenuation during signal transmission, electromagnetic interference, and insufficient heat dissipation performance, all of which may affect the overall performance and reliability of the POP package. Summary of the invention

[0004] The present invention provides a method and structure for packaging a chip using vertical bonding and FC, which solves the problem that the adapter board used in existing POP products only serves as a transfer medium for connection, which may cause attenuation, electromagnetic interference and insufficient heat dissipation performance during signal transmission.

[0005] To achieve the above object, the present invention provides the following technical solutions: A chip packaging method using vertical wire bonding and FC, comprising: arranging a substrate carrier, including a top substrate and a bottom substrate; Arranging a chip layer and an FC chip on a bottom substrate; Using vertical bonding, the chip layer and FC chip are connected to the top substrate to achieve a pathway and form a preliminary product; The preliminary product is packaged and the bottom substrate is removed after packaging.

[0006] Preferably, the bottom substrate is made of fiberglass board.

[0007] Preferably, the chip layer is connected to the top substrate via a FOW chip adhesive film.

[0008] Preferably, solder balls are arranged on the upper surface of the top substrate.

[0009] Preferably, each layer of chips in the chip layer is connected to the top substrate via vertical bonding.

[0010] Preferably, the FC chip is bonded to the bottom substrate by chip glue.

[0011] Preferably, a bump is provided on a side of the FC chip close to the bottom substrate.

[0012] Preferably, a molding compound filler is filled between the top substrate and the bottom substrate.

[0013] Preferably, the chips on the chip layer are connected by a chip adhesive film.

[0014] A packaging structure utilizing vertical bonding and FC chips is obtained based on a packaging method utilizing vertical bonding and FC chips.

[0015] Compared with the prior art, the present invention has the following beneficial effects: the present invention provides a packaging method using vertical wire bonding and FC chips, which eliminates the redundant design of the adapter plate, can reduce the thickness of the product package, meet the demand for thinness and lightness, and at the same time, due to the change in product size, can also reduce the packaging cost; in addition, because the FC chip is used instead of the adapter plate, the product is increased in performance by one more chip on the original basis, thereby achieving the purpose of improving the performance of the entire product. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a flow chart of a method for packaging a chip using vertical bonding and FC; Figure 2 This is a front view of a packaging structure utilizing vertical bonding and FC chips according to the present invention; Figure 3 This is a front view of a vertical bonding and FC chip packaging structure of the present invention after removing the bottom substrate; Figure 4 A top view of a packaging structure using vertical bonding and FC chips according to the present invention; Figure 5 This is a front view of a vertical bonding and FC chip packaging structure and a combined external connection view of the present invention.

[0017] In the figure, 1- solder ball; 2- top substrate; 3- FOW chip adhesive film; 4- chip; 5- chip adhesive film; 6- bottom substrate; 7- chip glue; 8- FC chip bump; 9- FC chip; 10- solder wire; 11- plastic filling; 12- another IC DETAILED DESCRIPTION In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0020] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0021] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0022] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0024] like Figure 3 As shown, the present invention provides a method for packaging a chip using vertical bonding and FC, comprising: S101 arranges a substrate carrier, including a top substrate 2 and a bottom substrate 6; S102: arranging a chip layer and an FC chip 9 on the bottom substrate; S103 uses vertical bonding to connect the chip layer and the FC chip 9 to the top substrate 2 to achieve a path, forming a preliminary product; S104 packages the preliminary product, and removes the bottom substrate 6 after packaging.

[0025] The bottom substrate 6 is made of glass fiber board.

[0026] Glass fiber board has high strength, good insulation performance and thermal stability, which can effectively support the packaging structure and improve the reliability and stability of the packaging. At the same time, it also has good processing performance and is easy to manufacture and process into the required shape and size.

[0027] The chip layer is connected to the top substrate through the FOW chip adhesive film.

[0028] FOW (Film Over Wire) chip adhesive film can provide excellent electrical performance and mechanical strength, while having good thermal and chemical stability. This connection method helps to ensure a strong connection between the chip layer and the top substrate, improving the overall reliability of the package.

[0029] Solder balls 1 are arranged on the upper surface of the top substrate 2 .

[0030] As an external connection point, the solder ball 1 can be easily connected to other electronic components or circuit boards. This connection method has the characteristics of high density, low resistance and low inductance, which helps to improve the electrical performance of the package and the signal transmission speed.

[0031] Each chip layer of the chip layer is connected to the top substrate 2 through vertical bonding.

[0032] Vertical bonding technology can achieve high-density, high-reliability connections between the chip layer and the top substrate. This connection method can significantly reduce the package volume and improve the package integration and performance.

[0033] The FC chip 9 is bonded to the bottom substrate 6 by chip glue 7 .

[0034] The chip glue 7 can provide a strong bonding effect to ensure the stability and reliability of the FC chip 9 during the packaging process. At the same time, it can also provide a certain buffering and shock absorbing effect to help protect the FC chip 9 from mechanical damage.

[0035] The FC chip 9 is provided with a bump on one side close to the bottom substrate 6 , which can optimize the signal transmission path, reduce signal attenuation and reflection, and improve the electrical performance of the package.

[0036] A molding compound filler 11 is filled between the top substrate 2 and the bottom substrate 6 .

[0037] The plastic filling material 11 can provide additional mechanical support and protection, and enhance the overall structural strength of the package. At the same time, it can also prevent external factors such as moisture and dust from corroding and damaging the internal circuit of the package, and improve the reliability and stability of the package.

[0038] The chips on the chip layer are connected by a chip adhesive film 5 .

[0039] The chip adhesive film 5 can provide a stable connection effect, ensuring the electrical connection and signal transmission between the chips on the chip layer. At the same time, it can also provide a certain buffering and shock absorption effect, helping to protect the chip from mechanical damage. In addition, this connection method can also simplify the packaging process and reduce manufacturing costs.

[0040] The present invention also provides a packaging structure utilizing vertical bonding and FC chips, which is obtained based on a packaging method utilizing vertical bonding and FC chips.

[0041] Although the embodiments of the present invention are described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific embodiments and application fields, and the above-mentioned specific embodiments are only illustrative and instructive, rather than restrictive. Under the guidance of the specification, a person skilled in the art can also make many forms without departing from the scope of protection of the claims of the present invention, all of which belong to the scope of protection of the present invention.

Claims

1. A method for packaging a chip using vertical bonding and FC, characterized in that: include: Arranging a substrate carrier, including a top substrate (2) and a bottom substrate (6); Arranging a chip layer and an FC chip (9) on a bottom substrate; Using vertical bonding, the chip layer and the FC chip (9) are connected to the top substrate (2) to achieve a path, thereby forming a preliminary product; The preliminary product is packaged, and after the packaging is completed, the bottom substrate (6) is removed.

2. A method for packaging a chip using vertical bonding and FC according to claim 1, characterized in that: The bottom substrate (6) is made of a glass fiber board.

3. The method for packaging a chip using vertical bonding and FC according to claim 1, characterized in that: The chip layer is connected to the top substrate via a FOW chip adhesive film (3).

4. The method for packaging a chip using vertical bonding and FC according to claim 1, characterized in that: Solder balls (1) are arranged on the upper surface of the top substrate (2).

5. The method for packaging a chip using vertical bonding and FC according to claim 1, characterized in that: Each layer of chips in the chip layer is connected to the top substrate (2) via vertical bonding.

6. The method for packaging a chip using vertical bonding and FC according to claim 1, characterized in that: The FC chip (9) is bonded to the bottom substrate (6) by means of chip glue (7).

7. A method for packaging a chip using vertical bonding and FC according to claim 6, characterized in that: A bump is provided on one side of the FC chip (9) close to the bottom substrate (6).

8. The method for packaging a chip using vertical bonding and FC according to claim 1, characterized in that: A plastic encapsulation filler (11) is filled between the top substrate (2) and the bottom substrate (6).

9. The method for packaging a chip using vertical bonding and FC according to claim 1, characterized in that: The chips (4) on the chip layer are connected via a chip adhesive film (5).

10. A chip packaging structure using vertical bonding and FC, characterized in that: Based on any one of claims 1-9, the method is obtained by packaging using vertical bonding and FC chip packaging methods.

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