Wafer and manufacturing method thereof
By forming doped regions and anti-warping structures in the substrate structure of the wafer, the warpage of the wafer is controlled, and a patterned film layer is formed on the epitaxial layer to inject the second doped region, the serious problem of wafer warping is solved, the photolithography accuracy is improved and the transport risk is reduced.
Patent Information
- Application Number
- CN202510008512.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-11
AI Technical Summary
The serious warpage problems arise during the wafer production process affect the lithography accuracy and the performance of transistor devices, while increasing the risk of scribing and chipping of wafers during the transport process.
By forming a plurality of first doped regions at the epitaxial layer of the substrate structure, and forming an anti-warping structure on both sides of the epitaxial layer and the substrate, the warpage of the wafer is controlled. The first anti-warping structure is then removed, and a patterned film layer is formed on the side where the epitaxial layer is away from the substrate, and a second set type ions are injected into the epitaxial layer using it as a mask to form a second doping region.
It effectively improves the warping problem of wafers during production, improves the accuracy of ion implantation positions, and reduces the risk of wafers being scribbled and broken during transport.
Smart Images
Figure CN119812093A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer and a manufacturing method thereof. Background Art
[0002] In the production process of transistor devices, the flatness of the wafer substrate has a crucial impact on the process technology such as lithography and etching. The existence of warpage will change the shape of the wafer, thereby reducing the lithography accuracy during lithography, seriously affecting the performance of the manufactured transistor device. At the same time, the existence of a large warpage will also increase the risk of wafer dicing and breakage during the transportation process. Summary of the invention
[0003] The present invention provides a wafer and a method for manufacturing the same, which can improve the serious warping problem of the wafer during the manufacturing process, thereby improving the accuracy of the ion implantation position and reducing the risk of the wafer being diced and broken during transportation.
[0004] According to one aspect of the present invention, a wafer manufacturing method is provided, the wafer manufacturing method comprising:
[0005] Providing a substrate structure, wherein the substrate structure comprises a substrate and an epitaxial layer located on one side of the substrate;
[0006] Implanting a first set type of ions at a plurality of set positions of the epitaxial layer to form a plurality of first doping regions;
[0007] Forming a first anti-warping structure with a first set thickness on a side of the epitaxial layer away from the substrate, and forming a second anti-warping structure with a second set thickness on a side of the substrate away from the epitaxial layer, so that the warping of the current wafer is less than or equal to the set warping;
[0008] removing the first anti-warping structure;
[0009] forming a patterned thin film layer on a side of the epitaxial layer away from the substrate;
[0010] Using the patterned thin film layer as a mask, ions of a second set type are implanted into the epitaxial layer to form a second doped region.
[0011] Optionally, forming a patterned thin film layer on a side of the epitaxial layer away from the substrate includes:
[0012] forming an oxide film layer on a side of the epitaxial layer away from the substrate;
[0013] The oxide film layer is patterned to form the patterned film layer.
[0014] Optionally, the first anti-warping structure includes at least one first oxide layer and at least one first nitride layer;
[0015] The second anti-warping structure includes at least one second oxide layer and at least one second nitride layer.
[0016] Optionally, the first anti-warping structure includes at least two first oxide layers and at least two first nitride layers;
[0017] The second anti-warping structure includes at least two second oxide layers and at least two second nitride layers;
[0018] The first oxide layer and the first nitride layer are alternately stacked;
[0019] The second oxide layer and the second nitride layer are alternately stacked.
[0020] Optionally, the film layer adjacent to the epitaxial layer in the first anti-warping structure is the first oxide layer;
[0021] The film layer adjacent to the substrate in the second anti-warping structure is the second oxide layer.
[0022] Optionally, the material of the substrate and the material of the epitaxial layer both include silicon carbide.
[0023] Optionally, the material of the first oxide layer and the material of the second oxide layer both include silicon oxide;
[0024] The material of the first nitride layer and the material of the second nitride layer both include silicon nitride.
[0025] Optionally, the first set type ions and the second set type ions are the same type of ions.
[0026] Optionally, the first set type of ions includes P-type ions, and the second set type of ions includes N-type ions; or, the first set type of ions includes N-type ions, and the second set type of ions includes P-type ions.
[0027] According to another aspect of the present invention, a wafer is provided. The wafer is manufactured by the wafer manufacturing method provided by any embodiment of the present invention.
[0028] The embodiment of the present invention provides a wafer manufacturing method, which includes: after forming a plurality of first doping regions on the side of the epitaxial layer away from the substrate in the substrate structure, forming a first anti-warping structure with a first set thickness on the side of the epitaxial layer away from the substrate, and forming a second anti-warping structure with a second set thickness on the side of the substrate away from the epitaxial layer. The warping of the current wafer is controlled by controlling the value of the first set thickness and the value of the second set thickness, so that the warping of the current wafer is less than or equal to the set warping, thereby improving the problem of severe warping of the wafer caused by forming the first doping region. Then, the first anti-warping structure is removed, and then a patterned film layer is formed on the side of the epitaxial layer away from the substrate, and the second doping region is manufactured using the patterned film layer as a mask. Since the wafer is relatively flat before the second doping region is manufactured, the patterned film layer will not move during the process of forming the second doping region, thereby ensuring that the position accuracy of the formed second doping region is high. The wafer manufacturing method provided in this embodiment can improve the problem of severe warping of the wafer during the manufacturing process, thereby improving the accuracy of the ion implantation position, and reducing the risk of wafer being diced and broken during transportation.
[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0031] Figure 1 is a schematic flow chart of a wafer manufacturing method provided according to an embodiment of the present invention;
[0032] Figure 2-Figure 9 It is a schematic diagram of the structure of the process of manufacturing a wafer using the wafer manufacturing method provided by an embodiment of the present invention;
[0033] Fig.10 It is a schematic diagram of the structure of a wafer provided according to an embodiment of the present invention. DETAILED DESCRIPTION
[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0036] Figure 1 is a schematic diagram of a wafer manufacturing method according to an embodiment of the present invention, referring to Figure 1 The wafer manufacturing method provided in this embodiment includes the following steps:
[0037] S110, providing a substrate structure.
[0038] Among them, reference Figure 2 , Figure 2 2 is a schematic structural diagram of a substrate structure provided according to an embodiment of the present invention. The substrate structure provided in this embodiment includes a substrate 210 and an epitaxial layer 220 located on one side of the substrate 210 .
[0039] Specifically, the substrate 210 and the epitaxial layer 220 are both made of semiconductor materials. Exemplarily, the substrate 210 and the epitaxial layer 220 can be made of the same material or different materials. The wafer manufactured by the wafer manufacturing method provided in this embodiment includes a plurality of transistors. Among them, the transistors are P-type transistors or N-type transistors.
[0040] S120 , implanting first set type ions at multiple set positions of the epitaxial layer to form multiple first doping regions.
[0041] Specifically, refer to Figure 3 , Figure 3 The schematic diagram of the wafer structure after forming a plurality of first doping regions 230 is shown, and the first doping regions 230 are spaced apart from each other.
[0042] The size, depth and specific position of the set position in this embodiment can be set according to actual needs. The first set type of ions can be P-type ions or N-type ions. The P-type ions can be at least one of B, Al, Ga or In, and the N-type ions can be at least one of P, As or Sb ions.
[0043] S130, forming a first anti-warping structure with a first set thickness on a side of the epitaxial layer away from the substrate, and forming a second anti-warping structure with a second set thickness on a side of the substrate away from the epitaxial layer, so that the warping of the current wafer is less than or equal to the set warping.
[0044] Specifically, refer to Figure 4 , Figure 4 Schematic diagram of the wafer structure formed in step S130, the first anti-warping structure 240 covers each first doping region 230, and the second anti-warping structure 250 covers the substrate 210. In step S120, ions are usually implanted at high temperature to form multiple first doping regions 230. After the multiple first doping regions 230 are formed, the wafer may be severely warped. In this embodiment, the first anti-warping structure 240 is set to press down the warping generated in step S120, and the second anti-warping structure 250 can pull down the warping generated in step S120, so that the surface of the wafer becomes flat and avoids serious warping problems of the wafer.
[0045] The value of the first set thickness and the value of the second set thickness are related to the degree of warping of the wafer after step S120. The first set thickness can be equal to the second set thickness. The first set thickness and the second set thickness can affect the warping of the wafer. When forming the first anti-warping structure 240 and the second anti-warping structure 250, the warping of the wafer is controlled by controlling the value of the first set thickness and the value of the second set thickness, so that the warping of the wafer is finally not greater than the set warping, and the set warping can be 0. If the warping of the wafer is not greater than the set warping, the surface of the wafer is relatively flat, so that the current wafer will not be affected by the warping of the wafer in the subsequent process. The subsequent structure is formed, and the problem of wafer breakage caused by wafer warping is avoided.
[0046] S140, removing the first anti-warping structure.
[0047] Specifically, refer to Figure 5 , Figure 5 Schematic diagram of the wafer structure after the first anti-warping structure is removed. The first anti-warping structure can be removed by wet etching. For example, a HF solution of a set concentration is sprayed on the surface of the first anti-warping structure to remove the first anti-warping structure, and DIW (deionized water) and N are formed on the surface of the second anti-warping structure 250. 2The protective film prevents the HF solution from corroding the second warpage preventing structure 250, so as to retain the second warpage preventing structure 250. The set concentration may be 49%.
[0048] S150, forming a patterned thin film layer on a side of the epitaxial layer away from the substrate.
[0049] Specifically, refer to Figure 6 , Figure 6 The schematic diagram of the wafer structure for forming the patterned film layer 260 is shown in FIG. 2 . The patterned film layer 260 may include a plurality of set through holes 271, and the set through holes 271 expose a portion of the epitaxial layer 220. Doping ions are injected into the epitaxial layer 220 through the set through holes 271 to form a second doping region. The patterned film layer 260 may press down the wafer formed in step S140 again to further reduce the warpage of the current wafer.
[0050] It should be noted that Figure 6 The pattern of the patterned thin film layer 260 shown is only an embodiment, and the pattern of the patterned thin film layer 260 can be set according to actual needs.
[0051] S160 , using the patterned thin film layer as a mask, injecting a second set type of ions into the epitaxial layer to form a second doped region.
[0052] Specifically, refer to Figure 7 , Figure 7 The second doping region 270 is a schematic diagram of a wafer structure including a second doping region 270, which may be adjacent to the first doping region 230. In this embodiment, the second doping region 270 is manufactured using the patterned film layer 260 as a mask, without using a photolithography process to form a photoresist mask layer.
[0053] Steps S130 to S150 reduce the warpage of the wafer. During the process of forming the second doped region 270 in step S160, the flattened wafer allows the set through hole 271 in the patterned thin film layer 260 to remain stable, thereby improving the position accuracy of forming the second doped region 270 and avoiding the set through hole 271 from being offset during the process of forming the second doped region 270 due to the high warpage of the wafer.
[0054] After step S160 , the patterned film layer and the second anti-warping structure may be removed.
[0055] Specifically, refer to Figure 8 , Figure 8 The schematic diagram of the wafer structure after removing the patterned film layer and the second anti-warping structure. After removing the patterned film layer and the second anti-warping structure, other structures of the transistor can be manufactured, such as the active layer, gate, gate electrode and other structures of the transistor.
[0056] Steps S130 to S150 can improve the warpage of the wafer. When other structures of the transistor are subsequently manufactured, steps S130 to S150 can be repeatedly performed to avoid the problem of inaccurate precision of other structures caused by severe wafer warpage.
[0057] The present embodiment provides a wafer manufacturing method, which includes: after forming a plurality of first doping regions on the side of the epitaxial layer away from the substrate in the substrate structure, forming a first anti-warping structure with a first set thickness on the side of the epitaxial layer away from the substrate, and forming a second anti-warping structure with a second set thickness on the side of the substrate away from the epitaxial layer. The warping of the current wafer is controlled by controlling the value of the first set thickness and the value of the second set thickness, so that the warping of the current wafer is less than or equal to the set warping, thereby improving the problem of severe warping of the wafer caused by the formation of the first doping region. Then, the first anti-warping structure is removed, and then a patterned film layer is formed on the side of the epitaxial layer away from the substrate, and the second doping region is manufactured using the patterned film layer as a mask. Since the wafer is relatively flat before the second doping region is manufactured, the patterned film layer will not move during the process of forming the second doping region, thereby ensuring that the position accuracy of the formed second doping region is high. The wafer manufacturing method provided in the present embodiment can improve the problem of severe warping of the wafer during the manufacturing process, thereby improving the accuracy of the ion implantation position, and reducing the risk of wafer being diced and broken during transportation.
[0058] Optionally, forming a patterned thin film layer on a side of the epitaxial layer away from the substrate comprises the following steps:
[0059] S151. Form an oxide film layer on a side of the epitaxial layer away from the substrate.
[0060] Specifically, refer to Fig. 9 , Fig. 9 To form a wafer structure diagram of an oxide film layer 261, a chemical vapor deposition (CVD) process can be used to form the oxide film layer 261 on the side of the epitaxial layer 220 away from the substrate 210. The oxide film layer 261 has a certain pressure on the epitaxial layer 220, which can make the wafer after step S151 smoother and further improve the warping problem of the wafer.
[0061] S152, patterning the oxide film layer to form a patterned film layer.
[0062] Specifically, the oxide film layer can be patterned by photolithography to form a patterned film layer, and then the photoresist can be removed by ashing and wet method to form a patterned film layer. Figure 6 The wafer structure is shown.
[0063] Optional, continue to refer to Figure 4The first anti-warping structure 240 includes at least one first oxide layer 241 and at least one first nitride layer 242 ; the second anti-warping structure 250 includes at least one second oxide layer 251 and at least one second nitride layer 252 .
[0064] Specifically, the first anti-warping structure 240 and the second anti-warping structure 250 can be formed in a furnace tube. The material of the first oxide layer 241 and the material of the second oxide layer 251 can be the same, and the material of the first nitride layer 242 and the material of the second nitride layer 252 can be the same. The thickness of the first oxide layer 241 and the thickness of the second oxide layer 251 can also be the same, and the thickness of the first nitride layer 242 and the thickness of the second nitride layer 252 can also be the same. The first anti-warping structure 240 includes at least one first oxide layer 241 and at least one first nitride layer 242, and the second anti-warping structure 250 includes at least one second oxide layer 251 and at least one second nitride layer 252, which can further reduce the warpage of the wafer.
[0065] Optional, Fig.10 is a schematic diagram of a structure of a wafer provided according to an embodiment of the present invention, with reference to Fig.10 The first anti-warping structure 240 includes at least two first oxide layers 241 and at least two first nitride layers 242; the second anti-warping structure 250 includes at least two second oxide layers 251 and at least two second nitride layers 252; the first oxide layers 241 and the first nitride layers 242 are alternately stacked; the second oxide layers 251 and the second nitride layers 252 are alternately stacked. This arrangement can further reduce the warpage of the wafer.
[0066] Specifically, the thickness of each first oxide layer 241 in the first anti-warping structure 240 may be the same or different, and the thickness of each first nitride layer 242 in the first anti-warping structure 240 may be the same or different. The thickness of each second oxide layer 251 in the second anti-warping structure 250 may be the same or different, and the thickness of each second nitride layer 252 in the second anti-warping structure 250 may be the same or different. This embodiment can control the warpage of the current wafer by controlling the thickness of each first oxide layer 241, the thickness of each first nitride layer 242, the thickness of each second oxide layer 251, and the thickness of each second nitride layer 252.
[0067] Optional, continue to refer to Figure 4 or Fig.10The film layer adjacent to the epitaxial layer 220 in the first anti-warping structure 240 is the first oxide layer 241; the film layer adjacent to the substrate 210 in the second anti-warping structure 250 is the second oxide layer 251. This arrangement allows the first oxide layer 241 to grow better on the epitaxial layer 220, and the second oxide layer 251 to grow better on the substrate 210, thereby preventing the first anti-warping structure 240 and the second anti-warping structure 250 from detaching from the substrate structure.
[0068] Optionally, the material of the substrate and the material of the epitaxial layer both include silicon carbide.
[0069] Specifically, silicon carbide materials have the characteristics of large bandgap width, strong critical breakdown electric field, high thermal conductivity, high temperature resistance and excellent heat dissipation performance. Transistors in wafers made of silicon carbide materials work in high temperature environments without the need for additional heat dissipation devices, thereby improving the application scenarios of transistors.
[0070] Optionally, the material of the first oxide layer and the material of the second oxide layer both include silicon oxide; the material of the first nitride layer and the material of the second nitride layer both include silicon nitride.
[0071] Specifically, silicon oxide and silicon nitride are low in cost and easy to obtain. Using silicon oxide to make the first oxide layer and the second oxide layer, and using silicon nitride to make the first nitride layer and the second nitride layer can reduce the production cost of the wafer. In addition, the material for setting the first oxide layer and the material for the second oxide layer both include silicon oxide, and the material for the first nitride layer and the material for the second nitride layer both include silicon nitride, so that the first oxide layer, the second oxide layer, the first nitride layer and the second nitride layer can be closely connected to the respective adjacent film layers.
[0072] Optionally, the first set type ions and the second set type ions are the same type of ions.
[0073] Specifically, the first set type ions and the second set type ions may both be P-type ions, or the first set type ions and the second set type ions may both be N-type ions. When the first set type ions and the second set type ions are the same type of ions, the ion concentration in the first doping region may be different from the ion concentration in the second doping region. For example, the ion concentration in the first doping region may be greater than the ion concentration in the second doping region.
[0074] Optionally, the first set type of ions includes P-type ions, and the second set type of ions includes N-type ions; or, the first set type of ions includes N-type ions, and the second set type of ions includes P-type ions.
[0075] Specifically, the first set type of ions may be opposite to the second set type of ions.
[0076] This embodiment also provides a wafer, which is manufactured by the wafer manufacturing method provided by any embodiment of the present invention.
[0077] Specifically, the wafer produced by the wafer production method provided by any embodiment of the present invention has a small warpage.
[0078] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0079] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A wafer manufacturing method, characterized in that: include: Providing a substrate structure, wherein the substrate structure comprises a substrate and an epitaxial layer located on one side of the substrate; Implanting a first set type of ions at a plurality of set positions of the epitaxial layer to form a plurality of first doping regions; Forming a first anti-warping structure with a first set thickness on a side of the epitaxial layer away from the substrate, and forming a second anti-warping structure with a second set thickness on a side of the substrate away from the epitaxial layer, so that the warping of the current wafer is less than or equal to the set warping; removing the first anti-warping structure; forming a patterned thin film layer on a side of the epitaxial layer away from the substrate; Using the patterned thin film layer as a mask, ions of a second set type are implanted into the epitaxial layer to form a second doped region.
2. The wafer manufacturing method according to claim 1, characterized in that: The step of forming a patterned thin film layer on a side of the epitaxial layer away from the substrate comprises: forming an oxide film layer on a side of the epitaxial layer away from the substrate; The oxide film layer is patterned to form the patterned film layer.
3. The wafer manufacturing method according to claim 1, characterized in that: The first anti-warping structure includes at least one first oxide layer and at least one first nitride layer; The second anti-warping structure includes at least one second oxide layer and at least one second nitride layer.
4. The wafer manufacturing method according to claim 3, characterized in that: The first anti-warping structure includes at least two first oxide layers and at least two first nitride layers; The second anti-warping structure includes at least two second oxide layers and at least two second nitride layers; The first oxide layer and the first nitride layer are alternately stacked; The second oxide layer and the second nitride layer are alternately stacked.
5. The wafer manufacturing method according to claim 3 or 4, characterized in that: The film layer adjacent to the epitaxial layer in the first anti-warping structure is the first oxide layer; The film layer adjacent to the substrate in the second anti-warping structure is the second oxide layer.
6. The wafer manufacturing method according to claim 1, characterized in that: The material of the substrate and the material of the epitaxial layer both include silicon carbide.
7. The wafer manufacturing method according to claim 3, characterized in that: The material of the first oxide layer and the material of the second oxide layer both include silicon oxide; The material of the first nitride layer and the material of the second nitride layer both include silicon nitride.
8. The wafer manufacturing method according to claim 1, characterized in that: The first set type ions and the second set type ions are the same type of ions.
9. The wafer manufacturing method according to claim 1, characterized in that: The first set type of ions includes P type ions, and the second set type of ions includes N type ions; or, the first set type of ions includes N type ions, and the second set type of ions includes P type ions.
10. A wafer, characterized in that: The wafer is manufactured by the wafer manufacturing method according to any one of claims 1 to 9.