Compound semiconductor integrated device and preparation method thereof

Abstract

The invention provides a compound semiconductor integrated device and a preparation method thereof, and belongs to the technical field of semiconductor devices. According to the method, a plurality of device regions are prepared on a compound semiconductor heteroepitaxial wafer, isolation grooves are etched among the device regions needing to be isolated from one another, the isolation grooves are filled, then an interconnection dielectric layer is manufactured on the surface of the epitaxial wafer, through holes are formed in the interconnection dielectric layer, and the compound semiconductor heteroepitaxial wafer is formed. Depositing metal in the through hole and on the surface of the interconnection dielectric layer to form electrical connection between the device regions; and finally, the substrate is thinned, so that the isolation groove completely penetrates through the substrate. Through the method, substrate potential isolation of an integrated device or / and an integrated circuit can be realized on the heteroepitaxial substrate. High-frequency signals can be blocked between the substrates of the prepared compound semiconductor integrated device, and adverse effects on normal functions of a single device or a circuit in the integrated device due to a parasitic electrical structure are avoided.

Description

[0001] This application claims priority to Chinese patent application No. 202411041105.1 filed with the State Intellectual Property Office on July 31, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a compound semiconductor integrated device and a preparation method thereof. Background Art

[0003] Generally, planar compound semiconductor devices based on heteroepitaxial substrates need to connect the device source to the device substrate potential so that all parts of the device active area are on the substrate with the same potential. For example, in existing commercial silicon-based gallium nitride power transistors, the P-type high-conductivity Si substrate connected to the source makes each device cell connected in parallel with an interdigitated structure have the same switching characteristics, ensuring that the current in each device cell is evenly distributed; at the same time, the device substrate at the same bias as the device source can suppress the dynamic characteristic degradation related to defects in the compound epitaxial layer. However, when multiple power devices working in coordination are prepared on the same silicon-based gallium nitride substrate (forming circuits such as half-bridge and full-bridge converters), the switching states of each device are different and the source potentials of each device are different. For example, in a half-bridge circuit, when the high-side transistor is turned on, the high-voltage source of the high-side transistor forms electrical stress on other devices through the substrate, causing crosstalk on the substrate. These crosstalks will interfere with the operation of other devices, and even directly form a short circuit between the device sources, causing the circuit to burn out.

[0004] In addition, the development of compound semiconductor integrated circuit technology also requires further integration of functional modules such as logic circuits, drive circuits, and protection circuits. These circuit modules have a low operating drive voltage. For example, the gallium nitride logic circuit integrated with the gallium nitride power transistor in the EPC23101 chip of EPC Power Conversion requires an additional 5V or 3.3V drive voltage. Since other circuit modules and power devices are prepared on the same substrate, if the substrate where the circuit module is located is subjected to crosstalk caused by electrical stress, the corresponding circuit module will fail. This problem will become more serious when the circuit power loop level conversion speed and operating voltage are increased, which seriously limits the performance of power integrated circuits on compound heteroepitaxial substrates.

[0005] Therefore, a major problem facing the integration of compound semiconductor power devices is how to isolate high-frequency and high-voltage electrical stresses. This problem is particularly critical for compound semiconductor integration platforms obtained based on heteroepitaxial growth.

[0006] The existing technology 1, "200V Enhancement-Mode p-GaN HEMTs Fabricated on 200mm GaN-on-SOI With Trench Isolation for Monolithic Integration" (DOI: 10.1109 / LED.2017.2703304), is based on GaN-on-SOI (SOI: silicon on insulator) isolation technology. By inserting a silicon dioxide (SiO2) insulating layer into the Si substrate, the Si (111) substrate voltage in the power device drops in the SiO2 insulating layer in the vertical direction, preventing it from entering the compound buffer layer under other devices through the Si (100) substrate. In the lateral direction, the isolation between devices is achieved by trenches filled with insulating materials. This solution can improve the substrate withstand voltage capability by increasing the thickness of the SiO2 insulating layer to adapt to different operating voltages; in the homogeneous integrated circuit based on this solution, the same GaN-on-SOI isolation structure is present under the power switch tube and the low-voltage circuit, which can achieve better independent isolation effect. However, in this solution, the isolation capacitance of the SiO2 insulation layer is large, and the capacitive reactance is small at high frequencies. Crosstalk coupling is prone to occur under high-frequency switching, resulting in isolation failure. In addition, the thermal conductivity of SiO2 is low, which is not conducive to system heat dissipation. The complex stress modulation engineering in this solution also increases the difficulty of compound semiconductor epitaxy technology and increases the substrate cost.

[0007] Prior art 2 US20230282710A1 discloses that in GaN-on-Si technology, N-type doping is performed on the surface of a P-type Si substrate to form a top-down NP junction in the Si substrate. The source of the device is connected to the N-Si layer through a metal plug, and the P-type Si potential at the bottom of the substrate is kept suspended. The high-side device in the half-bridge drops the voltage in the depletion region below itself through the reverse-biased PN junction below, preventing it from entering the compound buffer layer below other devices in the circuit through the substrate; and the lateral crosstalk is blocked by a trench filled with insulating material. The trench depth requires the removal of all compound semiconductor materials and all N-Si in the trench to avoid lateral short circuits between device substrates. The advantages of this solution are that the substrate cost is low; the substrate heat dissipation performance is consistent with conventional GaN-on-Si technology, and the industry acceptance is high; the unit capacitance of the PN junction capacitor is reduced under high-voltage reverse bias, and the impedance to high-frequency electrical signals is increased, which can achieve better high-frequency isolation relative to GaN-on-SOI technology. However, in this solution, since P-type Si is used as the PN junction voltage-withstanding structure, the doping concentration in this area must be controlled, and there are requirements for the manufacturing type of the substrate sheet; however, the PN junction voltage-withstanding capability formed by the III-V material epitaxial technology based on the high-conductivity P-type Si substrate is limited and cannot be used to achieve high-voltage integration of power devices above 650V.

[0008] The substrate in the prior art three "GaN on Engineered Bulk Si (GaN-on-EBUS) Substrate for Monolithic Integration of High- / Low-Side Switches in Bridge Circuits" (DOI: 10.1109 / TED.2022.3178361) uses a low-doped N-type Si substrate, and P-type ion implantation is performed on the crystal surface of the compound material epitaxy to form a PN junction for blocking the high-side potential, and the crosstalk generated by the high-side potential during the switching process of the half-bridge circuit is blocked by reverse biasing the PN junction. Its characteristic is that in a half-bridge circuit based on GaN-on-EBUS (EBUS: engineered bulk silicon), the circuit substrate N-type Si is connected to the bus voltage connected to the half-bridge, so that its potential is the same as the half-bridge input voltage. As a result, the PN junction in the substrate below the low-side switch tube is always in a reverse bias or zero bias state, blocking the high-side voltage transmitted from the SW node (switch node) to the substrate when the high-side switch tube is turned on. The advantages of this solution are that the substrate cost is low; the heat dissipation performance of the substrate is consistent with that of conventional GaN-on-Si technology, and the industry acceptance is high; the unit capacitance of the PN junction capacitor decreases under high-voltage reverse bias, and the impedance to high-frequency electrical signals increases, which can achieve better high-frequency isolation than GaN-on-SOI technology; the bidirectional transient voltage suppression diode can be integrated inside the substrate for overvoltage protection. However, this solution also has shortcomings. For example, when working, the bottom of the substrate needs to be connected to the input voltage of the half-bridge circuit, so that the PN junction in the substrate is in a high-voltage reverse bias and high-electrical stress state for a long time, which is not conducive to the life of the circuit; the main pressure-bearing structure on the substrate is below the high-side switch tube of the half-bridge, and only one side withstands the pressure; using low-doped N-type Si in the Si substrate as a pressure-bearing structure also has strict requirements on the processing and manufacturing method of the Si substrate. Low N-type doping (high resistance) Si substrates are mostly prepared by zone melting (FZ), and their low mechanical strength problem further affects the pressure-bearing performance of the epitaxial layer of III-V materials. The working voltage of the GaN power half-bridge prepared by this method cannot reach 650V. Summary of the invention

[0009] Based on the above technical problems, the present invention provides a compound semiconductor integrated device and a method for preparing the same. By opening an isolation groove that penetrates the compound semiconductor heteroepitaxial wafer and filling the isolation groove, devices with electrical functions are isolated from each other. The compound semiconductor integrated device prepared by the preparation method can block high-frequency signals, and will not adversely affect the normal function of a single device or circuit in the integrated device due to parasitic electrical structures.

[0010] In order to achieve the above object, the present invention adopts the following technical solution: A method for preparing a compound semiconductor integrated device comprises the following steps: S1. providing a compound semiconductor heteroepitaxial wafer, wherein the compound semiconductor heteroepitaxial wafer comprises a substrate and a compound semiconductor layer deposited on the substrate; S2, preparing a plurality of device regions on the compound semiconductor heteroepitaxial wafer, each of the device regions comprising at least one device or at least one circuit formed by interconnecting a plurality of devices; S3, forming an isolation groove between the device regions that need to be isolated from each other and forming an interconnect dielectric layer on the surface of the compound semiconductor layer away from the substrate; the isolation groove is filled with a filling material and annealed; S4, opening a through hole in the interconnect dielectric layer, and depositing metal in the through hole and on the surface of the interconnect dielectric layer away from the compound semiconductor layer, so as to form an electrical connection between the isolated device regions; S5. Thinning the side of the substrate away from the compound semiconductor layer, so that the isolation groove penetrates the thinned substrate.

[0011] In a preferred embodiment, step S3 includes any one of the following steps: A. Depositing a first dielectric layer and a second dielectric layer in sequence on the upper surface of the compound semiconductor layer; forming a first isolation groove by etching between the device regions that need to be isolated from each other; the first isolation groove penetrates the first dielectric layer, the second dielectric layer and the compound semiconductor layer; etching a second isolation groove in the substrate; the second isolation groove is connected to the first isolation groove, and the bottom of the second isolation groove is located in the substrate; spin coating a filling material on the upper surface of the obtained device structure and in the first isolation groove and the second isolation groove, and annealing; B. Forming a first isolation groove by etching between the device regions that need to be isolated from each other; the first isolation groove penetrates the compound semiconductor layer; depositing a first dielectric layer and a second dielectric layer in sequence on the surface of the compound semiconductor layer away from the substrate and on the sidewall of the first isolation groove; etching a second isolation groove in the substrate; the second isolation groove is connected to the first isolation groove, and its bottom is located in the substrate; spin coating a filling material on the upper surface of the obtained device structure and in the first isolation groove and the second isolation groove, and annealing; C. Forming a first isolation groove by etching between the device regions to be isolated from each other; the first isolation groove penetrates the compound semiconductor layer; etching a second isolation groove in the substrate; the second isolation groove is connected to the first isolation groove, and the bottom of the second isolation groove is located in the substrate; spin coating a filling material on the upper surface of the obtained device structure and in the first isolation groove and the second isolation groove, and annealing; D. Form a first isolation groove by etching between the device areas that need to be isolated from each other; the first isolation groove penetrates the compound semiconductor layer; deposit a first dielectric layer on the sidewall of the first isolation groove and the surface of the compound semiconductor layer facing away from the substrate; etch a second isolation groove in the substrate; the second isolation groove is connected to the first isolation groove, and its bottom is located in the substrate; deposit a second dielectric layer on the surface of the first dielectric layer exposed to the outside, and on the sidewall of the second isolation groove or the sidewall and bottom of the second isolation groove; spin-coat a filling material on the upper surface of the obtained device structure and inside the first isolation groove and inside the second isolation groove, and anneal.

[0012] In a further preferred solution, step A further includes the following steps: performing ion implantation on the compound semiconductor layer on both sides of the first isolation trench to form a high resistance region.

[0013] In a further preferred solution, step B further includes the following steps: performing ion implantation on the compound semiconductor layer on both sides of the first isolation trench to form a high resistance region.

[0014] In a further preferred solution, step C also includes the following steps: performing ion implantation on the compound semiconductor layer on both sides of the first isolation trench to form a high resistance region.

[0015] In a further preferred solution, step D also includes the following steps: performing ion implantation on the compound semiconductor layer on both sides of the first isolation trench to form a high resistance region.

[0016] In a further preferred embodiment, in any one of steps A to D, the step of spin coating the filling material and the step of annealing are performed alternately multiple times.

[0017] In a further preferred embodiment, when step S3 includes step C, the method for forming the interconnect dielectric layer in step S3 includes step (a) or step (b); when step S3 includes any one of steps A, B, and D, the method for forming the interconnect dielectric layer in step S3 includes any one of steps (a) to (c); wherein steps (a) to (c) are as follows: (a) thinning the filling material on the upper surface of the device structure, and using the remaining filling material on the upper surface as the interconnect dielectric layer; (b) removing all the filling materials on the upper surface of the device structure, and retaining the filling materials in the first isolation trench and the second isolation trench; and then depositing a dielectric material on the upper surface of the obtained device structure to obtain the interconnect dielectric layer; (c) removing all filling materials on the upper surface of the device structure and retaining the filling materials in the first isolation trench and the second isolation trench; the first dielectric layer, the second dielectric layer and the filling material in the first isolation trench together constitute the interconnect dielectric layer.

[0018] In a further preferred embodiment, the dielectric material in step (b) includes at least one of silicon nitride, silicon dioxide, silicon oxynitride, aluminum nitride, aluminum oxide, and aluminum oxynitride.

[0019] In a preferred embodiment, the substrate includes at least one of a silicon substrate, a GaN substrate, a GaO substrate, a SiC substrate, a diamond substrate, an SOI substrate, and a sapphire substrate.

[0020] In a preferred embodiment, the material of the compound semiconductor layer includes at least one of GaN, GaAs, SiC, GaO, AlN, and AlGaN.

[0021] In a preferred embodiment, the filling material includes at least one of polyimide, polybenzocyclobutene, poly(p-phenylene benzobisoxazole), and spin-on glass.

[0022] In a preferred embodiment, the device is selected from one or more of the following device types: a transistor, a diode, a passive device, a sensor for detecting non-electrical physical quantities, a light emitter and a waveguide.

[0023] In a preferred embodiment, the annealing in step S3 includes the following steps: heating from room temperature to 95-105°C and keeping the temperature constant for 10-30 minutes; continuing to heat to 160-260°C and keeping the temperature constant for 10-30 minutes; further heating to 280-360°C and keeping the temperature constant for 10-30 minutes; lowering the temperature to below 80°C.

[0024] The present invention also provides a compound semiconductor integrated device prepared by the preparation method described in any one of the above schemes.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) In the structure of the compound semiconductor integrated device prepared by the present invention, the isolation groove completely cuts off the uncontrollable electrical connection between the isolated device area and the other circuit structures of the integrated device in the compound semiconductor layer and the substrate, and provides an independent substrate potential for a single device or circuit through a metal plug. (2) Since the present invention does not rely on the insulating insertion layer or PN junction depletion region in the substrate to achieve the blocking of substrate crosstalk, low-cost substrate materials and types can be selected. (3) The solution of the present invention is suitable for isolating vertical structure devices, and can realize the integration of vertical structure devices or / and planar circuits on heteroepitaxial substrates. (4) The filling material used to fill the isolation groove has a low dielectric constant and good voltage resistance, so that the integrated device can achieve the blocking of high-frequency signals, and will not have an adverse effect on the normal function of a single device or circuit in the integrated device due to the parasitic electrical structure. (5) The solution of the present invention addresses the complex stress conditions in compound heteroepitaxial substrates. Before substrate thinning, the etching of deep isolation trenches, the filling and solidification of filling materials that serve as mechanical connections, and the metal interconnection between isolation regions are completed. This avoids the problems of wafer warping, post-processing difficulties, and low yield that occur after thinning of the compound heteroepitaxial substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic structural diagram of compound semiconductor heteroepitaxial growth in step S1 of a specific embodiment of the present invention; Figure 2 A schematic diagram of the structure obtained in step S2 of a specific embodiment of the present invention; Figure 3 A schematic diagram of a first isolation trench obtained in step S3 of a specific implementation of the present invention; Figure 4 A schematic diagram of a second isolation trench obtained in step S3 of a specific implementation of the present invention; Figure 5 A schematic diagram of filling a filling material in step S3 of a specific embodiment of the present invention; Figure 6 is a schematic diagram of a structure obtained when all the filling materials on the surface of the compound semiconductor layer are removed in step S3 of a specific embodiment of the present invention; Figure 7 This is a schematic diagram of a structure obtained by manufacturing an interconnect dielectric layer on the surface of a compound semiconductor layer in step S3 of a specific embodiment of the present invention; Figure 8 A schematic diagram of opening a through hole in step S4 of a specific embodiment of the present invention; Fig. 9A schematic diagram of a structure obtained by depositing metal in step S4 of a specific embodiment of the present invention; Fig.10 A schematic diagram of the structure of a compound semiconductor integrated device obtained in step S5 of a specific embodiment of the present invention; Fig.11 A schematic diagram of the structure of another compound semiconductor integrated device provided in the present invention; Fig.12 A schematic diagram of the structure of another compound semiconductor integrated device provided in the present invention; Fig.13 A schematic diagram of the structure of another compound semiconductor integrated device provided in the present invention; Fig.14 A schematic diagram of the structure of another compound semiconductor integrated device provided in the present invention; Figures 15-17 Various projection patterns of the second isolation trench of the compound semiconductor integrated device in the present invention on a plane parallel to the substrate; Fig.18 It is a schematic diagram of a structure obtained after depositing the first dielectric layer and the second dielectric layer in step S3 of another specific embodiment of the present invention; Fig.19 It is a schematic diagram of a structure obtained after etching the first isolation groove in step S3 of another specific embodiment of the present invention; Fig. 20 is a schematic diagram of a structure obtained after etching the second isolation trench in step S3 of another specific embodiment of the present invention; Fig.21 It is a schematic diagram of a structure obtained after filling the filling material in step S3 and opening the through hole in step S4 in another specific embodiment of the present invention; Fig. 22 It is a schematic diagram of a structure obtained after metal is deposited in step S4 and substrate is thinned in step S5 in another specific embodiment of the present invention; Fig.23 It is a schematic diagram of a structure obtained after etching a first isolation groove and depositing a first dielectric layer and a second dielectric layer in step S3 of another specific embodiment of the present invention; Fig.24 It is a schematic diagram of a structure obtained after etching the second isolation groove in step S3 of another specific embodiment of the present invention; Fig.25 It is a schematic diagram of a structure obtained after filling the filling material in step S3 and opening the through hole in step S4 in another specific embodiment of the present invention; Fig.26It is a schematic diagram of a structure obtained after metal is deposited in step S4 and substrate is thinned in step S5 in another specific embodiment of the present invention; Fig. 27 A schematic diagram of the structure of another compound semiconductor integrated device provided in the present invention; Fig.28 The figure is a schematic diagram of the structure of another compound semiconductor integrated device provided in the present invention.

[0027] In the figure: 1, substrate; 2, compound semiconductor layer; 21, high resistance region; 3, device region; 31, source; 32, drain; 33, gate; 41, first isolation trench; 42, second isolation trench; 51, first dielectric layer; 52, second dielectric layer; 6, filling material; 7, interconnection dielectric layer; 8, through hole; 9, metal; 10, metal plug. DETAILED DESCRIPTION

[0028] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0029] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate directions or positional relationships based on directions or positional relationships in the drawings of the specification, or directions or positional relationships in which the products of this application are usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above", and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below", and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The "vertical" in "vertical leakage" in this application means that the starting point and the end point of the voltage, current, etc. vector are not on the same structural plane. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0030] Reference Figure 1 to Figure 28 A specific embodiment of the present invention provides a method for preparing a compound semiconductor integrated device, comprising the following steps: S1. Provide a compound semiconductor heteroepitaxial wafer, wherein the compound semiconductor heteroepitaxial wafer comprises a substrate 1 and a compound semiconductor layer 2 deposited on a surface of the substrate.

[0031] As an example, the substrate 1 includes at least one of a silicon substrate, a GaN substrate, a GaO substrate, a SiC substrate, a diamond substrate, an SOI substrate, and a sapphire substrate. The function of the substrate is to provide a substrate required for a compound semiconductor layer (or a compound semiconductor epitaxial layer). The substrate can be conductive, insulating, or semi-insulating. The substrate can also be composed of a variety of substrate materials with different components, doping concentrations, and bandgap widths, for example, a Si substrate with multiple layers of different doping concentrations, doping types, or crystalline phase substrate layers, a 3C-SiC on Si substrate, or an SOI substrate.

[0032] As an example, the material of the compound semiconductor layer 2 includes at least one of GaN, GaAs, SiC, GaO, AlN, and AlGaN. The doping types or doping concentrations of the compound semiconductor layers may be the same or different. These compound semiconductor materials are deposited on the substrate as a single material or in a certain manner and sequence to combine and deposit on the substrate to play various functions such as modulating stress, modulating heterojunction polarization effect, modulating energy bands, and blocking leakage current.

[0033] As an example, the compound semiconductor heteroepitaxial wafer includes a P-type silicon substrate (or written as a P-type Si substrate) and a nitride semiconductor layer deposited on a surface of the P-type silicon substrate.

[0034] As an example, the nitride semiconductor layer includes at least one layer of Al x Ga 1-x N (0<x≤1) layer and at least one GaN layer, wherein the GaN layer is deposited on the P-type silicon substrate, the Al x Ga 1-x The N layer is deposited on the surface of the GaN layer away from the P-type silicon substrate. x Ga 1-x The doping type of the N layer is the same as or different from that of the GaN layer; x Ga 1-x The doping concentration of the N layer is the same as or different from that of the GaN layer. S2. Prepare multiple device regions 3 on the compound semiconductor heteroepitaxial wafer, each device region 3 including at least one device or at least one circuit formed by interconnecting several devices. Multiple device regions 3 are interconnected with each other in a certain topological structure by optical or / and electrical means.

[0035] As an example, a device or circuit may be connected to the substrate below the device through a metal plug 10 passing through the compound semiconductor layer 2 to control the potential of the substrate below the device region 3 or the circuit region.

[0036] As an example, the device is selected from one or more of the following device types: transistors, diodes, passive devices, sensors for detecting non-electrical physical quantities, light emitters, and waveguides. For example, various field effect transistors with a source 31, a drain 32, and a gate 33; diodes with an anode and a cathode; various passive devices such as resistors, capacitors, and inductors prepared on the same substrate; light emitting devices or sensors for detecting non-electrical physical quantities prepared on the same substrate; and waveguides prepared on the same substrate with electromagnetic signal modulation processing capabilities.

[0037] Specifically, the transistor includes at least one of a high electron mobility field effect transistor (HEMT), a metal-insulator-semiconductor field effect transistor (MISFET), a metal-oxide-semiconductor field effect transistor (MOSFET), and a bipolar junction transistor (BJT).

[0038] S3, forming isolation grooves between the device regions 3 that need to be isolated from each other and forming an interconnect dielectric layer on the surface of the compound semiconductor layer 2 facing away from the substrate; filling the isolation grooves with a filling material, which is an insulating material, and annealing.

[0039] In some preferred embodiments, the specific steps of step S3 are as follows: a first isolation groove 41 is formed by etching between the device regions 3 that need to be isolated from each other, and the first isolation groove 41 penetrates the compound semiconductor layer 2 ( Figure 3 ). A second isolation groove 42 is etched in the substrate 1. The second isolation groove 42 is connected to the first isolation groove 41, and its bottom is located in the substrate 1 ( Figure 4 The filling material is spin-coated on the surface of the compound semiconductor layer 2 facing away from the substrate 1 and the first isolation groove 41 and the second isolation groove 42 ( Figure 5 ). An interconnect dielectric layer is formed on the surface of the compound semiconductor layer 2 facing away from the substrate 1. Vacuum annealing is performed to solidify the filling materials in the first isolation trench 41 and the second isolation trench 42.

[0040] As an example, plasma etching is first performed to penetrate the compound semiconductor layer 2 and directly reach the surface of the substrate 1 to form a first isolation groove 41 ( Figure 3 Specifically, the compound semiconductor layer 2 is etched by plasma coupled reactive ion etching using Cl2 and BCl3 as reactive etching gases and N2 as carrier gas until the substrate 1 is exposed, that is, the etching is terminated at the surface where the substrate 1 contacts the compound semiconductor layer 2.

[0041] As an example, ion implantation may be further performed on the compound semiconductor layer 2 around the first isolation trench 41 to form a high resistance region 21 ( Figure 3 ), in order to reduce the vertical leakage of the edge of the device region 3 along the first isolation groove 41. The element of ion implantation is Ar or F or N. For example, when N ion implantation is used, a two-step ion implantation can be used. First, 2×10 14 cm -2 dose N ions, followed by 6.5×10 14 cm -2 Dose of N ions.

[0042] As an example, a first dielectric layer 51 ( Fig.11 The first dielectric layer 51 can passivate and protect the sidewalls of the device region 3 and the first isolation trench 41 (the sidewalls are compound semiconductor layers containing high resistance regions). The material of the first dielectric layer 51 is at least one of silicon nitride, aluminum nitride, silicon dioxide, aluminum oxide, silicon oxynitride, and aluminum oxynitride.

[0043] The width of the top and bottom of the first isolation groove 41 ( Figure 3 As an example, the angles between the sidewalls on both sides of the first isolation trench 41 and the surface of the compound semiconductor layer 2 contacting the substrate 1 are 20° to 60° (i.e., the width of the top of the first isolation trench is greater than the width of the bottom), for example, 20°, 30°, 40°, 50°, or 60°.

[0044] As an example, the second isolation groove 42 is etched in the P-type silicon substrate by deep silicon etching technology. The silicon substrate exposed at the bottom of the first isolation groove 41 is etched for multiple cycles using SF6 as etching gas to form the second isolation groove 42; between cycles, the sidewall of the second isolation groove 42 is passivated and protected using C4F8 as passivation gas to ensure that the inclination angle of the sidewall of the second isolation groove 42 is controllable. The first isolation groove 41 and the second isolation groove 42 are collectively referred to as isolation grooves.

[0045] As an example, along the direction from the substrate 1 to the compound semiconductor layer 2 , the depth of the second isolation trench 42 is greater than or equal to the thickness of the substrate 1 after thinning (ie, the second isolation trench 42 penetrates the thinned substrate 1 ).

[0046] As an example, a second dielectric layer 52 ( Fig.11 ), in order to strengthen the passivation protection of the device region 3 and the compound semiconductor layer 2. Under the joint action of the high resistance region 21, the first dielectric layer 51 and the second dielectric layer 52, the leakage channels on the two side walls of the isolation groove are passivated, which can further reduce the vertical leakage.

[0047] As an example, a material having resistance to CMP, silicon etching or corrosion (for example, silicon nitride or / and aluminum nitride) can be further used as the material of the second dielectric layer 52, and the second dielectric layer 52 is also deposited on the surface of the substrate 1 exposed at the bottom of the second isolation trench 42 ( Fig.13 ), so that the self-termination function can be achieved when the substrate 1 is thinned in the subsequent steps.

[0048] As an example, the number of the second isolation trenches 42 may be multiple ( Fig.14 ). The substrate 1 between two adjacent second isolation grooves 42 is retained as a spacing region, so that the second isolation grooves 42 can play the role of modulating lateral stress, modulating isolation region capacitance, and improving connection strength.

[0049] Depending on the thickness of the substrate after thinning in subsequent steps, the depth of the second isolation groove 42 from the compound semiconductor layer to the substrate is 100-350 μm; for example, 100 μm, 101 μm, 102 μm, 103 μm, 110 μm, 120 μm, 130 μm, ... 350 μm.

[0050] According to the circuit voltage level and the process conditions of the deep silicon etching equipment, the width of the second isolation groove 42 is 25-200 μm; for example, 25 μm, 30 μm, 40 μm, 50 μm, 100 μm, . . . 200 μm.

[0051] As an example, the filling material is a polymer, and the polymer includes at least one of polyimide (PI), polybenzocyclobutene (BCB), and poly(p-phenylenebenzobisoxazole) (PBO).

[0052] As an example, the filling material is a dielectric material formed by curing a solvent containing a dielectric material, such as spin-on glass (SOG).

[0053] As an example, the filling material 6 is a polymer, and the polymer layer on the surface of the compound semiconductor layer 2 facing away from the substrate 1 is removed by RIE etching (reactive ion etching) using a mixed gas of O 2 and CH 3 F.

[0054] The filling material on the surface of the compound semiconductor layer 2 facing away from the substrate 1 may be completely removed or partially removed. As an example, when the filling material on the surface of the compound semiconductor layer 2 facing away from the substrate 1 is partially removed (i.e., the filling material on the surface of the compound semiconductor layer 2 facing away from the substrate 1 is thinned, such as Fig.12 , Fig.13 As shown), the thickness of the material layer of the filling material retained on the surface of the compound semiconductor layer 2 is 2~10μm; for example, 2μm, 3μm, 4μm, 6μm, 8μm, 10μm. When the filling material is partially removed, the process can be simplified and the polymer material can be prevented from entering the high-cleanliness equipment; the retained material layer serves as the interconnect dielectric layer 7, which can provide a certain strength of mechanical support for the wafer in subsequent processes such as polishing and cutting. As an example, in some embodiments, when the filling material on the surface of the compound semiconductor layer 2 facing away from the substrate 1 is completely removed, a dielectric material is deposited on the surface of the compound semiconductor layer 2 facing away from the substrate 1 to obtain an interconnect dielectric layer 7 (see Figure 7 The interconnect dielectric layer 7 serves as a supporting material for the interconnect metal between the device regions 3 and also plays a role in passivation protection for the device regions 3 and the filling materials in the isolation trenches.

[0055] Further, in some other embodiments, after the first isolation trench 41 is etched, a first dielectric layer 51 is deposited on the sidewalls of the first isolation trench 41 and the surface of the compound semiconductor layer 2 facing away from the substrate 1. After the second isolation trench 42 is etched, a second dielectric layer 52 is deposited on the two sidewalls of the second isolation trench 42 and the surface of the first dielectric layer 51 facing away from the compound semiconductor layer 2. Then, a filling material is spin-coated on the upper surface of the second dielectric layer 52, inside the first isolation trench 41 and inside the second isolation trench 42, and vacuum annealing is performed to solidify the filling material. When the filling material on the surface of the second dielectric layer 52 facing away from the first dielectric layer 51 is completely removed, the first dielectric layer 51, the second dielectric layer 52 and the filling material 6 in the first isolation trench deposited on the surface of the compound semiconductor layer 2 facing away from the substrate 1 are used together as the interconnect dielectric layer 7 ( Fig. 27 Alternatively, when the filling material on the surface of the second dielectric layer 52 facing away from the first dielectric layer 51 is completely removed, a dielectric material is deposited on the upper surface of the second dielectric layer 52 to obtain an interconnect dielectric layer. Alternatively, the filling material on the upper surface of the second dielectric layer 52 is thinned, and the remaining filling material is used as the interconnect dielectric layer.

[0056] Furthermore, the second dielectric layer 52 is also deposited on the surface of the substrate 1 exposed at the bottom of the second isolation trench 42 ( Fig.28 ), so that the self-termination function can be achieved when the substrate 1 is thinned in the subsequent steps.

[0057] As an example, Figure 15-16 As shown, the projection of the second isolation groove 42 on a plane parallel to the substrate 1 is a combination of various pattern shapes (for example, Fig.15 The right angle in the left picture and the chamfer in the right picture, Fig.16 A combination of at least two of the obtuse angle in the left figure and the gear shape in the right figure) to adapt to the circuit shape, enhance the connection strength and adjust the stress at the connection ( Fig.15 When the projection pattern of the second isolation groove in the upper left figure is a right angle, stress concentration exists at the right angle). When the connection portion of the substrate 1 is narrow enough and the connection portion is far away from the metal plug 10 in the substrate 1, the electrical stress in the substrate 1 will be fully attenuated and the degree of electrical connection will be greatly limited. Therefore, the projection pattern of the second isolation groove 42 is Fig.17 The graph on . Among them, Fig.17 The left figure shows that the projection of the second isolation trench 42 is an incompletely closed figure; the middle figure shows that the second isolation trench 42 passes through the chip plane; and the right figure shows that the second isolation trench 42 does not pass through the chip plane. Fig.17 The unclosed portion in the left figure above indicates that the substrate 1 is not completely cut off by the second isolation groove 42, and the uncut portion cuts off the electrical stress with electrical resistance. Fig.17 In the right figure, the portion of the substrate 1 not penetrated by the second isolation groove 42 cuts off the electrical stress through electrical impedance.

[0058] The projection of the second isolation groove 42 on a plane parallel to the substrate 1 can also be Figure 15-16 At least one pattern shown and Fig.17 A combination of any of the patterns shown above.

[0059] Figure 15-17 The dotted frame around the upper substrate 1 represents the boundary of the chip after dicing.

[0060] As an example, taking the polymer as polyimide (or PI glue) as an example, the step of vacuum annealing to solidify the polymer specifically includes the following steps: (1) Raise the temperature from room temperature to 95-105°C (e.g., 95°C, 98°C, 100°C, 102°C, 105°C), and maintain the constant temperature for 10-30 min (e.g., 10 min, 20 min, 30 min) to ensure uniform distribution of the polymer; (2) Raise the temperature to 160-260°C (e.g., 160°C, 180°C, 200°C, 210°C, 240°C, 260°C), and maintain the temperature for 10-30 min (e.g., 10 min, 15 min, 20 min, 25 min, 30 min) to allow the solvent in the PI glue to fully evaporate; (3) Continue to raise the temperature to 280-360°C (for example, 280°C, 290°C, 300°C, 320°C, 340°C, 360°C), and keep the temperature constant for about 10-30 minutes (for example, 10 minutes, 20 minutes, 25 minutes, 30 minutes), so that the PI glue is cured to form a low dielectric polymer film layer; (4) Lower the temperature to below 80°C (e.g. 75°C, 70°C, 65°C).

[0061] It should be noted that when the filling material is a polymer, since different polymers have different fluidities and the filling effect is affected by the geometric dimensions of the isolation groove, the polymer can be filled into the isolation groove by "spin coating-curing" multiple times. That is, the step S3 of spin coating the filling material and the step of annealing to cure the filling material are performed alternately multiple times.

[0062] As an example, the method of depositing the dielectric material is selected from any one of plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD, including plasma enhanced atomic layer deposition), and inductively coupled chemical vapor deposition (ICPCVD).

[0063] As an example, the dielectric material includes at least one of silicon nitride, silicon dioxide, silicon oxynitride, aluminum nitride, aluminum oxide, and aluminum oxynitride.

[0064] In some other preferred embodiments, the specific steps of step S3 are as follows: a first dielectric layer 51 and a second dielectric layer 52 are sequentially deposited on the upper surface of the compound semiconductor layer 2 ( Fig.18 The first dielectric layer 51, the second dielectric layer 52 and the filling material 6 in the first isolation trench together serve as an interconnect dielectric layer 7 ( Figure 21-22 A first isolation groove 41 is formed by etching between the device regions 3 that need to be isolated from each other ( Fig.19 ). The first isolation groove 41 penetrates the first dielectric layer 51, the second dielectric layer 52 and the compound semiconductor layer 2. The second isolation groove 42 ( Fig. 20 The second isolation trench 42 is connected to the first isolation trench 41, and its bottom is located in the substrate 1. The filling material 6 is spin-coated on the upper surface of the second dielectric layer 52, the first isolation trench 41 and the second isolation trench 42 ( Fig.21 ); annealing. It is understood that after the solidified filling material on the upper surface of the second dielectric layer 52 is thinned, the remaining filling material can also be used as an interconnect dielectric layer. Alternatively, the solidified filling material on the upper surface of the second dielectric layer 52 can be completely removed, and then a dielectric material can be deposited on the upper surface of the second dielectric layer 52 as an interconnect dielectric layer. Similarly, the dielectric material includes at least one of silicon nitride, silicon dioxide, silicon oxynitride, aluminum nitride, aluminum oxide, and aluminum oxynitride.

[0065] Furthermore, ion implantation may be performed on the compound semiconductor layer 2 around the first isolation trench 41 to form a high resistance region 21 ( Figure 19-22 ), so as to reduce the vertical leakage along the edge of the device region 3 and the first isolation trench 41.

[0066] In some other preferred embodiments, the specific steps of step S3 are as follows: a first isolation groove 41 is formed by etching between the device regions 3 that need to be isolated from each other. The first isolation groove 41 penetrates the compound semiconductor layer 2. A first dielectric layer 51 and a second dielectric layer 52 are sequentially deposited on the surface of the compound semiconductor layer 2 facing away from the substrate 1 and on the sidewalls of the first isolation groove 41 ( Fig.23 The first dielectric layer 51, the second dielectric layer 52 and the filling material 6 in the first isolation groove on the surface of the compound semiconductor layer 2 facing away from the substrate 1 are used together as the interconnection dielectric layer 7 ( Figure 25-26). A second isolation groove 42 is etched in the substrate 1. The second isolation groove 42 is connected to the first isolation groove 41, and its bottom is located in the substrate 1. The filling material 6 is spin-coated on the upper surface of the second dielectric layer 52, the first isolation groove 41 and the second isolation groove 42; annealing. It can be understood that after the filling material solidified on the upper surface of the second dielectric layer 52 is thinned, the remaining filling material can also be used as an interconnect dielectric layer. Alternatively, the filling material solidified on the upper surface of the second dielectric layer 52 can be completely removed, and then a dielectric material can be deposited on the upper surface of the second dielectric layer 52 as an interconnect dielectric layer. Similarly, the dielectric material includes at least one of silicon nitride, silicon dioxide, silicon oxynitride, aluminum nitride, aluminum oxide, and aluminum oxynitride.

[0067] Furthermore, ion implantation may be performed on the compound semiconductor layer 2 around the first isolation trench 41 to form a high resistance region 21 ( Fig.23 ), so as to reduce the vertical leakage along the edge of the device region 3 and the first isolation trench 41.

[0068] S7, opening a through hole 8 in the interconnect dielectric layer 7 ( Figure 8 , Fig.21 , Fig.25 ), and depositing metal 9 in the through hole 8 and on the surface of the interconnect dielectric layer 7 facing away from the compound semiconductor layer 2, so as to form an electrical connection between the isolated device areas.

[0069] S8. Thinning the side of the substrate 1 away from the compound semiconductor layer 2, so that the second isolation groove 42 passes through the thinned substrate 1. After the substrate 1 is thinned, the substrate 1 at the bottom of the second isolation groove 42 is completely removed, so the electrical connection between the device areas on both sides of the isolation groove is cut off. At this time, the polymer in the isolation groove provides mechanical connection for the mutually isolated areas in the epitaxial wafer, and provides sufficient mechanical strength to ensure the reliability of the electrical connection (such as interconnect metal).

[0070] As an example, the method of thinning the substrate 1 includes at least one of chemical etching, polishing, chemical mechanical polishing (CMP), and dry etching.

[0071] As an example, a dry etching method is used to open holes in the interconnect dielectric layer 7. For example, holes are opened in the interconnect dielectric layer 7 by using F-based gas RIE etching technology.

[0072] As an example, metal 9 is prepared by electroplating Cu metal and then patterning it by metal etching; alternatively, the preparation method of metal 9 is as follows: Al metal is deposited by electron beam evaporation or magnetron sputtering, and then the wafer surface is patterned using a negative photoresist, and then excess Al metal is removed by a stripping process.

[0073] It can be understood that the same component structures in the embodiments of the present application can be prepared using the same method and materials.

[0074] The following content provides a specific and complete implementation scheme so that those skilled in the art can more clearly understand the technical solution of the present invention.

[0075] Example 1 Reference Figure 1 to Figure 10 Taking the GaN-on-Si (i.e., heteroepitaxial growth of GaN compound semiconductors on a silicon substrate) integrated platform as an example, this embodiment provides a method for preparing a compound semiconductor integrated device, comprising the following steps: S1. Provide a compound semiconductor heteroepitaxial wafer, the compound semiconductor heteroepitaxial wafer comprising a P-type silicon substrate and a compound semiconductor layer deposited on the P-type silicon substrate; the compound semiconductor layer comprises a layer of Al x Ga 1-x N (0<x≤1) layer and a GaN layer. x Ga 1-x The doping type and doping concentration of the N layer and GaN layer are the same. The GaN layer is located on the surface of the P-type silicon substrate. x Ga 1-x The N layer is located on the surface of the GaN layer facing away from the P-type silicon substrate.

[0076] S2. Prepare multiple device regions on the compound semiconductor heteroepitaxial wafer, each device region including a HEMT device.

[0077] S3. Form a first isolation groove by etching between the device areas that need to be isolated from each other; the first isolation groove penetrates the compound semiconductor layer, and its bottom is located on the surface where the P-type silicon substrate contacts the compound semiconductor layer. The compound semiconductor layer is etched by plasma-coupled reactive ion etching with Cl2 and BCl3 as reactive etching gases and N2 as carrier gas until the P-type silicon substrate is exposed. F ions are implanted into the compound semiconductor layer on both sides of the first isolation groove to form a high resistance region in the compound semiconductor layer on the side wall of the first isolation groove. The angle between the side walls on both sides of the first isolation groove and the surface of the compound semiconductor layer contacting the substrate is 45°; that is, the width of the top of the first isolation groove is greater than the width of the bottom.

[0078] A second isolation groove is etched in the P-type silicon substrate by deep silicon etching technology. The P-type silicon substrate exposed at the bottom of the first isolation groove is etched for multiple cycles using SF6 as etching gas to form a second isolation groove; between cycles, the sidewalls of the second isolation groove are passivated and protected using C4F8 as passivation gas to ensure that the verticality of the sidewalls of the second isolation groove is controllable. The second isolation groove is connected to the first isolation groove, and its bottom is located in the P-type silicon substrate; that is, the second isolation groove does not penetrate the P-type silicon substrate. The depth of the second isolation groove is 150μm and the width is 100μm. The first isolation groove and the second isolation groove are collectively referred to as isolation grooves.

[0079] Polyimide is spin-coated on the surface of the compound semiconductor layer away from the P-type silicon substrate and inside the first isolation groove and the second isolation groove.

[0080] RIE etching with a mixture of O2 and CH3F is used to remove all polyimide on the surface of the compound semiconductor layer away from the P-type silicon substrate, and the polyimide in the first isolation groove and the second isolation groove is retained. Vacuum annealing is performed to solidify the polyimide in the isolation groove. The specific annealing conditions are as follows: heating from room temperature to 100°C and keeping the temperature constant for 20 minutes; continuing to heat to 200°C and keeping the temperature constant for 25 minutes; then continuing to heat to 320°C and keeping the temperature constant for 15 minutes; lowering the temperature to below 80°C (for example, lowering the temperature to 70°C). Silicon nitride is deposited on the surface of the compound semiconductor layer away from the P-type silicon substrate by PECVD to obtain an interconnect dielectric layer.

[0081] S4. A through hole is opened in the interconnect dielectric layer using F-based gas RIE etching technology, and metal copper is deposited in the through hole and on the surface of the interconnect dielectric layer away from the compound semiconductor layer by electroplating to form an electrical connection between the isolated device areas.

[0082] S5, using CMP to thin the side of the P-type silicon substrate away from the compound semiconductor layer, so that the second isolation trench penetrates the thinned P-type silicon substrate; thereby the electrical connection between the device regions on both sides of the isolation trench is cut off. At this point, a complete compound semiconductor integrated device is prepared.

[0083] Example 2 Reference Figure 1 , 2 , 18-22, taking the GaN-on-Si (i.e., GaN compound semiconductor heteroepitaxially grown on a silicon substrate) integrated platform as an example, this embodiment provides a method for preparing a compound semiconductor integrated device, comprising the following steps: S1. Provide a compound semiconductor heteroepitaxial wafer, the compound semiconductor heteroepitaxial wafer comprising a P-type silicon substrate and a compound semiconductor layer deposited on the P-type silicon substrate; the compound semiconductor layer comprises a layer of Al x Ga 1-xN (0<x≤1) layer and a GaN layer. x Ga 1-x The doping type and doping concentration of the N layer and GaN layer are the same. The GaN layer is located on the surface of the P-type silicon substrate. x Ga 1-x The N layer is located on the surface of the GaN layer facing away from the P-type silicon substrate.

[0084] S2. Prepare multiple device regions on the compound semiconductor heteroepitaxial wafer, each device region including a HEMT device.

[0085] S3, depositing a first dielectric layer and a second dielectric layer in sequence on the upper surface of the compound semiconductor layer. The first dielectric layer and the second dielectric layer serve as interconnect dielectric layers. The material of the first dielectric layer is silicon nitride. The material of the second dielectric layer is aluminum nitride.

[0086] Plasma coupled reactive ion etching with Cl2 and BCl3 as reactive etching gases and N2 as carrier gas is used to form a first isolation groove between the device areas that need to be isolated from each other, and the etching is performed until the P-type silicon substrate is exposed. The first isolation groove runs through the first dielectric layer, the second dielectric layer and the compound semiconductor layer. The angle between the side walls on both sides of the first isolation groove and the surface of the compound semiconductor layer contacting the substrate is 20°.

[0087] F ions are implanted into the compound semiconductor layer on both sides of the first isolation trench to form a high resistance region in the compound semiconductor layer on the sidewall of the first isolation trench.

[0088] The P-type silicon substrate exposed at the bottom of the first isolation groove is etched for multiple cycles using SF6 as etching gas to form a second isolation groove in the P-type silicon substrate. Between cycles, the sidewalls of the second isolation groove are passivated and protected using C4F8 as passivation gas to ensure that the verticality of the sidewalls of the second isolation groove is controllable. The second isolation groove is connected to the first isolation groove, and its bottom is located in the substrate. The depth of the second isolation groove is 100μm and the width is 50μm. The first isolation groove and the second isolation groove are collectively referred to as isolation grooves.

[0089] SOG is spin-coated on the surface of the compound semiconductor layer away from the P-type silicon substrate and inside the first isolation groove and the second isolation groove. All SOG on the surface of the compound semiconductor layer away from the P-type silicon substrate is removed by RIE etching using a mixed gas of O2 and CH3F, and the SOG in the first isolation groove and the second isolation groove is retained. The first dielectric layer and the second dielectric layer located on the surface of the compound semiconductor layer away from the P-type silicon substrate serve together as interconnect dielectric layers. Vacuum annealing is performed to solidify the SOG in the isolation groove. The specific annealing conditions are as follows: heating from room temperature to 95°C and keeping the temperature constant for 15 minutes; continuing to heat up to 180°C and keeping the temperature constant for 20 minutes; continuing to heat up to 280°C and keeping the temperature constant for 30 minutes; reducing the temperature to below 80°C (for example, reducing the temperature to 65°C).

[0090] S4. A through hole is opened in the interconnect dielectric layer using F-based gas RIE etching technology, and metal copper is deposited in the through hole and on the surface of the interconnect dielectric layer away from the compound semiconductor layer by electroplating to form an electrical connection between the isolated device areas.

[0091] S5, using chemical etching to thin the side of the P-type silicon substrate away from the compound semiconductor layer, so that the second isolation groove penetrates the thinned P-type silicon substrate; thereby the electrical connection between the device areas on both sides of the isolation groove is cut off. At this point, a complete compound semiconductor integrated device is prepared.

[0092] Example 3 Reference Figure 1 , 2 , 23 to 28, taking the GaN-on-Si (i.e., GaN compound semiconductor heteroepitaxially grown on a silicon substrate) integrated platform as an example, this embodiment provides a method for preparing a compound semiconductor integrated device, comprising the following steps: S1. Provide a compound semiconductor heteroepitaxial wafer, the compound semiconductor heteroepitaxial wafer comprising a P-type silicon substrate and a compound semiconductor layer deposited on the P-type silicon substrate; the compound semiconductor layer comprises a layer of Al x Ga 1-x N (0<x≤1) layer and a GaN layer. x Ga 1-x The doping type and doping concentration of the N layer and GaN layer are the same. The GaN layer is located on the surface of the P-type silicon substrate. x Ga 1-x The N layer is located on the surface of the GaN layer facing away from the P-type silicon substrate.

[0093] S2. Prepare multiple device regions on the compound semiconductor heteroepitaxial wafer, each device region including a HEMT device.

[0094] S3, using Cl2 and BCl3 as reactive etching gases and N2 as carrier gas, plasma coupled reactive ion etching, forming a first isolation groove between the device regions that need to be isolated from each other by etching, and etching until the P-type silicon substrate is exposed. The angle between the side walls on both sides of the first isolation groove and the surface of the compound semiconductor layer contacting the substrate is 60°. The first isolation groove penetrates the compound semiconductor layer.

[0095] A first dielectric layer and a second dielectric layer are sequentially deposited on the surface of the compound semiconductor layer away from the P-type silicon substrate and on the sidewall of the first isolation groove. The materials of the first dielectric layer and the second dielectric layer are both silicon nitride.

[0096] The P-type silicon substrate exposed at the bottom of the first isolation groove is etched for multiple cycles using SF6 as etching gas to form a second isolation groove in the P-type silicon substrate. The sidewalls of the second isolation groove are passivated and protected using C4F8 as passivation gas between cycles to ensure that the verticality of the sidewalls of the second isolation groove is controllable. The second isolation groove is connected to the first isolation groove, and its bottom is located in the substrate. The second isolation groove has a depth of 200 μm and a width of 200 μm. The first isolation groove and the second isolation groove are collectively referred to as isolation grooves.

[0097] Polyphenylcyclobutene is spin-coated on the surface of the compound semiconductor layer away from the P-type silicon substrate and inside the first isolation groove and the second isolation groove. All polyphenylcyclobutene on the surface of the compound semiconductor layer away from the P-type silicon substrate is removed by RIE etching using a mixed gas of O2 and CH3F, and the polyphenylcyclobutene in the first isolation groove and the second isolation groove is retained. The first dielectric layer and the second dielectric layer located on the surface of the compound semiconductor layer away from the P-type silicon substrate serve together as interconnect dielectric layers. Vacuum annealing is performed to solidify the polyphenylcyclobutene in the isolation groove. The specific annealing conditions are as follows: heating from room temperature to 105°C and keeping the temperature constant for 10 minutes; continuing to heat up to 160°C and keeping the temperature constant for 15 minutes; continuing to heat up to 360°C and keeping the temperature constant for 10 minutes; reducing the temperature to below 80°C (for example, reducing the temperature to 75°C).

[0098] S4. A through hole is opened in the interconnect dielectric layer using F-based gas RIE etching technology, and metal copper is deposited in the through hole and on the surface of the interconnect dielectric layer away from the compound semiconductor layer by electroplating to form an electrical connection between the isolated device areas.

[0099] S5, using dry etching to thin the side of the P-type silicon substrate away from the compound semiconductor layer, so that the second isolation groove penetrates the thinned P-type silicon substrate; thereby the electrical connection between the device areas on both sides of the isolation groove is cut off. At this point, a complete compound semiconductor integrated device is prepared.

[0100] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A method for preparing a compound semiconductor integrated device, characterized in that: The following steps are involved: S1. providing a compound semiconductor heteroepitaxial wafer, wherein the compound semiconductor heteroepitaxial wafer comprises a substrate and a compound semiconductor layer deposited on the substrate; S2, preparing a plurality of device regions on the compound semiconductor heteroepitaxial wafer, each of the device regions comprising at least one device or at least one circuit formed by interconnecting a plurality of devices; S3, forming an isolation groove between the device regions that need to be isolated from each other and forming an interconnect dielectric layer on the surface of the compound semiconductor layer away from the substrate; the isolation groove is filled with a filling material and annealed; S4, opening a through hole in the interconnect dielectric layer, and depositing metal in the through hole and on the surface of the interconnect dielectric layer away from the compound semiconductor layer, so as to form an electrical connection between the isolated device regions; S5. Thinning the side of the substrate away from the compound semiconductor layer, so that the isolation groove penetrates the thinned substrate.

2. The method for preparing a compound semiconductor integrated device according to claim 1, characterized in that: Step S3 includes any one of the following steps: A. Depositing a first dielectric layer and a second dielectric layer in sequence on the upper surface of the compound semiconductor layer; forming a first isolation groove by etching between the device regions that need to be isolated from each other; the first isolation groove penetrates the first dielectric layer, the second dielectric layer and the compound semiconductor layer; etching a second isolation groove in the substrate; the second isolation groove is connected to the first isolation groove, and the bottom of the second isolation groove is located in the substrate; spin coating a filling material on the upper surface of the obtained device structure and in the first isolation groove and the second isolation groove, and annealing; B. forming a first isolation groove by etching between the device regions that need to be isolated from each other; The first isolation trench penetrates the compound semiconductor layer; a first dielectric layer and a second dielectric layer are sequentially deposited on a surface of the compound semiconductor layer away from the substrate and on a sidewall of the first isolation trench; Etching a second isolation trench in the substrate; the second isolation trench is connected to the first isolation trench, and the bottom of the second isolation trench is located in the substrate; spin coating a filling material on the upper surface of the obtained device structure and in the first isolation trench and the second isolation trench, and annealing; C. Forming a first isolation groove by etching between the device regions to be isolated from each other; the first isolation groove penetrates the compound semiconductor layer; etching a second isolation groove in the substrate; the second isolation groove is connected to the first isolation groove, and the bottom of the second isolation groove is located in the substrate; spin coating a filling material on the upper surface of the obtained device structure and in the first isolation groove and the second isolation groove, and annealing; D. forming a first isolation groove by etching between the device regions that need to be isolated from each other; The first isolation trench penetrates the compound semiconductor layer; a first dielectric layer is deposited on the sidewall of the first isolation trench and on the surface of the compound semiconductor layer facing away from the substrate; etching a second isolation trench in the substrate; The second isolation trench is connected to the first isolation trench, and a bottom of the second isolation trench is located in the substrate; A second dielectric layer is deposited on the exposed surface of the first dielectric layer and on the sidewalls of the second isolation trench or the sidewalls and bottom of the second isolation trench; a filling material is spin-coated on the upper surface of the obtained device structure and inside the first isolation trench and inside the second isolation trench, and annealed.

3. The method for preparing a compound semiconductor integrated device according to claim 2, characterized in that: Any one of steps A to D further includes the following step: performing ion implantation on the compound semiconductor layer on both sides of the first isolation trench to form a high resistance region.

4. The method for preparing a compound semiconductor integrated device according to claim 2, characterized in that: The method for forming the interconnect dielectric layer in step C is selected from one of the two methods (a) or (b); or, the method for forming the interconnect dielectric layer in step A, B or D is selected from any one of the three methods (a) to (c); the steps of the three methods (a) to (c) are as follows: (a) thinning the filling material on the upper surface of the device structure, and using the remaining filling material on the upper surface as the interconnect dielectric layer; (b) removing all filling materials on the upper surface of the device structure, and retaining the filling materials in the first isolation trench and the second isolation trench; Then, a dielectric material is deposited on the upper surface of the obtained device structure to obtain the interconnect dielectric layer; (c) removing all filling materials on the upper surface of the device structure, and retaining the filling materials in the first isolation trench and the second isolation trench; The first dielectric layer, the second dielectric layer and the filling material located in the first isolation trench together constitute the interconnection dielectric layer.

5. The method for preparing a compound semiconductor integrated device according to claim 4, characterized in that: The dielectric material in step (b) includes at least one of silicon nitride, silicon dioxide, silicon oxynitride, aluminum nitride, aluminum oxide, and aluminum oxynitride.

6. The method for preparing a compound semiconductor integrated device according to claim 2, characterized in that: In any one of steps A to D, the step of spin coating the filling material and the step of annealing are performed alternately for multiple times.

7. The method for preparing a compound semiconductor integrated device according to claim 1, characterized in that: The substrate includes at least one of a silicon substrate, a GaN substrate, a GaO substrate, a SiC substrate, a diamond substrate, an SOI substrate, and a sapphire substrate; Or / and, the material of the compound semiconductor layer includes at least one of GaN, GaAs, SiC, GaO, AlN, and AlGaN; Or / and, the filling material includes at least one of polyimide, polybenzocyclobutene, poly(p-phenylene benzobisoxazole), and spin-on glass.

8. The method for preparing a compound semiconductor integrated device according to claim 1, characterized in that: The device is selected from one or more of the following device categories: transistors, diodes, passive devices, sensors for detecting non-electrical physical quantities, light emitters and waveguides.

9. The method for preparing a compound semiconductor integrated device according to claim 1, characterized in that: The annealing in step S3 includes the following steps: heating from room temperature to 95-105°C and keeping the temperature constant for 10-30 minutes; continuing to heat to 160-260°C and keeping the temperature constant for 10-30 minutes; further heating to 280-360°C and keeping the temperature constant for 10-30 minutes; lowering the temperature to below 80°C.

10. A compound semiconductor integrated device, characterized in that: The method is prepared by any one of claims 1 to 9.

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