Metal silicide layer forming method, semiconductor device and chip

Abstract

The invention provides a metal silicide layer forming method, a semiconductor device and a chip, and relates to the technical field of semiconductors. The forming method of the metal silicide layer comprises the following steps: providing a substrate, and forming an isolation structure, a gate structure, a source-drain injection region and a self-aligned barrier layer on the substrate; sequentially removing the second protection layer and the first protection layer outside the blank groove wall of the isolation groove by using protection layer etching treatment; wherein the ratio of the etching rate of the first protection layer to the etching rate of the second protection layer ranges from 1: 5 to 1: 10 in the etching treatment process of the protection layers; the blank groove wall is the groove wall, not covered by the isolation structure, of the isolation groove; and forming a metal silicide layer on the upper surface of the gate structure and the upper surface of the substrate outside the isolation groove. According to the invention, the lateral growth abnormity of the metal silicide can be reduced, the electric leakage abnormity of the device is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a metal silicide layer, a semiconductor device and a chip. Background Art

[0002] Metal silicide (Salicide) is a metal silicide formed by the reaction of metal and silicon substrate. In the semiconductor process, metal silicide needs to be formed between the contact hole and the silicon substrate to form an ohmic contact and reduce resistance.

[0003] In the prior art, after forming the isolation structure, a gate structure and a self-aligned barrier layer are formed on the surface of the substrate, and then a metal silicide layer is formed. However, in the process of forming the gate structure and the self-aligned barrier layer, the isolation structure is over-etched, resulting in the isolation structure being filled below the depth of the isolation groove, exposing part of the groove wall of the isolation groove. Therefore, when forming the metal silicide layer, the metal silicide will adhere to the groove wall of the isolation groove, resulting in abnormal device leakage and affecting device performance. Summary of the invention

[0004] In view of the technical problem in the prior art that abnormal device leakage affects device performance, the present invention provides a method for forming a metal silicide layer, a semiconductor device and a chip. The metal silicide layer formation method can reduce the lateral growth abnormality of metal silicide, reduce the device leakage abnormality and improve the device performance.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a method for forming a metal silicide layer, the method comprising: providing a substrate, and forming an isolation structure, a gate structure, a source-drain injection region and a self-aligned barrier layer on the substrate; wherein the substrate comprises a plurality of active regions and an isolation region formed between two adjacent active regions; the gate structure is formed on the upper surface of the active region; the source-drain injection region is formed on both sides of the gate structure in the active region; the self-aligned barrier layer is formed on the upper surface of the gate structure; the isolation structure is formed in an isolation groove in the isolation region, and the surface height of the isolation structure is low. at the notch of the isolation groove; forming a first protective layer and a second protective layer covering the first protective layer on the surfaces of the substrate, the gate structure and the self-aligned barrier layer in sequence; removing the second protective layer and the first protective layer outside the blank groove wall of the isolation groove in sequence by using a protective layer etching process; wherein, during the protective layer etching process, the etching rate of the first protective layer and the etching rate of the second protective layer are in a ratio of 1:5 to 1:10; the blank groove wall is the groove wall of the isolation groove not covered by the isolation structure; forming a metal silicide layer on the upper surface of the gate structure and the upper surface of the substrate outside the isolation groove.

[0006] Furthermore, during the etching process of the protective layer, the ratio of the etching rate of the first protective layer to the etching rate of the second protective layer is between 1:7.5 and 1:10.

[0007] Furthermore, the first protective layer is a silicon oxide protective layer, and the second protective layer is a silicon nitride protective layer.

[0008] Furthermore, the protection layer etching process adopts an anisotropic etching process.

[0009] Furthermore, the etching gas used in the anisotropic etching process includes but is not limited to: one or more of CF4, CHF3 or CH3F.

[0010] Furthermore, the etching conditions of the protective layer etching process include: the flow rate of the etching gas is between 100 sccm and 500 sccm, the bias voltage is between 100 V and 200 V, the etching pressure is between 30 mTorr and 40 mTorr, and the etching time is between 30 s and 45 s.

[0011] Furthermore, the thickness of the first protective layer is between to The thickness of the second protective layer is between to

[0012] Furthermore, the forming of a metal silicide layer on the upper surface of the gate structure and the upper surface of the substrate outside the isolation groove includes: forming a metal layer on the upper surface of the gate structure and the upper surface of the substrate outside the isolation groove; performing a first annealing treatment on the metal layer to form a high-resistance metal silicide layer; wherein the resistivity of the high-resistance metal silicide layer is greater than the resistivity of the metal silicide layer; and performing a second annealing treatment on the high-resistance metal silicide layer to form the metal silicide layer.

[0013] A second aspect of the present invention provides a semiconductor device, comprising a metal silicide layer formed by the metal silicide layer forming method described above.

[0014] A third aspect of the present invention provides a chip, which includes the semiconductor device described above.

[0015] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0016] The metal silicide layer forming method of the present invention forms an isolation structure, a gate structure, a source-drain injection region and a self-aligned barrier layer on a substrate, and then forms a first protective layer and a second protective layer on the upper surface of the substrate, the gate structure and the self-aligned barrier layer in sequence, and sequentially removes the second protective layer and the first protective layer outside the blank groove wall of the isolation groove by using a protective layer etching process. The etched second protective layer and the first protective layer can protect the blank groove wall to prevent metal silicide from growing on the blank groove wall, and the etching rate of the first protective layer and the etching rate of the second protective layer during the protective layer etching process are between 1:5 and 1:10, and the substrate surface will not be etched during the protective layer etching process, which can reduce damage to the substrate. Then, a metal silicide layer is formed on the upper surface of the gate structure and the upper surface of the substrate outside the isolation groove. Through the present invention, the lateral growth anomaly of the metal silicide can be reduced, the leakage anomaly of the device can be reduced, and the device performance can be improved.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0019] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0020] Figure 1 A flow chart of a method for forming a metal silicide layer provided in an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of a metal silicide layer formed in a method for forming a metal silicide layer in the prior art;

[0022] Figure 3 A schematic structural diagram of a substrate and an isolation groove formed in an embodiment of a method for forming a metal silicide layer provided in an embodiment of the present invention;

[0023] Figure 4 A schematic structural diagram of an isolation structure formed in an embodiment of a method for forming a metal silicide layer provided in an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of the structure of a gate oxide layer and a gate layer formed in an embodiment of a method for forming a metal silicide layer provided in an embodiment of the present invention;

[0025] Figure 6A schematic diagram of the structure of a gate oxide, a gate, a sidewall spacer and a gate structure formed in an embodiment of a method for forming a metal silicide layer provided in an embodiment of the present invention;

[0026] Figure 7 A schematic structural diagram of a self-aligned barrier layer and a photoresist layer formed in an embodiment of a method for forming a metal silicide layer provided in an embodiment of the present invention;

[0027] Figure 8 A schematic diagram of the structure after etching the self-aligned barrier layer in an embodiment of the method for forming a metal silicide layer provided in an embodiment of the present invention;

[0028] Fig. 9 A schematic diagram of the structure of a first protective layer and a second protective layer formed in an embodiment of a method for forming a metal silicide layer provided in an embodiment of the present invention;

[0029] Fig.10 A schematic diagram of a structure after removing the second protective layer and the first protective layer other than the blank groove wall of the isolation groove in an embodiment of the method for forming a metal silicide layer provided by an embodiment of the present invention;

[0030] Fig.11 A schematic structural diagram of a metal silicide layer formed in an embodiment of a method for forming a metal silicide layer provided in an embodiment of the present invention.

[0031] Description of Reference Numerals

[0032] 100-substrate; 101-isolation structure; 102-source-drain injection region; 103-metal silicide layer; 200-substrate; 201-isolation structure; 202-gate structure; 203-source-drain injection region; 204-self-aligned barrier layer; 205-photoresist layer; 206-first protective layer; 207-second protective layer; 208-metal silicide layer; 2011-second isolation layer; 2012-first isolation layer; 2013-isolation groove; 2021-gate oxide; 2022-gate; 2023-side wall. DETAILED DESCRIPTION

[0033] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0035] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0036] As the background technology, the performance of existing semiconductor devices is relatively poor.

[0037] Please refer to Figure 2 In the prior art, after forming the isolation structure 101 on the substrate 100, a gate structure, a self-aligned barrier layer (not shown in the figure) and a source-drain injection region 102 are formed on the surface of the substrate 100, and then a metal silicide layer 103 is formed. However, in the process of forming the gate structure and the self-aligned barrier layer, it is necessary to etch and remove the oxide layer and the self-aligned barrier layer, and the isolation structure 101 will be over-etched during the etching process, resulting in the filled isolation structure 101 being lower than the depth of the isolation groove, exposing a portion of the groove wall of the isolation groove. Therefore, when forming the metal silicide layer 103, the metal silicide will adhere to the groove wall of the isolation groove, resulting in abnormal leakage of the device and affecting the device performance.

[0038] On this basis, the present invention provides a method for forming a metal silicide layer. After forming an isolation structure 201, a gate structure, a source-drain injection region 203 and a self-aligned barrier layer 204 on a substrate 200, a first protective layer 206 and a second protective layer 207 are sequentially formed on the upper surfaces of the substrate 200, the gate structure 202 and the self-aligned barrier layer 204. The second protective layer 207 and the first protective layer 206 outside the blank groove wall of the isolation groove 2013 are sequentially removed by protective layer etching. The etched second protective layer 207 and the first protective layer 206 can protect the blank groove wall and prevent metal silicide from growing on the blank groove wall. In addition, during the protective layer etching process, the etching rate of the first protective layer 206 and the etching rate of the second protective layer 207 are in a ratio of 1:5 to 1:10. During the protective layer etching process, the surface of the substrate 200 will not be etched, which can reduce damage to the substrate 200. Then, a metal silicide layer 208 is formed on the upper surface of the gate structure 202 and the upper surface of the substrate 200 outside the isolation groove 2013. The present invention can reduce the lateral growth anomaly of the metal silicide, reduce the device leakage anomaly, and improve the device performance.

[0039] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0040] Please refer to Figure 1According to a first aspect of an embodiment of the present invention, a method for forming a metal silicide layer is provided, the method comprising: S101: providing a substrate 200, and forming an isolation structure 201, a gate structure 202, a source-drain injection region 203 and a self-aligned barrier layer 204 on the substrate 200; wherein the substrate 200 comprises a plurality of active regions and an isolation region formed between two adjacent active regions; the gate structure 202 is formed on the upper surface of the active region; the source-drain injection region 203 is formed on both sides of the gate structure 202 in the active region; the self-aligned barrier layer 204 is formed on the upper surface of the gate structure 202; the isolation structure 201 is formed in an isolation groove 2013 in the isolation region, and the surface height of the isolation structure 201 is lower than the notch of the isolation groove 2013; S1 S102: forming a first protective layer 206 and a second protective layer 207 covering the first protective layer 206 on the surfaces of the substrate 200, the gate structure 202 and the self-aligned barrier layer 204 in sequence; S103: removing the second protective layer 207 and the first protective layer 206 outside the blank groove wall of the isolation groove 2013 in sequence by protective layer etching; wherein, during the protective layer etching process, the etching rate of the first protective layer 206 and the etching rate of the second protective layer 207 are in a ratio of 1:5 to 1:10; the blank groove wall is the groove wall of the isolation groove 2013 that is not covered by the isolation structure 201; S104: forming a metal silicide layer 208 on the upper surface of the gate structure 202 and the upper surface of the substrate 200 outside the isolation groove 2013.

[0041] Specifically, step S101 is first performed: a substrate 200 is provided, and an isolation structure 201, a gate structure 202, a source-drain injection region 203 and a self-aligned barrier layer 204 are formed on the substrate 200; wherein the substrate 200 includes a plurality of active regions and an isolation region formed between two adjacent active regions; the gate structure 202 is formed on the upper surface of the active region; the source-drain injection region 203 is formed on both sides of the gate structure 202 in the active region; the self-aligned barrier layer 204 is formed on the upper surface of the gate structure 202; the isolation structure 201 is formed in an isolation groove 2013 in the isolation region, and the surface height of the isolation structure 201 is lower than the notch of the isolation groove 2013.

[0042] Specifically, in the embodiment of the present invention, first provide Figure 3 The substrate 200 shown is one of a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium gallium substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. The substrate 200 includes a plurality of active regions I and an isolation region II located between adjacent active regions I.

[0043] A photoresist layer is formed on the substrate 200 of the active region I. The substrate 200 on the isolation region II is etched using the photoresist layer as a mask to form an isolation groove 2013. The isolation groove 2013 may be in an inverted trapezoidal configuration. The isolation groove 2013 is formed by etching using a dry etching process. The process parameters are: the chamber pressure is between 5mT and 15mT, the source power is between 350W and 1200W, the bias voltage is between 150V and 600V, the gas flow rate is between 20sccm and 200sccm, and the etching time is between 8s and 60s. The depth of the isolation groove 2013 is between to

[0044] like Figure 4 As shown, the isolation groove 2013 is filled by a chemical vapor deposition process: a first isolation layer 2012 is deposited in the isolation groove 2013, and a second isolation layer 2011 is formed on the first isolation layer 2012. The material of the first isolation layer 2012 is silicon oxide, and the material of the second isolation layer 2011 is silicon nitride, forming an isolation structure 201. The isolation structure 201 can avoid electrical crosstalk between adjacent active devices.

[0045] Please refer to Figure 5 A gate oxide layer and a gate layer are sequentially formed on the surface of the substrate 200 and the surface of the isolation structure 201 by chemical vapor deposition process. The thickness of the gate oxide layer is between to The thickness of the gate layer is between to The material of the gate oxide layer is silicon nitride or silicon oxide. The material of the gate layer is single crystal silicon or polycrystalline silicon.

[0046] Please refer to Figure 6 , a first photoresist layer (not shown) is formed on the surface of the gate oxide layer, and the first photoresist layer (not shown) is used as a mask to etch and remove the gate oxide layer and the gate layer on the isolation region II until the substrate 200 is exposed, thereby obtaining the gate oxide 2021 and the gate 2022, and forming the gate structure 202 on the active region I. The parameters of the dry etching process include: the pressure of the chamber is between 5.5mT and 50mT, the source power is between 180W and 1000W, the etching gas includes one or more of CH2F2, Cl2 or HBr, the gas flow rate is between 20sccm and 200sccm, and the etching time is between 6s and 40s. In the above scheme, the gate oxide layer and the gate layer are located on the isolation structure 201, so when etching the gate oxide layer and the gate layer, the isolation structure 201 will be over-etched, thereby resulting in a chamfer between the top of the isolation structure 201 and the sidewall surface of the substrate 200, thereby exposing the surface of the isolation groove 2013.

[0047] After etching the gate oxide layer and the gate layer, a chemical vapor deposition process is used to deposit the sidewalls of the gate oxide 2021 and the gate 2022 to form a sidewall spacer 2023. The material of the sidewall spacer 2023 is silicon nitride and silicon oxide.

[0048] Please refer to Figure 7 , in the active area, conductive ions are implanted into the substrate 200 on both sides of the gate structure 202 by an ion implantation process to form a source-drain implantation region 203. The process parameters of the ion implantation process include: the ion doping type of the source-drain implantation region 203 is N-type ion or P-type ion, and the ion doping concentration of the P-type ion is between 1E15atom / cm 3 To 3E15atom / cm 3 , N-type ion doping concentration is between 0.9E15atom / cm 3 To 2.7E15atom / cm3.

[0049] Then, a self-aligned block (SAB) 204 is formed on the substrate 200, the gate structure 202 and the isolation structure 201 by chemical vapor deposition. The material of the self-aligned block 204 is silicon oxide and silicon nitride, and the thickness is between to A photoresist layer 205 having a metal silicide pattern is formed on the self-aligned barrier layer 204. Using the photoresist layer 205 as a mask, the self-aligned barrier layer 204 is etched until the substrate 200, the top of the gate structure 202 and the top of the isolation structure 201 are exposed, and the self-aligned barrier layer 204 on the top of the sidewall 2023 is retained. The etching process parameters are: the etching gas includes CF4 and / or CHF3, the etching pressure is between 60mTorr and 100mTorr, the etching power is between 250W and 350W, the gas flow rate of the etching gas is between 20sccm and 400sccm, and the etching time is between 20s and 30s.

[0050] Please refer to Figure 8 In the process of etching the self-aligned barrier layer 204, since the self-aligned barrier layer 204 also exists on the isolation structure 201, part of the isolation structure 201 will be etched while etching the self-aligned barrier layer 204, resulting in the depth of the isolation structure 201 being less than the depth of the isolation groove 2013, exposing the groove wall of the isolation groove 2013. Figure 7 The smaller dashed box shows the

[0051] Then, step S102 is performed: a first protection layer 206 and a second protection layer 207 covering the first protection layer 206 are sequentially formed on the surfaces of the substrate 200 , the gate structure 202 and the self-aligned barrier layer 204 .

[0052] Then, step S103 is performed: the second protective layer 207 and the first protective layer 206 outside the blank groove wall of the isolation groove 2013 are removed in sequence by using protective layer etching treatment; wherein, during the protective layer etching treatment, the etching rate of the first protective layer 206 and the etching rate of the second protective layer 207 are in a ratio of 1:5 to 1:10; the blank groove wall is the groove wall of the isolation groove 2013 that is not covered by the isolation structure 201.

[0053] Furthermore, during the protective layer etching process, the ratio of the etching rate of the first protective layer 206 to the etching rate of the second protective layer 207 is between 1:7.5 and 1:10.

[0054] Furthermore, the first protective layer 206 is a silicon oxide protective layer, and the second protective layer 207 is a silicon nitride protective layer.

[0055] Furthermore, the protection layer etching process adopts an anisotropic etching process.

[0056] Furthermore, the etching gas used in the anisotropic etching process includes but is not limited to: one or more of CF4, CHF3 or CH3F.

[0057] Furthermore, the etching conditions of the protective layer etching process include: the flow rate of the etching gas is between 100 sccm and 500 sccm, the bias voltage is between 100 V and 200 V, the etching pressure is between 30 mTorr and 40 mTorr, and the etching time is between 30 s and 45 s.

[0058] Furthermore, the thickness of the first protective layer 206 is between to The thickness of the second protective layer 207 is between to

[0059] Specifically, in the embodiment of the present invention, Fig. 9 for Figure 8 The enlarged display of the dotted line frame in the middle shows that a first protective layer 206 and a second protective layer 207 are sequentially formed on the upper surfaces of the substrate 200, the gate structure 202 and the self-aligned barrier layer 204 by chemical vapor deposition process. The thickness of the first protective layer 206 is between to Deposition rate is between to every minute The deposition time is between 5s and 10s. The thickness of the second protective layer 207 is between to 150, with a deposition rate of to every minute The deposition time ranges from 3s to 10s.

[0060] like Fig.10 As shown, the second protective layer 207 and the first protective layer 206 outside the blank groove wall of the isolation groove 2013 are sequentially removed by protective layer etching, and only the second protective layer 207 and the first protective layer 206 of the blank groove wall of the isolation groove 2013 are retained. The protective layer etching process adopts an anisotropic etching process, and the etching rate of the first protective layer 206 and the etching rate of the second protective layer 207 during the protective layer etching process are between 1:7.5 and 1:10. The etching gas used includes but is not limited to: one or more of CF4, CHF3 or CH3F. The etching conditions are as follows: the flow rate of the etching gas is between 100sccm and 500sccm, the bias voltage is between 100V and 200V, the etching pressure is between 30mTorr and 40mTorr, and the etching time is between 30s and 45s. The material of the first protective layer 206 includes silicon oxide, and the material of the second protective layer 207 includes silicon nitride, silicon oxynitride or silicon carbonitride.

[0061] The etching direction of the anisotropic etching process is perpendicular to the direction of the substrate 200. The etching rate in the direction perpendicular to the substrate 200 is greater than the etching rate in the direction parallel to the substrate 200. Part of the first protective layer 206 and the second protective layer 207 of the blank groove wall will be retained, thereby avoiding the subsequent formation of metal silicide on the surface of the blank groove wall, thereby avoiding device leakage anomalies.

[0062] Furthermore, due to process deviation, the thickness of the first protective layer 206 and the second protective layer 207 deposited on all blank groove walls may not be uniform; and when removing the first protective layer 206 and the second protective layer 207 outside the blank groove walls, the thickness removed may be different due to process deviation, so part of the blank groove walls may be exposed again, so after the first deposition and etching to remove the first protective layer 206 and the second protective layer 207, the deposition and etching steps are repeated several times to ensure that all blank groove walls are covered with the first protective layer 206 and the second protective layer 207.

[0063] In this embodiment, if only the second protective layer 207 is deposited, there is no stop layer when the second protective layer 207 is etched during dry etching, which will easily etch the surface of the substrate 200, thereby causing damage to the substrate 200; if only the first protective layer 206 is deposited, the first protective layer 206 will be removed during the SiCoNi process pre-cleaning treatment before forming the metal silicide layer 208, and the purpose of protection cannot be achieved. Therefore, in this embodiment, the first protective layer 206 and the second protective layer 207 are used at the same time to protect the substrate 200 from damage while forming the blank groove wall protection. The etching rate of the first protective layer 206 and the etching rate of the second protective layer 207 are in the range of 1:5 to 1:10. When etching the second protective layer 207, it is not easy to remove the first protective layer 206, thereby protecting the substrate 200 from being etched, thereby ensuring the integrity of the substrate 200.

[0064] Finally, step S104 is performed: a metal silicide layer 208 is formed on the upper surface of the gate structure 202 and the upper surface of the substrate 200 outside the isolation groove 2013 .

[0065] Furthermore, the forming of the metal silicide layer 208 on the upper surface of the gate structure 202 and the upper surface of the substrate 200 outside the isolation groove 2013 includes: forming a metal layer on the upper surface of the gate structure 202 and the upper surface of the substrate 200 outside the isolation groove 2013; performing a first annealing treatment on the metal layer to form a high-resistance metal silicide layer; wherein the resistivity of the high-resistance metal silicide layer is greater than the resistivity of the metal silicide layer 208; and performing a second annealing treatment on the high-resistance metal silicide layer to form the metal silicide layer 208.

[0066] Specifically, in the embodiment of the present invention, Fig.11 As shown, a metal layer is formed on the upper surface of the gate structure 202 and the upper surface of the substrate 200 outside the isolation groove 2013, and the metal layer is subjected to a first annealing process to react with the substrate 200 to form a high-resistance metal silicide layer, and the resistivity of the high-resistance metal silicide layer is greater than the resistivity of the metal silicide layer 208. The first annealing process uses a rapid thermal annealing furnace, the annealing temperature is between 200° C. and 350° C., and the annealing time is between 15s and 45s.

[0067] Then, the metal layer that does not react with silicon is removed by wet etching to prevent bridges from causing circuit short circuits. Then, the high-resistance metal silicide layer is subjected to a second annealing process to form a metal silicide layer 208. The second annealing process uses a rapid thermal annealing furnace with an annealing temperature between 300° C. and 600° C. and a time between 15s and 45s.

[0068] The temperature of the first annealing process is lower than the temperature of the second annealing process. In the first annealing process, the annealing temperature is between 200°C and 350°C. The metal layer will only react with the silicon epitaxial layer to form a high-resistance metal silicide layer. If the annealing temperature is outside the range of 200°C to 350°C, the metal layer and the silicon epitaxial layer will not react completely or will over-react. In the second annealing process, the annealing temperature is between 300°C and 600°C. The high-resistance metal silicide layer is converted into a low-resistance metal silicide layer. If the annealing temperature is outside the range of 300°C to 600°C, the high-resistance metal silicide layer will not be completely converted into a low-resistance metal silicide layer.

[0069] The metal silicide layer 208 is formed by two annealing processes, which avoids the problem of short circuit caused by generating a low-resistance metal silicide layer by only one annealing process. Because the process temperature under the one annealing process is very high, in such a high temperature environment, silicon can diffuse along the grain boundary of the metal silicide layer, resulting in excessive growth of the metal silicide layer on the silicon oxide boundary, and the subsequent wet etching cannot remove the metal silicide layer on the oxide, resulting in a short circuit.

[0070] Before forming the metal silicide layer 208, the process further includes: using a surface pre-cleaning process (SiCoNi) to remove the natural oxide layer on the surface of the substrate 200 until the surface of the substrate 200 is exposed, so that the substrate 200 and the metal layer react completely to form metal silicide. The reaction gas of the surface pre-cleaning process (SiCoNi) is NF3 and NH3, and the reaction temperature is between 150°C and 250°C.

[0071] After the metal silicide layer 208 is formed, a dielectric layer (not shown in the figure) is formed on the substrate 200, and a conductive plug (not shown in the figure) is formed in the dielectric layer.

[0072] A second aspect of the present invention provides a semiconductor device, comprising a metal silicide layer formed by the metal silicide layer forming method described above.

[0073] A third aspect of the present invention provides a chip, which includes the semiconductor device described above.

[0074] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0075] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0076] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A method for forming a metal silicide layer, characterized in that: The method for forming a metal silicide layer comprises: A substrate is provided, and an isolation structure, a gate structure, a source-drain injection region, and a self-aligned barrier layer are formed on the substrate; wherein the substrate comprises a plurality of active regions and an isolation region formed between two adjacent active regions; the gate structure is formed on the upper surface of the active region; the source-drain injection region is formed on both sides of the gate structure in the active region; the self-aligned barrier layer is formed on the upper surface of the gate structure; the isolation structure is formed in an isolation groove in the isolation region, and the surface height of the isolation structure is lower than the notch of the isolation groove; Forming a first protective layer and a second protective layer covering the first protective layer on the surfaces of the substrate, the gate structure and the self-aligned barrier layer in sequence; The second protective layer and the first protective layer outside the blank groove wall of the isolation groove are sequentially removed by using a protective layer etching process; wherein, during the protective layer etching process, the ratio of the etching rate of the first protective layer to the etching rate of the second protective layer is between 1:5 and 1:10; the blank groove wall is the groove wall of the isolation groove not covered by the isolation structure; A metal silicide layer is formed on the upper surface of the gate structure and the upper surface of the substrate outside the isolation groove.

2. The method for forming a metal silicide layer according to claim 1, wherein: During the etching process of the protective layer, the ratio of the etching rate of the first protective layer to the etching rate of the second protective layer is between 1:7.5 and 1:

10.

3. The method for forming a metal silicide layer according to claim 1, wherein: The first protective layer is a silicon oxide protective layer, and the second protective layer is a silicon nitride protective layer.

4. The method for forming a metal silicide layer according to claim 1, wherein: The protection layer etching process adopts an anisotropic etching process.

5. The method for forming a metal silicide layer according to claim 4, wherein: The etching gas used in the anisotropic etching process includes but is not limited to: one or more of CF4, CHF3 or CH3F.

6. The method for forming a metal silicide layer according to claim 5, wherein: The etching conditions of the protective layer etching process include: the flow rate of the etching gas is between 100 sccm and 500 sccm, the bias voltage is between 100 V and 200 V, the etching pressure is between 30 mTorr and 40 mTorr, and the etching time is between 30 s and 45 s.

7. The method for forming a metal silicide layer according to claim 1, wherein: The thickness of the first protective layer is between to The thickness of the second protective layer is between to 8. The method for forming a metal silicide layer according to claim 1, wherein: The forming of a metal silicide layer on the upper surface of the gate structure and the upper surface of the substrate outside the isolation groove comprises: forming a metal layer on an upper surface of the gate structure and an upper surface of the substrate outside the isolation groove; Performing a first annealing treatment on the metal layer to form a high-resistance metal silicide layer; wherein the resistivity of the high-resistance metal silicide layer is greater than the resistivity of the metal silicide layer; The high-resistance metal silicide layer is subjected to a second annealing process to form the metal silicide layer.

9. A semiconductor device, characterized in that: The semiconductor device includes a metal silicide layer formed by the metal silicide layer forming method according to any one of claims 1 to 8.

10. A chip, characterized in that: The chip includes the semiconductor device according to claim 9.

Images