Method for manufacturing semiconductor device
By adopting a pulse etching process in the semiconductor substrate etching process, the passivation layer is formed using the passivation period of high source power, which solves the current leakage problem caused by trench bending and improves the efficiency of the semiconductor device.
Patent Information
- Application Number
- CN202510041007.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-28
- Filing Date
- 2025-01-10
- Publication Date
- 2025-04-11
AI Technical Summary
In the existing semiconductor substrate etching process, the profile of the trench may be bent, causing the protruding portion of the semiconductor substrate to bend, thereby causing problems such as current leakage and reduced device performance.
Using a pulsed etching process, each cycle includes an etching cycle and a passivation cycle, with the source power of the passivation cycle being higher than the source power of the etching cycle to form a passivation layer along the trench surface to prevent lateral overetching.
The bending problem of the protruding part of the semiconductor substrate is effectively improved, the sidewall etching of the trench is reduced, the flatness and galvanic isolation capability of the isolation structure are improved, and the efficiency of the device is improved.
Smart Images
Figure CN119812101A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Art
[0002] Isolation structures, such as shallow trench isolation (STI), are integrated circuit features used to prevent current leakage between adjacent semiconductor device components. Generally speaking, isolation structures are formed by etching a semiconductor substrate to form a trench in the semiconductor substrate, and then filling the trench of the semiconductor substrate with a dielectric material. During etching of the semiconductor substrate, the profile of the trench may be wiggling, which causes the profile of the protruding portion of the semiconductor substrate to bend. The bending problem of the protruding portion of the semiconductor substrate can cause some problems in the final product. Summary of the invention
[0003] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: performing a pulsed etching process on a substrate to form a groove in the substrate, wherein the pulsed etching process includes multiple cycles, each of the cycles includes an etching period and a passivation period, and the source power of the passivation period is higher than the source power of the etching period; and forming an isolation structure in the groove.
[0004] In some embodiments of the present invention, the bias power of the passivation period is lower than the bias power of the etching period.
[0005] In some embodiments of the present invention, the bias power during the passivation period is zero.
[0006] In some embodiments of the present invention, the bias power of the etching cycle is between 1100W and 1300W.
[0007] In some embodiments of the present invention, the duration of the etching period occupies 15% to 30% of the duration of each of the cycles.
[0008] In some embodiments of the present invention, the source power during the passivation period is between 850W and 1050W.
[0009] In some embodiments of the present invention, the source power of the passivation cycle is 250W to 800W higher than the source power of the etching cycle.
[0010] In some embodiments of the present invention, the source power of the passivation cycle is 250W to 650W higher than the source power of the etching cycle.
[0011] In some embodiments of the present invention, the process gas used in the etch cycle is the same as the process gas used in the passivation cycle.
[0012] In some embodiments of the present invention, the pulsed etching process includes a first cycle, and performing the pulsed etching process includes introducing a processing gas to recess the substrate during an etching period of the first cycle, and using the processing gas to oxidize sidewalls of the recess during a passivation period of the first cycle.
[0013] In some embodiments of the present invention, during the etching period of the first cycle, the processing gas etches the substrate faster than it oxidizes the surface of the substrate.
[0014] In some embodiments of the present invention, during the passivation period of the first cycle, the processing gas oxidizes the substrate faster than it etches the substrate.
[0015] According to some embodiments of the present invention, the bottom of the groove is oxidized during the passivation period of the first cycle to form a passivation layer.
[0016] In some embodiments of the present invention, the pulsed etching process further includes a second cycle after the first cycle, and performing the pulsed etching process further includes etching the passivation layer at the bottom of the groove after the bottom of the groove is oxidized during the etching period of the second cycle.
[0017] In some embodiments of the present invention, during the etching period of the second cycle, the processing gas etches the passivation layer at the bottom of the groove faster than the passivation layer at the sidewall of the groove.
[0018] In some embodiments of the present invention, during the etching period of the second cycle, the processing gas etches the substrate faster than the passivation layer on the sidewall of the groove.
[0019] In some embodiments of the present invention, the processing gas used in the pulse etching process is a combination of chlorine, oxygen and helium.
[0020] In some embodiments of the present invention, the manufacturing method further includes forming a hard mask layer over the substrate before forming the trench in the substrate, wherein the trench is formed by etching the substrate through the hard mask layer.
[0021] In some embodiments of the present invention, forming the isolation structure in the trench includes forming a dielectric layer that overfills the trench, and performing a planarization process to remove excess portions of the dielectric layer.
[0022] In some embodiments of the present invention, a top surface of the isolation structure is flush with a top surface of the substrate.
[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary only, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The disclosure will be best understood by reading the following detailed description of the embodiments with reference to the accompanying drawings as follows:
[0025] Figure 1 Detailed Description of the Invention An etching apparatus 10 is used in some embodiments of the present invention.
[0026] Figures 2 to 8 A method of manufacturing a semiconductor device in some embodiments is provided.
[0027] Fig. 9 The following are scanning electron microscope (SEM) images of semiconductor devices in some embodiments of the present invention.
[0028] FIG. 10A to FIG. 10F for Fig. 9 Cross-sectional views of a semiconductor device at different depths. DETAILED DESCRIPTION
[0029] Some embodiments of the present invention provide a method for forming an isolation structure and an active region in a substrate. The method includes performing a pulsed etching process to form a trench in the substrate. A dielectric material is then filled in the trench to form the isolation structure. The pulsed etching process is used to improve the bending problem of the active region. The bending problem of the active region may cause voids after the isolation structure is formed in the trench, thereby causing current leakage and affecting device performance.
[0030] Figure 1 1 is an etching apparatus 10 used in some embodiments of the present invention. The etching apparatus 10 may be a plasma processing system and may include a chamber 20, a gas supply system 30, a gas exhaust system 40, a temperature controller 50, an electrode 60, a holder 70, and RF power supplies 65 and 75.
[0031] The holder 70 is placed in the chamber 20 and is used to hold the substrate 100 during the etching process. The etching process is used for the later discussed Figures 2 to 8 A trench is formed in the substrate 100 in the chamber 20. A gas supply system 30 and a gas exhaust system 40 are connected to the chamber 20 to respectively deliver process gas to and from the chamber 20. The electrode 60 is above the holder 70. The electrode 60 and the holder 70 are coupled to RF power 65 and 75, respectively. The RF power 65 is used to adjust the source power, and the RF power 75 is used to adjust the bias power during the etching process.
[0032] Specifically, during the process of forming a groove in the substrate 100, the processing gas delivered to the chamber 20 by the gas supply system 30 is ionized between the electrode 60 coupled to the RF power 65 and the holder 70 coupled to the RF power 75. The ionized processing gas is used to form the groove in the substrate 100. Adjusting the value of the RF power 65 can adjust the amount of the ionized processing gas. Adjusting the value of the RF power 75 can adjust the directionality of the ionized processing gas. The higher the value of the RF power 65, the greater the amount of the ionized processing gas. The higher the value of the RF power 75, the higher the directionality of the ionized processing gas toward the substrate 100.
[0033] Figures 2 to 8 A method of manufacturing a semiconductor device in some embodiments. Figure 2 , the substrate 100 is arranged on Figure 1 Specifically, the substrate 100 is placed in the chamber 20. Figure 1 The substrate 100 is placed at the holder 70 in the substrate 100, and the upper surface of the substrate 100 faces the electrode 60. The substrate 100 may be a semiconductor substrate. In some embodiments, the substrate 100 may be made of silicon, germanium, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.
[0034] Subsequently, a hard mask layer 110 is formed over the substrate 100. The hard mask layer 110 may include one or more dielectric layers. In some embodiments, the hard mask layer 110 may include a first hard mask layer 112 and a second hard mask layer 114 over the first hard mask layer 112, and the first hard mask layer 112 and the second hard mask layer 114 may be formed of different materials. For example, the first hard mask layer 112 may be made of silicon oxide, and the second hard mask layer 114 may be made of silicon nitride.
[0035] See also Figure 3 , the hard mask layer 110 is patterned to form an opening O in the hard mask layer 110 , and thus the opening O exposes the substrate 100 thereunder.
[0036] See also Figure 4, a pulsed etching process is performed on the substrate 100 to form a trench T in the substrate 100. The trench T is used to accommodate an isolation structure in a subsequent process, and the protruding portion of the substrate 100 can serve as an active area in the final product. The trench T can be formed by etching the substrate 100 through the hard mask layer 110. The pulsed etching process can be used to provide protection at the sidewalls of the trench T. Specifically, during the pulsed etching process, a passivation layer 120 is naturally formed along the surface of the trench T. The passivation layer 120 is used to prevent the trench T from being over-etched laterally. Therefore, the width of each individual trench T remains substantially the same throughout the entire trench T. The width of each protruding portion of the substrate 100 also remains substantially the same throughout the entire protruding portion of the substrate 100. That is, the bending problem of the protruding portion of the substrate 100 is improved. In some embodiments, the passivation layer 120 is made of silicon oxide.
[0037] Figure 5 is a recipe for the pulsed etching process in some embodiments of the present invention. Figure 5 The pulsed etching process includes a plurality of cycles C, such as a first cycle C1 and a second cycle C2, and each of the cycles C includes an etching period E and a passivation period P. The processing gas may be introduced into Figure 4 The substrate 100 is formed Figure 4 The trench T in the etching period E and the passivation period P are adjusted to form a groove along the Figure 4 The passivation layer 120 is formed on the surface of the trench T. In some embodiments, the processing gas used in the pulsed etching process is a combination of chlorine, oxygen, and helium. Therefore, the speed of etching the substrate 100 and the speed of forming the passivation layer may be different between the etching period E and the passivation period P. In the present invention, the speed of etching the substrate 100 by the processing gas during the etching period E is faster than the speed of oxidizing the surface of the substrate 100, and the speed of oxidizing the surface of the substrate 100 by the processing gas during the passivation period P is faster than the speed of etching the substrate 100.
[0038] The first cycle C1 of the pulsed etching process is performed. The first cycle C1 starts from the etching period E. During the etching period E, the first source power SP1 is applied (ie, the first source power SP1 is adjusted to Figure 1 The RF power 65 in the first source power SP1) to Figure 1 The electrode 60 above the substrate 100 is placed in the middle and a first bias power BP1 is applied (ie, the voltage is adjusted Figure 1The RF power 75 in the etching cycle E is supplied to the holder 70 below the substrate 100 to ionize the process gas to etch the substrate 100. In some embodiments, the first bias power BP1 of the etching cycle E is between 1100 W and 1300 W. If the first bias power BP1 is lower than the range disclosed above, the directionality of the ionized process gas is not sufficient to provide sufficient etching capability. In some embodiments, the first source power SP1 of the etching cycle E is between 350 W and 500 W.
[0039] FIG. 6A to FIG. 6D The steps of the pulse etching process in some embodiments of the present invention. Figure 5 and Fig. 6A , introducing the process gas to Figure 5 During the etching period E in the process gas is recessed into the substrate 100 through the hard mask layer 110. The process gas may be vertically recessed into the substrate 100 to form the groove R. Specifically, during the etching period E, the first bias power BP1 is high, and thus the directionality of the etching process of the substrate 100 is high. In other words, the ionized process gas moves toward the substrate 100 with high directionality during the etching period E, and thus the ionized process gas has high etching capability.
[0040] Next, look back Figure 5 In the first cycle C1, the passivation period P is followed by the etching period E. During the passivation period P, the second source power SP2 is applied to the electrode above the substrate 100 (ie, the Figure 1 The RF power 65 in the second source power SP2 is applied, and the second bias power BP2 is applied to the holder below the substrate 100 (ie, adjusting Figure 1The RF power in the passivation period P is 75 to the second bias power BP2). The second bias power BP2 of the passivation period P is lower than the first bias power BP1 of the etching period E. In some embodiments, the second bias power BP2 of the etching period E is 0W. The second source power SP2 of the passivation period P is higher than the first source power SP1 of the etching period E. In some embodiments, the second source power SP2 of the passivation period P is between 850W and 1050W. In some embodiments, the second source power SP2 of the passivation period P is 250W to 800W higher than the first source power SP1 of the etching period E. In some embodiments, the second source power SP2 of the passivation period P is approximately 250W to 650W higher than the first source power SP1 of the etching period E. If the second source power SP2 is lower than the range disclosed above, the amount of ionized processing gas may not be sufficient to oxidize the surface of the substrate 100 to form the passivation layer 120. If the second source power SP2 exceeds the range disclosed above, the surface of the substrate 100 may be over-oxidized to stop etching when forming the grooves, or the difference between the sizes of the grooves may increase due to the microloading effect. In some embodiments, the flow rate of the process gas during the etching period E and the passivation period P is the same. Therefore, the amount of the process gas ionized is determined only by the value of the source power.
[0041] See also Figure 5 and Figure 6B , the process gas is used to oxidize the sidewall of the groove R during the passivation period P of the first cycle C1. Specifically, the process gas used in the passivation period P is the same as the process gas used in the etching period E, and the process gas includes oxygen. The oxygen oxidizes the sidewall of the groove R to convert the surface of the substrate 100 into the passivation layer 120. Specifically, the second bias power BP2 of the passivation period P is lower than the first bias power BP1 of the etching period E, and the second source power SP2 of the passivation period P is higher than the first source power SP1 of the etching period E. Therefore, the amount of the process gas ionized during the passivation period P is greater than the amount of the process gas ionized during the etching period E, and the directionality of the process gas ionized during the etching period E is lower than the directionality of the process gas ionized during the passivation period P. In other words, the substrate 100 is exposed to an environment of the ionized process gas having a weak etching ability. Since the amount of the ionized process gas during the passivation period P is greater than the amount of the ionized process gas during the etching period E, the amount of the ionized process gas can oxidize the sidewall of the groove R to convert the surface of the substrate 100 into the passivation layer 120. In some embodiments where the substrate 100 is made of silicon, the passivation layer 120 is made of silicon oxide. The passivation layer 120 prevents the substrate 100 from being overetched laterally. In some embodiments, the bottom of the groove R is also oxidized during the passivation period P.
[0042] Replay Figure 5 The duty cycle of the first cycle C1 can be adjusted. The term "duty cycle" is defined as the ratio of the duration of the etching period E to the duration of the cycle C. The duration of the etching period E is shorter than the duration of the passivation period P, so that a layer along the Figure 4 In some embodiments, the duration of the etching period E accounts for 15% to 30% of the duration of the first cycle C1. If the duration of the etching period E is lower than the range disclosed above, then Figure 4 The surface of the substrate 100 may be over-oxidized while forming the trench T and the etching may stop. If the duration of the etching cycle E exceeds the range disclosed above, the passivation layer 120 may not be thick enough to protect the substrate 100 from being oxidized. Figure 4 The sidewall of the trench T is etched laterally, which causes the trench T to bend.
[0043] Then, the second cycle C2 is performed after the first cycle C1 is completed. The processes of the second cycle C2 and the first cycle C1 may be the same. That is, the first source power SP1 of the etching period E of the second cycle C2 may be the same as the first source power SP1 of the etching period E of the first cycle C1. The first bias power BP1 of the etching period E of the second cycle C2 may be the same as the first bias power BP1 of the etching period E of the first cycle C1.
[0044] See also Figure 5 and Figure 6C , further recessing the substrate 100 during the etching period E of the second cycle C2. The processing gas etches the passivation layer 120 at the bottom of the groove R faster than the passivation layer 120 at the sidewall of the groove R, and the processing gas etches the substrate 100 faster than the passivation layer 120 at the sidewall of the groove R. Therefore, in Figure 6C During the etching period E of the second cycle C2 in FIG. 1 , the passivation layer 120 at the sidewall of the groove R prevents a portion of the substrate 100 covered by the passivation layer 120 from being over-etched laterally.
[0045] Next, look back Figure 5 , in the second cycle C2, the passivation period P is performed following the etching period E. The processes of the second cycle C2 and the first cycle C1 may be the same. That is, the second source power SP2 of the passivation period P of the second cycle C2 may be the same as the second source power SP2 of the passivation period P of the first cycle C1. The second bias power BP2 of the passivation period P of the second cycle C2 may be the same as the second bias power BP2 of the passivation period P of the first cycle C1. The working cycle of the second cycle C2 may be the same as the working cycle of the first cycle C1.
[0046] See also Figure 5 and Fig.6DDuring the passivation period P of the second cycle C2, a passivation layer 120 is also formed along the surface of the exposed substrate 100. The process of the passivation period P of the second cycle C2 is the same as the process of the passivation period P of the first cycle C1. Therefore, the relevant details are not repeatedly described herein. After the second cycle C2 is finished, Figure 6C and Fig.6D The process in is repeated until the depth of the groove R reaches a predetermined value. Figure 4 The groove T is formed in the middle.
[0047] See also Figure 7 , a dielectric layer 130 is formed to overfill the trench T and cover the hard mask layer 110. In some embodiments, the dielectric layer 130 is made of silicon oxide.
[0048] See also Figure 8 , removing the excess portion of the dielectric layer 130 to form an isolation structure 140 in the trench T. In some embodiments, the isolation structure 140 may be formed by performing a planarization process to remove the excess portion of the dielectric layer 130 and the hard mask layer 110 until the top surface of the substrate 100 is exposed. In some other embodiments, the isolation structure 140 is formed by performing a planarization process to remove the excess portion of the dielectric layer 130 until the top surface of the hard mask layer 110 is exposed, and then performing an etching process to remove the hard mask layer 110 and the dielectric layer 130 protruding from the substrate 100. In some embodiments, the top surface of the isolation structure 140 is flush with the top surface of the substrate 100. In some other embodiments, the top surface of the isolation structure 140 is slightly higher than the top surface of the substrate 100.
[0049] Fig. 9 The scanning electron microscope (SEM) images of the semiconductor device in some embodiments of the present invention are shown. Since the substrate 100 is etched by performing a pulse etching process, the width of the trench T is substantially maintained, and thus the width of the protruding portion of the substrate 100 is also substantially maintained. Therefore, the bending problem of the protruding portion of the substrate 100 can be reduced.
[0050] FIG. 10A to FIG. 10F for Fig. 9 Specifically, Fig. 10A For along Fig. 9 1 is a cross-sectional view of the semiconductor device taken along line L1. Fig. 10B For along Fig. 9 1 is a cross-sectional view of the semiconductor device taken along line L2. Fig. 10C For along Fig. 9 1 is a cross-sectional view of the semiconductor device taken along line L3. Fig. 10D For along Fig. 91 is a cross-sectional view of the semiconductor device taken along line L4.
[0051] Fig.10E For along Fig. 9 1 is a cross-sectional view of the semiconductor device taken along line L5. Fig.10F For along Fig. 9 FIG. 1 is a cross-sectional view of a semiconductor device taken along line L6. FIG. 10A to FIG. 10F , the bending problem of the protruding portion of the substrate 100 is improved from the top view. Specifically, the maximum width W1 of the protruding portion of the substrate 100 is FIG. 10A to FIG. 10F The tip width W2 of the protruding portion of the substrate 100 remains substantially the same in FIG. 10A to FIG. 10F In some embodiments, the tip width W2 is substantially the same as FIG. 10A to FIG. 10F In some embodiments, if Figure 5 In the embodiment, the second source power of the passivation period is 250W to 800W higher than the first source power of the etching period E, the error of the maximum width W1 is less than 15% throughout the protruding portion of the substrate 100, and the error of the tip width W2 is less than 15% throughout the protruding portion of the substrate 100. In some embodiments, if Figure 5 In the embodiment, the second source power of the passivation period is 250W to 650W higher than the first source power of the etching period E, and the error of the maximum width W1 is less than 10% of the protruding portion of the substrate 100, and the error of the tip width W2 is less than 10% of the protruding portion of the substrate 100.
[0052] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0053] It should be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the spirit or scope of the disclosure. In view of the foregoing, it is intended to cover modifications and variations of the present invention, with the limitation that the modifications and variations are within the scope of the appended claims.
[0054]
Explanation of symbols
[0055] 10: Etching equipment
[0056] 20: Chamber
[0057] 30: Gas supply system
[0058] 40: Gas exhaust system
[0059] 50: Temperature controller
[0060] 60: Electrode
[0061] 65: RF power
[0062] 70: Holder
[0063] 75: RF power
[0064] 100:Substrate
[0065] 110: Hard mask layer
[0066] 112: First hard mask layer
[0067] 114: Second hard mask layer
[0068] 120: passivation layer
[0069] 130: Dielectric layer
[0070] 140: Isolation Structure
[0071] BP1: First bias power
[0072] BP2: Second bias power
[0073] C: Loop
[0074] C1: First cycle
[0075] C2: Second cycle
[0076] E: Etching cycle
[0077] L1, L2, L3, L4, L5, L6: lines
[0078] O: Open
[0079] P: passivation period
[0080] R: Groove
[0081] SP2: Second source power
[0082] SP1: First Source Power
[0083] T: Groove
[0084] W1: Maximum width
[0085] W2: tip width.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: Include: performing a pulsed etching process on a substrate to form a trench in the substrate, wherein the pulsed etching process comprises a plurality of cycles, each of the plurality of cycles comprises an etching period and a passivation period, and a source power of the passivation period is higher than a source power of the etching period; and An isolation structure is formed in the trench.
2. The manufacturing method according to claim 1, characterized in that: The bias power of the passivation period is lower than the bias power of the etching period.
3. The manufacturing method according to claim 2, characterized in that: The bias power during the passivation period is zero.
4. The manufacturing method according to claim 1, characterized in that: The bias power of the etching cycle is between 1100W and 1300W.
5. The manufacturing method according to claim 1, characterized in that: The duration of the etching period accounts for 15% to 30% of the duration of each of the plurality of cycles.
6. The manufacturing method according to claim 1, characterized in that: The source power of the passivation period is between 850W and 1050W.
7. The manufacturing method according to claim 6, characterized in that: The source power of the passivation cycle is 250W to 800W higher than the source power of the etching cycle.
8. The manufacturing method according to claim 7, characterized in that: The source power of the passivation cycle is 250W to 650W higher than the source power of the etching cycle.
9. The manufacturing method according to claim 1, characterized in that: The processing gas used in the etching cycle is the same as the processing gas used in the passivation cycle.
10. The manufacturing method according to claim 1, characterized in that: The pulsed etching process includes a first cycle, and performing the pulsed etching process includes: introducing a process gas during the etching period of the first cycle to recess the substrate to form a groove; and The process gas is used to oxidize sidewalls of the recess during the passivation period of the first cycle.
11. The manufacturing method according to claim 10, characterized in that: During the etching period of the first cycle, the processing gas etches the substrate faster than it oxidizes the surface of the substrate.
12. The manufacturing method according to claim 10, characterized in that: During the passivation period of the first cycle, the processing gas oxidizes the substrate faster than it etches the substrate.
13. The manufacturing method according to claim 10, characterized in that: The bottom of the groove is oxidized during the passivation period of the first cycle to form a passivation layer.
14. The manufacturing method according to claim 13, characterized in that: The pulsed etching process further comprises a second cycle after the first cycle, and performing the pulsed etching process further comprises: After the bottom of the groove is oxidized during the etching period of the second cycle, the passivation layer at the bottom of the groove is etched.
15. The manufacturing method according to claim 14, characterized in that: During the etching period of the second cycle, the processing gas etches the passivation layer at the bottom of the groove faster than etching the passivation layer at the sidewall of the groove.
16. The manufacturing method according to claim 14, characterized in that: During the etching period of the second cycle, the processing gas etches the substrate faster than etching the passivation layer on the sidewall of the groove.
17. The manufacturing method according to claim 1, characterized in that: The processing gas used in the pulse etching process is a combination of chlorine, oxygen and helium.
18. The manufacturing method according to claim 1, characterized in that: Also includes: A hard mask layer is formed over the substrate before forming the trench in the substrate, wherein the trench is formed by etching the substrate through the hard mask layer.
19. The manufacturing method according to claim 18, characterized in that: Wherein forming the isolation structure in the trench comprises: forming a dielectric layer that overfills the trench; and A planarization process is performed to remove excess portions of the dielectric layer.
20. The manufacturing method according to claim 19, characterized in that: The top surface of the isolation structure is flush with the top surface of the substrate.