Packaging method and packaging structure for improving packaging density

Abstract

The invention discloses a packaging method and a packaging structure for improving packaging density. The packaging method comprises the following steps: firstly, respectively manufacturing an embedded chip structure and a plastic package body; the first signal export structure embedded in the chip structure is welded on the interposer on the plastic package body, vertical stacking of a plurality of chips is completed, electrical connection is achieved, and then overall thinning is carried out; forming a silicon through hole in the embedded chip structure; forming a second rewiring layer on the silicon through hole and the back surface of the chip; manufacturing a third passivation layer on the surface of the second rewiring layer; and forming a second signal export structure on the third passivation layer, and after the second signal export structure is manufactured, dividing the product into a plurality of independent Die through a cutting process. According to the invention, the interposer on the plastic package body and the first signal export structure are welded together, so that a plurality of chips are vertically stacked, more chips can be connected under the same volume, the packaging density is remarkably improved, the heat dissipation capability of a product is improved, and the packaging reliability is high.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging method and a packaging structure for improving packaging density. Background Art

[0002] With the development of technology, many electronic products have begun to pursue smaller size and more functions, thus placing higher requirements on packaging technology. How to package more chips in the smallest possible volume has become one of the biggest challenges in the packaging industry.

[0003] Based on this, the present invention discloses a packaging method and a packaging structure for improving packaging density. Summary of the invention

[0004] In order to solve the technical problems existing in the prior art, an object of the present invention is to provide a packaging method and a packaging structure for improving packaging density.

[0005] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0006] The present invention discloses a packaging method for improving packaging density, comprising the following steps:

[0007] 1) Mount several IC chips on the surface of EMC plastic packaging material;

[0008] 2) Plastic encapsulating the IC chip to form a plastic encapsulation body;

[0009] 3) forming a first passivation layer on the surface of the plastic package obtained in step 2) and forming a plurality of first openings;

[0010] 4) making a redistribution layer at the first opening;

[0011] 5) Fabricating an interposer on the redistribution layer;

[0012] 6) Making a bonding layer on the interposer, and grinding and thinning the back of the EMC plastic packaging material obtained in step 1);

[0013] 7) Remove the bonding layer to expose the interposer;

[0014] 8) embedding a number of chips on the silicon substrate, and then sequentially manufacturing a second passivation layer and a first rewiring layer, and implanting balls to form a first signal derivation structure;

[0015] 9) Welding the first signal derivation structure onto the interposer obtained in step 7) to complete the vertical stacking of multiple chips, achieve electrical connection, and then thin the entire chip;

[0016] 10) forming a through silicon via on a silicon substrate;

[0017] 11) forming a second redistribution layer on the through silicon via and the back side of the chip;

[0018] 12) forming a third passivation layer on the surface of the second redistribution layer;

[0019] 13) A second signal derivation structure is formed on the third passivation layer. After the second signal derivation structure is manufactured, the product is divided into a plurality of independent dies through a cutting process.

[0020] The present invention also discloses a packaging method for improving packaging density, comprising the following steps:

[0021] 1) embedding a number of chips on a silicon substrate, then sequentially manufacturing a second passivation layer and a first rewiring layer, and implanting balls to form a first signal derivation structure;

[0022] 2) Mount several IC chips on the surface of the EMC plastic packaging material;

[0023] 3) Plastic-sealing the IC chip to form a plastic-sealed body;

[0024] 4) forming a first passivation layer on the surface of the plastic package obtained in step 3) and forming a plurality of first openings;

[0025] 5) making a redistribution layer at the first opening;

[0026] 6) Fabricating an interposer on the redistribution layer;

[0027] 7) Making a bonding layer on the interposer, and grinding and thinning the back of the EMC plastic packaging material obtained in step 2);

[0028] 8) Remove the bonding layer to expose the interposer;

[0029] 9) Welding the first signal derivation structure onto the interposer obtained in step 7) to complete the vertical stacking of multiple chips, achieve electrical connection, and then thin the entire chip;

[0030] 10) forming a through silicon via on a silicon substrate;

[0031] 11) forming a second redistribution layer on the through silicon via and the back side of the chip;

[0032] 12) forming a third passivation layer on the surface of the second redistribution layer;

[0033] 13) A second signal derivation structure is formed on the third passivation layer. After the second signal derivation structure is manufactured, the product is divided into a plurality of independent dies through a cutting process.

[0034] Furthermore, the IC chip is flip-chip mounted on the surface of the EMC plastic packaging material.

[0035] Furthermore, the first passivation layer is made by pressing a photosensitive dry film or a non-photosensitive dry film, or coating a photosensitive adhesive, and the thickness of the first passivation layer is greater than 3 micrometers.

[0036] Furthermore, when the first passivation layer is made by pressing a photosensitive dry film, the first opening is made by an exposure and development process, otherwise the first opening is made by a laser drilling process, and the size of the first opening is smaller than the size of the IC chip surface Pad.

[0037] Furthermore, the esifo method is used to dig several grooves on the silicon substrate, and the chip is mounted in the grooves through the DAF film.

[0038] Furthermore, in step 10), a plurality of through silicon vias are opened on the silicon substrate by through silicon via technology.

[0039] Further, in step 13), a second opening is formed at a specific position of the third passivation layer and a second signal derivation structure is formed at the second opening.

[0040] The invention also discloses a packaging structure prepared by a packaging method for improving packaging density.

[0041] The invention discloses a packaging structure for improving packaging density, comprising a plastic packaging body, the plastic packaging body comprising an EMC plastic packaging material and an IC chip flip-chip mounted on the EMC plastic packaging material, a first passivation layer is made on the plastic packaging body and a first opening is formed at a specific position thereof, a redistribution layer is formed at the first opening, an intermediate layer is made on the redistribution layer through passivation and redistribution processes, the intermediate layer is welded together with a first signal derivation structure of an embedded chip structure, the embedded chip structure comprises a silicon base, a plurality of grooves are dug on the silicon base, the chip is buried in the matching grooves through a DAF film, a second passivation layer and a first redistribution layer are made on the silicon base and the chip in sequence, a first signal derivation structure is formed on the first redistribution layer, a plurality of through-silicon vias are opened on the silicon base, the through-silicon vias and the back side of the chip form a second redistribution layer, a third passivation layer is made on the surface of the second redistribution layer, a second opening is formed at a specific position of the third passivation layer and a second signal derivation structure is formed at the second opening.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The present invention discloses a packaging method and packaging structure for improving packaging density. First, an embedded chip structure and a plastic package body are separately manufactured, and then an intermediate layer on the plastic package body and a first signal derivation structure of the embedded chip structure are welded together, thereby realizing vertical stacking of multiple chips. More chip connections can be achieved in the same volume, which significantly improves the packaging density. At the same time, by vertically stacking the chips, the signal transmission distance can be shortened, which is beneficial to improving the heat dissipation capacity of the packaging structure and has high packaging reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a structural schematic diagram of step 1 of the present invention;

[0045] Figure 2 It is a structural schematic diagram of step 2 of the present invention;

[0046] Figure 3 It is a structural schematic diagram of step three of the present invention;

[0047] Figure 4 It is a structural schematic diagram of step 4 of the present invention;

[0048] Figure 5 It is a structural schematic diagram of step five of the present invention;

[0049] Figure 6-7 They are respectively structural schematic diagrams of step six of the present invention;

[0050] Figure 8 It is a structural schematic diagram of step seven of the present invention;

[0051] Figure 9-12 They are respectively structural schematic diagrams of step eight of the present invention;

[0052] Figure 13-14 They are respectively structural schematic diagrams of step nine of the present invention;

[0053] Fig.15 It is a structural schematic diagram of step ten of the present invention;

[0054] Fig.16 It is a structural schematic diagram of step eleven of the present invention;

[0055] Fig.17 It is a structural schematic diagram of step twelve of the present invention;

[0056] Figure 18-19 They are respectively structural schematic diagrams of step thirteen of the present invention. DETAILED DESCRIPTION

[0057] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0058] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0059] like Figure 1-19 As shown, the present invention discloses a packaging method for improving packaging density, comprising the following steps:

[0060] 1) If Figure 1 As shown, a plurality of IC chips 1 are flip-chip mounted on the surface of the EMC plastic packaging material 2;

[0061] 2) If Figure 2 As shown, the IC chip 1 is encapsulated with an EMC encapsulation material 2 to form a encapsulated body;

[0062] 3) If Figure 3 As shown, a first passivation layer 3 is made on the surface of the plastic package body obtained in step 2), the thickness of which is greater than 3 microns, and a plurality of first openings 4 are formed at specific positions, the size of the openings is smaller than the size of the IC chip surface pad, and the shape of the openings can be circular, square, irregular, etc. The first passivation layer 3 is not limited to any material or method, and can be formed by pressing a photosensitive dry film or a non-photosensitive dry film, or by coating a photosensitive adhesive, etc. The photosensitive type is formed by an exposure and development process to make the first opening 4, otherwise the first opening 4 is made by a laser drilling process;

[0063] 4) If Figure 4 As shown, a redistribution layer 5 is formed on the first passivation layer 3 and at the first opening 4;

[0064] 5) If Figure 5 As shown, an interposer 6 is manufactured on the redistribution layer 5 by passivation and rewiring processes. The thickness of the interposer 6 is selected according to the thickness of the redistribution layer, which is usually greater than or equal to the thickness of the redistribution layer, can withstand a certain voltage, ensures that the redistribution function is perfect, and is used to realize multi-chip connection in the post-process;

[0065] 6) If Figure 6-7 As shown, temporary bonding is performed on the interposer 6 to form a bonding layer 7, which may be glass, silicon, a film, etc., and the thickness may be flexibly selected according to actual needs, and the back side of the EMC molding compound 2 obtained in step 1) is ground and thinned;

[0066] 7) If Figure 8 As shown, the bonding layer 7 is removed to expose the interposer 6;

[0067] 8) If Figure 9-12 As shown, the esifo method is used to dig grooves 9 on the silicon substrate 8 and bury several chips 11 through the DAF film 10. The chip type is flexibly selected according to actual needs, and then the second passivation layer 12 and the first rewiring layer 13 are made in sequence. This wiring layer can be repeatedly operated to achieve high-density wiring function, and the ball is planted to form a first signal derivation structure 14, preferably tin-silver, to lead out the electrical signal;

[0068] 9) If Figure 13-14As shown, the first signal derivation structure 14 is welded on the interposer 6 by a Wafer To Wafer method, so as to complete the vertical stacking of multiple chips and realize electrical connection, and then grind the front side to complete the overall thinning action;

[0069] 10) As Fig.15 As shown, a plurality of through silicon vias 15 are formed on the silicon substrate 8 by through silicon via technology;

[0070] 11) If Fig.16 As shown, a second rewiring layer 16 is formed on the through silicon via 15 and the back of the chip 11. The manufacturing method of this wiring layer can be sputtering, chemical deposition, electroplating, etc., to lead out the rewiring layer signal on the front side of the chip 11;

[0071] 12) If Fig.17 As shown, a third passivation layer 17 is formed on the surface of the second redistribution layer 16, and the thickness is flexibly selected according to actual needs;

[0072] 13) If Figure 18-19 As shown, a second opening is formed at a specific position of the third passivation layer 17 and a second signal derivation structure 18 is formed at the second opening. The corresponding material of the second signal derivation structure 18 can be solder balls, metal bumps, metal columns, etc. After the second signal derivation structure 18 is completed, the product is divided into several independent dies through a cutting process.

[0073] In the present invention, steps 1)-7) can be interchanged with step 8) as a whole, that is, the esifo method is first used to dig grooves 9 on the silicon substrate 8 and bury a plurality of chips 11 through the DAF film 10, and then the second passivation layer 12 and the first rewiring layer 13 are successively manufactured, and the balls are implanted to form the first signal output structure 14, and then steps 1) to 7) are performed in sequence.

[0074] The present invention also discloses a packaging structure for improving packaging density, comprising a plastic package, the plastic package comprising an EMC plastic package 2 and an IC chip 1 flip-chip mounted on the EMC plastic package 2, a first passivation layer 3 is formed on the surface of the plastic package and a first opening 4 is formed at a specific position thereof, a rewiring layer 5 is formed at the first opening 4, an interposer 6 is formed on the rewiring layer 5 by passivation and rewiring processes, the interposer 6 is welded together with a first signal derivation structure 14 of an embedded chip structure, the embedded chip structure comprises a silicon base 8, a plurality of holes are dug on the silicon base 8, A groove 9 is formed, and a chip 11 is buried in the corresponding groove 9 through a DAF film 10. A second passivation layer 12 and a first rewiring layer 13 are sequentially formed on the silicon substrate 8 and the chip 11. A first signal derivation structure 14 is formed on the first rewiring layer 13. A plurality of through silicon vias 15 are opened on the silicon substrate 8. A second rewiring layer 16 is formed on the through silicon vias 15 and the back side of the chip 11. A third passivation layer 17 is formed on the surface of the second rewiring layer 16. A second opening is formed at a specific position of the third passivation layer 17 and a second signal derivation structure 18 is formed at the second opening.

[0075] Example 1

[0076] like Figure 1-19 As shown, a packaging method for improving packaging density includes the following steps:

[0077] 1) If Figure 1 As shown, two IC chips 1 are flip-chip mounted on the surface of the EMC plastic packaging material 2;

[0078] 2) If Figure 2 As shown, the IC chip 1 is then encapsulated with an EMC encapsulation material 2 to form a plastic encapsulation body;

[0079] 3) If Figure 3 As shown, on the surface of the plastic package obtained in step 2), a first passivation layer 3 with a thickness of 5 microns is formed by pressing a photosensitive dry film, and a first opening 4 is formed at a specific position by an exposure and development process, the opening size is smaller than the size of the IC chip surface Pad, and the opening shape is square;

[0080] 4) If Figure 4 As shown, a redistribution layer 5 is fabricated on the first passivation layer 3 in a conventional manner;

[0081] 5) If Figure 5 As shown, an interposer 6 is manufactured on the redistribution layer 5 by conventional passivation and rewiring processes. The thickness of the interposer 6 is selected according to the thickness of the redistribution layer, which is the same as the thickness of the redistribution layer and can withstand a certain voltage, ensuring that the redistribution function is perfect, and is used to realize multi-chip connection in the post-process;

[0082] 6) If Figure 6-7As shown, temporary bonding is performed on the interposer 6 to form a bonding layer 7, which is glass, and the back side of the EMC molding compound 2 of step 2) is ground and thinned;

[0083] 7) If Figure 8 As shown, the bonding layer 7 is removed to expose the interposer 6;

[0084] 8) If Figure 9-12 As shown, the esifo method is used to dig two grooves 9 on the silicon substrate 8, and a chip 11 is buried in each groove 9 through a DAF film 10. The chip type is flexibly selected according to actual needs, and then the second passivation layer 12 and the first rewiring layer 13 are made in sequence. This wiring layer can be repeatedly operated to achieve high-density wiring function, and the ball is planted to form a first signal lead-out structure 14, which is tin-silver, to lead out the electrical signal;

[0085] 9) If Figure 13-14 As shown, the first signal derivation structure 14 is welded on the interposer 6 by a Wafer To Wafer method, so as to complete the vertical stacking of multiple chips and realize electrical connection, and then grind the front side to complete the overall thinning action;

[0086] 10) Fig.15 As shown, a plurality of through silicon vias 15 are formed on the silicon substrate 8 by through silicon via technology;

[0087] 11) If Fig.16 As shown, a second rewiring layer 16 is formed on the through silicon via 15 and the back of the chip 11 by sputtering to lead out the rewiring layer signal on the front of the chip 11;

[0088] 12) If Fig.17 As shown, a third passivation layer 17 is formed on the surface of the second redistribution layer 16;

[0089] 13) If Figure 18-19 As shown, a second opening is formed at a specific position of the third passivation layer 17 and a second signal derivation structure 18 is formed at the second opening. The corresponding material of the second signal derivation structure 18 is a solder ball. After the second signal derivation structure 18 is manufactured, the product is divided into several independent dies through a cutting process.

[0090] A packaging structure with improved packaging density includes a plastic package, the plastic package includes an EMC plastic package 2 and an IC chip 1 flip-chip mounted on the EMC plastic package 2, a first passivation layer 3 is made on the surface of the plastic package and a first opening 4 is formed at a specific position thereof, a redistribution layer 5 is formed at the first opening 4, an interposer 6 is made on the redistribution layer 5 by passivation and redistribution processes, the interposer 6 is welded with a first signal derivation structure 14 of an embedded chip structure, the embedded chip structure includes a silicon base 8, two grooves 9 are dug on the silicon base 8, and two The chips 11 are respectively buried in the corresponding grooves 9 through the DAF film 10, and the second passivation layer 12 and the first rewiring layer 13 are successively made on the silicon substrate 8 and the chip 11, and the first signal derivation structure 14 is formed on the first rewiring layer 13. A plurality of through silicon vias 15 are opened on the silicon substrate 8, and the through silicon vias 15 and the back side of the chip 11 form a second rewiring layer 16. A third passivation layer 17 is made on the surface of the second rewiring layer 16, and a second opening is formed at a specific position of the third passivation layer 17 and a second signal derivation structure 18 is formed at the second opening.

[0091] Example 2

[0092] like Figure 1-19 As shown, a packaging method for improving packaging density includes the following steps:

[0093] 1) If Figure 9-12 As shown, the esifo method is used to dig a groove 9 on the silicon substrate 8 and bury the chip 11 through the DAF film 10, and then the second passivation layer 12 and the first rewiring layer 13 are made in sequence. This wiring layer can be repeatedly operated to achieve high-density wiring function, and the ball is planted to form a first signal lead-out structure 14, which is tin-silver, to lead out the electrical signal;

[0094] 2) If Figure 1 As shown, a plurality of IC chips 1 are flip-chip mounted on the surface of the EMC plastic packaging material 2;

[0095] 3) If Figure 2 As shown, the IC chip 1 is encapsulated with an EMC encapsulation material 2 to form a encapsulated body;

[0096] 4) If Figure 3 As shown, a first passivation layer 3 with a thickness of 5 microns is formed on the surface of the plastic package obtained in step 3), and a plurality of first openings 4 are formed at specific positions, the opening size is smaller than the size of the IC chip surface pad, and the opening shape is square;

[0097] 5) If Figure 4 As shown, a redistribution layer 5 is formed on the first passivation layer 3 and at the first opening 4;

[0098] 6) If Figure 5As shown, an interposer 6 is manufactured on the redistribution layer 5 through passivation and rewiring processes. The thickness of the interposer 6 is selected according to the thickness of the redistribution layer, and can withstand a certain voltage to ensure that the redistribution function is perfect, and is used to realize multi-chip connection in the post-process;

[0099] 7) If Figure 6-7 As shown, temporary bonding is performed on the interposer 6 to form a bonding layer 7, which may be glass, silicon, a film, etc., and the back side of the EMC molding compound 2 obtained in step 1) is ground and thinned;

[0100] 8) If Figure 8 As shown, the bonding layer 7 is removed to expose the interposer 6;

[0101] 9) If Figure 13-14 As shown, the first signal derivation structure 14 is welded on the interposer 6 by a Wafer To Wafer method, so as to complete the vertical stacking of multiple chips and realize electrical connection, and then grind the front side to complete the overall thinning action;

[0102] 10) As Fig.15 As shown, a through silicon via 15 is formed on the silicon substrate 8 by through silicon via technology;

[0103] 11) If Fig.16 As shown, a second rewiring layer 16 is formed on the through silicon via 15 and the back of the chip 11 by chemical deposition, and the rewiring layer signal on the front side of the chip 11 is led out;

[0104] 12) If Fig.17 As shown, a third passivation layer 17 is formed on the surface of the second redistribution layer 16;

[0105] 13) If Figure 18-19 As shown, a second opening is formed at a specific position of the third passivation layer 17 and a second signal derivation structure 18 is formed at the second opening. The corresponding material of the second signal derivation structure 18 is a metal bump. After the second signal derivation structure 18 is manufactured, the product is divided into several independent dies through a cutting process.

[0106] A packaging structure for improving packaging density comprises a plastic package, the plastic package comprises an EMC plastic package 2 and an IC chip 1 flip-chip mounted on the EMC plastic package 2, a first passivation layer 3 is formed on the surface of the plastic package and a first opening 4 is formed at a specific position thereof, a redistribution layer 5 is formed at the first opening 4, an interposer 6 is formed on the redistribution layer 5 by passivation and redistribution processes, the interposer 6 is welded to a first signal derivation structure 14 of an embedded chip structure, the embedded chip structure comprises a silicon base 8, a groove 9 is dug on the silicon base 8, The chip 11 is buried in the matching groove 9 through the DAF film 10, and the second passivation layer 12 and the first rewiring layer 13 are successively made on the silicon base 8 and the chip 11, and the first signal derivation structure 14 is formed on the first rewiring layer 13. A through silicon via 15 is opened on the silicon base 8, and the through silicon via 15 and the back side of the chip 11 form a second rewiring layer 16. A third passivation layer 17 is made on the surface of the second rewiring layer 16, and a second opening is formed at a specific position of the third passivation layer 17 and a second signal derivation structure 18 is formed at the second opening.

[0107] The rest is the same as in Example 1.

[0108] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0109] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A packaging method for improving packaging density, characterized in that: The following steps are involved: 1) Mount several IC chips on the surface of EMC plastic packaging material; 2) Plastic encapsulating the IC chip to form a plastic encapsulation body; 3) forming a first passivation layer on the surface of the plastic package obtained in step 2) and forming a plurality of first openings; 4) making a redistribution layer at the first opening; 5) Fabricating an interposer on the redistribution layer; 6) Making a bonding layer on the interposer, and grinding and thinning the back of the EMC plastic packaging material obtained in step 1); 7) Remove the bonding layer to expose the interposer; 8) embedding a number of chips on the silicon substrate, and then sequentially manufacturing a second passivation layer and a first rewiring layer, and implanting balls to form a first signal derivation structure; 9) Welding the first signal derivation structure onto the interposer obtained in step 7) to complete the vertical stacking of multiple chips, achieve electrical connection, and then thin the entire chip; 10) forming a through silicon via on a silicon substrate; 11) forming a second redistribution layer on the through silicon via and the back side of the chip; 12) forming a third passivation layer on the surface of the second redistribution layer; 13) A second signal derivation structure is formed on the third passivation layer. After the second signal derivation structure is manufactured, the product is divided into a plurality of independent dies through a cutting process.

2. A packaging method for improving packaging density, characterized in that: The following steps are involved: 1) embedding a number of chips on a silicon substrate, then sequentially manufacturing a second passivation layer and a first rewiring layer, and implanting balls to form a first signal derivation structure; 2) Mount several IC chips on the surface of the EMC plastic packaging material; 3) Plastic-sealing the IC chip to form a plastic-sealed body; 4) forming a first passivation layer on the surface of the plastic package obtained in step 3) and forming a plurality of first openings; 5) making a redistribution layer at the first opening; 6) Fabricating an interposer on the redistribution layer; 7) Making a bonding layer on the interposer, and grinding and thinning the back of the EMC plastic packaging material obtained in step 2); 8) Remove the bonding layer to expose the interposer; 9) Welding the first signal derivation structure onto the interposer obtained in step 7) to complete the vertical stacking of multiple chips, achieve electrical connection, and then thin the entire chip; 10) forming a through silicon via on a silicon substrate; 11) forming a second redistribution layer on the through silicon via and the back side of the chip; 12) forming a third passivation layer on the surface of the second redistribution layer; 13) A second signal derivation structure is formed on the third passivation layer. After the second signal derivation structure is manufactured, the product is divided into a plurality of independent dies through a cutting process.

3. A packaging method for improving packaging density according to claim 1 or 2, characterized in that: The IC chip is flip-chip mounted on the surface of the EMC plastic packaging material.

4. A packaging method for improving packaging density according to claim 1 or 2, characterized in that: The first passivation layer is made by pressing a photosensitive dry film or a non-photosensitive dry film, or by coating a photosensitive adhesive, and the thickness of the first passivation layer is greater than 3 micrometers.

5. A packaging method for improving packaging density according to claim 4, characterized in that: When the first passivation layer is made by pressing a photosensitive dry film, the first opening is made by an exposure and development process, otherwise the first opening is made by a laser drilling process, and the size of the first opening is smaller than the size of the IC chip surface Pad.

6. A packaging method for improving packaging density according to claim 1 or 2, characterized in that: Using the esifo method, several grooves are dug on the silicon substrate, and the chip is mounted in the groove through the DAF film.

7. A packaging method for improving packaging density according to claim 1 or 2, characterized in that: In step 10), a plurality of through silicon vias are opened on the silicon substrate by through silicon via technology.

8. A packaging method for improving packaging density according to claim 1 or 2, characterized in that: In step 13), a second opening is formed at a specific position of the third passivation layer and a second signal derivation structure is formed at the second opening.

9. A packaging structure prepared by a packaging method for improving packaging density as described in any one of claims 1 to 8.

10. A packaging structure for improving packaging density, characterized in that: The invention comprises a plastic package body, wherein the plastic package body comprises an EMC plastic package material and an IC chip flip-chip mounted on the EMC plastic package material. A first passivation layer is formed on the plastic package body and a first opening is formed at a specific position thereof. A rewiring layer is formed at the first opening. An intermediate layer is formed on the rewiring layer through passivation and rewiring processes. The intermediate layer is welded together with a first signal derivation structure of an embedded chip structure. The embedded chip structure comprises a silicon base, a plurality of grooves are dug on the silicon base, and the chip is embedded in the matching grooves through a DAF film. A second passivation layer and a first rewiring layer are sequentially formed on the silicon base and the chip, a first signal derivation structure is formed on the first rewiring layer, a plurality of through-silicon vias are opened on the silicon base, and the through-silicon vias and the back side of the chip form a second rewiring layer. A third passivation layer is formed on the surface of the second rewiring layer, a second opening is formed at a specific position of the third passivation layer, and a second signal derivation structure is formed at the second opening.

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