Chip interconnection method, device and equipment of multi-layer stacked memory packaging structure

Abstract

The invention relates to a chip interconnection method, device and equipment for a multi-layer stacked memory packaging structure, and the method comprises the following steps: carrying out the position arrangement of a plurality of thinned storage bare chips based on a preset chip layout diagram, and obtaining an arranged chip array; performing bonding surface alignment on each target storage bare chip in the arranged chip array through high-precision alignment equipment to obtain an aligned chip array; performing thermocompression bonding operation on the aligned chip array to obtain a bonded chip stack body; carrying out edge cutting on the bonded chip stack body to obtain a cut chip stack body; carrying out metal filling interconnection on the cut chip stack body through a micro-spacing interconnection technology to obtain an interconnected chip stack body; and carrying out vacuum resin packaging on the interconnected chip stack by adopting a heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure, thereby solving the technical problem of how to ensure that stable and efficient electrical connection can be established among multiple layers of stacked memories.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-layer stacked memory, and in particular to a chip interconnection method, device and equipment of a multi-layer stacked memory packaging structure. Background Art

[0002] With the rapid development of information technology, the demand for data storage continues to rise, and the traditional two-dimensional chip layout can no longer meet the needs of modern computing systems for high-performance and high-density storage. In order to overcome the physical limitations of planar expansion and improve performance, three-dimensional stacking technology came into being and became one of the important directions for exploration in the semiconductor industry. However, there are many challenges in the process of realizing multi-layer stacked memory packaging structures. For example, the mechanical strength of the die is reduced after thinning, making it easy to break or deform in subsequent processing; at the same time, due to the difference in thermal expansion coefficients between different materials, the stress generated during the bonding process may cause interface separation or crack formation. These problems greatly affect the reliability and yield of the final product.

[0003] Another key issue in the research background is the selection and implementation of interconnection technology. When multiple memory dies are stacked together, how to ensure that a stable and efficient electrical connection can be established between them is a technical problem that needs to be solved urgently. Existing interconnection methods are often limited by limited wiring space and signal transmission delays, which not only limits the performance of the chip, but also increases the cost of design and manufacturing. In addition, as the number of stacked layers increases, the heat accumulation effect becomes more significant, which puts higher requirements on heat dissipation management. Therefore, developing a new type of micro-pitch interconnection technology to improve these problems has become the main goal of researchers in this field.

[0004] Finally, considering the impact of packaging process on the performance of the entire memory, the application of heterogeneous integrated packaging technology is particularly important. Traditional packaging methods usually cannot provide sufficient protection to cope with the increasingly complex internal structure, and may introduce additional parasitic parameters, thereby weakening the functional performance of the device. In order to achieve high-performance multi-layer stacked memory, advanced packaging methods must be adopted, such as vacuum resin packaging, which can effectively reduce the interference of external environmental factors (such as temperature changes, humidity, etc.) on the working state of the chip. But at the same time, new packaging technology also brings new problems such as increased process complexity and rising costs. Therefore, this study aims to propose an innovative chip interconnection method to overcome the shortcomings of existing technologies by optimizing various manufacturing steps, including precise position arrangement, high-precision alignment bonding, edge cutting and three-dimensional through-hole interconnection, and lay a solid foundation for future high-performance storage solutions. Summary of the invention

[0005] The main purpose of the present invention is to provide a chip interconnection method, device and equipment for a multi-layer stacked memory packaging structure, which solves the technical problem of how to ensure that a stable and efficient electrical connection can be established between multi-layer stacked memories.

[0006] To achieve the above object, the present invention provides a chip interconnection method of a multi-layer stacked memory package structure, comprising the following steps: Arranging the positions of the plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; Aligning the bonding surfaces of the target storage dies in the arranged chip array by a high-precision alignment device to obtain an aligned chip array; Performing a thermal compression bonding operation on the alignment chip array using a thermal compression bonding technology to obtain a bonded chip stack; Using femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack; Performing metal filling interconnection on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack; The interconnected chip stack is packaged with vacuum resin using heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure.

[0007] Furthermore, the method of arranging the positions of the plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array includes: The preset chip layout diagram is analyzed for inter-layer interconnection paths by using a preset analysis algorithm to obtain an interconnection density distribution diagram and a chip function division table; Performing initial position allocation for the plurality of thinned memory dies based on the interconnection density distribution map to obtain an initial arrangement chip array; Based on the chip function division table, the initially arranged chip array is divided into layers to obtain a layered chip array; A preset high-precision robotic arm is controlled by a space filling curve algorithm to arrange the positions of each layer of chips in the layered chip array to obtain an arranged chip array.

[0008] Furthermore, the bonding surfaces of the target storage dies in the arranged chip array are aligned by a high-precision alignment device to obtain an aligned chip array, including: Performing dual-wavelength optical interference measurement on the arranged chip array to obtain chip surface profile data; Extracting edge features from the chip surface contour data using a sub-pixel edge detection algorithm to obtain a chip edge feature map; Based on the chip edge feature map, a six-degree-of-freedom posture analysis is performed on each of the target storage dies in the arranged chip array to obtain chip spatial posture data; Through the piezoelectric nano-displacement platform, the spatial posture data of the chip is subjected to real-time closed-loop feedback control to obtain a displacement compensation parameter set; wherein the displacement compensation parameter set includes XY plane displacement, Z axis height error and angle correction value; Generate a preset alignment execution instruction sequence of multi-axis linkage control in a high-precision alignment device based on the displacement compensation parameter set; The alignment execution instruction sequence is used to control the high-precision bonding surface alignment of each target storage die in the arranged chip array to obtain an aligned chip array.

[0009] Furthermore, the method of using a thermal compression bonding technique to perform a thermal compression bonding operation on the alignment chip array to obtain a bonded chip stack includes: Preheating the alignment chip array according to a preset temperature curve to obtain a preheated chip array, and simulating the bonding area temperature field of the preheated chip array to obtain temperature field distribution data; Based on the temperature field distribution data, parameters of a preset thermal compression bonding device are set to obtain set parameters, and real-time temperature monitoring and feedback control are performed on the set parameters to obtain a temperature control curve; Using the thermal compression bonding technology, the alignment chip array is subjected to thermal compression bonding operation through the set pressure curve and the temperature control curve to obtain an initial bonded chip stack, and a bonding interface stress analysis is performed on the initial bonded chip stack to obtain stress distribution data; Based on the stress distribution data, ultrasonic-assisted bonding treatment is performed on the bonding interface in the quasi-chip array to obtain a reinforced bonded chip stack, and bonding strength test is performed on the reinforced bonded chip stack to obtain bonding strength data; The vacuum annealing process technology is used to eliminate residual stress of the reinforced bonded chip stack based on the bonding strength data to obtain a bonded chip stack.

[0010] Furthermore, the edge cutting of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack includes: Performing three-dimensional X-ray tomography on the bonded chip stack to obtain a stacking structure image, and performing femtosecond laser scanning path planning based on the stacking structure image to obtain a laser scanning path diagram; Performing thermal effect simulation analysis on the laser scanning path diagram to obtain heat-affected zone distribution data, and setting parameters of a preset femtosecond laser based on the heat-affected zone distribution data to obtain laser processing parameters; Based on the laser processing parameters, the femtosecond laser is controlled to perform femtosecond laser cutting on the bonded chip stack to obtain a rough-cut chip stack, and a cutting edge morphology characterization is performed on the rough-cut chip stack to obtain cutting edge morphology data; Performing plasma-assisted etching on the rough-cut chip stack based on the cutting edge morphology data to obtain a fine-cut chip stack; The finely cut chip stack is subjected to chemical mechanical polishing and edge cutting to obtain a cut chip stack.

[0011] Furthermore, the cutting chip stack is metal-filled and interconnected by a micro-pitch interconnection technology to obtain an interconnected chip stack, including: Performing through-hole position planning on the cut chip stack based on a preset interconnection circuit diagram to obtain a through-hole position distribution map, and performing electromagnetic field simulation analysis on the through-hole position distribution map to obtain electromagnetic interference distribution data; Performing blind hole processing on the cut chip stack based on the electromagnetic interference distribution data by femtosecond laser ablation technology to obtain a blind hole chip stack, and measuring the blind hole depth of the blind hole chip stack to obtain blind hole depth data; Based on the blind hole depth data, the blind hole chip stack is subjected to a deep silicon etching process to obtain a through hole chip stack, and a through hole side wall roughness analysis is performed on the through hole chip stack to obtain side wall roughness data; Depositing an insulating layer on the through-hole chip stack based on the sidewall roughness data and the through-hole depth data by a selective atomic layer deposition technique to obtain an insulating coating chip stack, and calculating the thickness uniformity of the insulating layer on the insulating coating chip stack to obtain thickness uniformity data; Performing a planarization process on the insulating coating chip stack based on the thickness uniformity data to obtain a planarized chip stack; The planarized chip stack is metal-filled and interconnected by electrochemical deposition technology to obtain an interconnected chip stack.

[0012] Furthermore, the use of heterogeneous integrated packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure includes: Performing a three-dimensional structural scan on the interconnected chip stack to obtain three-dimensional structural data, and performing a structural design on the packaging cavity of the interconnected chip stack based on the three-dimensional structural data to obtain a packaging cavity model; The packaging cavity model is vacuum-sealed with resin by adopting heterogeneous integrated packaging technology to obtain a resin-filled chip stack, and a filling uniformity test is performed on the resin-filled chip stack to obtain resin filling uniformity data; Based on the resin filling uniformity data, ultraviolet curing is performed on the resin-filled chip stack to obtain a cured resin chip stack, and a curing degree detection is performed on the cured resin chip stack to obtain curing degree data; When the curing degree data reaches a preset curing degree range, the cured resin chip stack is laser demoulded by a preset femtosecond laser precision control system to obtain a demoulded chip stack; The demoulded chip stack is plasma cleaned to obtain a clean chip stack, and the clean chip stack is externally connected with wires by wire bonding technology to obtain a target packaged memory chip stack structure.

[0013] The present invention also provides a chip interconnection device of a multi-layer stacked memory packaging structure, comprising: An arrangement module, used for arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; An alignment module, used for aligning the bonding surfaces of the target storage dies in the arranged chip array by means of a high-precision alignment device to obtain an aligned chip array; A heat pressing module, used for performing heat pressing bonding operation on the alignment chip array by using heat pressing bonding technology to obtain a bonded chip stack; A cutting module, used for cutting the edges of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack; An interconnection module, used to perform metal filling interconnection on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack; The packaging module is used to perform vacuum resin packaging on the interconnected chip stack using heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure.

[0014] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0016] The chip interconnection method of the multi-layer stacked memory packaging structure provided by the present invention comprises the following steps: arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; aligning the bonding surfaces of each target memory die in the arranged chip array by a high-precision alignment device to obtain an aligned chip array; performing a hot pressing bonding operation on the aligned chip array to obtain a bonded chip stack; performing edge cutting on the bonded chip stack to obtain a cut chip stack; performing metal filling interconnection on the cut chip stack by micro-pitch interconnection technology to obtain an interconnected chip stack; performing vacuum resin encapsulation on the interconnected chip stack by heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure, solving the technical problem of how to ensure that a stable and efficient electrical connection can be established between multi-layer stacked memories, and realizing that by combining micro-pitch interconnection technology with three-dimensional through-hole interconnection, an efficient electrical connection path can be established in a limited space, reducing signal transmission delay and reducing power consumption. This not only improves the data reading and writing speed, but also helps to maintain a stable communication link, especially in a high-speed computing environment, and has a more outstanding technical effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the steps of a chip interconnection method of a multi-layer stacked memory packaging structure in one embodiment of the present invention; Figure 2 It is a structural block diagram of a chip interconnection device of a multi-layer stacked memory package structure in one embodiment of the present invention; Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0018] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] like Figure 1 As shown, Figure 1 It is a schematic diagram of the steps of a chip interconnection method of a multi-layer stacked memory packaging structure in one embodiment of the present invention; In one embodiment of the present invention, a chip interconnection method of a multi-layer stacked memory package structure is provided, comprising the following steps: Step S1, arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array.

[0021] Specifically, when implementing the above-mentioned step of "arranging the positions of multiple thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array", a detailed planning and design process is first required. The chip layout diagram referred to here is a blueprint carefully designed in advance based on factors such as the required performance parameters, space constraints, and electrical characteristics, which determines the relative position and arrangement of each memory die in the stack. For example, in an application scenario of a high-performance computing module, in order to ensure data access speed and reduce signal delay, the designer may place the die with a higher reading frequency close to the central processing unit, while considering the heat dissipation path to avoid local overheating problems. After such a layout scheme is determined, the next step is the actual operation stage. In this process, memory dies that have been processed by a specific process and have been significantly reduced in thickness are used to build the target structure. These thinned dies are not only lighter and thinner, but can also be stacked more closely together to achieve higher integration. However, because they become more fragile, they must be handled and positioned with extreme caution. Technicians use specialized equipment to assist in this step, such as high-precision robotic arms or suction cup tools, to ensure that each die can be accurately placed in place according to the predetermined coordinates. Once all the specified dies are properly placed, the so-called arranged chip array is formed, which is the basis for a series of subsequent processing steps, including bonding surface alignment, thermal compression bonding, etc. Each link is closely connected and works together to finally form a stable and reliable multi-layer stacked memory packaging structure. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers arrange different types of NAND flash die according to a pre-set chip layout diagram. Through this precise position arrangement, not only can the direction of internal data flow be optimized, but also enough space can be left for future expansion, thereby improving the efficiency and flexibility of the entire storage system. Throughout the process, from the initial design to the final product formation, every detail is to ensure that the end user can get the best experience.

[0022] Step S2, aligning the bonding surfaces of the target storage dies in the arranged chip array by using a high-precision alignment device to obtain an aligned chip array.

[0023] Specifically, when implementing the key step of "aligning the bonding surfaces of each target memory die in the arranged chip array by a high-precision alignment device to obtain an aligned chip array" described above, it should be emphasized that this process is performed after the position arrangement of multiple thinned memory dies based on a preset chip layout diagram has been completed. After the arranged chip array is formed, in order to ensure that each layer can be accurately bonded together and to ensure the quality and reliability of the electrical connection, a high-precision alignment device must be used for the next step. The high-precision alignment device mentioned here is usually equipped with advanced optical systems or laser measurement systems that can identify tiny marks or feature points on each target memory die, and then calculate the correct relative position through complex algorithms. For example, when building high-speed solid-state drives (SSDs) for data center servers, engineers use this equipment to ensure that each NAND flash memory die can be accurately aligned with other layers. This is because even a very small misalignment may cause bonding failure or affect the performance of the finished product, especially in the case of multi-layer stacking, where the deviation of any layer will be amplified, thereby affecting the function of the entire stack. Therefore, it is crucial to use high-precision alignment equipment, which not only improves production efficiency but also significantly reduces the scrap rate caused by misalignment. Once the correct position of all target memory dies is determined, they need to be fixed in this specific posture so that the subsequent thermocompression bonding process can proceed smoothly. During this process, the equipment may apply slight pressure to keep the contact surface between the dies stable, and may also adjust the alignment in real time in combination with the visual monitoring system to ensure the best bonding effect. Finally, the arranged chip array after this step is transformed into an aligned chip array, providing a solid foundation for the subsequent thermocompression bonding. Throughout the process, from the initial arrangement to the final alignment, each link is closely linked, and is committed to manufacturing a high-performance, high-quality multi-layer stacked memory packaging structure. In this way, not only the integration and performance of the product are improved, but also the growing demand for high-efficiency storage solutions in modern information technology is met.

[0024] Step S3, performing a thermal compression bonding operation on the aligned chip array using a thermal compression bonding technology to obtain a bonded chip stack.

[0025] Specifically, in the process of "using the hot compression bonding technology to perform hot compression bonding operation on the aligned chip array to obtain a bonded chip stack" mentioned above, the hot compression bonding technology plays a vital role. It not only ensures the physical connection between the individual memory dies, but also achieves reliable contact in terms of electrical performance. After the alignment is completed by the high-precision alignment equipment, the next step is to fix these precisely arranged dies into an integral structure. In order to achieve this, in actual operation, a special fixture is first prepared to carry the aligned chip array to ensure that all target memory dies maintain their relative positions unchanged throughout the hot pressing process. This fixture usually has a fine adjustment mechanism that can fine-tune the position of each die before being placed in the hot press to ensure the best bonding effect. Once the fixture is ready and loaded into the hot press, the technician will start the machine and operate it according to the pre-set temperature, pressure and time parameters. For example, when building high-speed solid-state drives (SSDs) for data center servers, engineers carefully adjust these parameters based on the specific properties of the materials used, such as the thermal expansion coefficient of silicon-based NAND flash die, to ensure that sensitive components are not damaged by excessive temperature or pressure, while achieving the ideal bonding strength. During the hot pressing process, uniform heating is one of the important factors to ensure high-quality bonding. The hot press is equipped with a precise temperature control system that can provide consistent and stable heat distribution so that each area to be bonded can obtain the same processing conditions. This not only avoids damage caused by local overheating, but also promotes atomic-level diffusion at the interface to form a stable chemical bond. At the same time, the appropriate cooling rate cannot be ignored because it is related to the final quality and performance of the finished product. If the cooling is too fast, it may cause stress concentration and cracks; conversely, if the cooling is too slow, it may extend the production cycle and affect efficiency. Therefore, during the cooling stage, the hot press will also adopt a gradual cooling method to ensure the stability and durability of the bonded chip stack. After the above series of precisely controlled operations, the originally individually arranged storage dies form a solid whole - the bonded chip stack. This integrated structure not only has excellent mechanical stability, but also provides a solid foundation for subsequent three-dimensional through-hole interconnection, further enhancing the speed and reliability of signal transmission. The multi-layer stacked memory manufactured in this way can significantly improve data reading and writing speeds and reduce latency. It is very suitable for use in high-performance computing environments and meets the needs of modern information technology for high-performance storage solutions.

[0026] Step S4, using femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack.

[0027] Specifically, in the step of "cutting the edge of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack" mentioned above, the application of femtosecond laser micromachining technology is the key to achieving high-precision and high-quality edge processing. The choice of this technology is based on its ability to provide extremely high temporal and spatial resolution, thereby ensuring that the cutting process is both accurate and efficient. When the hot-press bonding operation is completed, the formed bonded chip stack needs to be further processed to meet the requirements of the final size and shape, and at this time, a femtosecond laser is required to perform fine edge cutting. Specifically, before preparing for edge cutting, the bonded chip stack is first fixed on a special workbench with a high-precision positioning function to ensure that the stack will not be displaced during the cutting process. Then, the technician will set the various parameters of the femtosecond laser according to the design requirements, including laser pulse width, energy density, and scanning speed. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers pay special attention to the distance between NAND flash memory dies and the stability of the overall structure. Therefore, when setting the cutting parameters, these factors must be taken into account to ensure that the performance of the product after cutting is not affected. The characteristic of femtosecond laser is that it can release huge energy in a very short time. This characteristic allows it to instantly melt or vaporize the surface of the material. At the same time, due to the extremely short action time, the heat generated is almost not transferred to the surrounding materials, thus avoiding the common thermal damage problem in traditional cutting methods. Once all parameters are carefully calibrated, the femtosecond laser begins to cut the bonded chip stack according to the preset path. In this process, the laser beam forms a series of tiny grooves on the surface of the material. As the laser head moves along the specified route, these grooves gradually connect into a complete cutting line, and finally remove the excess material to obtain the ideal cut chip stack. It is worth mentioning that femtosecond laser micromachining technology is not limited to straight-line cutting. It can also achieve precise cutting of complex geometric shapes, which is particularly important for product design in certain special application scenarios. In addition, since there is almost no mechanical stress generated during the cutting process, cracks or other defects caused by cutting can be greatly reduced, significantly improving the yield rate. In this way, edge cutting completed by femtosecond laser micromachining technology can not only meet strict dimensional tolerance requirements, but also maintain the smoothness and flatness of the cutting surface, providing a good foundation for subsequent processes such as three-dimensional through-hole interconnection. Ultimately, the chip stack after careful cutting will show higher integration and better electrical performance, further improving the efficiency and reliability of the entire storage system, perfectly meeting the needs of modern information technology for high-performance storage solutions.

[0028] Step S5, performing metal filling interconnection on the cut chip stack by using a fine pitch interconnection technology to obtain an interconnected chip stack.

[0029] Specifically, in the key step of "interconnecting the cut chip stack by metal filling through micro-pitch interconnection technology to obtain an interconnected chip stack" described above, the metal filling interconnection technology is the core process for achieving efficient and stable electrical connections. After completing the edge cutting of the bonded chip stack by femtosecond laser micromachining technology, the next thing to be solved is how to establish a reliable conductive path between these closely arranged memory dies to ensure that data can be transmitted quickly and without error. This process is crucial for building high-performance multi-layer stacked memory. Specifically, before preparing for metal filling, it is first necessary to make through-holes that penetrate all levels on the cut chip stack. These through-holes will serve as conductive channels between different layers, allowing circuits to be directly connected. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers use advanced etching technology and deposition processes to form these through-holes. In this process, tiny holes are first drilled at selected locations, and then metal materials are filled into these holes by methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating. Commonly used metal materials include copper, tungsten, etc., which have excellent conductivity and mechanical properties, can ensure a low-resistance conductive path, thereby reducing signal transmission delay and improving overall performance. Once the through hole is successfully constructed and metal filling is completed, micro-pitch interconnection technology is needed to ensure that each through hole has precisely arranged solder joints or contact pads around it, and connect them to other circuit elements through ultra-fine wires or redistribution layers (RDL). This technology allows a large number of interconnects to be arranged in a very small space, greatly improving the connection density per unit area. Since the diameter of the through hole and the interconnection wires around it is very small, usually ranging from a few microns to tens of microns, it not only reduces the occupied space, but also enhances the integration and reliability of the system. In order to ensure the quality and reliability of the interconnection, the entire system must also undergo rigorous testing and verification, including electrical characteristics inspection, thermal cycle testing, etc., to ensure that there are no potential problems that affect the performance of the finished product. The resulting interconnected chip stack not only has a higher degree of integration and faster data transmission speed, but also significantly enhances the reliability and durability of the system. This advanced interconnect technology is particularly suitable for high-performance computing environments, such as SSDs used in data center servers, and it can meet the needs of modern information technology for large-capacity, high-speed storage solutions. In this way, not only efficient electrical connections between different layers are achieved, but also a stable communication link is provided for subsequent data read and write operations, further promoting the development of information technology.

[0030] Step S6, using heterogeneous integrated packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure.

[0031] Specifically, in the final step of "using heterogeneous integrated packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain the target packaged memory chip stack structure" described above, the heterogeneous integrated packaging technology and vacuum resin packaging work together to ensure that the multi-layer stacked memory not only has high performance, but also has excellent reliability and environmental adaptability. After the metal filling interconnection is completed by micro-pitch interconnection technology, these closely connected chip stacks need to be packaged to protect the complex internal circuits from external factors. Specifically, before preparing for packaging, it is necessary to first select suitable packaging materials and processes. The vacuum resin packaging mentioned here refers to the use of a specific type of resin material, which is injected into a pre-designed packaging cavity under a vacuum environment and then cured to form a solid whole. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will choose resin materials with excellent electrical insulation properties, low moisture absorption and good thermal stability. This material not only provides physical protection against the intrusion of external contaminants such as dust and moisture, but also effectively reduces stress caused by temperature changes, thereby extending the service life of the device. In actual operation, in order to ensure that the resin can be evenly filled into every tiny corner and avoid the introduction of air bubbles, the entire packaging process is usually carried out under high vacuum conditions. This can maximize the exclusion of gas components in the resin and ensure its compactness and integrity after curing. In addition, due to the use of heterogeneous integrated packaging technology, chips with different functions or process nodes, such as logic control units, storage units, etc., can be integrated in the same package, which not only improves the integration of the system, but also simplifies the subsequent design and assembly process. At the same time, heterogeneous integrated packaging can also optimize the signal transmission path, reduce the impact of parasitic parameters, and further improve the overall performance. Once the packaging process is completed, the target package memory chip stack structure is formed. This structure not only inherits all the advantages of the original stack, such as high density, fast data transmission, etc., but also obtains many additional benefits brought by vacuum resin packaging. For example, it can maintain stable operation in harsh working environments and perform well under both high and low temperature conditions. In addition, the packaged chip stack is also easier to install and maintain, and is very suitable for use in data center servers and other occasions with extremely high requirements for reliability and stability. In this way, not only is the goal of a high-efficiency storage solution achieved, but sufficient space is also reserved for future system upgrades and expansions, meeting the evolving needs of modern information technology.

[0032] In a specific embodiment, the method of arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array includes: The preset chip layout diagram is analyzed for inter-layer interconnection paths by using a preset analysis algorithm to obtain an interconnection density distribution diagram and a chip function division table; Performing initial position allocation for the plurality of thinned memory dies based on the interconnection density distribution map to obtain an initial arrangement chip array; Based on the chip function division table, the initially arranged chip array is divided into layers to obtain a layered chip array; A preset high-precision robotic arm is controlled by a space filling curve algorithm to arrange the positions of each layer of chips in the layered chip array to obtain an arranged chip array.

[0033] Specifically, the complex and precise process of "arranging the positions of multiple thinned memory dies based on the preset chip layout diagram to obtain an arranged chip array" described above includes multiple interrelated steps, which together ensure that the final chip array not only has high-density interconnection, but also can be reasonably distributed according to functional requirements. Specifically, the whole process starts with the analytical algorithm, and the interconnection density distribution map and the chip function division table are generated by parsing the inter-layer interconnection path of the preset chip layout diagram. These two results will provide important guidance information for subsequent position allocation and hierarchical division. First, the analytical algorithm is introduced in this process, the purpose of which is to analyze and optimize the electrical connection method between each layer in the multi-layer stacking structure. Through the algorithm, the interconnection density in different areas can be calculated by deeply parsing the preset chip layout diagram, and the interconnection density distribution map can be drawn accordingly. At the same time, the analytical algorithm will also identify the functional characteristics of each memory die, and then form a chip function division table. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will use this analytical algorithm to determine which areas require more interconnection to support high-frequency data transmission, and which parts can use lower interconnection density to save space. In addition, the chip function partition table can help clarify the specific tasks of each die, such as some dies are dedicated to data reading, while others are responsible for writing operations or executing control logic. With the interconnection density distribution map and the chip function partition table, the next step is to make initial position allocation based on the former. At this stage, technicians will make preliminary position arrangements for multiple thinned storage dies based on the information in the interconnection density distribution map to form the so-called initial arrangement chip array. The key here is to try to concentrate the interconnection dense areas in places where efficient connections can be easily achieved, reduce signal transmission delays and improve overall performance. For example, in the process of building an SSD, those dies that need to communicate frequently may be placed together first to facilitate the subsequent implementation of the three-dimensional through-hole interconnection process. After completing the initial arrangement, the initial arrangement chip array is divided into levels based on the chip function partition table to obtain a layered chip array. This link aims to further refine the role of each die in the entire system and ensure that dies with the same or similar functions can work together at the same level. For example, in a multi-layer stacked SSD design, all the dies used for data caching may be placed at the bottom layer because they usually need to interact directly with external interfaces; higher layers may contain more dies involved in data processing and management. Such a hierarchical division not only helps to simplify the internal architecture, but also improves the modularity of the system, making it easier to maintain and upgrade. Finally, when the layered chip array is determined, it is necessary to use a space filling curve algorithm to accurately control the preset high-precision robotic arm to arrange the final position of each layer of chips, thereby obtaining an arranged chip array.A space filling curve is a mathematical model that can effectively traverse every point in a two-dimensional or three-dimensional space to ensure that no corners are missed. In practical operation, this means that the robot arm can accurately place each storage die in the specified position according to the predetermined path, even in a very limited space. It can maintain a high degree of consistency and accuracy. For example, in SSD manufacturing, this method can ensure that even small deviations will not affect the quality and performance of the finished product. The resulting array of arranged chips not only achieves efficient interconnection and reasonable functional partitioning, but also lays a solid foundation for subsequent bonding, cutting and interconnection processes, and promotes the development of high-performance storage solutions. In summary, this series of steps are closely linked and work together to build a compact and efficient multi-layer stacked memory. From the initial design planning to the final actual arrangement, every link is to ensure that the final product can meet the strict performance indicators while also meeting the needs of modern information technology for large-capacity and high-speed storage.

[0034] In a specific embodiment, the step of aligning the bonding surfaces of the target storage dies in the arranged chip array by a high-precision alignment device to obtain an aligned chip array includes: Performing dual-wavelength light interference measurement on the arranged chip array to obtain chip surface profile data; Extracting edge features from the chip surface contour data using a sub-pixel edge detection algorithm to obtain a chip edge feature map; Based on the chip edge feature map, a six-degree-of-freedom posture analysis is performed on each of the target storage dies in the arranged chip array to obtain chip spatial posture data; Through the piezoelectric nano-displacement platform, the spatial position data of the chip is subjected to real-time closed-loop feedback control to obtain a displacement compensation parameter set; wherein the displacement compensation parameter set includes XY plane displacement, Z axis height error and angle correction value; Generate a preset alignment execution instruction sequence of multi-axis linkage control in a high-precision alignment device based on the displacement compensation parameter set; The alignment execution instruction sequence is used to control the high-precision bonding surface alignment of each target storage die in the arranged chip array to obtain an aligned chip array.

[0035] Specifically, in the process described above, "aligning the bonding surfaces of each target memory die in the array of arranged chips by a high-precision alignment device to obtain an aligned chip array", a series of precise technical steps are involved to ensure that each memory die in the multi-layer stacked structure can be accurately aligned with other layers. First, by performing dual-wavelength optical interferometry on the array of arranged chips, the chip surface profile data can be obtained, which is the basis for achieving high-precision alignment. Dual-wavelength optical interferometry is an advanced optical measurement technology that uses two light sources of different wavelengths to detect subtle height changes on the surface of an object to generate a high-resolution three-dimensional image. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers use this technology to obtain detailed surface information of each NAND flash memory die, including any tiny undulations or irregular shapes. Next, in order to further process these surface profile data, a sub-pixel edge detection algorithm is used to extract edge features, and finally a chip edge feature map is formed. This process can be understood as screening out key information points from a large amount of raw data, that is, data that defines the boundaries and important geometric features of each die. Sub-pixel edge detection algorithms can identify and mark edge locations at a finer level than a single pixel, which helps improve the accuracy of subsequent analysis. For example, in the process of building an SSD, this method can accurately capture the outer edge of each die, even if the difference between them is extremely small, it can be clearly presented. The chip edge feature map not only provides an intuitive visual reference, but also lays the foundation for the next step of posture analysis. Based on the chip edge feature map obtained above, technicians can perform six-degree-of-freedom posture analysis on each target storage die in the array chip array, and then obtain the chip spatial posture data. The six degrees of freedom here refer to the three translation directions of X, Y, and Z and the rotation angles around these three axes. Through such analysis, the exact position and orientation of each die in three-dimensional space can be determined, which is crucial to ensure that they are properly aligned during the subsequent bonding process. For example, in SSD manufacturing, even the slightest angular deviation may cause bonding failure or affect the performance of the finished product, so precise computing tools are needed to evaluate and correct the spatial posture of each die. Once the chip spatial posture data is obtained, it needs to be subjected to real-time closed-loop feedback control to achieve precise position adjustment. This step relies on a piezoelectric nano-displacement platform, which can provide sub-nanometer displacement accuracy and can respond quickly to input signals. Specifically, by analyzing the spatial position data of the chip, a series of displacement compensation parameter sets can be obtained, which include XY plane displacement, Z-axis height error and angle correction value. This means that for each die, the distance and direction it needs to move can be calculated to achieve the ideal alignment state.After receiving these instructions, the piezoelectric nano-displacement platform will perform the corresponding actions in a very short time, so that the die can be fine-tuned according to the predetermined requirements. Finally, based on the displacement compensation parameter set generated above, engineers will compile the alignment execution instruction sequence of the multi-axis linkage control in the preset high-precision alignment equipment. These instruction sequences specify in detail how to coordinate the actions of different axes to ensure that all target storage die can complete the bonding surface alignment synchronously. Through the control of the alignment execution instruction sequence, the high-precision alignment equipment will accurately adjust the position of each die until they fully meet the design requirements. For example, in SSD manufacturing, when all NAND flash memory die are successfully aligned, a so-called alignment chip array is formed. This integrated structure not only has good mechanical stability, but also provides a solid foundation for subsequent hot pressing bonding and other processing procedures. The whole process demonstrates a series of complex and precise technical means from data acquisition to the final alignment operation, ensuring the high performance and reliability of multi-layer stacked memory and meeting the needs of modern information technology for high-efficiency storage solutions. In summary, through the above series of carefully designed and technically implemented steps, not only the highly accurate bonding surface alignment between each target storage die is achieved, but also the production efficiency and product quality are greatly improved. This approach is particularly suitable for application scenarios that require strict alignment accuracy, such as high-speed solid-state drives (SSDs) in data center servers. The result is a significant enhancement in the overall performance and reliability of the system, driving the development of the information technology field.

[0036] In a specific embodiment, the step of performing a thermal compression bonding operation on the alignment chip array using a thermal compression bonding technique to obtain a bonded chip stack includes: Preheating the alignment chip array according to a preset temperature curve to obtain a preheated chip array, and simulating the bonding area temperature field of the preheated chip array to obtain temperature field distribution data; Based on the temperature field distribution data, parameters of a preset thermal compression bonding device are set to obtain set parameters, and real-time temperature monitoring and feedback control are performed on the set parameters to obtain a temperature control curve; Using the thermal compression bonding technology, the alignment chip array is subjected to thermal compression bonding operation through the set pressure curve and the temperature control curve to obtain an initial bonded chip stack, and a bonding interface stress analysis is performed on the initial bonded chip stack to obtain stress distribution data; Based on the stress distribution data, ultrasonic-assisted bonding treatment is performed on the bonding interface in the quasi-chip array to obtain a reinforced bonded chip stack, and bonding strength test is performed on the reinforced bonded chip stack to obtain bonding strength data; The vacuum annealing process technology is used to eliminate residual stress of the reinforced bonded chip stack based on the bonding strength data to obtain a bonded chip stack.

[0037] Specifically, in the process described above, "the said use of the thermocompression bonding technology to perform thermocompression bonding operation on the alignment chip array to obtain a bonded chip stack" includes multiple precise and interrelated technical steps to ensure that each storage die in the multi-layer stacking structure can be firmly connected together. The whole process starts from the preheating treatment to the final elimination of residual stress. Each step is crucial and jointly guarantees the quality and performance of the finished product. First, in order to ensure the success of the thermocompression bonding operation, the alignment chip array needs to be preheated through a preset temperature curve to obtain a preheated chip array. This step is intended to make each die reach a uniform and suitable initial temperature for bonding to avoid stress concentration or material damage caused by excessive temperature gradient. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will adjust the preheating curve according to the specific material properties to ensure that the silicon-based NAND flash memory die is in the best state before entering the formal bonding. At the same time, in order to evaluate the preheating effect, technicians will simulate the temperature field of the bonding area of ​​the preheated chip array to obtain temperature field distribution data. This simulation analysis not only provides an intuitive view of the temperature distribution, but also helps identify possible hot spots or cold spots, providing a basis for subsequent parameter settings. Based on the temperature field distribution data obtained above, the next step is to set the parameters of the preset hot-press bonding equipment, obtain the set parameters, and perform real-time temperature monitoring and feedback control on these set parameters to form a temperature control curve. This step is crucial because it is directly related to the consistency and stability of the temperature during the bonding process. For example, in SSD manufacturing, by accurately setting the various parameters of the hot-press bonding equipment, such as heating rate, holding time, etc., and combining real-time monitoring and feedback control systems, it can be ensured that the temperature is always kept within the ideal range during the entire bonding process. The temperature control curve not only reflects the temperature changes in actual operation, but also provides a guarantee for the subsequent bonding quality to avoid adverse effects caused by temperature fluctuations. Once the temperature control curve is determined, the hot-press bonding technology can be used to perform hot-press bonding operations on the aligned chip array through the set pressure curve and temperature control curve to obtain the initial bonded chip stack. At this stage, the design of the pressure curve is also critical, which determines the pressure distribution on the contact surface between different layers, thereby affecting the bonding effect. For example, in SSD manufacturing, appropriate pressure can promote atomic-level diffusion at the interface and form a stable chemical bond; while excessive pressure may cause deformation or damage to the material. In order to further optimize the bonding effect, technicians will perform bonding interface stress analysis on the initial bonded chip stack to obtain stress distribution data. These data not only reveal the specific stress conditions of the bonding interface, but also provide a scientific basis for subsequent improvements. Based on the stress distribution data obtained above, the next step is to perform ultrasonic assisted bonding treatment on the bonding interface in the chip array to obtain a reinforced bonded chip stack.Ultrasonic assisted bonding is a method that uses high-frequency vibration energy to enhance the bonding strength. It can effectively reduce the gap between interfaces, increase the contact area, and thus enhance the firmness of the bonding. For example, in SSD manufacturing, ultrasonic assisted bonding can significantly improve the quality of the bonding interface without adding additional pressure. After ultrasonic assisted bonding treatment, the bond strength test of the enhanced bonded chip stack is also required to obtain the bond strength data. These test results not only verify whether the bonding effect has reached the expected standard, but also provide an important reference for subsequent process adjustments. Finally, in order to eliminate the stress that may remain in the bonding process, the enhanced bonded chip stack needs to be treated by vacuum annealing process technology to obtain the final bonded chip stack. Vacuum annealing is a process of heating and slowly cooling the material under low pressure. It can effectively release internal stress and improve the physical properties of the material. For example, in SSD manufacturing, vacuum annealing can eliminate the tiny stress generated during the bonding process, ensuring that the finished product will not cause performance degradation or failure due to stress accumulation during long-term use. The vacuum annealing process design based on the bonding strength data makes the entire bonding process more complete and reliable. In summary, this series of carefully designed and technically implemented steps not only achieves highly accurate bonding of the aligned chip array, but also greatly improves production efficiency and product quality. This method is particularly suitable for application scenarios that require strict bonding accuracy, such as high-speed solid-state drives (SSDs) in data center servers. The result is a significant enhancement of the overall performance and reliability of the system, which has promoted the development of the information technology field. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance, but also maintains stable operation in various working environments, fully meeting the needs of the continuous development of modern information technology.

[0038] In a specific embodiment, the edge cutting of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack includes: Performing three-dimensional X-ray tomography on the bonded chip stack to obtain a stacking structure image, and performing femtosecond laser scanning path planning based on the stacking structure image to obtain a laser scanning path diagram; Performing thermal effect simulation analysis on the laser scanning path diagram to obtain heat-affected zone distribution data, and setting parameters of a preset femtosecond laser based on the heat-affected zone distribution data to obtain laser processing parameters; Based on the laser processing parameters, the femtosecond laser is controlled to perform femtosecond laser cutting on the bonded chip stack to obtain a rough-cut chip stack, and a cutting edge morphology characterization is performed on the rough-cut chip stack to obtain cutting edge morphology data; Performing plasma-assisted etching on the rough-cut chip stack based on the cutting edge morphology data to obtain a fine-cut chip stack; The finely cut chip stack is subjected to chemical mechanical polishing and edge cutting to obtain a cut chip stack.

[0039] Specifically, in the process described above, "the edge cutting of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack" includes a series of precise technical steps to ensure that the cutting process is both efficient and does not damage the internal structure of the chip. The entire process starts from three-dimensional X-ray tomography and finally achieves chemical mechanical polishing and cutting. Each step is closely linked to jointly ensure the quality and performance of the finished product. First, in order to accurately plan the scanning path of the femtosecond laser, three-dimensional X-ray tomography is required for the bonded chip stack to obtain a detailed stacking structure image. This technology can provide a high-resolution view of the internal structure, allowing engineers to clearly understand the location of each die, the number of layers, and possible subtle defects. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, this imaging technology can identify which areas need to be handled with special care to avoid any unnecessary damage caused by cutting. Based on these stacking structure images, technicians can develop an optimized femtosecond laser scanning path map to ensure that the cutting path covers all edges that need to be cut without accidentally damaging the internal circuit. Next, in order to evaluate the thermal effects that may occur during the cutting process, it is necessary to perform a thermal effect simulation analysis on the planned laser scanning path map to obtain the heat-affected zone distribution data. This step is crucial because it helps determine which areas may be at risk of material deformation or damage due to high temperature. Based on the simulation results, engineers will adjust the preset femtosecond laser parameters to set the most suitable laser processing parameters. These parameters include but are not limited to laser pulse energy, frequency, focal point size, etc. The purpose is to minimize the heat-affected zone while ensuring cutting efficiency and protect sensitive components from damage. For example, in SSD manufacturing, this method can ensure that the temperature change during the cutting process remains within a safe range and does not affect storage performance. Once the laser processing parameters are determined, the femtosecond laser can be controlled to actually cut the bonded chip stack according to the predetermined path to obtain a rough-cut chip stack. At this stage, the main goal of cutting is to remove excess material and form a rough edge contour. However, since femtosecond laser cutting, although with high precision, may still have tiny irregularities or rough surfaces, further processing is required. In order to evaluate the cutting effect, technicians will characterize the cutting edge morphology of the rough-cut chip stack and obtain cutting edge morphology data. These data not only provide intuitive visual feedback, but also provide a basis for subsequent improvements. For example, in SSD manufacturing, by checking the smoothness and flatness of the cutting edge, it can be determined whether it is necessary to adjust the laser parameters or optimize the cutting path. Based on the cutting edge morphology data obtained above, the next step is to perform plasma-assisted etching on the rough-cut chip stack to achieve a more refined cutting effect.Plasma-assisted etching is a method that uses plasma to chemically react with the surface of the material to remove excess material. It can further improve the quality of the cutting edge without damaging the internal structure of the chip. For example, in SSD manufacturing, this method can effectively remove the tiny burrs or protrusions left after femtosecond laser cutting, making the cutting edge smoother. After plasma-assisted etching, a fine-cut chip stack is obtained, and its edge is very close to the final ideal state. Finally, in order to ensure that the cutting edge fully meets the design requirements and has good electrical and physical properties, the fine-cut chip stack needs to be cut by chemical mechanical polishing. Chemical mechanical polishing (CMP) is a process that combines chemical etching and mechanical grinding. It can eliminate subtle surface irregularities and give the cutting edge an extremely high finish. For example, in SSD manufacturing, chemical mechanical polishing can make the cutting edge not only look flawless, but also significantly improve the uniformity and reliability of contact resistance. The resulting cut chip stack is not only beautiful in appearance, but more importantly, it has excellent electrical performance, providing a solid foundation for subsequent processes such as three-dimensional through-hole interconnection. In summary, this series of carefully designed and technically implemented steps not only achieves precise edge cutting of the bonded chip stack, but also greatly improves production efficiency and product quality. This method is particularly suitable for application scenarios that require strict cutting accuracy, such as high-speed solid-state drives (SSDs) in data center servers. The result is a significant enhancement of the overall performance and reliability of the system, promoting the development of the information technology field. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance, but also maintains stable operation in various working environments, fully meeting the needs of the continuous development of modern information technology.

[0040] In a specific embodiment, the metal filling interconnection is performed on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack, including: Performing through-hole position planning on the cut chip stack based on a preset interconnection circuit diagram to obtain a through-hole position distribution map, and performing electromagnetic field simulation analysis on the through-hole position distribution map to obtain electromagnetic interference distribution data; Performing blind hole processing on the cut chip stack based on the electromagnetic interference distribution data by femtosecond laser ablation technology to obtain a blind hole chip stack, and measuring the blind hole depth of the blind hole chip stack to obtain blind hole depth data; Based on the blind hole depth data, the blind hole chip stack is subjected to a deep silicon etching process to obtain a through hole chip stack, and a through hole side wall roughness analysis is performed on the through hole chip stack to obtain side wall roughness data; Depositing an insulating layer on the through-hole chip stack based on the sidewall roughness data and the through-hole depth data by a selective atomic layer deposition technique to obtain an insulating coating chip stack, and calculating the thickness uniformity of the insulating layer on the insulating coating chip stack to obtain thickness uniformity data; Performing a planarization process on the insulating coating chip stack based on the thickness uniformity data to obtain a planarized chip stack; The planarized chip stack is metal-filled and interconnected by electrochemical deposition technology to obtain an interconnected chip stack.

[0041] Specifically, in the process described above, "the metal filling interconnection of the cut chip stack body by the micro-pitch interconnection technology to obtain the interconnected chip stack body" includes multiple precise and interrelated technical steps to ensure efficient and stable electrical connection between different levels in the multi-layer stacked memory. The whole process starts from the planning of the through-hole position of the cut chip stack body based on the preset interconnection circuit diagram to the final completion of the metal filling interconnection. Each step is crucial and jointly guarantees the quality and performance of the finished product. First, in order to ensure the rationality and optimal distribution of the through-hole position, it is necessary to carry out detailed through-hole position planning of the cut chip stack body based on the preset interconnection circuit diagram to obtain a through-hole position distribution map. This step not only takes into account the electrical connection requirements between each bare chip, but also must take into account factors such as the stability of the overall structure and the heat dissipation performance. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will determine which areas require more through-holes to support high-frequency data transmission based on the specific interconnection design, and which parts can use lower interconnection density to save space. At the same time, in order to evaluate the electromagnetic interference problems that these through holes may cause, technicians will perform electromagnetic field simulation analysis on the through hole position distribution map to obtain electromagnetic interference distribution data. This simulation analysis helps to identify potential interference sources and take measures in advance to avoid them, such as adjusting the through hole layout or optimizing the interconnection path, thereby improving the reliability and anti-interference ability of the system. With the through hole position distribution map and electromagnetic interference distribution data, the next step is to use femtosecond laser ablation technology to perform blind hole processing on the cut chip stack to form the so-called blind hole chip stack. Femtosecond laser ablation is an extremely precise material removal method that can release huge energy in a very short time, instantly melting or vaporizing the surface of the material. At the same time, due to the extremely short action time, the heat generated will hardly be transferred to the surrounding materials, avoiding the common thermal damage problems in traditional drilling methods. For example, in SSD manufacturing, femtosecond laser ablation can accurately form tiny and uniform blind holes at specified locations to ensure the quality of subsequent interconnection processes. In order to ensure that each blind hole can reach the expected depth, it is also necessary to measure the blind hole depth to obtain the blind hole depth data. These data are not only an important reference for the subsequent deep silicon etching process, but also directly related to the final interconnection effect. Based on the blind hole depth data obtained above, the next step is to perform a deep silicon etching process on the blind hole chip stack to form a through-hole chip stack. Deep silicon etching is a high-precision material removal technology that can go deeper along the pre-formed blind hole until it penetrates the entire chip stack to form a through hole that runs through all layers. This process is critical to ensuring that reliable electrical connections can be established between different levels. For example, in SSD manufacturing, the deep silicon etching process can create a low-resistance conductive path, thereby reducing signal transmission delays and improving overall performance.In order to evaluate the quality of the through-hole, it is also necessary to perform a roughness analysis on the through-hole sidewall to obtain the sidewall roughness data. The smoothness of the sidewall directly affects the effect of the subsequent insulation layer deposition, so it must be strictly controlled. Once the through-hole sidewall roughness data is obtained, it is necessary to use selective atomic layer deposition (ALD) technology to deposit an insulation layer on the through-hole chip stack to form an insulation coating chip stack. Selective atomic layer deposition is a technology that can accurately control the thickness of a film at the nanoscale. It can uniformly deposit a thin layer of insulating material, such as silicon dioxide or other high-performance insulating materials, on the sidewall of the through-hole. For example, in SSD manufacturing, ALD technology can ensure that each through-hole sidewall is covered with a dense and uniform insulation layer to prevent current leakage or short circuit. In order to verify the quality of the insulation layer, it is also necessary to calculate the thickness uniformity of the insulation layer to obtain thickness uniformity data. These data not only provide intuitive visual feedback, but also provide a basis for the subsequent planarization process. Based on the thickness uniformity data obtained above, the next step is to perform a planarization process on the insulation coating chip stack to form a planarized chip stack. The planarization process aims to eliminate the slight unevenness of the surface and give the chip stack a very high finish. For example, in SSD manufacturing, the surface of the insulating layer can be made smoother by methods such as chemical mechanical polishing (CMP), providing ideal conditions for subsequent metal filling interconnection. The quality of planarization is directly related to the effect of the final interconnection, so it is necessary to ensure that every detail meets the design requirements. Finally, the metal filling interconnection of the planarized chip stack is carried out by electrochemical deposition technology to obtain an interconnected chip stack. Electrochemical deposition is a method of reducing metal ions to metal atoms and depositing them on the electrode surface. It can arrange a large number of interconnection lines in a very small space, greatly improving the connection density per unit area. For example, in SSD manufacturing, metal materials such as copper or tungsten can be uniformly filled into each through hole through electrochemical deposition to form a low-resistance conductive path. This method not only reduces the occupied space, but also enhances the integration and reliability of the system. The resulting interconnected chip stack not only has a higher integration and faster data transmission speed, but also significantly enhances the reliability and durability of the system. In summary, this series of carefully designed and technically implemented steps not only achieves efficient and stable electrical connections between different levels inside the cut chip stack, but also greatly improves production efficiency and product quality. This method is particularly suitable for application scenarios that require strict interconnection accuracy, such as high-speed solid-state drives (SSDs) in data center servers. The result is a significant enhancement of the overall performance and reliability of the system, which has promoted the development of the information technology field. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance, but also maintains stable operation in various working environments, fully meeting the needs of the continuous development of modern information technology.

[0042] In a specific embodiment, the method of using heterogeneous integrated packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure includes: Performing a three-dimensional structural scan on the interconnected chip stack to obtain three-dimensional structural data, and performing a structural design on the packaging cavity of the interconnected chip stack based on the three-dimensional structural data to obtain a packaging cavity model; The packaging cavity model is vacuum-sealed with resin by adopting heterogeneous integrated packaging technology to obtain a resin-filled chip stack, and a filling uniformity test is performed on the resin-filled chip stack to obtain resin filling uniformity data; Based on the resin filling uniformity data, ultraviolet curing is performed on the resin-filled chip stack to obtain a cured resin chip stack, and a curing degree detection is performed on the cured resin chip stack to obtain curing degree data; When the curing degree data reaches a preset curing degree range, the cured resin chip stack is laser demoulded by a preset femtosecond laser precision control system to obtain a demoulded chip stack; The demoulded chip stack is plasma cleaned to obtain a clean chip stack, and the clean chip stack is externally connected with wires by wire bonding technology to obtain a target packaged memory chip stack structure.

[0043] Specifically, in the process described above, "the use of heterogeneous integrated packaging technology to vacuum resin encapsulate the interconnected chip stack to obtain the target package memory chip stack structure" includes multiple precise and interrelated technical steps, which ensure that the multi-layer stack memory not only has high performance, but also has excellent reliability and environmental adaptability. The whole process starts from three-dimensional structure scanning to the final realization of external lead connection. Each step is crucial and jointly guarantees the quality and performance of the finished product. First, in order to accurately design the packaging cavity suitable for the interconnected chip stack, it is necessary to perform a three-dimensional structure scan on it to obtain detailed three-dimensional structure data. This technology uses high-resolution imaging equipment to capture every detail of the chip stack, including its external dimensions, internal through-hole distribution, and relative positions between layers. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers use this scanning method to fully understand the specific layout and connection method of each NAND flash memory die. Based on these three-dimensional structure data, technicians can further design the structure of the packaging cavity of the interconnected chip stack to form a packaging cavity model. This step not only takes into account the physical properties of the chip stack itself, but also must take into account factors such as heat dissipation and shockproof to ensure that the packaged device can operate stably under various working conditions. Next, the package cavity model is vacuum-filled with resin by using heterogeneous integrated packaging technology to obtain a resin-filled chip stack. Heterogeneous integrated packaging technology allows chips with different functions or process nodes, such as logic control units and storage units, to be integrated in the same package, thereby improving the system's integration and simplifying subsequent design and assembly processes. In actual operation, vacuum resin filling packaging is to inject a specific type of resin material into a pre-designed package cavity under a high vacuum environment and allow it to solidify to form a solid whole. This material not only provides physical protection to prevent the intrusion of external contaminants such as dust and moisture, but also effectively reduces stress caused by temperature changes and prolongs the service life of the device. In order to ensure the quality of packaging, it is also necessary to perform filling uniformity detection on the resin-filled chip stack to obtain resin filling uniformity data. These data not only provide intuitive visual feedback, but also provide important references for subsequent processing. For example, in SSD manufacturing, uniform resin filling helps maintain the consistency and stability of internal circuits. Once the resin filling uniformity data is obtained, the resin-filled chip stack needs to be UV-cured to obtain a cured resin chip stack. UV curing is a fast and efficient material hardening method that uses ultraviolet light of a specific wavelength to cause a chemical reaction in the resin, rapidly transforming it into a hard solid state. In order to ensure the curing effect, technicians will perform a curing degree test on the cured resin chip stack to obtain curing degree data. These data are directly related to the mechanical strength and electrical properties of the packaged device, so they must be strictly controlled.For example, in SSD manufacturing, the appropriate degree of curing can ensure that the resin can firmly fix the internal structure without causing any damage to it. When the curing degree data reaches the preset curing degree range, it means that the package has reached the expected quality standard. Next, the cured resin chip stack is laser demolded by the preset femtosecond laser precision control system to obtain a demolded chip stack. The femtosecond laser precision control system can release huge energy in a very short time to accurately cut or peel off excess materials. At the same time, due to the extremely short action time, the heat generated is almost not transferred to the surrounding materials, avoiding the common thermal damage problem in traditional cutting methods. For example, in SSD manufacturing, the femtosecond laser can accurately remove excess resin at the edge of the package, so that the chip stack can be smoothly removed from the mold without affecting its internal structure. The demolding process not only improves production efficiency, but also creates favorable conditions for subsequent processes. Finally, in order to ensure that the chip stack after encapsulation has good electrical connection performance, it needs to be plasma cleaned to obtain a clean chip stack. Plasma cleaning is a method that uses plasma to chemically react with the surface of the material to remove tiny impurities, which can significantly improve the cleanliness and flatness of the surface. For example, in SSD manufacturing, this method can remove possible residual particulate matter or organic contaminants and provide an ideal contact surface for wire bonding. After cleaning, technicians will use wire bonding technology to connect the clean chip stack to the external wires to obtain the target packaged memory chip stack structure. Wire bonding is the process of connecting thin metal wires between the pads on the chip and the external pins to achieve electrical connection. This method not only ensures the reliability of signal transmission, but also reserves enough space for future system upgrades and expansions. In summary, this series of carefully designed and technically implemented steps not only achieves efficient packaging of interconnected chip stacks, but also greatly improves production efficiency and product quality. This method is particularly suitable for application scenarios that require strict packaging accuracy, such as high-speed solid-state drives (SSDs) in data center servers. The result is a significant enhancement of the overall performance and reliability of the system, which promotes the development of the field of information technology. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance, but also maintains stable operation in various working environments, fully meeting the needs of the continuous development of modern information technology.

[0044] The above describes the chip interconnection method of the multi-layer stacked memory package structure in the embodiment of the present invention. The following describes the chip interconnection device of the multi-layer stacked memory package structure in the embodiment of the present invention. Figure 2 An embodiment of a chip interconnection device of a multi-layer stacked memory package structure in an embodiment of the present invention includes: An arrangement module 21 is used to arrange the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; An alignment module 22, configured to align bonding surfaces of each target storage die in the arranged chip array by using a high-precision alignment device to obtain an aligned chip array; A heat pressing module 23 is used to perform heat pressing bonding operation on the alignment chip array using heat pressing bonding technology to obtain a bonded chip stack; A cutting module 24 is used to perform edge cutting on the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack; An interconnection module 25, used to perform three-dimensional through-hole interconnection on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack; The packaging module 26 is used to perform vacuum resin packaging on the interconnected chip stack using heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure.

[0045] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0046] Reference Figure 3 The present invention also provides a computer device in an embodiment, wherein the internal structure of the computer device can be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0047] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0048] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0049] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0050] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0051] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip interconnection method for a multi-layer stacked memory packaging structure, characterized in that: The following steps are involved: Arranging the positions of the plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; Aligning the bonding surfaces of the target storage dies in the arranged chip array by a high-precision alignment device to obtain an aligned chip array; Performing a thermal compression bonding operation on the alignment chip array using a thermal compression bonding technology to obtain a bonded chip stack; Using femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack; Performing metal filling interconnection on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack; The interconnected chip stack is packaged with vacuum resin using heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure.

2. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of arranging the positions of the plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array includes: The preset chip layout diagram is analyzed for inter-layer interconnection paths by using a preset analysis algorithm to obtain an interconnection density distribution diagram and a chip function division table; Performing initial position allocation for the plurality of thinned memory dies based on the interconnection density distribution map to obtain an initial arrangement chip array; Based on the chip function division table, the initially arranged chip array is divided into layers to obtain a layered chip array; A preset high-precision robotic arm is controlled by a space filling curve algorithm to arrange the positions of each layer of chips in the layered chip array to obtain an arranged chip array.

3. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The step of aligning the bonding surfaces of the target storage dies in the arranged chip array by a high-precision alignment device to obtain an aligned chip array includes: Performing dual-wavelength light interference measurement on the arranged chip array to obtain chip surface profile data; Extracting edge features from the chip surface contour data using a sub-pixel edge detection algorithm to obtain a chip edge feature map; Based on the chip edge feature map, a six-degree-of-freedom posture analysis is performed on each of the target storage dies in the arranged chip array to obtain chip spatial posture data; Through the piezoelectric nano-displacement platform, the spatial position data of the chip is subjected to real-time closed-loop feedback control to obtain a displacement compensation parameter set; wherein the displacement compensation parameter set includes XY plane displacement, Z axis height error and angle correction value; Generate a preset alignment execution instruction sequence of multi-axis linkage control in a high-precision alignment device based on the displacement compensation parameter set; The alignment execution instruction sequence is used to control the high-precision bonding surface alignment of each target storage die in the arranged chip array to obtain an aligned chip array.

4. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of using a thermal compression bonding technology to perform a thermal compression bonding operation on the alignment chip array to obtain a bonded chip stack includes: Preheating the aligned chip array using a preset temperature curve to obtain a preheated chip array, and simulating the bonding area temperature field of the preheated chip array to obtain temperature field distribution data; Based on the temperature field distribution data, parameters of a preset thermal compression bonding device are set to obtain set parameters, and real-time temperature monitoring and feedback control are performed on the set parameters to obtain a temperature control curve; Using the thermal compression bonding technology, the alignment chip array is subjected to thermal compression bonding operation through the set pressure curve and the temperature control curve to obtain an initial bonded chip stack, and a bonding interface stress analysis is performed on the initial bonded chip stack to obtain stress distribution data; Based on the stress distribution data, ultrasonic-assisted bonding treatment is performed on the bonding interface in the quasi-chip array to obtain a reinforced bonded chip stack, and bonding strength test is performed on the reinforced bonded chip stack to obtain bonding strength data; The vacuum annealing process technology is used to eliminate residual stress of the reinforced bonded chip stack based on the bonding strength data to obtain a bonded chip stack.

5. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of cutting the edges of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack comprises: Performing three-dimensional X-ray tomography on the bonded chip stack to obtain a stacking structure image, and performing femtosecond laser scanning path planning based on the stacking structure image to obtain a laser scanning path diagram; Performing thermal effect simulation analysis on the laser scanning path diagram to obtain heat-affected zone distribution data, and setting parameters of a preset femtosecond laser based on the heat-affected zone distribution data to obtain laser processing parameters; Based on the laser processing parameters, the femtosecond laser is controlled to perform femtosecond laser cutting on the bonded chip stack to obtain a rough-cut chip stack, and a cutting edge morphology characterization is performed on the rough-cut chip stack to obtain cutting edge morphology data; Performing plasma-assisted etching on the rough-cut chip stack based on the cutting edge morphology data to obtain a fine-cut chip stack; The finely cut chip stack is subjected to chemical mechanical polishing and edge cutting to obtain a cut chip stack.

6. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of performing metal filling interconnection on the cut chip stack by using a micro-pitch interconnection technology to obtain an interconnected chip stack comprises: Performing through-hole position planning on the cut chip stack based on a preset interconnection circuit diagram to obtain a through-hole position distribution map, and performing electromagnetic field simulation analysis on the through-hole position distribution map to obtain electromagnetic interference distribution data; Performing blind hole processing on the cut chip stack based on the electromagnetic interference distribution data by femtosecond laser ablation technology to obtain a blind hole chip stack, and measuring the blind hole depth of the blind hole chip stack to obtain blind hole depth data; Based on the blind hole depth data, the blind hole chip stack is subjected to a deep silicon etching process to obtain a through hole chip stack, and a through hole side wall roughness analysis is performed on the through hole chip stack to obtain side wall roughness data; Depositing an insulating layer on the through-hole chip stack based on the sidewall roughness data and the through-hole depth data by a selective atomic layer deposition technique to obtain an insulating coating chip stack, and calculating the thickness uniformity of the insulating layer on the insulating coating chip stack to obtain thickness uniformity data; Performing a planarization process on the insulating coating chip stack based on the thickness uniformity data to obtain a planarized chip stack; The planarized chip stack is metal-filled and interconnected by electrochemical deposition technology to obtain an interconnected chip stack.

7. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of using the heterogeneous integrated packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure includes: Performing a three-dimensional structural scan on the interconnected chip stack to obtain three-dimensional structural data, and performing a structural design on the packaging cavity of the interconnected chip stack based on the three-dimensional structural data to obtain a packaging cavity model; The packaging cavity model is vacuum-sealed with resin by adopting heterogeneous integrated packaging technology to obtain a resin-filled chip stack, and a filling uniformity test is performed on the resin-filled chip stack to obtain resin filling uniformity data; Based on the resin filling uniformity data, ultraviolet curing is performed on the resin-filled chip stack to obtain a cured resin chip stack, and a curing degree detection is performed on the cured resin chip stack to obtain curing degree data; When the curing degree data reaches a preset curing degree range, the cured resin chip stack is laser demoulded by a preset femtosecond laser precision control system to obtain a demoulded chip stack; The demoulded chip stack is plasma cleaned to obtain a clean chip stack, and the clean chip stack is externally connected with wires by wire bonding technology to obtain a target packaged memory chip stack structure.

8. A chip interconnection device of a multi-layer stacked memory packaging structure, characterized in that: include: An arrangement module, used for arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; An alignment module, used for aligning the bonding surfaces of the target storage dies in the arranged chip array by means of a high-precision alignment device to obtain an aligned chip array; A thermal compression module, used for performing thermal compression bonding operation on the alignment chip array using thermal compression bonding technology to obtain a bonded chip stack; A cutting module, used for cutting the edges of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack; An interconnection module, used to perform metal filling interconnection on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack; The packaging module is used to perform vacuum resin packaging on the interconnected chip stack using heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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