Method for preventing defects in integrated etching process and fabricating metal interconnect structure

Abstract

The present invention discloses a method for preventing defects in an integrated etching process and fabricating a metal interconnect structure. First, a multi-layer film structure is fabricated on a target wafer having a first metal layer, and then an integrated etching process is used to fabricate a notch exposing the first metal layer in the multi-layer film structure. After etching is completed, a CO / N2 mixed gas is introduced as a plasma gas in the static elimination process to deposit a stable isolation protection layer on the surface of the notch to isolate the residual polymer generated in the notch during the etching process. After static elimination is completed, the wafer is lifted and transferred to a wafer cassette. The wafer in the wafer cassette is transferred to a wet cleaning process to clean the deposited metal layer. The CMP process is used to remove the excess metal layer and the multi-layer film structure to complete the fabrication of the metal interconnect structure. The present invention prevents defects from occurring in the integrated etching process by improving the static elimination process, achieving unexpected effects, enabling the wafer in the wafer cassette not to require high-purity nitrogen protection during transfer, and greatly extending the maximum waiting time.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to an integrated etching process, and specifically relates to a method for preventing defects in the integrated etching process and preparing a metal interconnect structure. Background Art

[0002] The all-in-one (AIO) etching process is a method of synchronously etching trenches and vias, also known as the integrated etching of a metal hard mask damascene. After the hard mask is opened, a trench pattern is defined, and then a via pattern is defined by exposure and development. Finally, the trenches and vias are etched simultaneously, and the patterns of the trenches and vias are completed in one step. After etching, the electrostatic chuck's clamping of the wafer is released through a dechucking process, and then the wafer is transferred to a front opening unified pod (Foup). The wafer needs to wait for a certain time in the wafer transfer cassette before entering the wet cleaning process (WET). After cleaning through the wet cleaning process, a Cu layer of a certain thickness is grown in the vias and trenches through an electroplated copper process (Cu ECP). Finally, through a chemical mechanical polishing process (CMP), the unnecessary Cu and the metal hard mask are removed to obtain a metal interconnect structure.

[0003] After the integrated etching is completed, due to etching process problems, by-products will be generated. The by-products are residual polymers containing carbon and fluorine elements (C x F y polymer). When the wafer is transferred to the front opening unified pod, it will come into contact with air and water vapor. At this time, the residual polymer (C x F y polymer) will form titanium fluoride residues (Ti x F y residue) with water vapor, TiN (the metal hard mask is generally TiN), etc. The titanium fluoride residues cover the inner surfaces of the trenches and vias (collectively referred to as the notch), and are removed during the subsequent wet cleaning process. It is difficult to completely remove the titanium fluoride residues. The remaining titanium fluoride prevents Cu from filling in during electroplated copper. After the CMP process, the titanium fluoride residues are ground off to form voids, resulting in interconnect defects.

[0004] In addition, after etching is completed and before entering the wet cleaning process, the waiting time of the wafer in the wafer transfer cassette is often several hours to dozens of hours. During this process, the wafer will also come into contact with air or water vapor. The water vapor and the residual polymer (Cx F y reacts with the polymer to produce titanium fluoride residues that are difficult to remove.

[0005] In the prior art, the conventional solution is to add a post-etch treatment (PET) after the integrated etching is completed. A plasma gas (using N2 / H2) is used to remove the fluoropolymer in the grooves formed by the integrated etching. However, the removal effect is limited. Therefore, high-purity nitrogen needs to be replenished in the wafer cassette at intervals (usually 2 hours) to prevent the remaining fluoropolymer from reacting with the water vapor in the air to produce titanium fluoride residues that are difficult to remove in the subsequent wet cleaning process when the wafer stays for a long time. Even so, the waiting time of the wafer in the wafer cassette cannot exceed 4 hours. This not only has high costs and cumbersome operations but also seriously affects the flexible allocation of subsequent processes.

[0006] The prior art CN106206422A discloses a method for reducing the growth of defects in the integrated etching of a metal hard mask damascene. The first step: perform the integrated etching treatment of the metal hard mask damascene. The second step: use an etching device to clean the polymer generated during the etching process on the wafer surface. The third step: use an etching device to deposit a relatively stable polymer on the wafer surface to prevent the device surface on the wafer from reacting with the air to produce polymers that block etching defects. The second step is actually the above PET process. In the third step, nitrogen and carbon monoxide react to obtain carbon nitride and oxygen. Carbon nitride is a stable polymer that blocks the reaction between the device surface on the wafer and the air to produce polymers that block etching defects. Due to effective trapping, the waiting time of the integrated etched wafer of the metal hard mask damascene before wet etching is extended. The process flexibility is increased. However, this process still has the PET process in the second step. Without this step, the actual effect cannot reach the ideal effect. And when the electrostatic chuck releases the clamping of the wafer during the dechucking process after the third step, an inert gas needs to be introduced. The commonly used inert gas Ar will bombard the stable polymer generated in the third step, causing partial failure of the stable polymer and affecting the isolation effect of the stable polymer.

[0007] Therefore, it is necessary to further research and develop to improve the residue removal or isolation efficiency and significantly extend the waiting time of the integrated etched wafer of the metal hard mask damascene before wet etching without nitrogen protection. Summary of the Invention

[0008] One object of the present invention is to provide a method for preventing defects in the integrated etching process to solve the problem of preventing by-products in the integrated etching process from causing defects.

[0009] Another object of the present invention is to provide a method for preparing a metal interconnect structure. By using the above method to prepare the metal interconnect structure, the yield of the metal interconnect structure is improved.

[0010] To solve the above technical problems, the present invention adopts the following technical solutions:

[0011] On the one hand, the present invention provides a method for preventing defects in an integrated etching process, including the following steps:

[0012] Form a notch using an integrated etching process;

[0013] After the etching is completed, in the static elimination process, a CO / N2 mixed gas is introduced as the plasma gas, so that the plasma gas reacts, and a stable isolation protection layer is deposited on the surface of the notch to isolate the residual polymer generated at the notch during the etching process.

[0014] Further, the static elimination process includes the following three stages:

[0015] The first stage: Prepare the static elimination conditions. After the etching is completed, a CO / N2 mixed gas is introduced into the etching chamber, and after reaching the first pressure, it is maintained for a period of time;

[0016] The second stage: Maintain the first pressure, start the radio frequency power supply, dissociate the CO / N2 mixed gas into plasma gas, and under the interaction of ions, the plasma gas quickly reacts on the surface of the notch to generate a stable isolation protection layer;

[0017] The third stage: Apply a reverse voltage to the electrostatic chuck to release the clamping of the wafer.

[0018] Further, in the first stage, the first pressure is 100 mT - 400 mT, and the maintenance time after reaching the first pressure is 4 - 20 s. During the pressure maintenance process, the CO / N2 mixed gas is continuously introduced for purging and replacement.

[0019] Further, in the second stage, the pressure of the first stage is maintained, the radio frequency energy is set to 100 - 400 W, the maintenance time of the second stage is 2 - 8 s, and the continuous presence of the plasma gas is maintained.

[0020] Further, the maintenance time of the third stage is 0.5 - 4 s, and the continuous presence of the plasma gas is maintained.

[0021] On the other hand, the present invention provides a method for preparing a metal interconnect structure, including the following steps:

[0022] Provide a target wafer with a first metal layer, and the first metal layer is a metal line on the target wafer;

[0023] Fabricate a multi-layer film structure on the first metal layer;

[0024] Use an integrated etching process to fabricate a notch exposing the first metal layer in the multi-layer film structure;

[0025] After etching is completed, in the de-charging process, a CO / N2 mixed gas is introduced as the plasma gas, causing the plasma gas to react and deposit a stable isolation protection layer on the surface of the notch to isolate the residual polymer generated in the notch during the etching process;

[0026] After de-charging is completed, lift the wafer and transfer it to the wafer cassette;

[0027] Transfer the wafer in the wafer cassette to the wet cleaning process to clean off the stable isolation protection layer and the residual polymer;

[0028] Deposit a metal layer in the notch;

[0029] Adopt the CMP process to remove the excess metal layer and the multi-layer film structure to complete the fabrication of the metal interconnection structure.

[0030] Further, the multi-layer film structure includes a first etch stop layer, a low-k dielectric layer, a second etch stop layer, and a hard mask layer sequentially fabricated on the first metal layer.

[0031] Further, when using the integrated etching process, an anti-reflection coating is coated on the hard mask layer during the integrated etching.

[0032] Further, the first etch stop layer includes, but is not limited to, nitride-doped silicon carbide, silicon nitride; the second etch stop layer includes, but is not limited to, tetraethyl orthosilicate layer, silicon dioxide, silicon nitride.

[0033] On the other hand, the present invention provides a metal interconnection structure fabricated by the preparation method.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] The present invention eliminates the post-etch treatment (PET) process in the prior art, significantly reducing costs after reducing the number of processes and improving process controllability; on the basis of eliminating the post-etch treatment process, in the de-chuck step of the present invention, the original inert gas Ar is changed to a CO / N2 mixed gas, and the RF power supply is started during the de-charging process to dissociate the CO / N2 mixed gas into a plasma gas. Unexpectedly, this plasma gas can not only eliminate the surface charge of the wafer but also react with each other to generate a stable isolation protection layer, isolating and covering the residual polymer (C x F y polymer), avoiding the transfer through the front-opening unified pod, and the residual polymer (C x Fy The polymer reacts with water vapor to produce titanium fluoride residues that are difficult to remove during subsequent wet cleaning processes. Unexpectedly, due to the excellent isolation and protection effect of the isolation protection layer of the present invention, during the transfer process in the wafer transfer cassette, the wafer transfer cassette does not require high-purity nitrogen protection, and the maximum waiting time of the wafers in the wafer transfer cassette of the present invention is also extended from 4 hours in the prior art to 24 hours, greatly improving the flexibility of subsequent processes and the yield of the finally obtained semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a flowchart of the method for preventing defects in the integrated etching process in Embodiment 1 of the present invention.

[0037] Figure 2 It is a flowchart of the method for preparing a metal interconnect structure in Embodiment 2 of the present invention.

[0038] Figure 3 It is a schematic diagram of the target wafer provided in step S210 of Embodiment 2 of the present invention.

[0039] Figure 4 It is a schematic diagram of fabricating a multi-layer film structure in step S220 of Embodiment 2 of the present invention.

[0040] Figure 5 It is a schematic diagram of completing trench definition during integrated etching in step S230 of Embodiment 2 of the present invention.

[0041] Figure 6 It is a schematic diagram of completing trench profile etching during integrated etching in step S230 of Embodiment 2 of the present invention.

[0042] Figure 7 It is a schematic diagram of completing via definition during integrated etching in step S230 of Embodiment 2 of the present invention.

[0043] Figure 8 It is a schematic diagram of fabricating a notch in the multi-layer film structure using the integrated etching process in step S230 of Embodiment 2 of the present invention.

[0044] Figure 9 It is a schematic diagram of generating an isolation protection layer during the de-energization process in step S240 of Embodiment 2 of the present invention.

[0045] Figure 10 It is a schematic diagram of depositing a metal layer in the notch in step S270 of Embodiment 2 of the present invention.

[0046] Figure 11 It is a schematic diagram of obtaining a metal interconnect structure in step S280 of Embodiment 2 of the present invention.

[0047] Figure 12Schematic diagram of connecting a second metal layer to the metal interconnect structure in Embodiment 2 of the present invention to achieve the interconnection of two semiconductor structures.

[0048] Figure 13 Schematic diagram of the optimal key parameter control for the electroplating process in Embodiment 2 of the present invention.

[0049] Figure 14 Comparison diagram of the effects of Embodiment 2 of the present invention with the prior art.

[0050] Figure 15 Comparison diagram of the void defects in Embodiment 2 of the present invention and the void defects in the prior art. Among them, Figure 15 A in the figure is the electron microscopy image of the metal interconnect structure with void defects in the prior art, Figure 15 B in the figure is the electron microscopy image of the void defects in Embodiment 2 of the present invention.

[0051] 100 - Target wafer, 110 - First metal layer, 120 - Dielectric layer;

[0052] 200 - Multilayer film structure, 210 - First etch stop layer, 220 - Low-k dielectric layer, 230 - Second etch stop layer, 240 - Hard mask layer, 250 - Organic anti-reflection coating, 260 - Inorganic anti-reflection coating, 270 - PR layer;

[0053] 310 - Residual polymer, 320 - Isolation protection layer; 400 - Metal layer, 410 - Metal interconnect structure, 500 - Semiconductor structure, 510 - Second metal layer. Detailed implementation manners

[0054] The following further describes in detail the implementation manners of the present invention in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0055] The dechuck process is an essential process in wafer processing. To prevent the wafer from displacing in the etching chamber and ensure the wafer processing accuracy, in the prior art, an electrostatic chuck (ESC) is set in the etching chamber. The ESC applies an electric field to adsorb and fix the wafer. When one process ends and it is necessary to transfer to the next process, a plasma gas formed by an inert gas is introduced to neutralize the surface charge of the wafer. Then, a reverse voltage is applied to the ESC to release the clamping of the wafer, and a robotic arm or other tools are used to transfer the wafer into a front-opening unified pod (Foup). The Foup is transferred to the next station to perform the next process. In the present invention, integrated etching and wet cleaning are two processes, and they need to be transferred through the wafer transfer box in the middle. During the transfer process, the wafer will come into contact with the water vapor in the air. The residual polymer (C x F y polymer) generated by the integrated etching will form titanium fluoride residues (Ti x F y residue) with water vapor, TiN (the metal hard mask is generally TiN), etc. The titanium fluoride residues cover the inner surfaces of the trenches and vias (collectively referred to as the notch). They are removed during the subsequent wet cleaning process. It is difficult to completely remove the titanium fluoride residues, thus forming defects. In addition, during the transfer process of the wafer transfer box, it needs to stay for a period of time to flexibly adjust the process. However, the longer the waiting time, the greater the probability that the wafer will come into contact with the water vapor in the air, the more titanium fluoride residues will be generated, and the greater the possibility of subsequent defects. In the prior art, a limit residence time is set in the center protected by high-purity nitrogen, generally set to about 4 hours. After the waiting time exceeds 4 hours, even with the protection of high-purity nitrogen, more defects will be generated, thus affecting the yield of the semiconductor structure. The present invention has carried out relevant research and development to solve the above problems. The following is an example of the present invention.

[0056] Example 1: As Figure 1 shown, this example provides a method for preventing defects in the integrated etching process, including the following steps:

[0057] S110. Form a notch using an integrated etching process, where the notch includes vias and trenches;

[0058] S120. After etching is completed, introduce a CO / N2 mixed gas as the plasma gas in the dechuck process to make the plasma gas react, and deposit a stable isolation protection layer on the surface of the notch to isolate the residual polymer generated in the notch during the etching process.

[0059] In this embodiment, the object of the integrated etching process can be any interconnect structure in the prior art. The interconnect structure at least includes a lower metal line ( Figure 12 the first metal layer 110 in x F y ). The formation of a notch by the integrated etching process generally includes a through hole and a trench, and the lower metal line is exposed in the through hole. In this embodiment, the post-etch treatment (PET) in the prior art is removed. Directly in the Dechuck step, the original inert gas Ar is changed to a CO / N2 mixed gas. During the Dechuck process, the RF power supply is started, and the CO / N2 mixed gas is dissociated into a plasma gas. The unexpected technical effect is that while the plasma gas eliminates the surface charge of the wafer (the function of the original inert gas), it can also react with each other to generate a stable isolation protection layer, isolating and covering the residual polymer ( x F y polymer), avoiding the reaction between the residual polymer (

[0060]

[0061]

[0062]

[0063] x F y polymer) and water vapor during the transfer through the front-opening wafer cassette, which is difficult to remove in the subsequent wet cleaning process. Due to the good isolation and protection effect of the isolation protection layer of the present invention, during the transfer of the wafer cassette, the wafer cassette does not require high-purity nitrogen protection, and the maximum waiting time of the wafer in the wafer cassette of the present invention is extended from 4 hours in the prior art to 24 hours, greatly improving the flexibility of the subsequent process and the yield of the final obtained semiconductor structure.

[0063] Example 2: As Figure 2 shown, the present invention provides a method for manufacturing a metal interconnect structure, including the following steps:

[0064] S210. Provide a target wafer 100 having a first metal layer 110. The first metal layer 110 is a metal circuit on the target wafer 100 and is isolated by a dielectric layer 120, as Figure 3 shown;

[0065] S220. Fabricate a multi-layer film structure 200 on the first metal layer 110. The multi-layer film structure 200 includes a first etch stop layer 210, a low-k dielectric layer 220, a second etch stop layer 230, and a hard mask layer 240 sequentially fabricated on the first metal layer 110, as Figure 4 shown;

[0066] S230. As Figures 5 to 8 shown, use an integrated etching process to fabricate a notch exposing the first metal layer 110 in the multi-layer film structure 200. The notch includes a trench and a via hole. The via hole is used to connect the first metal layer 110, and the trench is a wire trench connected to the via hole. As Figure 8 shown, a residual polymer 310 is present in the fabricated notch;

[0067] S240. After etching is completed, introduce a CO / N2 gas mixture as a plasma gas during the de-energization process to cause the plasma gas to react and deposit a stable isolation protection layer 320 on the surface of the notch to isolate the residual polymer 310 generated in the notch during the etching process, as Figure 9 shown;

[0068] S250. After de-energization is completed, lift the target wafer 100 and transfer it to a wafer cassette;

[0069] S260. Transfer the wafer in the wafer cassette to a wet cleaning process to clean and remove the stable isolation protection layer 320 and the residual polymer 310;

[0070] S270. Deposit a metal layer 400 in the notch, as Figure 10 shown;

[0071] S280. Use a CMP process to remove the excess metal layer 400 and the multi-layer film structure 200 to complete the fabrication of the metal interconnect structure 410, as Figure 11 shown.

[0072] A second metal layer 510 can be fabricated on the metal interconnect structure 410 or a semiconductor structure 500 having a second metal layer 510 can be bonded to the metal interconnect structure 410 to achieve the interconnection of two semiconductor structures, as Figure 12 shown.

[0073] By preparing the metal interconnect structure through the method of this embodiment, the post-etch treatment (PET) process is eliminated. Instead of the original inert gas, a plasma gas that can react to form a stable polymer is directly used in the Dechuck step to deposit an isolation protection layer 320 that isolates the residual polymer (C x F y polymer) from the external environment, avoiding the conversion of the residual polymer (C x F y polymer) into titanium fluoride residues that are difficult to clean by wet cleaning when it comes into contact with water vapor. This enables subsequent transfer through the wafer cassette without the protection of high-purity nitrogen, reducing costs and process complexity. At the same time, the maximum waiting time of the wafer in the wafer transfer cassette is extended to about 24 hours, greatly improving process flexibility, reducing the probability of voids in the metal layer of the metal interconnect structure, and improving the yield of the semiconductor structure.

[0074] In step S210, as Figure 3 shown, the target wafer 100 provided in this embodiment has already prepared the required semiconductor structure, and a first metal layer 110 is reserved on the upper surface for metal interconnect. Generally, a dielectric layer is filled in the interval of the first metal layer 110, and the dielectric layer is an insulating material, such as silicon dioxide, etc.

[0075] The first etch stop layer 210 can be a common etch stop layer material in the prior art, including but not limited to nitride-doped silicon carbide, silicon nitride; in this embodiment, it is preferably a nitride-doped silicon carbide (NDC) layer; the low-k dielectric layer 220 is a low dielectric constant material layer, which can be made of silicon dioxide (SiO2) or a BD layer. The BD (Black Diamond) layer is a low dielectric constant material based on chemically vapor-deposited carbon-doped silicon dioxide launched by Applied Materials (AMAT), and its dielectric constant k = 2.7; the second etch stop layer can be a common etch stop layer material in the prior art, including but not limited to tetraethyl orthosilicate layer, silicon dioxide, silicon nitride, and in this embodiment, it is preferably tetraethyl orthosilicate (TEOS); the hard mask layer 240 serves as a mask, and the hard mask layer 240 generally uses a titanium nitride (TiN) layer.

[0076] In step S230, in order to improve the quality and efficiency of the integrated etching, before the integrated etching, an anti-reflection coating (ARC) is first coated on the hard mask layer 240, and a photoresist (PR) is coated to form a PR layer 270; as Figure 5As shown, in this embodiment, the anti-reflection coating has a two-layer structure, which are an organic anti-reflection coating 250 and an inorganic anti-reflection coating 260 from bottom to top. The organic anti-reflection coating 250 is a common bottom anti-reflection coating (BARC) in the prior art, and its main components are crosslinkable resin, thermally acid-generating agent, surfactant, and solvent; the inorganic anti-reflection coating 260 is silicon oxynitride (SiON), and the inorganic anti-reflection coating 260 mainly acts as a barrier layer in the AIO etching to reduce the bombardment damage to the hard mask layer 240 (TIN).

[0077] In step S230, during the integrated etching, first, a lithography (exposure, development) is performed to complete the trench definition, as Figure 5 shown; then, the hard mask layer 240 is etched, and the inorganic anti-reflection coating 260 and the organic anti-reflection coating 250 stay on the second etch stop layer 230 (tetraethyl orthosilicate (TEOS) layer) in sequence to complete the trench topography etching, as Figure 6 shown; after that, a second lithography (exposure, development) is performed to complete the via definition, as Figure 7 shown; then, a dry etching process is used to complete the etching of the trench and via at one time. This step is completed in the same etching chamber, so it is called all-in-one (AIO) etching; after the etching is completed, the first metal layer 110 is exposed at the bottom of the via. The trench and via together are collectively called the notch. Due to the etching process problem, a residual polymer containing carbon and fluorine elements (C x F y polymer) will be generated during the etching process. The residual polymer (C x F y polymer) mainly accumulates on the inner surface of the notch, as Figure 8 shown. If these residual polymers (C x F y polymer) are not removed or isolated and covered, they will come into contact with water vapor and air during the subsequent wafer transfer process and react with the water vapor to generate titanium fluoride residues (residual particles) that are difficult to remove by subsequent wet cleaning.

[0078] In S240, after the etching is completed, the de-electrification process includes the following three stages:

[0079] The first stage, preparing the de-electrification conditions. After the etching is completed, a CO / N2 mixed gas is introduced into the etching chamber, and it is maintained for a period of time after reaching the first pressure;

[0080] Second stage: Maintain the first pressure, start the RF power supply for glow discharge, dissociate the CO / N2 mixed gas into plasma gas. Under the interaction of ions, the plasma gas rapidly reacts on the notch surface to generate a stable isolation protection layer 320;

[0081] Third stage: Apply a reverse voltage to the electrostatic chuck to release the clamping of the wafer, and at the same time turn off the RF power supply.

[0082] In the first stage, the first pressure is 100mT - 400mT. Exemplarily, a more appropriate pressure is 250mT. After reaching the first pressure, the holding time T1 is 4 - 20s, and a suitable time is 8s. During the process of maintaining the pressure, continuously introduce the CO / N2 mixed gas for purging and replacement. The longer the holding time T1 after the first pressure, the better the purging and replacement effect. Residual gas and some impurities can be removed through purging and replacement, but if the time is too long, the energy efficiency ratio is not high.

[0083] In the second stage, set the RF power supply power at 250 - 450W as the glow discharge power. The greater the power of the power supply, the higher the degree of gas dissociation, and it is easier to form the isolation protection layer 320 to isolate water vapor. 250W is the lowest effective power verified by the production line. When it is lower than 250W, the obtained isolation protection layer 320 cannot produce an effective isolation effect. Of course, if the power of the power supply is too high, on the one hand, it is limited by the total power of the equipment, and on the other hand, the energy consumption is high, resulting in a large amount of energy waste. Therefore, a suitable power of the power supply is 350W.

[0084] In the second stage, the holding time after glow discharge determines the thickness of the isolation protection layer 320. If the holding time is too short, the generated isolation film cannot fully cover or the thickness is too small to play an effective isolation role; if the holding time is too long, the thickness of the generated isolation film is too large, making it difficult to remove in the subsequent wet cleaning process and causing waste of raw materials. Therefore, the holding time T2 for generating plasma gas by starting the power supply is generally 2 - 8s. Exemplarily, a suitable time is 3s.

[0085] In the second stage, during the glow discharge process, the CO / N2 mixed gas needs to be continuously introduced. The flow ratio of CO gas and N2 gas in the CO / N2 mixed gas has a great influence on the quality of the produced isolation protection layer 320. Theoretically, the higher the proportion of CO gas, the better the quality of the produced isolation protection layer 320 and the better the isolation effect. However, too high a proportion will affect the de - electrification process. Therefore, the appropriate N2 / CO ratio is 2:1 - 5:1 (mole ratio or volume flow ratio under the same pressure), and the optimal ratio is 3:1.

[0086] In the second stage, during the starting-up process, if the flow rate of CO gas is too small, an isolation protection film cannot be effectively formed, and if the flow rate is too large, it will cause waste of raw materials and energy. Therefore, the flow rate of CO gas should be no less than 100 sccm (standard cubic centimeters per minute) to form an effective isolation protection film. Generally, a CO gas flow rate in the range of 100 - 250 sccm is more appropriate.

[0087] In the second stage, both the pressure and flow rate of the CO / N2 mixed gas need to be maintained stable, and the same as in the first stage. Stable flow rate and pressure can ensure the acquisition of a high-quality isolation layer.

[0088] In the third stage, when applying a reverse voltage to the electrostatic chuck, there are generally no special requirements for the magnitude of the applied reverse voltage. For example, during adsorption, when the forward voltage is 2000V, the reverse voltage can be -100V at this time. In addition, applying the reverse voltage needs to be maintained for a short time T3 to fully release the charges on the wafer and enable it to smoothly detach from the electrostatic chuck. This short time is generally 0.5 - 4s. Exemplarily, 1s is generally adopted.

[0089] A schematic diagram of controlling a preferred key parameter in the above charge removal process is as Figure 13 shown. Using this parameter control to prepare an interconnection structure, after waiting for 24 hours (without high-purity nitrogen protection) in the wafer cassette, the void defect count is carried out, and the comparison results with the conventional post-etch treatment (PET) in the prior art and CN106206422A are as Figure 14 shown. Figure 14 In, the POR experimental conditions are: the PET process removes the fluorine-containing residual polymer (C x F y polymer) during the integrated etching process;

[0090] The EXP experimental conditions are: the PET process removes the fluorine-containing residual polymer (C x F y polymer) and generates a relatively stable polymer to isolate the residual polymer, that is, the technical solution conditions described in CN106206422A.

[0091] The CIP experimental conditions are: in the present invention, the charge is removed in the charge removal process (Dechuck) and a protective film is generated simultaneously. In the charge removal process, a CO / N2 mixed gas is introduced as the plasma gas, so that the plasma gas reacts, and a stable isolation protection layer 320 is deposited on the notch surface to isolate air and moisture.

[0092] By Figure 14It can be seen that after 24 hours of waiting, all the interconnect structures in the prior art that only adopt the post-etch treatment (PET) are invalid voids and cannot be used; when adopting the solution in the prior art CN106206422A, there are 13 invalid voids, which affect the yield. The microscopic structure diagram of the invalid void defect is as shown in Figure 15 Figure A in it. It can be seen that there is a void defect on the line at about the middle position, which affects the electrical performance of the line; the technical solution of the present invention has no defects and the yield is 100%, as shown in Figure 15 Figure B in it. It can be seen that the edge of the interconnect structure is clear and defect-free; the present invention not only has a better yield than the prior art CN106206422A, but also omits the post-etch treatment (PET), greatly reducing the cost.

[0093] In step S250, the target wafer 100 does not need to be protected by high-purity nitrogen in the wafer cassette, and the waiting limit time can reach about 24 hours; far exceeding 4 hours in the prior art.

[0094] In step S260, the target wafer 100 is soaked or sprayed and cleaned in a liquid cleaning agent to remove the contaminants on the chip surface through chemical reactions and physical actions. Common wet cleaning processes include immersion cleaning, spray cleaning, and ultrasonic cleaning.

[0095] In step S270, a certain thickness of Cu layer is grown in the through holes and trenches by an electrochemical copper plating process (Cu ECP) as the metal of the interconnect layer.

[0096] In step S280, the excess Cu layer, tetraethyl orthosilicate layer 230, and hard mask layer 240 are removed by a CMP process, and stopped at the low-k dielectric layer 220 to obtain the metal interconnect structure 410. A second metal layer 510 can be fabricated on the metal interconnect structure 410, or the second metal layer 510 and the metal interconnect structure 410 are bonded to achieve the interconnection of subsequent semiconductor processes.

[0097] The above embodiments are only used to illustrate the present invention, rather than limiting the present invention. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that various combinations, modifications, or equivalent replacements of the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and should all be covered within the scope of the claims of the present invention.

Claims

1. A method for preventing defects in an integrated etching process, characterized in that, It includes the following steps: An integrated etching process is adopted to form a notch; After the etching is completed, in the static elimination process, a CO / N2 mixed gas is introduced as the plasma gas, so that the plasma gas reacts to deposit a stable isolation protective layer on the surface of the notch to isolate the residual polymer generated in the notch during the etching process; After the static elimination is completed, the wafer is lifted and transferred to a wafer cassette; The wafer in the wafer cassette is transferred to a wet cleaning process to clean off the stable isolation protective layer and the residual polymer; In the static elimination process, the radio frequency power supply is set to 250W - 450W, and the flow ratio of N2 gas to CO gas in the CO / N2 mixed gas is 2:1 - 5:1, and the CO gas flow is not less than 100 sccm; The static elimination process includes the following three stages: The first stage: Prepare the static elimination conditions. After the etching is completed, a CO / N2 mixed gas is introduced into the etching chamber, and after reaching the first pressure, it is maintained for a period of time; The second stage: Maintain the first pressure, start the radio frequency power supply, dissociate the CO / N2 mixed gas into plasma gas, and under the interaction of ions, the plasma gas quickly reacts on the notch and its surface to generate a stable isolation protective layer; The third stage: Apply a reverse voltage to the electrostatic chuck to release the clamping of the wafer.

2. The method for preventing defects in the integrated etching process according to claim 1, wherein In the first stage, the first pressure is 100mT - 400mT, and the maintenance time after reaching the first pressure is 4 - 20s. During the pressure maintenance process, the CO / N2 mixed gas is continuously introduced for purging and replacement.

3. The method for preventing defects in the integrated etching process according to claim 1, characterized in that, In the second stage, maintain the pressure of the first stage, the maintenance time of the second stage is 2 - 8s, and the continuous existence of the plasma gas is maintained.

4. The method for preventing defects in an integrated etching process according to claim 1, wherein The maintenance time of the third stage is 0.5 - 4s, and the continuous existence of the plasma gas is maintained.

5. A method for preparing a metal interconnect structure, characterized in that, It includes the following steps: Provide a target wafer with a first metal layer, and the first metal layer is the metal wiring on the target wafer; Fabricate a multi-layer film structure on the first metal layer; Use an integrated etching process to fabricate a notch on the multi-layer film structure to expose the first metal layer; After the etching is completed, in the static elimination process, a CO / N2 mixed gas is introduced as the plasma gas, so that the plasma gas reacts to deposit a stable isolation protective layer on the surface of the notch to isolate the residual polymer generated in the notch during the etching process; After the static elimination is completed, the wafer is lifted and transferred to a wafer cassette; The wafer in the wafer cassette is transferred to a wet cleaning process to clean off the stable isolation protective layer and the residual polymer; Deposit a metal layer in the notch; Use the CMP process to remove the excess metal layer and the multi-layer film structure to complete the fabrication of the metal interconnection structure; In the static elimination process, the radio frequency power supply is set to 250W - 450W, and the flow ratio of N2 gas to CO gas in the CO / N2 mixed gas is 2:1 - 5:1, and the CO gas flow is not less than 100 sccm; The static elimination process includes the following three stages: The first stage: Prepare the static elimination conditions. After the etching is completed, a CO / N2 mixed gas is introduced into the etching chamber, and after reaching the first pressure, it is maintained for a period of time; Second stage: Maintain the first pressure, start the radio frequency power supply, dissociate the CO / N2 combined gas into plasma gas, and under the interaction of ions, the plasma gas rapidly reacts on the notch surface to generate a stable isolation protection layer; Third stage: Apply a reverse voltage to the electrostatic chuck to release the clamping of the wafer.

6. The manufacturing method of the metal interconnect structure according to claim 5, characterized in that, The multi-layer film structure includes a first etch stop layer, a low-k dielectric layer, a second etch stop layer, and a hard mask layer sequentially formed on the first metal layer.

7. The manufacturing method of the metal interconnect structure according to claim 6, wherein, During integrated etching, an anti-reflection coating is coated on the hard mask layer.

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