Semiconductor device reliability test structure and test method

Abstract

The invention provides a semiconductor device reliability test structure and test method. The semiconductor device reliability test structure is characterized in that a first Mn metal layer is connected with a source end, a second Mn metal layer is connected with a grid electrode, and a fourth Mn metal layer is connected with a substrate; the first Mn + 1 metal layer, the second Mn + 1 metal layer, the third Mn + 1 metal layer and the fourth Mn + 1 metal layer are sequentially connected with the first Mn metal layer, the second Mn metal layer, the third Mn metal layer and the fourth Mn metal layer one by one; the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are sequentially arranged on the first Mn + 1 metal layer, the second Mn + 1 metal layer, the third Mn + 1 metal layer and the fourth Mn + 1 metal layer; a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer is located between the third Mn metal layer and the fourth Mn metal layer, and the second interlayer dielectric layer is located between the second Mn + 1 metal layer and the third Mn + 1 metal layer; and the metal fuse is located between the third Mn + 1 metal layer and the first interlayer dielectric layer.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor device reliability test structure and a test method. Background Art

[0002] In the process of manufacturing semiconductor devices, in order to monitor the manufacturing process and ensure the reliability of semiconductor devices, it is usually a common practice to form a reliability test structure (test key) in the semiconductor device for reliability testing of some device layers of the semiconductor device. At present, in the design of reliability test structures, the test structures are usually distributed in different test keys for different evaluation items in the front and back stages of the process flow. In view of the sample quantity requirements for dielectric reliability evaluation, a large number of front-end and back-end dielectric reliability test structures are usually placed repeatedly. For example, the reliability test of the gate oxide layer belongs to the front stage, and the reliability test of the interlayer dielectric layer belongs to the back stage.

[0003] In the prior art, the gate oxide layer reliability test structure and the interlayer dielectric layer reliability test structure are formed separately. Figure 1 The semiconductor device includes: a substrate 110, a gate oxide layer 120 and a gate electrode 130 on the surface of the substrate 110, and a source terminal 140 and a drain terminal in the substrate 110 located on both sides of the gate electrode 130. The test structure for testing the reliability of the gate oxide layer is used to test the reliability of the gate oxide layer 120. The test structure for testing the reliability of the gate oxide layer includes: a first Mn metal layer 211, a second Mn metal layer 212 and a third Mn metal layer 213, the first Mn metal layer 211 is connected to the source terminal 140 through a through-hole structure 240, the second Mn metal layer 212 is connected to the gate electrode 130, and the third Mn metal layer 213 is connected to the substrate 110. A first Mn+1 metal layer 221, a second Mn+1 metal layer 222 and a third Mn+1 metal layer 223 are sequentially connected to the first Mn metal layer 211, the second Mn metal layer 212 and the third Mn metal layer 213 through the through-hole structure 240. The first test key 231, the second test key 232 and the third test key 233 are sequentially arranged on the first Mn+1 metal layer 221, the second Mn+1 metal layer 222 and the third Mn+1 metal layer 223. A high voltage is applied to the second test key 232, and the first test key 231 and the third test key 233 are grounded, so that the reliability of the gate oxide layer 120 can be tested.

[0004] like Figure 2The test structure for testing the reliability of the interlayer dielectric layer includes: a fourth Mn metal layer 214 and a fifth Mn metal layer 215, a fourth Mn+1 metal layer 224 and a fifth Mn+1 metal layer 225 which are connected to the fourth Mn metal layer 214 and the fifth Mn+1 metal layer 215 in sequence through a through-hole structure 240. And a fourth test key 234 and a fifth test key 235 are arranged on the fourth Mn+1 metal layer 224 and the fifth Mn+1 metal layer 225. A high voltage is applied to the fourth test key 234, and the fifth test key 235 is grounded, so that the reliability of the interlayer dielectric layer 250 between the fourth Mn metal layer 214 and the fifth Mn metal layer 215 can be tested.

[0005] However, in the prior art, the gate oxide layer reliability test structure and the interlayer dielectric layer reliability test structure occupy different test keys respectively, so that the area of ​​the back-end interconnection line of the gate oxide layer reliability test structure is lost, while the area of ​​the front-end gate oxide structure of the interlayer dielectric layer reliability test structure is lost. If a large number of repeated structures are placed, a large number of test keys are occupied, and a lot of available area is wasted in the front and back stages. Therefore, the reliability test structure of the prior art occupies a large amount of layout area. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device reliability test structure and a test method, which can reduce the layout area occupied by the semiconductor reliability test structure.

[0007] In order to achieve the above object, the present invention provides a semiconductor device reliability test structure, comprising:

[0008] a first Mn metal layer, a second Mn metal layer, a third Mn metal layer and a fourth Mn metal layer, wherein the first Mn metal layer is connected to the source terminal, the second Mn metal layer is connected to the gate terminal, and the fourth Mn metal layer is connected to the substrate, wherein n is a positive integer;

[0009] a first Mn+1 metal layer, a second Mn+1 metal layer, a third Mn+1 metal layer and a fourth Mn+1 metal layer, wherein the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer are sequentially connected to the first Mn metal layer, the second Mn metal layer, the third Mn metal layer and the fourth Mn metal layer one by one;

[0010] A first test key, a second test key, a third test key and a fourth test key, wherein the first test key, the second test key, the third test key and the fourth test key are sequentially arranged on the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer;

[0011] a first interlayer dielectric layer and a second interlayer dielectric layer, wherein the first interlayer dielectric layer is located between the third Mn metal layer and the fourth Mn metal layer, and the second interlayer dielectric layer is located between the second Mn+1 metal layer and the third Mn+1 metal layer; and

[0012] The metal fuse is located between the third Mn+1 metal layer and the first interlayer dielectric layer.

[0013] Optionally, in the semiconductor device reliability test structure, the semiconductor device includes:

[0014] substrate;

[0015] A gate oxide layer and a gate electrode are sequentially disposed on the surface of the substrate;

[0016] The source and drain terminals are located in the substrate on both sides of the gate.

[0017] Optionally, in the semiconductor device reliability test structure, the first Mn metal layer is connected to the source terminal through a through-hole structure, the second Mn metal layer is connected to the gate through a through-hole structure, and the fourth Mn metal layer is connected to the substrate through a through-hole structure.

[0018] Optionally, in the semiconductor device reliability test structure, the first Mn+1 metal layer is connected to the first Mn metal layer through a through-hole structure, the second Mn+1 metal layer is connected to the second Mn metal layer through a through-hole structure, the third Mn+1 metal layer is connected to the third Mn metal layer through a through-hole structure, and the fourth Mn+1 metal layer is connected to the fourth Mn metal layer through a through-hole structure.

[0019] Optionally, in the semiconductor device reliability test structure, the metal fuse is located on the third Mn metal layer.

[0020] Optionally, in the semiconductor device reliability test structure, the first test key, the second test key, the third test key and the fourth test key all include metal pads.

[0021] Optionally, in the semiconductor device reliability test structure, the gate oxide layer includes oxide.

[0022] Optionally, in the semiconductor device reliability test structure, the first Mn metal layer, the second Mn metal layer, the third Mn metal layer, the fourth Mn metal layer, the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer all include copper metal.

[0023] Optionally, in the semiconductor device reliability test structure, both the first interlayer dielectric layer and the second interlayer dielectric layer include oxide.

[0024] The present invention also provides a semiconductor device reliability testing method, comprising:

[0025] The third test key is connected to a high voltage, and the fourth test key is connected to a low voltage to test the reliability of the first interlayer dielectric layer;

[0026] When the first interlayer dielectric layer is broken down, the metal fuse is blown, the second test key is connected to a high voltage, and the first test key and the fourth test key are connected to a low voltage to test the reliability of the gate oxide layer;

[0027] The third test key is connected to a high voltage, and the second test key is connected to a low voltage, so as to continue to test the reliability of the second interlayer dielectric layer.

[0028] In the semiconductor device reliability test structure and test method provided by the present invention, the structure includes: a first Mn metal layer, a second Mn metal layer, a third Mn metal layer and a fourth Mn metal layer, the first Mn metal layer is connected to the source end, the second Mn metal layer is connected to the gate, and the fourth Mn metal layer is connected to the substrate, wherein n is a positive integer; a first Mn+1 metal layer, a second Mn+1 metal layer, a third Mn+1 metal layer and a fourth Mn+1 metal layer, the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer are connected to the first Mn metal layer, the second Mn metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer in sequence. The Mn metal layer and the fourth Mn metal layer are connected one by one; the first test key, the second test key, the third test key and the fourth test key are arranged on the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer in sequence; the first interlayer dielectric layer and the second interlayer dielectric layer, the first interlayer dielectric layer is located between the third Mn metal layer and the fourth Mn metal layer, and the second interlayer dielectric layer is located between the second Mn+1 metal layer and the third Mn+1 metal layer; the metal fuse is located between the third Mn+1 metal layer and the first interlayer dielectric layer. The method includes: the third test key is connected to a high voltage, and the fourth test key is connected to a low voltage to test the reliability of the first interlayer dielectric layer; when the first interlayer dielectric layer is broken down, the metal fuse is blown, the second test key is connected to a high voltage, and the first test key and the fourth test key are connected to a low voltage to test the reliability of the gate oxide layer; the third test key is connected to a high voltage, and the second test key is connected to a low voltage to continue to test the reliability of the second interlayer dielectric layer. The present invention integrates the gate oxide layer reliability test and the interlayer dielectric layer reliability test into one test structure, which can test both the gate oxide layer reliability and the interlayer dielectric layer reliability. At the same time, the number of test keys is reduced, and the layout area is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of a gate oxide layer reliability test structure of the prior art;

[0030] Figure 2 is a schematic diagram of a prior art interlayer dielectric layer reliability test structure;

[0031] Figure 3 is a schematic diagram of a semiconductor device reliability test structure according to an embodiment of the present invention;

[0032] Figure 4 is a flow chart of a semiconductor device reliability testing method according to an embodiment of the present invention;

[0033] In the figure: 110-substrate, 120-gate oxide layer, 130-gate, 140-source terminal, 211-first Mn metal layer, 212-second Mn metal layer, 213-third Mn metal layer, 214-fourth Mn metal layer, 215-fifth Mn metal layer, 221-first Mn+1 metal layer, 222-second Mn+1 metal layer, 223-third Mn+1 metal layer, 224-fourth Mn+1 metal layer, 225-fifth Mn+1 metal layer, 231-first test key, 232-second test key, 233-third test key, 234-fourth test key, 235-fifth Test key, 240-through hole structure, 250-interlayer dielectric layer, 311-first Mn metal layer, 312-second Mn metal layer, 313-third Mn metal layer, 314-fourth Mn metal layer, 321-first Mn+1 metal layer, 322-second Mn+1 metal layer, 323-third Mn+1 metal layer, 324-fourth Mn+1 metal layer, 331-first test key, 332-second test key, 333-third test key, 334-fourth test key, 340-through hole structure, 351-first interlayer dielectric layer, 352-second interlayer dielectric layer, 360-metal fuse. DETAILED DESCRIPTION

[0034] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0036] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0037] Please refer to Figure 3 The present invention provides a semiconductor device reliability test structure for testing the reliability of a semiconductor device. Figure 3 Only a partial structure of the semiconductor device is shown, including: a substrate 110 ; a gate oxide layer 120 and a gate 130 sequentially located on the surface of the substrate 110 ; and a source terminal 140 and a drain terminal located in the substrate 110 on both sides of the gate 130 .

[0038] The semiconductor device reliability test structure provided by the present invention comprises: a first Mn metal layer 311, a second Mn metal layer 312, a third Mn metal layer 313 and a fourth Mn metal layer 314, wherein the first Mn metal layer 311 is connected to a source terminal 140, the second Mn metal layer 312 is connected to a gate 130, and the fourth Mn metal layer 314 is connected to a substrate 110, wherein n is a positive integer; a first Mn+1 metal layer 321, a second Mn+1 metal layer 322, a third Mn+1 metal layer 323 and a fourth Mn+1 metal layer 324, wherein the first Mn+1 metal layer 321, the second Mn+1 metal layer 322, the third Mn+1 metal layer 323 and the fourth Mn+1 metal layer 324 are connected to the first Mn metal layer 311, the second Mn metal layer 312, the third Mn metal layer 313 and the fourth Mn metal layer 314 in sequence. The metal layers 314 are connected one by one; the first test key 331, the second test key 332, the third test key 333 and the fourth test key 334, the first test key 331, the second test key 332, the third test key 333 and the fourth test key 334 are arranged on the first Mn+1 metal layer 321, the second Mn+1 metal layer 322, the third Mn+1 metal layer 323 and the fourth Mn+1 metal layer 324 in sequence; the first interlayer dielectric layer 351 and the second interlayer dielectric layer 352, the first interlayer dielectric layer 351 is located between the third Mn metal layer 313 and the fourth Mn metal layer 314, the second interlayer dielectric layer 352 is located between the second Mn+1 metal layer 322 and the third Mn+1 metal layer 323; and the metal fuse 360 ​​is located between the third Mn+1 metal layer 323 and the first interlayer dielectric layer 351.

[0039] More specifically, the first Mn metal layer 311 is connected to the source terminal 140 through the through-hole structure 340, the second Mn metal layer 312 is connected to the gate 130 through the through-hole structure 340, and the fourth Mn metal layer 314 is connected to the substrate 110 through the through-hole structure 340. The first Mn+1 metal layer 321 is connected to the first Mn metal layer 311 through the through-hole structure 340, the second Mn+1 metal layer 322 is connected to the second Mn metal layer 312 through the through-hole structure 340, the third Mn+1 metal layer 323 is connected to the third Mn metal layer 313 through the through-hole structure 340, and the fourth Mn+1 metal layer 324 is connected to the fourth Mn metal layer 314 through the through-hole structure 340. The metal fuse 360 ​​is located on the third Mn metal layer 313.

[0040] In the embodiment of the present invention, the first test key 331, the second test key 332, the third test key 333 and the fourth test key 334 all include metal pads. The gate oxide layer 120 includes oxide. The first Mn metal layer 311, the second Mn metal layer 312, the third Mn metal layer 313, the fourth Mn metal layer 314, the first Mn+1 metal layer 321, the second Mn+1 metal layer 322, the third Mn+1 metal layer 323 and the fourth Mn+1 metal layer 324 all include copper metal, and in other embodiments of the present invention, they may also be other metal materials. The first interlayer dielectric layer 351 and the second interlayer dielectric layer 352 all include oxide, and in other embodiments of the present invention, they may also be other materials.

[0041] Accordingly, please refer to Figure 4 The present invention also provides a semiconductor device reliability testing method using the semiconductor device reliability testing structure, comprising:

[0042] S11: the third test key is connected to a high voltage, and the fourth test key is connected to a low voltage, so as to test the reliability of the first interlayer dielectric layer;

[0043] S12: When the first interlayer dielectric layer is broken down, the metal fuse is blown, the second test key is connected to a high voltage, and the first test key and the fourth test key are connected to a low voltage to test the reliability of the gate oxide layer;

[0044] S13: The third test key is connected to a high voltage, and the second test key is connected to a low voltage, so as to continue to test the reliability of the second interlayer dielectric layer.

[0045] The embodiment of the present invention integrates the gate oxide layer reliability test and the interlayer dielectric layer reliability test on one test structure by optimizing the metal interconnection line, and realizes repeated placement. The Bulk end of the front-stage gate oxide layer reliability test and the low potential (GND) of the back-stage interlayer dielectric layer reliability test share a test key. The gate pad of the gate oxide layer reliability test and the low potential pad of the back-stage interlayer dielectric layer reliability test share the second test key. The high potential pad of the back-stage interlayer dielectric layer reliability test is led out separately, which is the third test key. Take the conventional 12 pad test key as an example: the prior art can only place 2 groups of gate oxide structures and 3 groups of metal interlayer dielectric test structures; the embodiment of the present invention can place 3 groups of gate oxide structures and 3 groups of metal interlayer dielectric test structures, and the area utilization rate of the entire TSK layout can be increased by 80%.

[0046] In summary, in the semiconductor device reliability test structure and test method provided by the embodiment of the present invention, the structure includes: a first Mn metal layer, a second Mn metal layer, a third Mn metal layer and a fourth Mn metal layer, the first Mn metal layer is connected to the source terminal, the second Mn metal layer is connected to the gate terminal, and the fourth Mn metal layer is connected to the substrate, wherein n is a positive integer; a first Mn+1 metal layer, a second Mn+1 metal layer, a third Mn+1 metal layer and a fourth Mn+1 metal layer, the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer are connected to the first Mn metal layer, the second Mn metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer in sequence; , the third Mn metal layer and the fourth Mn metal layer are connected one by one; the first test key, the second test key, the third test key and the fourth test key, the first test key, the second test key, the third test key and the fourth test key are arranged on the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer in sequence; the first interlayer dielectric layer and the second interlayer dielectric layer, the first interlayer dielectric layer is located between the third Mn metal layer and the fourth Mn metal layer, and the second interlayer dielectric layer is located between the second Mn+1 metal layer and the third Mn+1 metal layer; the metal fuse is located between the third Mn+1 metal layer and the first interlayer dielectric layer. The method includes: the third test key is connected to a high voltage, the fourth test key is connected to a low voltage, so as to test the reliability of the first interlayer dielectric layer; when the first interlayer dielectric layer is broken down, the metal fuse is blown, the second test key is connected to a high voltage, and the first test key and the fourth test key are connected to a low voltage, so as to test the reliability of the gate oxide layer; the third test key is connected to a high voltage, and the second test key is connected to a low voltage, so as to continue to test the reliability of the second interlayer dielectric layer. The present invention integrates the gate oxide layer reliability test and the interlayer dielectric layer reliability test into one test structure. It can test the reliability of both the gate oxide layer and the interlayer dielectric layer. At the same time, the number of test keys is reduced, and the layout area is reduced.

[0047] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor device reliability test structure, characterized in that: include: a first Mn metal layer, a second Mn metal layer, a third Mn metal layer and a fourth Mn metal layer, wherein the first Mn metal layer is connected to the source terminal, the second Mn metal layer is connected to the gate terminal, and the fourth Mn metal layer is connected to the substrate, wherein n is a positive integer; a first Mn+1 metal layer, a second Mn+1 metal layer, a third Mn+1 metal layer and a fourth Mn+1 metal layer, wherein the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer are sequentially connected to the first Mn metal layer, the second Mn metal layer, the third Mn metal layer and the fourth Mn metal layer one by one; A first test key, a second test key, a third test key and a fourth test key, wherein the first test key, the second test key, the third test key and the fourth test key are sequentially arranged on the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer; a first interlayer dielectric layer and a second interlayer dielectric layer, wherein the first interlayer dielectric layer is located between the third Mn metal layer and the fourth Mn metal layer, and the second interlayer dielectric layer is located between the second Mn+1 metal layer and the third Mn+1 metal layer; and The metal fuse is located between the third Mn+1 metal layer and the first interlayer dielectric layer.

2. The semiconductor device reliability test structure according to claim 1, characterized in that: The semiconductor device comprises: substrate; A gate oxide layer and a gate electrode are sequentially disposed on the surface of the substrate; The source and drain terminals are located in the substrate on both sides of the gate.

3. The semiconductor device reliability test structure according to claim 1, characterized in that: The first Mn metal layer is connected to the source terminal through a through-hole structure, the second Mn metal layer is connected to the gate through a through-hole structure, and the fourth Mn metal layer is connected to the substrate through a through-hole structure.

4. The semiconductor device reliability test structure according to claim 1, characterized in that: The first Mn+1 metal layer is connected to the first Mn metal layer through a through-hole structure, the second Mn+1 metal layer is connected to the second Mn metal layer through a through-hole structure, the third Mn+1 metal layer is connected to the third Mn metal layer through a through-hole structure, and the fourth Mn+1 metal layer is connected to the fourth Mn metal layer through a through-hole structure.

5. The semiconductor device reliability test structure according to claim 1, characterized in that: The metal fuse is located on the third Mn metal layer.

6. The semiconductor device reliability test structure according to claim 1, characterized in that: The first test key, the second test key, the third test key and the fourth test key each include a metal pad.

7. The semiconductor device reliability test structure according to claim 2, characterized in that: The gate oxide layer includes oxide.

8. The semiconductor device reliability test structure according to claim 1, characterized in that: The first Mn metal layer, the second Mn metal layer, the third Mn metal layer, the fourth Mn metal layer, the first Mn+1 metal layer, the second Mn+1 metal layer, the third Mn+1 metal layer and the fourth Mn+1 metal layer all include copper metal.

9. The semiconductor device reliability test structure according to claim 1, characterized in that: The first interlayer dielectric layer and the second interlayer dielectric layer both include oxide.

10. A testing method using the semiconductor device reliability testing structure according to any one of claims 1 to 9, characterized in that: include: The third test key is connected to a high voltage, and the fourth test key is connected to a low voltage to test the reliability of the first interlayer dielectric layer; When the first interlayer dielectric layer is broken down, the metal fuse is blown, the second test key is connected to a high voltage, and the first test key and the fourth test key are connected to a low voltage to test the reliability of the gate oxide layer; The third test key is connected to a high voltage, and the second test key is connected to a low voltage, so as to continue to test the reliability of the second interlayer dielectric layer.

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