Detection adjusting circuit, switching power supply, chip and electronic equipment

Abstract

The invention provides a detection adjusting circuit, a switching power supply, a chip and electronic equipment. The detection adjusting circuit comprises a detection circuit, an adjusting circuit and a COT control circuit. A square wave signal and a first control signal are obtained through a detection circuit, a detection signal is obtained according to the square wave signal and the first control signal, and the detection signal is transmitted to an adjusting circuit. Therefore, the adjusting circuit can obtain the clock signal in the next switching period, obtain the adjusting signal according to the clock signal and the detection signal, and transmit the adjusting signal to the COT control circuit. Furthermore, the COT control circuit can change the switching period of the switching power supply according to the adjusting signal and the second control signal so as to dynamically adjust the switching frequency of the switching power supply. Therefore, the output voltage of the switching power supply reaches the preset stable voltage value, the switching power supply is ensured to have the capability of adjusting the output voltage, and the performance of the switching power supply is improved.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a detection and regulation circuit, a switching power supply, a chip and an electronic device. Background Art

[0002] The switching power supply converts the input voltage of the switching power supply into an output voltage of a preset voltage value by periodically turning on or off the power tube in the switching power supply through a pulse width modulation (PWM) signal with a certain duty cycle. When the pulse width modulation signal is modulated by a variable frequency modulation method with constant on-time or constant off-time modulation, when the voltage conversion ratio between the input voltage and the output voltage causes the pulse width modulation signal to approach the minimum on-time or minimum off-time, the output voltage value cannot reach the preset voltage value, resulting in reduced performance of the switching power supply. Summary of the invention

[0003] The present application provides a detection and regulation circuit, a switching power supply, a chip and an electronic device, which can ensure that the output voltage reaches a preset voltage value and improve the performance of the switching power supply.

[0004] In a first aspect, the present application provides a detection and regulation circuit, which is applied to a switching power supply, and the switching power supply includes: a pulse width modulation comparator; the detection and regulation circuit includes: a detection circuit, a regulation circuit and a COT control circuit;

[0005] The first input terminal of the detection circuit is electrically connected to the output terminal of the pulse width modulation comparator, the second input terminal of the detection circuit is electrically connected to the output terminal of the COT control circuit, the first output terminal of the detection circuit is electrically connected to the first input terminal of the adjustment circuit, the second output terminal of the detection circuit is electrically connected to the second input terminal of the adjustment circuit, and the output terminal of the adjustment circuit is electrically connected to the input terminal of the COT control circuit;

[0006] The detection circuit is used to obtain a square wave signal from the pulse width modulation comparator, and to obtain a first control signal from the COT control circuit, and to obtain a detection signal according to the square wave signal and the first control signal, and to transmit the detection signal to the regulation circuit, wherein the square wave signal is used to indicate whether the switching power supply is in a constant on-time control mode or a constant off-time control mode, the first control signal is used to indicate the duration of the on-time or off-time of the switching power supply in a previous switching cycle, and the detection signal is used to indicate whether the switching power supply enters a minimum off-time or a minimum on-time in the previous switching cycle;

[0007] The regulating circuit is used to obtain a clock signal from the detection circuit in a subsequent switching cycle, obtain a regulating signal according to the clock signal and the detection signal, and transmit the regulating signal to the COT control circuit, wherein the regulating signal is used to determine whether it is necessary to extend the duration of the on-time or the off-time in the subsequent switching cycle;

[0008] The COT control circuit is used to obtain the second control signal according to the adjustment signal to dynamically adjust the switching frequency of the switching power supply, and the second control signal is used to characterize the duration of the on-time or off-time of the switching power supply in the next switching cycle.

[0009] Through the detection and adjustment circuit provided in the first aspect, a square wave signal representing that the switching power supply is in a constant on-time control mode or a constant off-time control mode is obtained from the pulse width modulation comparator through the detection circuit, and a first control signal representing the duration of the on-time or off-time of the switching power supply in the previous switching cycle is obtained from the COT control circuit, and a detection signal representing whether the switching power supply enters the minimum off-time or minimum on-time in the previous switching cycle is obtained according to the square wave signal and the first control signal, and the detection signal is transmitted to the adjustment circuit so that the adjustment circuit can obtain the detection signal. In this way, the adjustment circuit can obtain a clock signal from the detection circuit in the next switching cycle, and obtain an adjustment signal according to the clock signal and the detection signal, and transmit an adjustment signal used to determine whether the duration of the on-time or off-time in the next switching cycle needs to be extended to the COT control circuit, so that the COT control circuit can obtain the adjustment signal. Furthermore, the COT control circuit can obtain a second control signal for characterizing the duration of the on-time or off-time of the switching power supply in the next switching cycle according to the adjustment signal, so that the on-time or off-time of the pulse width modulation signal generated based on the second control signal and the square wave signal in the next switching cycle changes, so that the switching cycle of the switching power supply can be changed to dynamically adjust the switching frequency of the switching power supply. Thus, the output voltage of the switching power supply reaches a preset stable voltage value, ensuring that the switching power supply has the ability to adjust the output voltage, and improving the performance of the switching power supply.

[0010] In one possible design, the first control signal includes: a first sub-control signal and a second sub-control signal, the detection signal includes: a first detection signal and a second detection signal, the clock signal includes: a first clock signal and a second clock signal, the adjustment signal includes: a first adjustment signal and a second adjustment signal, and the second control signal includes: a third sub-control signal and a fourth sub-control signal;

[0011] The detection circuit is specifically used to obtain the first detection signal according to the square wave signal and the first sub-control signal when the square wave signal indicates that the switching power supply is in the constant on-time control mode, and transmit the first detection signal to the regulation circuit, the first sub-control signal is used to indicate the duration of the on-time of the switching power supply in the previous switching cycle, and the first detection signal is used to indicate whether the switching power supply enters the minimum off-time in the previous switching cycle;

[0012] The regulating circuit is specifically used to obtain the first regulating signal according to the first clock signal and the first detection signal in the next switching cycle, and transmit the first regulating signal to the COT control circuit, wherein the first regulating signal is used to determine whether it is necessary to extend the duration of the conduction time in the next switching cycle;

[0013] The COT control circuit is specifically used to obtain the third sub-control signal according to the first adjustment signal, and the third sub-control signal is used to represent the duration of the conduction time of the switching power supply in the next switching cycle;

[0014] or,

[0015] The detection circuit is specifically used to obtain the second detection signal according to the square wave signal and the second sub-control signal when the square wave signal indicates that the switching power supply is in the constant off-time control mode, and transmit the second detection signal to the regulation circuit, the second sub-control signal is used to indicate the duration of the off-time of the switching power supply in the previous switching cycle, and the second detection signal is used to indicate whether the switching power supply enters the minimum on-time in the previous switching cycle;

[0016] The regulating circuit is specifically used to obtain the second regulating signal according to the second clock signal and the second detection signal in a subsequent switching cycle, and transmit the second regulating signal to the COT control circuit, wherein the second regulating signal is used to determine whether it is necessary to extend the duration of the off time in the subsequent switching cycle;

[0017] The COT control circuit is specifically used to obtain the fourth sub-control signal according to the second adjustment signal, and the fourth sub-control signal is used to characterize the duration of the conduction time of the switching power supply in the next switching cycle.

[0018] In one possible design, the detection circuit includes: a detection control component, a clock signal output component and a detection signal output component;

[0019] The first input end of the detection control component is electrically connected to the output end of the pulse width modulation comparator, the second input end of the detection control component is electrically connected to the output end of the COT control circuit, the input end of the clock signal output component is electrically connected to the first output end or the second output end of the detection control component, the output end of the clock signal output component is electrically connected to the second input end of the regulating circuit and the first input end of the detection signal output component respectively, the second input end of the detection signal output component is used to access the power supply voltage, and the output end of the detection signal output component is electrically connected to the first input end of the regulating circuit;

[0020] The detection control component is used to control the first output end of the detection control component to be electrically connected to the input end of the clock signal output component when the square wave signal indicates that the switching power supply is in a constant on-time control mode, and to obtain a first pulse width modulation signal according to the square wave signal and the first sub-control signal, and transmit the first pulse width modulation signal to the clock signal output component;

[0021] The clock signal output component is used to transmit the first clock signal to the detection signal output component according to the first pulse width modulation signal;

[0022] The detection signal output component is used to detect whether the switching power supply enters the minimum off time in the previous switching cycle according to the first clock signal, so as to obtain the first detection signal;

[0023] or,

[0024] The detection control component is used to control the second output end of the detection control component to be electrically connected to the input end of the clock signal output component when the square wave signal indicates that the switching power supply is in a constant off-time control mode, and to obtain a second pulse width modulation signal according to the square wave signal and the second sub-control signal, and transmit the second pulse width modulation signal to the clock signal output component;

[0025] The clock signal output component is used to transmit the second clock signal to the detection signal output component according to the second pulse width modulation signal;

[0026] The detection signal output component is used to detect whether the switching power supply enters the minimum on-time in the previous switching cycle according to the second clock signal, so as to obtain the second detection signal.

[0027] In one possible design, the detection control component includes: a first trigger;

[0028] The set end of the first trigger is electrically connected to the output end of the pulse width modulation comparator, the reset end of the first trigger is electrically connected to the output end of the COT control circuit, and the forward output end or the reverse output end of the first trigger is electrically connected to the input end of the clock signal output component.

[0029] In a possible design, the clock signal output component includes: a first switch tube, a second switch tube and a first inverter;

[0030] The first end of the second switch tube is electrically connected to the first output end or the second output end of the detection control component, the second end of the second switch tube is electrically connected to the first end of the first switch tube and the input end of the first inverter respectively, the second end of the first switch tube and the output end of the first inverter are both electrically connected to the first input end of the detection signal output component, and the control end of the first switch tube and the control end of the second switch tube are both used to access the switch signal, and the switch signal is used to control the conduction or shutdown of the switch tube.

[0031] In a possible design, the detection signal output component includes: a second inverter, a delay device, and a second trigger;

[0032] The input end of the second inverter and the input end of the delay device are both electrically connected to the output end of the clock signal output component, the output end of the second inverter is electrically connected to the clock input end of the second trigger, the output end of the delay device is electrically connected to the set input end of the second trigger, the data input end of the second trigger is used to access the power supply voltage, and the output end of the second trigger is electrically connected to the first input end of the regulation circuit.

[0033] In one possible design, the regulating circuit includes: a counter;

[0034] The clock input terminal of the counter is electrically connected to the second output terminal of the detection circuit, the count input terminal of the counter is electrically connected to the first output terminal of the detection circuit, and the output terminal of the counter is electrically connected to the input terminal of the COT control circuit;

[0035] The counter is used to obtain the first clock signal from the detection circuit in the next switching cycle, and determine whether to count up the first value of the counter according to the first detection signal at the rising edge of the first clock signal to obtain the first adjustment signal;

[0036] or,

[0037] The counter is used to obtain the second clock signal from the detection circuit during the next switching cycle, and determine whether to count up the first value of the counter based on the second detection signal at the rising edge of the second clock signal to obtain the second adjustment signal.

[0038] In one possible design, the regulating circuit further includes: a frequency divider;

[0039] The input end of the frequency divider is electrically connected to the second output end of the detection circuit, and the output end of the frequency divider is electrically connected to the clock input end of the counter;

[0040] The frequency divider is used to divide the first clock signal to obtain a first frequency-divided clock signal, and transmit the first frequency-divided clock signal to the counter so that the counter obtains the first adjustment signal;

[0041] or,

[0042] The frequency divider is used to divide the second clock signal to obtain a second divided clock signal, and transmit the second divided clock signal to the counter so that the counter obtains the second adjustment signal.

[0043] In one possible design, the COT control circuit includes: a current output component, a capacitor, and a timing comparator;

[0044] The control end of the current output component is electrically connected to the output end of the regulating circuit, the output end of the current output component is electrically connected to the first plate of the capacitor, the positive phase input end of the timing comparator is electrically connected between the output end of the current output component and the first plate of the capacitor, the negative phase input end of the timing comparator is used to access a reference voltage, the reference voltage is related to the square wave signal, and the output end of the timing comparator is electrically connected to the first input end of the detection circuit;

[0045] The current output component is used to output a first charging current corresponding to the first adjustment signal, and use the first charging current to charge the capacitor;

[0046] The timing comparator is used to compare the voltage on the capacitor with the reference voltage to obtain the third sub-control signal;

[0047] or,

[0048] The current output component is used to output a second charging current corresponding to the second adjustment signal, and use the second charging current to charge the capacitor;

[0049] The timing comparator is used to compare the voltage on the capacitor with the reference voltage to obtain the fourth sub-control signal.

[0050] In one possible design, the current output component includes: a current source, a first N-type crystal, a second N-type transistor, a first P-type transistor, a second P-type transistor, a plurality of N-type transistor groups, and a plurality of third inverters;

[0051] The output end of the current source is electrically connected to the drain end of the first N-type transistor, the gate end of the first N-type transistor is electrically connected to the gate end of the second N-type transistor and the first gate end of each N-type transistor group, the drain end of the first N-type transistor is electrically connected to the drain end of each N-type transistor group, the drain end of the first P-type transistor, the gate end of the first P-type transistor and the gate end of the second P-type transistor, the drain end of the second P-type transistor is electrically connected to the first plate of the capacitor, the source end of the first P-type transistor and the source end of the second P-type transistor are both used to access the power supply voltage, the second gate end of each N-type transistor group is electrically connected to the output end of each third inverter, the input end of each third inverter is electrically connected to the output end of the regulation circuit, and the source end of the first N-type transistor, the source end of the second N-type transistor and the source end of each N-type transistor group are all grounded.

[0052] In one possible design, the number of the first N-type transistors is the sum of the number of the second N-type transistors and the number of the multiple N-type transistor groups, the number of the first P-type transistors is equal to the number of the second P-type transistors, the number of the second N-type transistors is related to the longest duration of the on-time or off-time of the switching power supply, and the number of the multiple N-type transistor groups is related to the step size of the adjustment of the switching frequency.

[0053] In a second aspect, the present application provides a switching power supply, the switching power supply comprising: a high-side power transistor, a low-side power transistor, an inductor, an output capacitor, a first resistor, a second resistor, a pulse width modulation comparator, a controller, a loop-controlled current output circuit, and a detection and regulation circuit in the first aspect and each possible design of the first aspect;

[0054] The input end of the loop-controlled current output circuit is electrically connected to the second end of the inductor and the first plate of the output capacitor respectively, the second end of the inductor is also used to output the output voltage of the switching power supply, the output end of the loop-controlled current output circuit is electrically connected to the first end of the first resistor, the second end of the first resistor is electrically connected to the negative phase input end of the pulse width modulation comparator, the first end of the second resistor is used to detect the current of the inductor, the second end of the second resistor is electrically connected to the positive phase input end of the pulse width modulation comparator, and the output end of the pulse width modulation comparator is respectively connected to the first input end of the detection circuit and the first input end of the controller. The input end of the COT control circuit is electrically connected to the second input end of the controller, the first output end of the controller is electrically connected to the control end of the high-side power transistor, the second output end of the controller is electrically connected to the control end of the low-side power transistor, the first end of the high-side power transistor is used to access the input voltage of the switching power supply, the second end of the high-side power transistor is electrically connected to the first end of the low-side power transistor, the first end of the inductor is electrically connected between the second end of the high-side power transistor and the first end of the low-side power transistor, and the second end of the low-side power transistor and the second plate of the output capacitor are both grounded.

[0055] The beneficial effects of the switching power supply provided in the above-mentioned second aspect and each possible design of the above-mentioned second aspect can be referred to the beneficial effects brought about by the above-mentioned first aspect and each possible implementation method of the first aspect, and will not be repeated here.

[0056] In a third aspect, the present application provides a chip, comprising: the detection and regulation circuit in the above-mentioned first aspect and each possible design of the above-mentioned first aspect, and / or the switching power supply in the above-mentioned second aspect.

[0057] In a fourth aspect, the present application provides an electronic device, comprising: the chip in the third aspect above.

[0058] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 A schematic diagram of the structure of a detection and adjustment circuit provided in one embodiment of the present application;

[0061] Figure 2 A schematic diagram of the structure of a COT control circuit in a detection and regulation circuit provided in an embodiment of the present application;

[0062] Figure 3 A detection timing diagram of a detection and adjustment circuit provided in one embodiment of the present application;

[0063] Figure 4 A detection timing diagram of another detection and adjustment circuit provided in an embodiment of the present application;

[0064] Figure 5 A schematic diagram of the structure of a switching power supply provided in one embodiment of the present application. DETAILED DESCRIPTION

[0065] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0066] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0067] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0068] Generally, the modulation modes of pulse width modulation signals include fixed frequency modulation and variable frequency modulation. Compared with fixed frequency modulation, variable frequency modulation has a faster response speed. Among them, variable frequency modulation includes constant on-time or constant off-time modulation.

[0069] When the input voltage and output voltage of the switching power supply are stable, the duty cycle of the pulse width modulation signal is fixed.

[0070] For a switching power supply in constant on time (COT) control mode, i.e., valley current mode, the constant on time control will only work when the switching frequency of the switching power supply changes due to changes in input voltage or output voltage. Therefore, in order to stabilize the switching frequency of the switching power supply, the switching power supply introduces an adaptive controller COT timer1 to achieve adaptive on time control when the input voltage and output voltage change.

[0071] Taking a buck converter (Buck) as an example, the voltage conversion ratio between the input voltage and the output voltage of the Buck converter can be expressed by formula (1):

[0072]

[0073] Wherein, VOUT1 is the output voltage, VIN1 is the input voltage, Ton' is the on-time, Toff' is the off-time, and Tsw' is the switching period.

[0074] When the output voltage VOUT1 remains unchanged and the input voltage VIN1 gradually decreases. Due to the use of adaptive on-time control, the on-time Ton' will gradually increase, while the switching period Tsw' remains unchanged. Therefore, the loop in the Buck converter will adjust the off-time Toff' to gradually decrease. Since the off-time Toff' cannot be reduced indefinitely. Therefore, the off-time Toff' of the Buck converter will be fixed to a minimum off-time Toff_min1. When the input voltage VIN1 continues to decrease, since the loop can no longer adjust the off-time Toff' lower than the minimum off-time Toff_min1. Therefore, the output voltage VOUT1 will drop, so that the output voltage VOUT1 cannot reach the preset voltage value, resulting in reduced performance of the Buck converter.

[0075] For a switching power supply in a constant off time (COT) control mode, i.e., a peak current mode, in order to stabilize the switching frequency of the switching power supply, when the input voltage and the output voltage change, the switching power supply introduces an adaptive controller COT timer1 to achieve adaptive off time control. Similarly, taking a buck converter as an example, when there is a large difference between the input voltage VIN1 and the output voltage VOUT1, due to the use of adaptive on time control, the off time Toff' will gradually increase, while the switching period Tsw' remains unchanged. Therefore, the loop will adjust the on time Ton' to gradually decrease. Since the on time Ton' cannot be infinitely reduced. Therefore, the on time Ton' of the Buck converter will be fixed to a minimum on time Ton_min1. When the output voltage VOUT1 remains unchanged and the input voltage VIN1 gradually increases, the loop will adjust the on time Ton' to gradually decrease to ensure the stability of the output voltage VOUT1. When the on time Ton' is lower than the minimum on time Ton_min1, the loop cannot continue to adjust downward. Therefore, the output voltage VOUT1 will increase due to the excessive energy transferred, so that the output voltage VOUT1 cannot reach the preset voltage value, resulting in the performance of the Buck converter being reduced.

[0076] Based on the above description, it can be seen that when the voltage conversion ratio between the input voltage and the output voltage causes the pulse width modulation signal to approach the minimum on-time or the minimum off-time, that is, when the switching power supply enters the minimum on-time or the minimum off-time, the voltage value of the output voltage cannot reach the preset voltage value, resulting in a decrease in the performance of the switching power supply.

[0077] In order to solve the above problems, the present application provides a detection and regulation circuit, which dynamically adjusts the switching frequency of the switching power supply by detecting whether the switching power supply enters the minimum on-time or off-time and adjusting the on-time or off-time. Thus, it can ensure that the output voltage of the switching power supply reaches the preset voltage value and improve the performance of the switching power supply.

[0078] Reference Figure 1 , Figure 1 This is a schematic diagram of a detection and adjustment circuit provided in one embodiment of the present application. Figure 1 As shown, the detection and regulation circuit 100 may include: a detection circuit 110 , a regulation circuit 120 and a COT control circuit 130 .

[0079] The first input terminal of the detection circuit 110 is electrically connected to the output terminal of the pulse width modulation comparator PWM Comp, the second input terminal of the detection circuit 110 is electrically connected to the output terminal of the COT control circuit 130, the first output terminal of the detection circuit 110 is electrically connected to the first input terminal of the adjustment circuit 120, the second output terminal of the detection circuit 110 is electrically connected to the second input terminal of the adjustment circuit 120, and the output terminal of the adjustment circuit 120 is electrically connected to the input terminal of the COT control circuit 130.

[0080] The detection circuit 110 , the adjustment circuit 120 and the COT control circuit 130 may be provided separately or integrated, and this is not specifically limited in the embodiment of the present application.

[0081] The detection circuit 110 can obtain the square wave signal CMPO from the pulse width modulation comparator PWM Comp, and obtain the first control signal TCOT1 from the COT control circuit 130. In addition, the detection circuit 110 can detect whether the switching power supply 1000 enters the minimum off time Toff_min2 or the minimum on time Ton_min2 in the previous switching cycle according to the square wave signal CMPO and the first control signal TCOT1, obtain the detection signal DROP, and transmit the detection signal DROP to the regulation circuit 120, so that the regulation circuit 120 can obtain the detection signal DROP.

[0082] The square wave signal CMPO is used to indicate that the switching power supply 1000 is in a constant on-time control mode or a constant off-time control mode, and the first control signal TCOT1 is used to indicate the on-time or off-time duration of the switching power supply 1000 in the previous switching cycle.

[0083] For example, when the square wave signal CMPO is at a low level, the current of the inductor L1 in the switching power supply 1000 starts to decrease from the peak current. When the square wave signal CMPO turns from a low level to a high level, the current of the inductor L1 decreases to a valley current. In other words, the switching power supply 1000 is in a constant on-time control mode. In this way, the detection and regulation circuit 100 can detect the valley current of the switching power supply 1000.

[0084] For example, when the square wave signal CMPO is at a low level, the current of the inductor L1 starts to increase from the valley current. When the square wave signal CMPO turns from a low level to a high level, the current of the inductor L1 increases to the peak current. In other words, the switching power supply 1000 is in a constant off-time control mode. In this way, the detection and regulation circuit 100 can detect the peak current of the switching power supply 1000.

[0085] For example, when the detection signal DROP is at a high level, the detection signal DROP can indicate that the switching power supply 1000 has entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle. When the detection signal DROP is at a low level, the detection signal DROP can indicate that the switching power supply 1000 has not entered the minimum off-time Toff_min2 or the minimum on-time Ton_min2 in the previous switching cycle.

[0086] In this way, the regulating circuit 120 can obtain the clock signal from the detection circuit 110 in the next switching cycle. In addition, the regulating circuit 120 can obtain the regulating signal Q according to the clock signal and the detection signal DROP. <n:1>, and transmits the adjustment signal Q to the COT control circuit 130 <n:1>, so that the COT control circuit 130 can obtain the adjustment signal Q <n:1>.

[0087] Among them, the adjustment signal Q <n:1>It is used to determine whether it is necessary to extend the on-time or off-time in the next switching cycle. <n:1>When the corresponding value increases, it means that the adjustment signal Q <n:1>It is used to determine the length of time to extend the on-time or off-time in the next switching cycle. <n:1>When the corresponding value decreases, it means that the adjustment signal Q <n:1>Used to determine the length of time during which the on-time or off-time does not need to be extended in the following switching cycle.

[0088] For example, when the detection signal DROP indicates that the switching power supply 1000 has entered the minimum off time Toff_min2 or the minimum on time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding value increases, adjusting the signal Q <n:1>For multiple switching cycles, if the detection signal DROP indicates that the switching power supply 1000 has entered the minimum off time Toff_min2 or the minimum on time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding values ​​are getting bigger and bigger.

[0089] When the detection signal DROP indicates that the switching power supply 1000 has not entered the minimum off time Toff_min2 or the minimum on time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding value decreases, adjusting the signal Q <n:1>For multiple switching cycles, if the detection signal DROP indicates that the switching power supply 1000 has not entered the minimum off time Toff_min2 or the minimum on time Ton_min2 in the previous switching cycle, the adjustment signal Q <n:1>The corresponding values ​​are getting smaller and smaller.

[0090] Furthermore, the COT control circuit 130 can adjust the signal Q <n:1>, a second control signal TCOT2 is obtained, so that the on-time or off-time of the pulse width modulation signal generated based on the second control signal TCOT2 and the square wave signal CMPO in the next switching cycle is changed, so that the switching cycle of the switching power supply 1000 can be changed to dynamically adjust the switching frequency of the switching power supply 1000. Thus, the output voltage of the switching power supply 1000 reaches a preset stable voltage value, ensuring that the switching power supply 1000 has the ability to adjust the output voltage, and improving the performance of the switching power supply 1000.

[0091] The second control signal TCOT2 is used to represent the duration of the on-time or off-time of the switching power supply 1000 in the next switching cycle.

[0092] For example, when adjusting the signal Q <n:1>When determining the duration of the on-time or off-time that needs to be extended in the next switching cycle, the COT control circuit 130 can adjust the signal Q <n:1>, prolonging the timing of the on-time or off-time in the next switching cycle, so that the on-time or off-time in the next switching cycle is prolonged, so that the COT control circuit 130 can obtain the second control signal TCOT2. For multiple switching cycles, if the adjustment signal Q <n:1>To determine the length of time for which the on-time or off-time in the next switching cycle needs to be extended, the COT control circuit 130 counts the on-time or off-time longer and longer, thereby achieving a spread spectrum of the switching frequency.

[0093] When the adjustment signal Q <n:1>When it is determined that there is no need to extend the on-time or off-time in the next switching cycle, the COT control circuit 130 can adjust the signal Q <n:1>, the timing of the on-time or off-time in the next switching cycle is not extended, so that the on-time or off-time in the next switching cycle is reduced, so that the COT control circuit 130 can obtain the second control signal TCOT2. For multiple switching cycles, if the adjustment signal Q <n:1>To determine that there is no need to extend the duration of the on-time or off-time in the next switching cycle, the COT control circuit 130 makes the timing of the on-time or off-time shorter and shorter until the spread spectrum of the switching frequency is completely exited.

[0094] The detection and regulation circuit provided in the present application obtains a square wave signal representing that the switching power supply is in a constant on-time control mode or a constant off-time control mode from a pulse width modulation comparator through a detection circuit, and obtains a first control signal representing the duration of the on-time or off-time of the switching power supply in the previous switching cycle from a COT control circuit, and obtains a detection signal representing whether the switching power supply enters the minimum off-time or minimum on-time in the previous switching cycle according to the square wave signal and the first control signal, and transmits the detection signal to the regulation circuit so that the regulation circuit can obtain the detection signal. In this way, the regulation circuit can obtain a clock signal from the detection circuit in the next switching cycle, and obtain a regulation signal according to the clock signal and the detection signal, and transmits a regulation signal to the COT control circuit for determining whether it is necessary to extend the duration of the on-time or off-time in the next switching cycle, so that the COT control circuit can obtain the regulation signal. Furthermore, the COT control circuit can obtain a second control signal for characterizing the duration of the on-time or off-time of the switching power supply in the next switching cycle according to the adjustment signal, so that the on-time or off-time of the pulse width modulation signal generated based on the second control signal and the square wave signal in the next switching cycle changes, so that the switching cycle of the switching power supply can be changed to dynamically adjust the switching frequency of the switching power supply. Thus, the output voltage of the switching power supply reaches a preset stable voltage value, ensuring that the switching power supply has the ability to adjust the output voltage, and improving the performance of the switching power supply.

[0095] The first control signal TCOT1 may include: a first sub-control signal TCOT1-1 and a second sub-control signal TCOT1-2. The detection signal DROP may include: a first detection signal DROP1 and a second detection signal DROP2. The clock signal may include: a first clock signal and a second clock signal. The adjustment signal Q <n:1>It may include: a first adjustment signal Q1 <n:1>and the second adjustment signal Q2 <n:1>The second control signal TCOT2 may include a third sub-control signal TCOT2-1 and a fourth sub-control signal TCOT2-2.

[0096] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant on-time control mode, the detection circuit 110 can obtain the first detection signal DROP1 according to the square wave signal CMPO and the first sub-control signal TCOT1-1, and transmit the first detection signal DROP1 to the regulation circuit 120, so that the regulation circuit 120 can obtain the first detection signal DROP1.

[0097] The first sub-control signal TCOT1-1 is used to indicate the duration of the on-time of the switching power supply 1000 in the previous switching cycle, and the first detection signal DROP1 is used to indicate whether the switching power supply 1000 enters the minimum off-time Toff_min2 in the previous switching cycle.

[0098] In this way, the regulating circuit 120 can obtain the first regulating signal Q1 according to the first clock signal and the first detection signal DROP1 in the next switching cycle. <n:1>, and transmits the first adjustment signal Q1 to the COT control circuit 130 <n:1>, so that the COT control circuit 130 can obtain the first adjustment signal Q1 <n:1>.

[0099] Among them, the first adjustment signal Q1 <n:1>Used to determine whether it is necessary to extend the on-time in the next switching cycle.

[0100] Thus, the COT control circuit 130 can adjust the first adjustment signal Q1 <n:1>, and obtain the third sub-control signal TCOT2-1.

[0101] The third sub-control signal TCOT2-1 is used to represent the duration of the on-time of the switching power supply 1000 in the next switching cycle.

[0102] Based on this, when the square wave signal indicates that the switching power supply is in a constant on-time control mode, the detection circuit can obtain a first detection signal for indicating whether the switching power supply enters the minimum off-time in the previous switching cycle according to the square wave signal and the first sub-control signal for indicating the duration of the on-time of the switching power supply in the previous switching cycle, and transmit the first detection signal to the adjustment circuit so that the adjustment circuit can obtain the first detection signal. In this way, in the next switching cycle, the adjustment circuit can obtain a first adjustment signal for determining whether the duration of the on-time in the next switching cycle needs to be extended according to the first clock signal and the first detection signal, and transmit the first adjustment signal to the COT control circuit so that the COT control circuit can obtain the first adjustment signal. Furthermore, the COT control circuit can obtain a third sub-control signal for indicating the duration of the on-time of the switching power supply in the next switching cycle according to the first adjustment signal. Thus, the COT control circuit can obtain the third sub-control signal.

[0103] When the square wave signal CMPO indicates that the switching power supply 1000 is in a constant off-time control mode, the detection circuit 110 can obtain the second detection signal DROP2 according to the square wave signal CMPO and the second sub-control signal TCOT1-2, and transmit the second detection signal DROP2 to the regulation circuit 120, so that the regulation circuit 120 can obtain the second detection signal DROP2.

[0104] The second sub-control signal TCOT1-2 is used to indicate the duration of the off time of the switching power supply 1000 in the previous switching cycle, and the second detection signal DROP2 is used to indicate whether the switching power supply 1000 enters the minimum on time Ton_min2 in the previous switching cycle.

[0105] In this way, the regulating circuit 120 can obtain the second regulating signal Q2 according to the second clock signal and the second detection signal DROP2 in the next switching cycle. <n:1>, and transmits the second adjustment signal Q2 to the COT control circuit 130 <n:1>, so that the COT control circuit 130 can obtain the second adjustment signal Q2 <n:1>.

[0106] Among them, the second adjustment signal Q2 <n:1>Used to determine whether it is necessary to extend the off time in the next switching cycle.

[0107] Thus, the COT control circuit 130 can adjust the second signal Q2 <n:1>, a fourth sub-control signal TCOT2-2 is obtained, and the fourth sub-control signal TCOT2-2 is used to characterize the duration of the conduction time of the switching power supply 1000 in the next switching cycle.

[0108] Based on this, when the square wave signal indicates that the switching power supply is in a constant off-time control mode, the detection circuit can obtain a second detection signal for indicating whether the switching power supply enters the minimum on-time in the previous switching cycle according to the square wave signal and the second sub-control signal for indicating the duration of the off-time of the switching power supply in the previous switching cycle, and transmit the second detection signal to the adjustment circuit so that the adjustment circuit can obtain the second detection signal. In this way, in the next switching cycle, the adjustment circuit can obtain a second adjustment signal for determining whether the duration of the off-time in the next switching cycle needs to be extended according to the second clock signal and the second detection signal, and transmit the second adjustment signal to the COT control circuit so that the COT control circuit can obtain the second adjustment signal. Furthermore, the COT control circuit can obtain a fourth sub-control signal for indicating the duration of the on-time of the switching power supply in the next switching cycle according to the second adjustment signal. Thus, the COT control circuit 130 can obtain the fourth sub-control signal.

[0109] Based on the description of the above embodiment, a possible implementation of the detection circuit 110 is exemplified. Figure 1 As shown, the detection circuit 110 may include: a detection control component 111 , a clock signal output component 112 and a detection signal output component 113 .

[0110] The first input terminal of the detection and control component 111 is electrically connected to the output terminal of the pulse width modulation comparator PWM Comp, the second input terminal of the detection and control component 111 is electrically connected to the output terminal of the COT control circuit 130, the input terminal of the clock signal output component 112 is electrically connected to the first output terminal or the second output terminal of the detection and control component 111, the output terminal of the clock signal output component 112 is electrically connected to the second input terminal of the adjustment circuit 120 and the first input terminal of the detection signal output component 113 respectively, the second input terminal of the detection signal output component 113 is used to access the power supply voltage VDD, and the output terminal of the detection signal output component 113 is electrically connected to the first input terminal of the adjustment circuit 120.

[0111] Among them, the first input end of the detection control component 111 is the first input end of the detection circuit 110, the second input end of the detection control component 111 is the second input end of the detection circuit 110, the output end of the detection signal output component 113 is the first output end of the detection circuit 110, and the output end of the clock signal output component 112 is the second output end of the detection circuit 110.

[0112] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant on-time control mode, the detection control component 111 can control the first output terminal of the detection control component 111 to be electrically connected to the input terminal of the clock signal output component 112. In addition, the detection control component 111 can obtain the first pulse width modulation signal PWM1 according to the square wave signal CMPO and the first sub-control signal TCOT1-1, and transmit the first pulse width modulation signal PWM1 to the clock signal output component 112, so that the clock signal output component 112 can obtain the first pulse width modulation signal PWM1.

[0113] In this way, the clock signal output component 112 can transmit the first clock signal to the detection signal output component 113 according to the first pulse width modulation signal PWM1, so that the detection signal output component 113 can obtain the first clock signal.

[0114] Furthermore, the detection signal output component 113 can detect whether the switching power supply 1000 enters the minimum off time Toff_min2 in the previous switching cycle according to the first clock signal, and obtain the first detection signal DROP1, so that the detection circuit 110 can obtain the first detection signal DROP1.

[0115] Based on this, when the square wave signal indicates that the switching power supply is in a constant on-time control mode, the detection control component can control the first output end of the detection control component to be electrically connected to the input end of the clock signal output component, and obtain a first pulse width modulation signal according to the square wave signal and the first sub-control signal, and transmit the first pulse width modulation signal to the clock signal output component, so that the clock signal output component can obtain the first pulse width modulation signal. In this way, the clock signal output component can transmit the first clock signal to the detection signal output component according to the first pulse width modulation signal, so that the detection signal output component can obtain the first clock signal. Furthermore, the detection signal output component can detect whether the switching power supply enters the minimum off-time in the previous switching cycle according to the first clock signal, and obtain a first detection signal. Thus, the detection circuit can obtain the first detection signal.

[0116] When the square wave signal CMPO indicates that the switching power supply 1000 is in a constant off-time control mode, the detection control component 111 can control the second output end of the detection control component 111 to be electrically connected to the input end of the clock signal output component 112, and the detection control component 111 can obtain the second pulse width modulation signal PWM2 according to the square wave signal CMPO and the first control signal TCOT1, and transmit the second pulse width modulation signal PWM2 to the clock signal output component 112, so that the clock signal output component 112 can obtain the second pulse width modulation signal PWM2.

[0117] In this way, the clock signal output component 112 can transmit the second clock signal to the detection signal output component 113 according to the second pulse width modulation signal PWM2, so that the detection signal output component 113 can obtain the second clock signal.

[0118] Furthermore, the detection signal output component 113 can detect whether the switching power supply 1000 enters the minimum on-time Ton_min2 in the previous switching cycle according to the second clock signal, and obtain the second detection signal DROP2. Thus, the detection circuit 110 can obtain the second detection signal DROP2.

[0119] Based on this, when the square wave signal indicates that the switching power supply is in a constant off-time control mode, the detection control component can control the second output end of the detection control component to be electrically connected to the input end of the clock signal output component, and obtain a second pulse width modulation signal according to the square wave signal and the second sub-control signal, and transmit the second pulse width modulation signal to the clock signal output component, so that the clock signal output component can obtain the second pulse width modulation signal. In this way, the clock signal output component can transmit the second clock signal to the detection signal output component according to the second pulse width modulation signal, so that the detection signal output component can obtain the second clock signal. Furthermore, the detection signal output component can detect whether the switching power supply enters the minimum on-time in the previous switching cycle according to the second clock signal, and obtain a second detection signal. Thus, the detection circuit can obtain the second detection signal.

[0120] Based on the description of the above embodiment, a possible implementation of the detection control component 111 is exemplified. Figure 1 As shown, the detection control component 111 may include: a first trigger SR.

[0121] The set terminal S of the first trigger SR is electrically connected to the output terminal of the pulse width modulation comparator PWM Comp, the reset terminal R of the first trigger SR is electrically connected to the output terminal of the COT control circuit 130, and the positive output terminal Q or the reverse output terminal QZ of the first trigger SR is electrically connected to the input terminal of the clock signal output component 112.

[0122] Among them, the set terminal S of the first trigger SR is the first input terminal of the detection control component 111, the reset terminal R of the first trigger SR is the second input terminal of the detection control component 111, the forward output terminal Q of the first trigger SR is the first output terminal of the detection control component 111, and the reverse output terminal QZ of the first trigger SR is the second output terminal of the detection control component 111.

[0123] Based on the description of the above embodiment, a possible implementation of the clock signal output component 112 is exemplified. Figure 1 As shown, the clock signal output component 112 may include: a first switch tube S1, a second switch tube S2 and a first inverter INV1.

[0124] The first end of the second switch tube S2 is electrically connected to the first output end or the second output end of the detection control component 111, the second end of the second switch tube S2 is electrically connected to the first end of the first switch tube S1 and the input end of the first inverter INV1 respectively, the second end of the first switch tube S1 and the output end of the first inverter INV1 are both electrically connected to the first input end of the detection signal output component 113, and the control end of the first switch tube S1 and the control end of the second switch tube S2 are both used to access the switch signal, and the switch signal is used to control the conduction or shutdown of the switch tube.

[0125] The first end of the second switch tube S2 is the input end of the clock signal output component 112 , and the second end of the first switch tube S1 and the output end of the first inverter INV1 are both output ends of the clock signal output component 112 .

[0126] The first switch tube S1 and the second switch tube S2 may include but are not limited to gallium nitride transistors, bipolar junction transistors, insulated gate bipolar transistors, metal-oxide semiconductor field effect transistors, field-controlled thyristors, gate turn-off thyristors and transmission gates.

[0127] For example, when the first switch tube S1 and the second switch tube S2 are gallium nitride transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gate of the gallium nitride transistor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the drain or source of the gallium nitride transistor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the source or drain of the gallium nitride transistor.

[0128] For example, when the first switch tube S1 and the second switch tube S2 are bipolar junction transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the base of the bipolar junction transistor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the collector or emitter of the bipolar junction transistor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the emitter or collector of the bipolar junction transistor.

[0129] For example, when the first switch tube S1 and the second switch tube S2 are insulated gate bipolar transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gate of the insulated gate bipolar transistor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the collector or emitter of the insulated gate bipolar transistor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the emitter or collector of the insulated gate bipolar transistor.

[0130] For example, when the first switch tube S1 and the second switch tube S2 are metal-oxide semiconductor field effect transistors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gate of the metal-oxide semiconductor field effect transistor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the drain or source of the metal-oxide semiconductor field effect transistor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the source or drain of the metal-oxide semiconductor field effect transistor.

[0131] For example, when the first switch tube S1 and the second switch tube S2 are field-controlled thyristors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gate of the field-controlled thyristor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the drain or source of the field-controlled thyristor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the source or drain of the field-controlled thyristor.

[0132] For example, when the first switch tube S1 and the second switch tube S2 are gate turn-off thyristors, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the gate of the gate turn-off thyristor, the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the cathode or anode of the gate turn-off thyristor, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the cathode or anode of the gate turn-off thyristor.

[0133] For example, when the first switch tube S1 and the second switch tube S2 are transmission gates, the control end of the first switch tube S1 and the control end of the second switch tube S2 refer to the ports of the transmission gate used to access the gate control signal, and the first end of the first switch tube S1 and the first end of the second switch tube S2 can be the input end or the output end of the transmission gate, and correspondingly, the second end of the first switch tube S1 and the second end of the second switch tube S2 can be the input end or the output end of the transmission gate.

[0134] When the square wave signal CMPO indicates that the switching power supply 1000 is in a constant on-time control mode, the first switch tube S1 is always on. When the square wave signal CMPO indicates that the switching power supply 1000 is in a constant off-time control mode, the first switch tube S1 is always off.

[0135] Based on the description of the above embodiment, a possible implementation of the detection signal output component 113 is exemplified. Figure 1 As shown, the detection signal output component 113 may include: a second inverter INV2, a delay device and a second trigger DFF.

[0136] The input end of the second inverter INV2 and the input end of the delay device are both electrically connected to the output end of the clock signal output component 112, the output end of the second inverter INV2 is electrically connected to the clock input end of the second trigger DFF, the output end of the delay device is electrically connected to the set input end of the second trigger DFF, the data input end of the second trigger DFF is used to access the power supply voltage VDD, and the output end of the second trigger DFF is electrically connected to the first input end of the adjustment circuit 120.

[0137] Among them, the input end of the second inverter INV2 and the input end of the delay device are both the first input end of the detection signal output component 113, the data input end of the second trigger DFF is the second input end of the detection signal output component 111, and the output end of the second trigger DFF is the output end of the detection signal output component 113.

[0138] Based on the description of the above embodiment, a possible implementation of the regulating circuit 120 is exemplified. Figure 1 As shown, the regulating circuit 120 may include: a counter Up Down Counter.

[0139] The clock input terminal of the counter Up Down Counter is electrically connected to the second output terminal of the detection circuit 110 , the counting input terminal of the counter Up Down Counter is electrically connected to the first output terminal of the detection circuit 110 , and the output terminal of the counter Up Down Counter is electrically connected to the input terminal of the COT control circuit 130 .

[0140] The clock input terminal of the counter Up Down Counter is the second input terminal of the regulating circuit 120 , the counting input terminal of the counter Up Down Counter is the first input terminal of the regulating circuit 120 , and the output terminal of the counter Up Down Counter is the output terminal of the regulating circuit 120 .

[0141] The counter Up Down Counter can obtain the first clock signal from the detection circuit 110 in the next switching cycle, and determine whether to count up the first value of the counter Up Down Counter according to the first detection signal DROP1 at the rising edge of the first clock signal to obtain the first adjustment signal Q1 <n:1>.

[0142] Alternatively, the counter Up Down Counter can obtain the second clock signal from the detection circuit 110 in the next switching cycle. Moreover, at the rising edge of the second clock signal, the counter Up Down Counter can determine whether to count up the first value of the counter Up Down Counter according to the second detection signal DROP2 to obtain the second adjustment signal Q2 <n:1>.

[0143] For example, in the second switching cycle, the first value is the value output by the counter Up Down Counter in the first switching cycle, that is, the first value is the value of the adjustment signal Q in the first switching cycle. <n:1>For example, in the fourth switching cycle, the first value is the value output by the counter Up Down Counter in the third switching cycle, that is, the first value is the value of the adjustment signal Q in the third switching cycle. <n:1>The corresponding numerical value.

[0144] In summary, in the next switching cycle, the counter can obtain the first clock signal from the detection circuit, and at the rising edge of the first clock signal, according to the first detection signal, determine whether to count up the first value of the counter to obtain the first adjustment signal. Alternatively, in the next switching cycle, the counter can obtain the second clock signal from the detection circuit, and at the rising edge of the second clock signal, according to the second detection signal, determine whether to count up the first value of the counter to obtain the second adjustment signal. Thus, the adjustment circuit can obtain the first adjustment signal or the second adjustment signal.

[0145] Based on the description of the above embodiment, a possible implementation of the regulating circuit 120 is exemplified. Figure 1 As shown, the regulating circuit 120 may further include: a frequency divider.

[0146] The input end of the frequency divider Divider is electrically connected to the second output end of the detection circuit 110 , and the output end of the frequency divider Divider is electrically connected to the clock input end of the counter Up Down Counter.

[0147] The frequency divider Divider can divide the first clock signal to obtain a first divided clock signal PWM_DIV1. In addition, the frequency divider Divider can transmit the first divided clock signal PWM_DIV1 to the counter Up Down Counter, so that the counter Up Down Counter can obtain the first adjustment signal Q1. <n:1>.

[0148] Alternatively, the frequency divider Divider can divide the second clock signal to obtain a second divided clock signal PWM_DIV2. Furthermore, the frequency divider Divider can transmit the second divided clock signal PWM_DIV2 to the counter Up Down Counter, so that the counter Up Down Counter can obtain the second adjustment signal Q2. <n:1>.

[0149] The first divided clock signal PWM_DIV1 and the second divided clock signal PWM_DIV2 are both divided clock signals PWM_DIV. The divided clock signal PWM_DIV output by the divider can reduce the adjustment signal Q <n:1>The change speed of the COT control circuit 130 is prevented from being adjusted too fast and causing the output voltage VOUT2 to fluctuate.

[0150] Based on the description of the above embodiment, a possible implementation of the COT control circuit 130 is exemplified. Figure 2 , Figure 2 This is a schematic diagram of the structure of a COT control circuit in a detection and regulation circuit provided in an embodiment of the present application. Figure 2 As shown, the COT control circuit 130 may include: a current output component 131, a capacitor Ccot and a timing comparator COT COMP.

[0151] The control end of the current output component 131 is electrically connected to the output end of the regulation circuit 120, the output end of the current output component 131 is electrically connected to the first plate of the capacitor Ccot, the positive input end of the timing comparator COT COMP is electrically connected between the output end of the current output component 131 and the first plate of the capacitor Ccot, the negative input end of the timing comparator COT COMP is used to access the reference voltage Vcot, the reference voltage Vcot is related to the square wave signal CMPO, and the output end of the timing comparator COT COMP is electrically connected to the first input end of the detection circuit 110.

[0152] The control end of the current output component 131 is the input end of the COT control circuit 130 , and the output end of the timing comparator COTCOMP is the output end of the COT control circuit 130 .

[0153] The current output component 131 can output a first adjustment signal Q1 <n:1>Furthermore, the current output component 131 can use the first charging current to charge the capacitor Ccot, so that the voltage on the capacitor Ccot increases.

[0154] In this way, the timing comparator COT COMP can compare the voltage on the capacitor Ccot with the reference voltage Vcot to obtain the third sub-control signal TCOT2 - 1 .

[0155] Alternatively, the current output component 131 can output a second adjustment signal Q2 <n:1>Furthermore, the current output component 131 can use the second charging current to charge the capacitor Ccot, so that the voltage on the capacitor Ccot increases.

[0156] In this way, the timing comparator COT COMP can compare the voltage on the capacitor Ccot with the reference voltage Vcot to obtain the fourth sub-control signal TCOT2-2.

[0157] The first charging current and the second charging current are both charging currents Icot.

[0158] In which, when the square wave signal CMPO represents that the switching power supply 1000 is in a constant on-time control mode, the reference voltage Vcot is the output voltage VOUT2 of the switching power supply 1000, that is, Vcot=VOUT2, and the charging current Icot is the ratio between the input voltage VIN2 of the switching power supply 1000 and the resistance Rcot of the current output component 131, that is, VIN2 / Rcot.

[0159] When the square wave signal CMPO indicates that the switching power supply 1000 is in the constant off-time control mode, the reference voltage Vcot is the difference between the input voltage VIN2 of the switching power supply 1000 and the output voltage VOUT2 of the switching power supply 1000, that is, Vcot=VIN2-VOUT2. The charging current Icot is the ratio between the input voltage VIN2 of the switching power supply 1000 and the resistance Rcot of the current output component 131, that is, VIN2 / Rcot.

[0160] In summary, the current output component can output the first charging current corresponding to the first adjustment signal, and use the first charging current to charge the capacitor. In this way, the timing comparator can compare the voltage on the capacitor with the reference voltage to obtain the third sub-control signal, so that the COT control circuit can obtain the third sub-control signal. Alternatively, the current output component can output the second charging current corresponding to the second adjustment signal, and use the second charging current to charge the capacitor. In this way, the timing comparator can compare the voltage on the capacitor with the reference voltage to obtain the fourth sub-control signal, so that the COT control circuit can obtain the fourth sub-control signal. Thus, the COT control circuit can obtain the third sub-control signal or the fourth sub-control signal.

[0161] Based on the description of the above embodiment, a possible implementation of the current output component 131 is exemplified. Figure 2 As shown, the current output component 131 may include: a current source, a first N-type transistor Mx, a second N-type transistor M0, a first P-type transistor MP1, a second P-type transistor MP2, a plurality of N-type transistor groups and a plurality of third inverters INV3.

[0162] The output end of the current source is electrically connected to the drain end of the first N-type transistor Mx, the gate end of the first N-type transistor Mx is electrically connected to the gate end of the second N-type transistor M0 and the first gate end of each N-type transistor group, the drain end of the first N-type transistor Mx is electrically connected to the drain end of each N-type transistor group, the drain end of the first P-type transistor MP1, the gate end of the first P-type transistor MP1 and the gate end of the second P-type transistor MP2, the drain end of the second P-type transistor MP2 is electrically connected to the first plate of the capacitor Ccot, the source end of the first P-type transistor MP1 and the source end of the second P-type transistor MP2 are both used to access the power supply voltage VDD, the second gate end of each N-type transistor group is electrically connected to the output end of each third inverter INV3, the input end of each third inverter INV3 is electrically connected to the output end of the adjustment circuit 120, and the source end of the first N-type crystal Mx, the source end of the second N-type transistor M0 and the source end of each N-type transistor group are all grounded.

[0163] In some examples, each N-type transistor group may include: a transistor Ms and a transistor M.

[0164] The drain terminal of transistor Ms is electrically connected to the drain terminal of the first N-type transistor Mx, the gate terminal of transistor Ms is electrically connected to the output terminal of the third inverter INV3, the source terminal of transistor Ms is electrically connected to the drain terminal of transistor M, the gate terminal of transistor Ms is electrically connected to the gate terminal of the second N-type transistor M0, and the source terminal of transistor M is grounded.

[0165] In some examples, the number of the first N-type transistors Mx is the sum of the number of the second N-type transistors M0 and the number of the plurality of N-type transistor groups, and the number of the first P-type transistors MP1 is equal to the number of the second P-type transistors MP2.

[0166] Among them, the number of the second N-type transistors M0 determines the maximum timing time of the COT control circuit 130 for the on-time or off-time within the switching cycle. In other words, the number of the second N-type transistors M0 is related to the maximum duration of the on-time or off-time of the switching power supply 1000. n current mirrors composed of the first N-type transistor Mx tube and multiple N-type transistor groups. The value of the number n of current mirrors will affect the step size of the frequency modulation of the switching frequency. When the number n of current mirrors is larger, the step size of each adjustment timing of the COT control circuit 130 is shorter, and the shorter the step size, the smaller the jitter of the output voltage VOUT2 will be. In other words, the number of multiple N-type transistor groups is related to the step size of the adjustment of the switching frequency.

[0167] When the counter Up Down Counter outputs the adjustment signal Q <n:1>When the corresponding values ​​are all 0, the output signal of each third inverter INV3 is at a high level, so that the transistors Ms1, Ms2 to Msn are all turned on. In this way, the reference current Icot-ef output by the current source is mirrored in equal proportion through the current mirror group composed of the first N-type transistor Mx, the second N-type transistor M0 and a plurality of N-type transistor groups to obtain the charging current Icot to charge the capacitor Ccot, so that the timing time of the on time or off time in the switching cycle by the COT control circuit 130 will not be extended.

[0168] When the output of the counter Up Down Counter is adjusted, the signal Q <n:1>When the corresponding value gradually increases, the output signal of each third inverter INV3 gradually changes to a low level, so that the transistors Ms1, Ms2 to Msn are also turned off bit by bit. In this way, the reference current Icot-ef output by the current source is mirrored at a reduced ratio through the current mirror composed of the first N-type transistor Mx, the second N-type transistor M0 and a plurality of N-type transistor groups to obtain the charging current Icot, which gradually decreases, so that the COT control circuit 130 prolongs the timing time of the on time or off time in the switching cycle, so as to extend the timing time and achieve the purpose of spectrum spreading.

[0169] When the output of the counter Up Down Counter is adjusted, the signal Q <n:1>When the corresponding values ​​are all 1, the adjustment signal Q <n:1>When the corresponding value reaches the maximum, the output signal of each third inverter INV3 is low level, so that the transistors Ms1, Ms2 to Msn are all turned off. In this way, the reduction ratio is minimized, the charging current Icot is minimized, and the timing time of the on-time or off-time in the switching cycle by the COT control circuit 130 reaches the longest delay.

[0170] Combine the following Figure 3 , Figure 3 A detection timing diagram of a detection and regulation circuit provided in an embodiment of the present application is provided. The working principle of the detection and regulation circuit 1000 is described in detail when the switching power supply 1000 is in a constant on-time control mode, as follows:

[0171] The first pulse width modulation signal PWM1 is generated by the square wave signal CMPO and the control signal TCOT. When the switching power supply 1000 is in the constant on-time control mode, the first switch tube S1 is turned on, and the second switch S2 is electrically connected to the positive phase output terminal Q of the first trigger SR. The detection circuit 110 detects whether the switching power supply 1000 enters the minimum off-time Toff_min2 after the first pulse width modulation signal PWM1 is at a low level.

[0172] At time t0, the control signal TCOT is at a low level, the current iL1 of the inductor L1 drops to a valley current, the square wave signal CMPO is at a high level, the positive phase output terminal Q of the first trigger SR outputs a high level, and the first pulse width modulation signal PWM1 is at a high level, so that the upper tube is turned on and the lower tube is turned off. At this moment, the COT control circuit 130 starts timing the on-time Ton1 of the first switching cycle Tsw1.

[0173] In the time period t0-t1, the COT control circuit 130 times the on-time Ton1 in the first switching cycle Tsw1, that is, the control signal TCOT in this time period represents the duration of the on-time Ton1 of the switching power supply 1000 in the first switching cycle Tsw1.

[0174] At time t1, the control signal TCOT is at a high level, the square wave signal CMPO is at a low level, and the positive phase output terminal Q of the first trigger SR outputs a low level, so that the first pulse width modulation signal PWM1 is at a low level, so that the upper tube is turned off and the lower tube is turned on. At this moment, the COT control circuit 130 ends the timing of the on-time Ton1 of the first switching cycle Tsw1. At this moment, when the first pulse width modulation signal PWM1 changes from a high level to a low level, a rising edge is input to the clock input terminal of the second trigger DFF, so that the output terminal of the second trigger DFF is set to a high level, so that the first detection signal DROP1 is at a high level. In other words, the switching power supply 1000 enters the state of the minimum off-time Toff_min2.

[0175] During the time period t1-t2, the duration of this period is the off time in the first switching cycle Tsw1.

[0176] During the time period t0-t2, the duration of this period is the first switching cycle Tsw1.

[0177] At time t2, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the positive phase output terminal Q of the first trigger SR outputs a high level, making the first pulse width modulation signal PWM1 at a high level, so that the upper tube is turned on and the lower tube is turned off. At this moment, the COT control circuit 130 starts timing the on-time Ton2 of the second switching cycle Tsw2. At this moment, when the first pulse width modulation signal PWM1 changes from a low level to a high level, a rising edge is input to the clock input terminal of the counter Up Down Counter, so that the counter Up Down Counter counts up the first value. In this way, the first adjustment signal Q1 output by the counter Up Down Counter is <n:1>Increases, causing the first charging current to decrease, so that the COT control circuit 130 prolongs the timing of the on-time Ton2 in the second switching cycle Tsw2.

[0178] In the time period t1-t3, the length of this period is the delay time Tdly of the delay device. Since the off time in the first switching cycle Tsw1 is less than the delay time Tdly of the delay device, the first detection signal DROP1 cannot be set to a low level during the off time in the first switching cycle Tsw1.

[0179] In the time period t2-t4, the COT control circuit 130 times the on-time Ton2 in the second switching cycle Tsw2, that is, the control signal TCOT in this time period represents the duration of the on-time Ton2 of the switching power supply 1000 in the second switching cycle Tsw2. Since the COT control circuit 130 extends the timing of the on-time Ton2 in the second switching cycle Tsw2, the duration of the on-time Ton2 is greater than the duration of the on-time Ton1, so as to achieve frequency spread.

[0180] At time t4, the control signal TCOT is at a high level, the square wave signal CMPO is at a low level, and the positive phase output terminal Q of the first flip-flop SR outputs a low level, making the first pulse width modulation signal PWM1 at a low level, so that the upper tube is turned off and the lower tube is turned on. At this moment, the COT control circuit 130 ends the timing of the on-time Ton2 of the second switching cycle Tsw2. At this moment, when the first pulse width modulation signal PWM1 changes from a high level to a low level, a rising edge is input to the clock input terminal of the second flip-flop DFF, so that the output terminal of the second flip-flop DFF is set to a high level, so that the first detection signal DROP1 is at a high level.

[0181] In the period t4-t5, after the on-time Ton1 is extended, the loop will readjust an off-time to obtain the off-time in the second switching cycle Tsw2. This period is the off-time in the second switching cycle Tsw2.

[0182] During the time period t2-t5, the duration of this period is the second switching cycle Tsw2.

[0183] At time t5, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the positive phase output terminal Q of the first trigger SR outputs a high level, making the first pulse width modulation signal PWM1 at a high level, so that the upper tube is turned on and the lower tube is turned off. At this moment, the COT control circuit 130 starts timing the on-time Ton3 of the third switching cycle Tsw3. At this moment, when the first pulse width modulation signal PWM1 changes from a low level to a high level, a rising edge is input to the clock input terminal of the counter Up Down Counter, so that the counter Up Down Counter continues to count upward. In this way, the first adjustment signal Q1 output by the counter Up Down Counter is <n:1>The first charging current continues to increase, so that the first charging current continues to decrease, and the COT control circuit 130 continues to extend the timing of the on-time Ton3 in the third switching cycle Tsw3.

[0184] In the period T4-t6, the length of this period is the delay time Tdly of the delay device. Since the off time in the second switching cycle Tsw2 is less than the delay time Tdly of the delay device, the first detection signal DROP1 cannot be set to a low level during the off time in the second switching cycle Tsw2.

[0185] At time t7, the control signal TCOT is at a high level, the square wave signal CMPO is at a low level, and the positive phase output terminal Q of the first flip-flop SR outputs a low level, making the first pulse width modulation signal PWM1 at a low level, so that the upper tube is turned off and the lower tube is turned on. At this moment, the COT control circuit 130 ends the timing of the on-time Ton3 of the third switching cycle Tsw3. At this moment, when the first pulse width modulation signal PWM1 changes from a high level to a low level, a rising edge is input to the clock input terminal of the second flip-flop DFF, so that the output terminal of the second flip-flop DFF is set to a high level, so that the first detection signal DROP1 is at a high level.

[0186] During the time period t7-t8, the length of this period is the delay time Tdly of the delay device.

[0187] At time t8, since the off time in the third switching cycle Tsw3 is greater than the delay time Tdly of the delay device, the set input terminal of the second flip-flop DFF is at a low level. Therefore, the first detection signal DROP1 is reset to a low level during the off time in the third switching cycle Tsw3. In other words, the switching power supply 1000 is not in a state of entering the minimum off time Toff_min2.

[0188] In the period t7-t9, after the on-time Ton2 is extended, the loop will readjust an off-time to obtain the off-time in the third switching cycle Tsw3. This period is the off-time in the third switching cycle Tsw3.

[0189] During the time period t5-t9, the duration of this period is the third switching cycle Tsw3.

[0190] After time t9, since the off time after the third switching cycle Tsw3 is greater than the delay time Tdly, the first detection signal DROP1 is set to a low level during the off time, so that the first adjustment signal Q1 output by the counter Up Down Counter <n:1>It will gradually decrease until it completely exits the spread spectrum.

[0191] Based on the above description, it can be known that by setting the delay time Tdly equal to the minimum off time Toff_min2, the detection of the minimum off time Toff_min2 is achieved.

[0192] Combine the following Figure 4 , Figure 4 This is a detection timing diagram of another detection and regulation circuit provided in an embodiment of the present application. The working principle of the detection and regulation circuit 1000 when the switching power supply 1000 is in a constant off-time control mode is described in detail as follows:

[0193] When the switching power supply 1000 is in the constant off-time control mode, the first switch tube S1 is turned off, so that the first inverter INV1 enters the control logic, and the second switch S2 is electrically connected to the negative phase output terminal QZ of the first trigger SR. The detection circuit 110 detects whether the switching power supply 1000 enters the minimum on-time Ton_min2 after the first pulse width modulation signal PWM1 is at a high level.

[0194] At time t0, the control signal TCOT is at a low level, the current iL1 of the inductor L1 increases to the peak current, the square wave signal CMPO is at a high level, the positive phase output terminal Q of the first trigger SR outputs a low level, and the first pulse width modulation signal PWM1 is at a low level, so that the upper tube is turned off and the lower tube is turned on. At this moment, the COT control circuit 130 starts timing the off time Toff1 of the first switching cycle Tsw1.

[0195] In the time period t0-t1, the COT control circuit 130 times the off time Toff1 in the first switching cycle Tsw1, that is, the control signal TCOT in this time period represents the duration of the off time Toff1 of the switching power supply 1000 in the first switching cycle Tsw1.

[0196] At time t1, the control signal TCOT is at a high level, the square wave signal CMPO is at a low level, and the negative phase output terminal QZ of the first trigger SR outputs a high level, making the second pulse width modulation signal PWM2 at a high level, so that the upper tube is turned on and the lower tube is turned off. At this moment, the COT control circuit 130 ends the timing of the off time Toff1 of the first switching cycle Tsw1. At this moment, when the first pulse width modulation signal PWM1 changes from a low level to a high level, a rising edge is input to the clock input terminal of the second trigger DFF, so that the output terminal of the second trigger DFF is set to a high level, and the second detection signal DROP2 is at a high level. In other words, the switching power supply 1000 enters the state of the minimum on time Ton_min2.

[0197] During the time period t1 - t2 , the duration of this period is the on-time of the first switching cycle Tsw1 .

[0198] During the time period t0-t2, the duration of this period is the first switching cycle Tsw1.

[0199] At time t2, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the negative phase output terminal QZ of the first trigger SR outputs a low level, making the second pulse width modulation signal PWM2 at a low level, so that the upper tube is turned off and the lower tube is turned on. At this moment, the COT control circuit 130 starts timing the off time Toff2 of the second switching cycle Tsw2. At this moment, when the second pulse width modulation signal PWM2 changes from a high level to a low level, a rising edge is input to the clock input terminal of the counter Up Down Counter, so that the counter Up Down Counter counts up the first value. In this way, the second adjustment signal Q2 output by the counter Up Down Counter is <n:1>The second charging current increases, which reduces the second charging current, so that the COT control circuit 130 prolongs the timing of the off time Toff2 in the second switching cycle Tsw2.

[0200] In the time period t1-t3, the length of this period is the delay time Tdly of the delay device. Since the on-time in the first switching cycle Tsw1 is less than the delay time Tdly of the delay device, the second detection signal DROP2 cannot be set to a low level during the on-time in the first switching cycle Tsw1.

[0201] In the time period t2-t4, the COT control circuit 130 counts the off time Toff2 in the second switching cycle Tsw2, that is, the control signal TCOT in this time period represents the duration of the off time Toff2 of the switching power supply 1000 in the second switching cycle Tsw2. Since the COT control circuit 130 extends the timing of the off time Toff2 in the second switching cycle Tsw2, the duration of the off time Toff2 is greater than the duration of the off time Toff1, so as to achieve frequency spread.

[0202] At time t4, the control signal TCOT is at a high level, the square wave signal CMPO is at a low level, and the negative phase output terminal QZ of the first flip-flop SR outputs a high level, making the second pulse width modulation signal PWM2 at a high level, so that the upper tube is turned on and the lower tube is turned off. At this moment, the COT control circuit 130 ends the timing of the off time Toff2 of the second switching cycle Tsw2. At this moment, when the second pulse width modulation signal PWM2 changes from a low level to a high level, a rising edge is input to the clock input terminal of the second flip-flop DFF, so that the output terminal of the second flip-flop DFF is set to a high level, so that the second detection signal DROP2 is at a high level.

[0203] In the time period t4-t5, after the off time Toff1 is extended, the loop will readjust the on time to obtain the on time in the second switching cycle Tsw2. This time period is the on time in the second switching cycle Tsw2.

[0204] During the time period t2-t5, the duration of this period is the second switching cycle Tsw2.

[0205] At time t5, the control signal TCOT is at a low level, the square wave signal CMPO is at a high level, and the negative phase output terminal QZ of the first trigger SR outputs a low level, making the second pulse width modulation signal PWM2 at a low level, so that the upper tube is turned off and the lower tube is turned on. At this moment, the COT control circuit 130 starts timing the off time Toff3 of the third switching cycle Tsw3. At this moment, when the second pulse width modulation signal PWM1 changes from a high level to a low level, a rising edge is input to the clock input terminal of the counter Up Down Counter, so that the counter Up Down Counter continues to count upward. In this way, the second adjustment signal Q2 output by the counter Up Down Counter is <n:1>The second charging current continues to increase, so that the second charging current continues to decrease, and the COT control circuit 130 continues to extend the timing of the off time Toff3 in the third switching cycle Tsw3.

[0206] In the period T4-t6, the length of this period is the delay time Tdly of the delay device. Since the on-time in the second switching cycle Tsw2 is less than the delay time Tdly of the delay device, the second detection signal DROP2 cannot be set to a low level during the on-time in the second switching cycle Tsw2.

[0207] At time t7, the control signal TCOT is at a high level, the square wave signal CMPO is at a low level, and the negative phase output terminal QZ of the first flip-flop SR outputs a high level, making the second pulse width modulation signal PWM2 at a high level, so that the upper tube is turned on and the lower tube is turned off. At this moment, the COT control circuit 130 ends the timing of the off time Toff3 of the third switching cycle Tsw3. At this moment, when the second pulse width modulation signal PWM1 changes from a low level to a high level, a rising edge is input to the clock input terminal of the second flip-flop DFF, so that the output terminal of the second flip-flop DFF is set to a high level, so that the second detection signal DROP2 is at a high level.

[0208] During the time period t7-t8, the length of this period is the delay time Tdly of the delay device.

[0209] At time t8, since the on-time in the third switching cycle Tsw3 is greater than the delay time Tdly of the delay device, the set input terminal of the second flip-flop DFF is at a low level. Therefore, the second detection signal DROP2 is reset to a low level during the on-time in the third switching cycle Tsw3. In other words, the switching power supply 1000 is not in a state of entering the minimum on-time Ton_min2.

[0210] In the period t7-t9, after the off time Toff2 is extended, the loop will readjust a conduction time to obtain the conduction time in the third switching cycle Tsw3. This period is the conduction time in the third switching cycle Tsw3.

[0211] During the time period t5-t9, the duration of this period is the third switching cycle Tsw3.

[0212] After time t9, since the on-time after the third switching cycle Tsw3 is greater than the delay time Tdly, the second detection signal DROP2 is set to a low level during the on-time, so that the counter Up Down Counter outputs the second adjustment signal Q2 <n:1>It will gradually decrease until it completely exits the spread spectrum.

[0213] Based on the above description, it can be known that by setting the delay time Tdly equal to the minimum on-time Ton_min2, the detection of the minimum on-time Ton_min2 is achieved.

[0214] Reference Figure 5 , Figure 5 This is a schematic diagram of the structure of a switching power supply provided by an embodiment of the present application. Figure 5 As shown, the switching power supply 1000 may include: a high-side power transistor M1, a low-side power transistor M2, an inductor L1, an output capacitor Cout, a first resistor Rsns1, a second resistor Rsns2, a pulse width modulation comparator PWM Comp, a controller 300, a loop-controlled current output circuit 200 and a detection and regulation circuit 100.

[0215] The input end of the loop-controlled current output circuit 200 is electrically connected to the second end of the inductor L1 and the first plate of the output capacitor Cout, respectively. The second end of the inductor L1 is also used to output the output voltage VOUT2 of the switching power supply 1000. The output end of the loop-controlled current output circuit 200 is electrically connected to the first end of the first resistor Rsns1. The second end of the first resistor Rsns1 is electrically connected to the negative phase input end of the pulse width modulation comparator PWM Comp. The first end of the second resistor Rsns2 is used to detect the current of the inductor L1. The second end of the second resistor Rsns2 is electrically connected to the positive phase input end of the pulse width modulation comparator PWM Comp. The pulse width modulation comparator PWM The output end of Comp is electrically connected to the first input end of the detection circuit 110 and the first input end of the controller 300 respectively, the output end of the COT control circuit 130 is electrically connected to the second input end of the controller 300, the first output end of the controller 300 is electrically connected to the control end of the high-side power transistor M1, the second output end of the controller 300 is electrically connected to the control end of the low-side power transistor M2, the first end of the high-side power transistor M1 is used to access the input voltage VIN2 of the switching power supply 1000, the second end of the high-side power transistor M1 is electrically connected to the first end of the low-side power transistor M2, the first end of the inductor L1 is electrically connected between the second end of the high-side power transistor M1 and the first end of the low-side power transistor M2, and the second end of the low-side power transistor M2 and the second plate of the output capacitor Cout are both grounded.

[0216] Among them, the high-side power transistor M1 usually refers to the upper tube, and the low-side power transistor M2 usually refers to the lower tube.

[0217] In some examples, the loop-controlled current output circuit 200 may include: a feedback circuit, an error amplifier, a compensation circuit, and a conversion circuit OTA&Ictrl.

[0218] The input end of the feedback circuit is electrically connected to the second end of the inductor L1, the output end of the feedback circuit is electrically connected to the negative phase input end of the error amplifier EA, the positive phase input end of the error amplifier EA is used to access the reference voltage VREF, the output end of the error amplifier EA is electrically connected to the input end of the conversion circuit OTA&Ictrl through the compensation circuit, and the output end of the conversion circuit OTA&Ictrl is electrically connected to the first end of the first resistor Rsns1.

[0219] Among them, the input end of the feedback circuit is the input end of the loop-controlled current output circuit 200 , and the output end of the conversion circuit OTA&Ictrl is the output end of the loop-controlled current output circuit 200 .

[0220] Exemplarily, the feedback circuit may include: a first feedback resistor RT and a second feedback resistor RB.

[0221] The first end of the first feedback resistor RT is electrically connected to the second end of the inductor L1, the second end of the first feedback resistor RT is electrically connected to the first end of the second feedback resistor RB, the negative phase input terminal of the error amplifier EA is electrically connected between the second end of the first feedback resistor RT and the first end of the second feedback resistor RB, and the second end of the second feedback resistor RB is grounded.

[0222] The first end of the first feedback resistor RT is the input end of the feedback circuit, and the output end of the feedback circuit is located between the second end of the first feedback resistor RT and the first end of the second feedback resistor RB.

[0223] Exemplarily, the compensation circuit may include: a resistor Rcmp and a capacitor Ccmp.

[0224] A first end of the resistor Rcmp is electrically connected to the output end of the error amplifier EA, a second end of the resistor Rcmp is electrically connected to a first plate of the capacitor Ccmp, and a second plate of the capacitor Ccmp is grounded.

[0225] Exemplarily, the conversion circuit OTA&Ictrl may include: a transconductance amplifier OTA and a current controller Ictrl.

[0226] The output voltage VOUT2 is sampled through the first feedback resistor RT and the second feedback resistor RB to obtain the feedback voltage VFB. The difference between the feedback voltage VFB and the reference voltage VREF is amplified by the error amplifier EA and filtered by the compensation circuit to obtain the loop compensation voltage Vcmp. The loop compensation voltage Vcmp is converted into a current through the transconductance amplifier OTA, and converted into a loop control current Iloop through the current controller Ictrl. In this way, the loop control current Iloop is compared with the sampled current of the inductor L1 to generate a square wave signal COMP. At the same time, the detection and regulation circuit 100 can transmit the control signal TCOT to the controller 300. In this way, the logic processing module logic in the controller 300 can process the square wave signal COMP and the control signal TCOT to obtain a pulse width modulation signal PWM that controls the high-side power transistor M1 and the low-side power transistor M2 to turn on or off.

[0227] The switching power supply provided in the embodiment of the present application has the same beneficial effects as the detection and regulation circuit provided in the embodiment of the present application, which will not be repeated here.

[0228] The embodiment of the present application further provides a chip, including: a detection and regulation circuit, and / or a switching power supply 1000 .

[0229] Among them, the detection and regulation circuit and the switching power supply can be integrated into one chip or into different chips, and the embodiments of the present application do not make specific limitations on this.

[0230] The chip provided in the embodiment of the present application has the same beneficial effects as the detection and adjustment circuit provided in the embodiment of the present application, which will not be repeated here.

[0231] An embodiment of the present application also provides an electronic device, including: a chip.

[0232] In this application, electronic devices may include, but are not limited to, tablet computers, routers, industrial robots, and televisions.

[0233] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be described in detail here.

[0234] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A detection and adjustment circuit, characterized in that: The detection and regulation circuit is applied to a switching power supply, and the switching power supply comprises: a pulse width modulation comparator; the detection and regulation circuit comprises: a detection circuit, a regulation circuit and a COT control circuit; The first input terminal of the detection circuit is electrically connected to the output terminal of the pulse width modulation comparator, the second input terminal of the detection circuit is electrically connected to the output terminal of the COT control circuit, the first output terminal of the detection circuit is electrically connected to the first input terminal of the adjustment circuit, the second output terminal of the detection circuit is electrically connected to the second input terminal of the adjustment circuit, and the output terminal of the adjustment circuit is electrically connected to the input terminal of the COT control circuit; The detection circuit is used to obtain a square wave signal from the pulse width modulation comparator, and to obtain a first control signal from the COT control circuit, and to obtain a detection signal according to the square wave signal and the first control signal, and to transmit the detection signal to the regulation circuit, wherein the square wave signal is used to indicate whether the switching power supply is in a constant on-time control mode or a constant off-time control mode, the first control signal is used to indicate the duration of the on-time or off-time of the switching power supply in a previous switching cycle, and the detection signal is used to indicate whether the switching power supply enters a minimum off-time or a minimum on-time in the previous switching cycle; The regulating circuit is used to obtain a clock signal from the detection circuit in a subsequent switching cycle, obtain a regulating signal according to the clock signal and the detection signal, and transmit the regulating signal to the COT control circuit, wherein the regulating signal is used to determine whether it is necessary to extend the duration of the on-time or the off-time in the subsequent switching cycle; The COT control circuit is used to obtain the second control signal according to the adjustment signal to dynamically adjust the switching frequency of the switching power supply, and the second control signal is used to characterize the duration of the on-time or off-time of the switching power supply in the next switching cycle.

2. The circuit according to claim 1, characterized in that The first control signal includes: a first sub-control signal and a second sub-control signal, the detection signal includes: a first detection signal and a second detection signal, the clock signal includes: a first clock signal and a second clock signal, the adjustment signal includes: a first adjustment signal and a second adjustment signal, and the second control signal includes: a third sub-control signal and a fourth sub-control signal; The detection circuit is specifically used to obtain the first detection signal according to the square wave signal and the first sub-control signal when the square wave signal indicates that the switching power supply is in the constant on-time control mode, and transmit the first detection signal to the regulation circuit, the first sub-control signal is used to indicate the duration of the on-time of the switching power supply in the previous switching cycle, and the first detection signal is used to indicate whether the switching power supply enters the minimum off-time in the previous switching cycle; The regulating circuit is specifically used to obtain the first regulating signal according to the first clock signal and the first detection signal in the next switching cycle, and transmit the first regulating signal to the COT control circuit, wherein the first regulating signal is used to determine whether it is necessary to extend the duration of the conduction time in the next switching cycle; The COT control circuit is specifically used to obtain the third sub-control signal according to the first adjustment signal, and the third sub-control signal is used to represent the duration of the conduction time of the switching power supply in the next switching cycle; or, The detection circuit is specifically used to obtain the second detection signal according to the square wave signal and the second sub-control signal when the square wave signal indicates that the switching power supply is in the constant off-time control mode, and transmit the second detection signal to the regulation circuit, the second sub-control signal is used to indicate the duration of the off-time of the switching power supply in the previous switching cycle, and the second detection signal is used to indicate whether the switching power supply enters the minimum on-time in the previous switching cycle; The regulating circuit is specifically used to obtain the second regulating signal according to the second clock signal and the second detection signal in the next switching cycle, and transmit the second regulating signal to the COT control circuit, wherein the second regulating signal is used to determine whether it is necessary to extend the duration of the off time in the next switching cycle; The COT control circuit is specifically used to obtain the fourth sub-control signal according to the second adjustment signal, and the fourth sub-control signal is used to characterize the duration of the conduction time of the switching power supply in the next switching cycle.

3. The circuit according to claim 2, characterized in that The detection circuit comprises: a detection control component, a clock signal output component and a detection signal output component; The first input end of the detection control component is electrically connected to the output end of the pulse width modulation comparator, the second input end of the detection control component is electrically connected to the output end of the COT control circuit, the input end of the clock signal output component is electrically connected to the first output end or the second output end of the detection control component, the output end of the clock signal output component is electrically connected to the second input end of the regulating circuit and the first input end of the detection signal output component respectively, the second input end of the detection signal output component is used to access the power supply voltage, and the output end of the detection signal output component is electrically connected to the first input end of the regulating circuit; The detection control component is used to control the first output end of the detection control component to be electrically connected to the input end of the clock signal output component when the square wave signal indicates that the switching power supply is in a constant on-time control mode, and to obtain a first pulse width modulation signal according to the square wave signal and the first sub-control signal, and transmit the first pulse width modulation signal to the clock signal output component; The clock signal output component is used to transmit the first clock signal to the detection signal output component according to the first pulse width modulation signal; The detection signal output component is used to detect whether the switching power supply enters the minimum off time in the previous switching cycle according to the first clock signal, so as to obtain the first detection signal; or, The detection control component is used to control the second output end of the detection control component to be electrically connected to the input end of the clock signal output component when the square wave signal indicates that the switching power supply is in a constant off-time control mode, and to obtain a second pulse width modulation signal according to the square wave signal and the second sub-control signal, and transmit the second pulse width modulation signal to the clock signal output component; The clock signal output component is used to transmit the second clock signal to the detection signal output component according to the second pulse width modulation signal; The detection signal output component is used to detect whether the switching power supply enters the minimum on-time in the previous switching cycle according to the second clock signal, so as to obtain the second detection signal.

4. The circuit according to claim 3, characterized in that The detection control component includes: a first trigger; The set end of the first trigger is electrically connected to the output end of the pulse width modulation comparator, the reset end of the first trigger is electrically connected to the output end of the COT control circuit, and the forward output end or the reverse output end of the first trigger is electrically connected to the input end of the clock signal output component.

5. The circuit according to claim 3, characterized in that The clock signal output component includes: a first switch tube, a second switch tube and a first inverter; The first end of the second switch tube is electrically connected to the first output end or the second output end of the detection control component, the second end of the second switch tube is electrically connected to the first end of the first switch tube and the input end of the first inverter respectively, the second end of the first switch tube and the output end of the first inverter are both electrically connected to the first input end of the detection signal output component, and the control end of the first switch tube and the control end of the second switch tube are both used to access the switch signal, and the switch signal is used to control the conduction or shutdown of the switch tube.

6. The circuit according to claim 3, characterized in that The detection signal output component includes: a second inverter, a delay device and a second trigger; The input end of the second inverter and the input end of the delay device are both electrically connected to the output end of the clock signal output component, the output end of the second inverter is electrically connected to the clock input end of the second trigger, the output end of the delay device is electrically connected to the set input end of the second trigger, the data input end of the second trigger is used to access the power supply voltage, and the output end of the second trigger is electrically connected to the first input end of the regulation circuit.

7. The circuit according to claim 2, characterized in that The regulating circuit comprises: a counter; The clock input terminal of the counter is electrically connected to the second output terminal of the detection circuit, the count input terminal of the counter is electrically connected to the first output terminal of the detection circuit, and the output terminal of the counter is electrically connected to the input terminal of the COT control circuit; The counter is used to obtain the first clock signal from the detection circuit in the next switching cycle, and determine whether to count up the first value of the counter according to the first detection signal at the rising edge of the first clock signal to obtain the first adjustment signal; or, The counter is used to obtain the second clock signal from the detection circuit during the next switching cycle, and determine whether to count up the first value of the counter based on the second detection signal at the rising edge of the second clock signal to obtain the second adjustment signal.

8. The circuit according to claim 7, characterized in that The regulating circuit further includes: a frequency divider; The input end of the frequency divider is electrically connected to the second output end of the detection circuit, and the output end of the frequency divider is electrically connected to the clock input end of the counter; The frequency divider is used to divide the first clock signal to obtain a first frequency-divided clock signal, and transmit the first frequency-divided clock signal to the counter so that the counter obtains the first adjustment signal; or, The frequency divider is used to divide the second clock signal to obtain a second frequency-divided clock signal, and transmit the second frequency-divided clock signal to the counter so that the counter obtains the second adjustment signal.

9. The circuit according to any one of claims 2 to 8, characterized in that: The COT control circuit includes: a current output component, a capacitor and a timing comparator; The control end of the current output component is electrically connected to the output end of the regulating circuit, the output end of the current output component is electrically connected to the first plate of the capacitor, the positive phase input end of the timing comparator is electrically connected between the output end of the current output component and the first plate of the capacitor, the negative phase input end of the timing comparator is used to access a reference voltage, the reference voltage is related to the square wave signal, and the output end of the timing comparator is electrically connected to the first input end of the detection circuit; The current output component is used to output a first charging current corresponding to the first adjustment signal, and use the first charging current to charge the capacitor; The timing comparator is used to compare the voltage on the capacitor with the reference voltage to obtain the third sub-control signal; or, The current output component is used to output a second charging current corresponding to the second adjustment signal, and use the second charging current to charge the capacitor; The timing comparator is used to compare the voltage on the capacitor with the reference voltage to obtain the fourth sub-control signal.

10. The circuit according to claim 9, characterized in that The current output component includes: a current source, a first N-type crystal, a second N-type transistor, a first P-type transistor, a second P-type transistor, a plurality of N-type transistor groups and a plurality of third inverters; The output end of the current source is electrically connected to the drain end of the first N-type transistor, the gate end of the first N-type transistor is electrically connected to the gate end of the second N-type transistor and the first gate end of each N-type transistor group, the drain end of the first N-type transistor is electrically connected to the drain end of each N-type transistor group, the drain end of the first P-type transistor, the gate end of the first P-type transistor and the gate end of the second P-type transistor, the drain end of the second P-type transistor is electrically connected to the first plate of the capacitor, the source end of the first P-type transistor and the source end of the second P-type transistor are both used to access the power supply voltage, the second gate end of each N-type transistor group is electrically connected to the output end of each third inverter, the input end of each third inverter is electrically connected to the output end of the regulation circuit, and the source end of the first N-type transistor, the source end of the second N-type transistor and the source end of each N-type transistor group are all grounded.

11. The circuit according to claim 10, characterized in that The number of the first N-type transistors is the sum of the number of the second N-type transistors and the number of the multiple N-type transistor groups, the number of the first P-type transistors is equal to the number of the second P-type transistors, the number of the second N-type transistors is related to the longest duration of the on-time or off-time of the switching power supply, and the number of the multiple N-type transistor groups is related to the step size of the adjustment of the switching frequency.

12. A switching power supply, characterized in that: The switching power supply comprises: a high-side power transistor, a low-side power transistor, an inductor, an output capacitor, a first resistor, a second resistor, a pulse width modulation comparator, a controller, a loop control current output circuit and a detection and regulation circuit as described in any one of claims 1 to 11; The input end of the loop-controlled current output circuit is electrically connected to the second end of the inductor and the first plate of the output capacitor respectively, the second end of the inductor is also used to output the output voltage of the switching power supply, the output end of the loop-controlled current output circuit is electrically connected to the first end of the first resistor, the second end of the first resistor is electrically connected to the negative phase input end of the pulse width modulation comparator, the first end of the second resistor is used to detect the current of the inductor, the second end of the second resistor is electrically connected to the positive phase input end of the pulse width modulation comparator, and the output end of the pulse width modulation comparator is respectively connected to the first input end of the detection circuit and the first input end of the controller. The input end of the COT control circuit is electrically connected to the second input end of the controller, the first output end of the controller is electrically connected to the control end of the high-side power transistor, the second output end of the controller is electrically connected to the control end of the low-side power transistor, the first end of the high-side power transistor is used to access the input voltage of the switching power supply, the second end of the high-side power transistor is electrically connected to the first end of the low-side power transistor, the first end of the inductor is electrically connected between the second end of the high-side power transistor and the first end of the low-side power transistor, and the second end of the low-side power transistor and the second plate of the output capacitor are both grounded.

13. A chip, characterized in that: include: The detection and regulation circuit according to any one of claims 1 to 11, and / or the switching power supply according to claim 12.

14. An electronic device, characterized in that: include: The chip as claimed in claim 13.

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