Output overcurrent suppression device and output overcurrent protection method of DCDC converter

Abstract

The application provides an output overcurrent suppression device and an output overcurrent protection method of a DCDC converter, wherein a reverse input end of a comparator is electrically connected with an output current sampling signal, and a forward input end of the comparator is electrically connected with an output overcurrent threshold signal; a set end of an RS flip-flop is electrically connected with an output end of the comparator, and a reset end is electrically connected with a switch tube; a digital signal processor U3 receives an output overcurrent latching signal, executes an output overcurrent protection strategy, and outputs a reset signal at a suitable time according to a protection algorithm logic; a first end of the switch tube is electrically connected with the reset signal output by the signal processor, and a third end of the switch tube is electrically connected with the reset end of the RS flip-flop. According to the technical scheme, the instantaneous output overcurrent signal can be detected and locked, the DCDC current loop integration is reduced when the output overcurrent occurs, the power switch tube drive is blocked for N1 switching periods, the output current rising is suppressed, and the converter can work stably when the output current is not serious.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-power power conversion, and particularly relates to an output overcurrent suppression device and an output overcurrent protection method of a DCDC converter. BACKGROUND

[0002] The DCDC converter is a device for converting electric energy of one voltage value into electric energy of another voltage value in a direct-current circuit, and is widely applied in the fields of communication, vehicle-mounted, industrial automation, medical equipment and the like to provide stable and reliable power supply guarantee for these devices.

[0003] In actual application, the output overcurrent phenomenon is a problem that must be faced due to the changeable field conditions. The output overcurrent can be caused by load short circuit, load mutation, improper control strategy and the like, and once the output overcurrent occurs, the converter and subsequent circuit will be seriously damaged.

[0004] The traditional output overcurrent hardware protection circuit compares the output current sampling signal with a protection threshold, and the comparator output level is reversed when overcurrent occurs, so that the converter is protected by being shut down. When the output current is disturbed, the converter will be frequently protected, which affects the continuous and stable work of the converter. The traditional output overcurrent software protection strategy has a certain delay in sampling and protection due to the use of a digital scheme, and can only protect the output overcurrent with a long duration, and cannot protect the instantaneous output overcurrent. In order to solve the above problems, it is necessary to design a more efficient and reliable output overcurrent suppression device and protection strategy to improve the reliability of the DCDC converter.

[0005] Therefore, how to provide an output overcurrent suppression device and an output overcurrent protection method of a DCDC converter, which can detect and lock the instantaneous output overcurrent signal, reduce the DCDC current loop integration when the output overcurrent occurs, and lock the power switch driving for N1 switching periods to suppress the output current rise, and ensure the stable work of the converter when the output current is not serious, has become a technical problem to be solved. SUMMARY

[0006] The embodiment of the application provides an output overcurrent suppression device and an output overcurrent protection method of a DCDC converter, which can detect and lock the instantaneous output overcurrent signal, reduce the DCDC current loop integration when the output overcurrent occurs, and lock the power switch driving for N1 switching periods to suppress the output current rise, and ensure the stable work of the converter when the output current is not serious.

[0007] In one embodiment of the application, an output overcurrent suppression device of a DCDC converter is provided, and the suppression device comprises a comparator U1, an RS flip-flop U2, a digital signal processor U3 and a switch Q1.

[0008] The comparator U1 has its inverted input electrically connected to the output current sampling signal Iout, and has its non-inverted input electrically connected to the output over-current threshold signal Vocp, which is obtained by voltage division of the first resistor R1 and the second resistor R2.

[0009] The RS flip-flop U2 has both the set terminal S and the reset terminal R electrically connected to the low-level effective, and the set terminal S and the reset terminal R are electrically connected to the high-level through the fourth pull-up resistor R4 and the twelfth pull-up resistor R12, respectively. The set terminal S is electrically connected to the output terminal of the comparator U1, and the reset terminal R is electrically connected to the switch tube Q1.

[0010] The digital signal processor U3 is a carrier of the output over-current protection strategy, receives the output over-current latch signal Ocp, executes the output over-current protection strategy, and outputs the reset signal Krst at the appropriate time according to the protection algorithm logic.

[0011] The switch tube Q1 has its first end electrically connected to the reset signal Krst output by the signal processor U3, its second end electrically connected to the ground AGND, and its third end electrically connected to the reset terminal R of the RS flip-flop U2.

[0012] Further, the output terminal of the comparator U1 is electrically connected to the set terminal S of the RS flip-flop U2. When the output current sampling signal Iout is greater than the output over-current threshold signal Vocp, the output terminal of the comparator U1 is at low level, and the RS flip-flop U2 is set.

[0013] Further, the forward output terminal Q of the RS flip-flop U2 is voltage-divided by the sixth resistor 6 and the seventh resistor R7 connected to the ground GND, to obtain the output over-current latch signal Ocp, which is electrically connected to the digital signal processor U3. The reverse output terminal Q' of the RS flip-flop U2 is the off driving signal DrvOff, which is electrically connected to the power switch tube driving network, and is a continuous low-level signal during the output over-current latch, so that the power switch tube driving is continuously closed.

[0014] Further, when the reset signal Krst is at high level, the switch tube Q1 is turned on, and the reset terminal R of the RS flip-flop U2 is at low level, so that the RS flip-flop U2 is reset.

[0015] Further, the output current sampling network uses a current Hall sensor or a shunt resistor to convert the output current of the DCDC main power circuit into an output current sampling voltage signal Iout.

[0016] In still another embodiment of the present application, a method for output overcurrent protection of a DCDC converter is provided, based on any one of the above-mentioned output overcurrent suppression device of a DCDC converter, comprising:

[0017] S101, setting a switching cycle counter and an output overcurrent accumulation counter, the switching cycle counter is incremented by 1 in each switching cycle, and the output overcurrent latch signal Ocp is detected;

[0018] S102, if the output overcurrent latch signal Ocp is detected as high, it means that output overcurrent occurs, and the output overcurrent latch signal Ocp is in a continuous high level locking state, at this time the output overcurrent is in an undetectable state, entering S103; otherwise, if the output overcurrent latch signal Ocp is low, entering step S105;

[0019] S103, the output overcurrent accumulation counter is incremented by 1, and the output current is suppressed from two aspects, one aspect is to reduce the DCDC current loop integral variable, the reduction method can be 1 / K1 of the original, the other aspect is to block the power switch tube drive for N1 switching cycles; wherein the coefficient K1 is a natural number, the value is 2-10, the coefficient N1 is a natural number, the value is 3-6; entering S104;

[0020] S104, setting the reset signal Krst to high level, resetting the RS flip-flop U2, so that the blocking of the power switch tube drive is released, and the locking state of the output overcurrent latch signal Ocp is released, and the output overcurrent returns to a detectable state;

[0021] S105, if the value of the output overcurrent accumulation counter is greater than N2, and the switching cycle counter is less than N3, an output overcurrent fault is reported, and the DCDC converter is shut down for protection; otherwise, the output overcurrent accumulation counter and the switching cycle counter are cleared; wherein the coefficients N2 and N3 are natural numbers, and N2>N3.

[0022] Further, the method comprises:

[0023] When the DCDC converter is working normally, the digital signal processor U3 sets the reset signal Krst to low level, then the switch tube Q1 is cut off, the reset end R of the RS flip-flop U2 is pulled up to high level, and the output overcurrent is in a detectable state;

[0024] When the output current sampling value is higher than the output overcurrent threshold value, the comparator U1 outputs low level, the RS flip-flop U2 is set and locked, the positive output end Q of the RS flip-flop U2 is in a continuous high level, and the negative output end Q' is in a continuous low level, continuously closing the power switch tube drive;

[0025] When the positive output end Q of the RS flip-flop U2 is continuously high, in order to inhibit the output overcurrent, the digital signal processor U3 reduces the DCDC current loop integral variable on one hand and controls the number of switch periods of the power switch tube drive to be closed on the other hand.

[0026] Further, the method comprises:

[0027] When the digital signal processor U3 detects that the power switch tube drive is closed for N1 switch periods, the reset signal Krst is set to high, the switch tube Q1 is turned on, the reset end R of the RS flip-flop U2 is pulled to low, the RS flip-flop U2 is reset, and the power switch tube drive is enabled again.

[0028] The digital signal processor U3 sets the reset signal Krst to low in the next switch period, so that the output overcurrent is restored to the detectable state.

[0029] Further, the method comprises:

[0030] A switch period counter and an output overcurrent accumulation counter are set in the digital signal processor U3, in each switch period, the switch period counter is added by 1, and the output overcurrent accumulation counter is added by 1 when the positive output end Q of the RS flip-flop U2 is high.

[0031] If the value of the output overcurrent accumulation counter is greater than N2 and the switch period counter is less than N3, an output overcurrent fault is reported, the DCDC converter is switched to a fault state and is protected by stopping, otherwise the output overcurrent accumulation counter and the switch period counter are cleared.

[0032] The present application has the following beneficial effects:

[0033] As can be seen from the above scheme, the present application provides a DCDC converter output overcurrent inhibition device and an output overcurrent protection method, the reverse input end of the comparator is electrically connected with the output current sampling signal, the positive input end of the comparator is electrically connected with the output overcurrent threshold signal; the electrical characteristics of the set end and the reset end of the RS flip-flop are low effective, the set end is electrically connected with the output end of the comparator, and the reset end is electrically connected with the switch tube; the digital signal processor U3 receives the output overcurrent latching signal, executes the output overcurrent protection strategy, and outputs the reset signal at a suitable time according to the protection algorithm logic; the first end of the switch tube is electrically connected with the reset signal output by the signal processor, and the third end of the switch tube is electrically connected with the reset end of the RS flip-flop. The technical scheme of the present application can detect and lock the instantaneous output overcurrent signal, reduce the DCDC current loop integral when the output overcurrent occurs, lock the power switch tube drive for N1 switch periods, inhibit the output current from rising, and ensure the stable operation of the converter when the output current is not serious. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 This diagram illustrates a circuit diagram of an output overcurrent suppression device for a DC-DC converter according to an embodiment of the present invention.

[0035] Figure 2 This is a flowchart illustrating an output overcurrent protection method for a DC-DC converter according to an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0037] like Figure 1 As shown, Figure 1 This is a schematic diagram of an output overcurrent suppression device circuit for a DC-DC converter according to an embodiment of the present invention.

[0038] Figure 1 In the present invention, an output overcurrent suppression device for a DC-DC converter is disclosed, the suppression device comprising: a comparator U1, an RS flip-flop U2, a digital signal processor U3, and a switching transistor Q1;

[0039] The comparator U1 has its inverting input electrically connected to the output current sampling signal Iout, and its non-inverting input electrically connected to the output overcurrent threshold signal Vocp. The output overcurrent threshold signal Vocp is obtained by voltage division by the first resistor R1 and the second resistor R2. The values ​​of R1 and R2 can be adjusted as needed to change the output overcurrent threshold.

[0040] The RS flip-flop U2 has a set terminal S and a reset terminal R that are both active low. The set terminal S and the reset terminal R are connected to a high level through the fourth pull-up resistor R4 and the twelfth pull-up resistor R12, respectively. The set terminal S is electrically connected to the output terminal of the comparator U1, and the reset terminal R is electrically connected to the switching transistor Q1.

[0041] The digital signal processor U3 serves as the carrier of the output overcurrent protection strategy. It receives the output overcurrent latch signal Ocp, executes the output overcurrent protection strategy, and outputs the reset signal Krst at an appropriate time according to the protection algorithm logic.

[0042] The switch tube Q1, first end and the reset signal Krst output by the signal processor U3 are electrically connected, the second end of the switch tube Q1 is grounded AGND, and the third end of the switch tube Q1 is electrically connected with the reset end R of the RS flip-flop U2.

[0043] In the embodiment of the present application, the DCDC converter needs to use a digital control mode, which is applicable to various DCDC power topology types, including half-bridge three-level converter, LLC converter, BUCK converter, etc.

[0044] In one embodiment of the present application, the output end of the comparator U1 is electrically connected with the set end S of the RS flip-flop U2, when the output current sampling signal Iout is greater than the output overcurrent threshold signal Vocp, the output end of the comparator U1 is low, and the RS flip-flop U2 is set.

[0045] In one embodiment of the present application, the forward output end Q of the RS flip-flop U2 is divided by the sixth resistor 6 and the seventh resistor R7 connected to the ground GND to obtain an output overcurrent latching signal Ocp, the output overcurrent latching signal Ocp is electrically connected to the digital signal processor U3; the reverse output end Q' of the RS flip-flop U2 is the off drive signal DrvOff, the off drive signal DrvOff is electrically connected to the power switch tube drive network, and is a continuous low level signal during output overcurrent latching, so that the power switch tube drive is continuously closed.

[0046] In another embodiment of the present application, when the reset signal Krst is high, the switch tube Q1 is turned on, and the reset end R of the RS flip-flop U2 is low, so that the RS flip-flop U2 is reset.

[0047] In another embodiment of the present application, the output current sampling network uses a current Hall sensor or a shunt resistor to convert the output current of the DCDC main power circuit into an output current sampling voltage signal Iout.

[0048] Figure 1 In one embodiment of the present application, in the circuit of the output overcurrent suppression device of the DCDC converter, the eighth resistor R8 and the first capacitor C1 are high-frequency filtering structures of the input current sampling signal, the second capacitor C2 is a high-frequency filtering capacitor of the reset end R of the RS flip-flop U2, and the third resistor R3, the fifth resistor R5, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11 and the fourteenth resistor R14 are device matching resistors.

[0049] As shown in Figure 2 , Figure 2 a flow chart of a DCDC converter output overcurrent protection method according to an embodiment of the present application.

[0050] Figure 2 In one embodiment, the method comprises:

[0051] S101, set a switch cycle counter and an output overcurrent accumulation counter, the switch cycle counter is added by 1 in each switch cycle, and detection is carried out on the output overcurrent latching signal Ocp;

[0052] S102, if the output overcurrent latching signal Ocp is detected as a high level, it is indicated that output overcurrent occurs, and the output overcurrent latching signal Ocp is in a sustained high level locking state, at this time, the output overcurrent is in an undetectable state, and S103 is entered; otherwise, if the output overcurrent latching signal Ocp is a low level, S105 is entered;

[0053] S103, the output overcurrent accumulation counter is added by 1, and the output current is suppressed from two aspects, one aspect is that the DCDC current loop integral variable is reduced, and the reduction mode can be 1 / K1 of the original, and the other aspect is that the power switch tube drive is blocked for N1 switch cycles; wherein the coefficient K1 is a natural number, and the value is 2-10, the coefficient N1 is a natural number, and the value is 3-6; S104 is entered;

[0054] S104, the reset signal Krst is set to a high level, the RS flip-flop U2 is reset, so that the blocking of the power switch tube drive is released, and the locking state of the output overcurrent latching signal Ocp is released, and the output overcurrent is restored to a detectable state;

[0055] S105, if the value of the output overcurrent accumulation counter is greater than N2, and the switch cycle counter is less than N3, an output overcurrent fault is reported, and the DCDC converter is shut down for protection; otherwise, the output overcurrent accumulation counter and the switch cycle counter are cleared; wherein the coefficient N2 and the coefficient N3 are natural numbers, and N2>N3.

[0056] In one embodiment of the application, the method comprises:

[0057] When the DCDC converter works normally, the digital signal processor U3 sets the reset signal Krst to a low level, the switch tube Q1 is cut off, the reset end R of the RS flip-flop U2 is pulled up to a high level, and the output overcurrent is in a detectable state;

[0058] When the output current sampling value is higher than the output overcurrent threshold value, the comparator U1 outputs a low level, the RS flip-flop U2 is set and locked, the positive output end Q of the RS flip-flop U2 is a sustained high level, the reverse output end Q' is a sustained low level, and the power switch tube drive is continuously closed;

[0059] When the positive output end Q of the RS flip-flop U2 is continuously high, in order to inhibit the output overcurrent, the digital signal processor U3 reduces the DCDC current loop integral variable on one hand and controls the number of switch periods of the power switch tube drive to be closed on the other hand.

[0060] In another embodiment of the present application, the method comprises:

[0061] When the digital signal processor U3 detects that the power switch tube drive is closed for N1 switch periods, the reset signal Krst is set to high, the switch tube Q1 is turned on, the reset end R of the RS flip-flop U2 is pulled to low, the RS flip-flop U2 is reset, and the power switch tube drive is enabled again.

[0062] The digital signal processor U3 sets the reset signal Krst to low in the next switch period, so that the output overcurrent is restored to the detectable state.

[0063] In another embodiment of the present application, the method comprises:

[0064] A switch period counter and an output overcurrent accumulation counter are set in the digital signal processor U3, in each switch period, the switch period counter is increased by 1, and the output overcurrent accumulation counter is increased by 1 when the positive output end Q of the RS flip-flop U2 is high.

[0065] If the value of the output overcurrent accumulation counter is greater than N2 and the switch period counter is less than N3, an output overcurrent fault is reported, the DCDC converter is switched to a fault state and is protected by shutdown, otherwise the output overcurrent accumulation counter and the switch period counter are cleared.

[0066] In the embodiment of the present application, the output overcurrent inhibition device and the output overcurrent protection method of the DCDC converter, the reverse input end of the comparator is electrically connected with the output current sampling signal, the positive input end of the comparator is electrically connected with the output overcurrent threshold signal; the electrical characteristics of the set end and the reset end of the RS flip-flop are low effective, the set end is electrically connected with the output end of the comparator, and the reset end is electrically connected with the switch tube; the digital signal processor U3 receives the output overcurrent latch signal, executes the output overcurrent protection strategy, and outputs the reset signal at a suitable time according to the protection algorithm logic; the first end of the switch tube is electrically connected with the reset signal output by the signal processor, and the third end of the switch tube is electrically connected with the reset end of the RS flip-flop. The technical scheme of the present application can detect and lock the instantaneous output overcurrent signal, reduce the DCDC current loop integral when the output overcurrent occurs, block the power switch tube drive for N1 switch periods, inhibit the output current from rising, and ensure the stable operation of the converter when the output current is not serious.

[0067] The DCDC converter output overcurrent suppression device and output overcurrent protection strategy can detect and lock the instantaneous output overcurrent signal, reduce the DCDC current loop integration on one hand, and lock the power switch driving for N1 switch cycles on the other hand to suppress the output current rise, and ensure the stable operation of the converter when the output current is not serious. The technical scheme of the present application adopts software to count the output overcurrent times in the preset switch cycle, and reports the output overcurrent fault when the output overcurrent exceeds the preset threshold, so as to make the converter stop and protect, and effectively avoid the damage or accident of the converter circuit device.

[0068] The above is the preferred embodiment of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present application.

Claims

1. A method of output overcurrent protection for a DCDC converter, comprising an output overcurrent suppression device, the suppression device comprising: The comparator U1, the RS flip-flop U2, the digital signal processor U3 and the switch tube Q1, the reverse input end of the comparator U1 is electrically connected with the output current sampling signal Iout, the forward input end of the comparator U1 is electrically connected with the output overcurrent threshold signal Vocp, and the output overcurrent threshold signal Vocp is obtained by voltage division of the first resistor R1 and the second resistor R2;The electrical characteristics of the set end S and the reset end R of the RS flip-flop U2 are both low-level effective, the set end S and the reset end R are connected to high level through the fourth pull-up resistor R4 and the twelfth pull-up resistor R12 respectively, the set end S is electrically connected with the output end of the comparator U1, and the reset end R is electrically connected with the switch tube Q1;The digital signal processor U3 is the carrier of the output overcurrent protection strategy, receives the output overcurrent latch signal Ocp, executes the output overcurrent protection strategy, and outputs the reset signal Krst at a suitable opportunity according to the protection algorithm logic;The first end of the switch tube Q1 is electrically connected with the reset signal Krst output by the signal processor U3, the second end of the switch tube Q1 is connected to the ground AGND, the third end of the switch tube Q1 is electrically connected with the reset end R of the RS flip-flop U2, and the protection method comprises: S101, a switch cycle counter and an output overcurrent accumulation counter are set, the switch cycle counter is incremented by 1 in each switch cycle, and the output overcurrent latch signal Ocp is detected; S102, if the output overcurrent latch signal Ocp is detected as high level, it indicates that output overcurrent occurs, and the output overcurrent latch signal Ocp is in a continuous high level locking state, at this time, the output overcurrent is in an undetectable state, and S103 is entered;Otherwise, if the output overcurrent latch signal Ocp is low level, S105 is entered; S103, the output overcurrent accumulation counter is incremented by 1, and the output current is suppressed from two aspects, one aspect is that the DCDC current loop integral variable is reduced, and the reduction mode is 1 / K1 of the original, the other aspect is that the power switch tube drive is blocked for N1 switch cycles;Wherein, the coefficient K1 is a natural number, and the value is 2-10, the coefficient N1 is a natural number, and the value is 3-6;S104 is entered; S104, the reset signal Krst is set to high level, the RS flip-flop U2 is reset, so that the power switch tube drive is unblocked, and the output overcurrent latch signal Ocp is unblocked, and the output overcurrent is restored to a detectable state; S105, if the value of the output overcurrent accumulation counter is greater than N2, and the switch cycle counter is less than N3, an output overcurrent fault is reported, and the DCDC converter is shut down for protection;Otherwise, the output overcurrent accumulation counter and the switch cycle counter are cleared;Wherein, the coefficients N2 and N3 are natural numbers, and N2>N3.

2. The output overcurrent protection method of a DCDC converter according to claim 1, characterized in that, The method comprises: When the DCDC converter works normally, the digital signal processor U3 sets the reset signal Krst to low level, the switch tube Q1 is cut off, the reset end R of the RS flip-flop U2 is pulled up to high level, and the output overcurrent is in a detectable state. When the output current sample value is higher than the output over-current threshold value, the comparator U1 outputs a low level, the RS flip-flop U2 is set and locked, the positive output end Q of the RS flip-flop U2 is a continuous high level, and the negative output end Q' is a continuous low level, thereby continuously closing the power switch tube drive; When the positive output end Q of the RS flip-flop U2 is a continuous high level, in order to inhibit the output over-current, the digital signal processor U3 reduces the DCDC current loop integral variable on one hand, and controls the number of switch cycles of the power switch tube drive to be closed on the other hand.

3. The output overcurrent protection method of a DCDC converter according to claim 1, characterized in that, The method comprises: When the digital signal processor U3 detects that the power switch tube drive is closed for N1 switch cycles, the reset signal Krst is set to a high level, the switch tube Q1 is turned on, the reset end R of the RS flip-flop U2 is pulled to a low level, the RS flip-flop U2 is reset, and the power switch tube drive is enabled again; The digital signal processor U3 sets the reset signal Krst to a low level in the next switch cycle, so that the output over-current is restored to a detectable state.

4. The output overcurrent protection method of a DCDC converter according to claim 1, characterized in that, The method comprises: A switch cycle counter and an output over-current accumulation counter are set in the digital signal processor U3, in each switch cycle, the switch cycle counter is increased by 1, and the output over-current accumulation counter is increased by 1 when the positive output end Q of the RS flip-flop U2 is a high level; If the value of the output over-current accumulation counter is greater than N2 and the switch cycle counter is less than N3, an output over-current fault is reported, the DCDC converter is switched to a fault state and is protected by being shut down, otherwise, the output over-current accumulation counter and the switch cycle counter are cleared.

5. The output overcurrent protection method of a DCDC converter according to claim 1, characterized in that, The output end of the comparator U1 is electrically connected to the set end S of the RS flip-flop U2, when the output current sample signal Iout is greater than the output over-current threshold value signal Vocp, the output end of the comparator U1 is a low level, and the RS flip-flop U2 is set.

6. The output overcurrent protection method of a DCDC converter according to claim 1, wherein, The positive output end Q of the RS flip-flop U2 is divided by a sixth resistor R6 and a seventh resistor R7 connected to the ground GND to obtain an output over-current latching signal Ocp, the output over-current latching signal Ocp is electrically connected to the digital signal processor U3, and the negative output end Q' of the RS flip-flop U2 is a drive-off signal DrvOff, the drive-off signal DrvOff is electrically connected to a power switch tube drive network, and is a continuous low level signal during output over-current latching, so that the power switch tube drive is continuously closed.

7. The output overcurrent protection method of a DCDC converter according to claim 1, characterized in that, When the reset signal Krst is a high level, the switch tube Q1 is turned on, and the reset end R of the RS flip-flop U2 is a low level, so that the RS flip-flop U2 is reset.

8. The output overcurrent protection method of a DCDC converter according to claim 1, characterized in that, The output current sample signal is converted from the output current of a DCDC main power circuit by using a current Hall sensor or a shunt resistor.

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