Broadband low-noise amplifier based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process ka waveband

Abstract

The invention discloses a broadband low-noise amplifier based on a CMOS (complementary metal oxide semiconductor) process ka wave band, which belongs to the field of broadband low-noise amplifiers in radio frequency transceiving and communication systems and comprises an input matching circuit, a first-stage amplifying circuit, an inter-stage matching circuit, a second-stage amplifying circuit and an output matching circuit. The input matching circuit is connected with the input end of the first-stage amplifying circuit, the output end of the first-stage amplifying circuit is connected with the input side of the inter-stage matching circuit, the output side of the inter-stage matching circuit is connected with the second-stage amplifying circuit, and the second-stage amplifying circuit is connected with the output matching circuit. The synthesis loss is reduced. And meanwhile, power synthesis and output matching are realized, and the chip area is reduced. The broadband characteristic is achieved, and the high integration level is achieved. The low-noise amplifier has the advantages of being wide in frequency band, high in gain and low in noise. The method has a good application prospect in a satellite communication system and millimeter wave communication.

Description

Technical Field

[0001] The invention relates to the field of wideband low noise amplifiers in radio frequency transceiver and communication systems, in particular to a wideband low noise amplifier based on CMOS process Ka band. Background Art

[0002] With the development of 5G wireless communication systems, millimeter wave receivers have received extensive attention from academia and industry. Ka-band applications such as 5G communications, astronomical detection, and automotive radar rely on the performance of broadband millimeter wave front-ends. As the first active module of the receiver front end, the low noise amplifier LNA is a key component because it is responsible for amplifying the signal from the antenna and the introduced noise needs to be as small as possible. Its noise figure NF, gain, and bandwidth characteristics directly affect the sensitivity of the receiver. Compared with narrowband low-band wireless networks, broadband low-band wireless networks have received extensive attention due to the inspiration of multi-band, multi-standard, ultra-wideband UWB radios.

[0003] The existing low noise amplifier LNA has a narrow frequency band and a low gain, and cannot meet the needs of the existing market. Summary of the invention

[0004] With regard to the above problems existing in the prior art, the object of the present invention is to provide a wideband low noise amplifier based on CMOS process ka-band to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A wide-band low-noise amplifier based on CMOS process ka band, comprising an input matching circuit, a first-stage amplification circuit, an inter-stage matching circuit, a second-stage amplification circuit and an output matching circuit;

[0007] The input matching circuit includes a transformer T1, one end of the input side of the transformer T1 is connected to the radio frequency signal input interface RFin, and the other end of the input side of the transformer T1 is grounded;

[0008] The first-stage amplifier circuit includes an NMOS tube M1 and an NMOS tube M2; the gate of the NMOS tube M1 is connected to one end of the output side of the transformer T1 in the input matching circuit; the gate of the NMOS tube M2 is connected to the other end of the output side of the transformer T1 in the input matching circuit;

[0009] The gate of the NMOS tube M1 is connected to one end of the capacitor Cn1, and the other end of the capacitor Cn1 is connected to the drain of the NMOS tube M2;

[0010] The gate of the NMOS tube M2 is connected to one end of the capacitor Cn2, and the other end of the capacitor Cn2 is connected to the drain of the NMOS tube M1;

[0011] The inter-stage matching circuit includes a transformer T2, one end of the input side of the transformer T2 is connected to the drain of the NMOS tube M1 in the first-stage amplifier circuit, and the other end of the input side of the transformer T2 is connected to the drain of the NMOS tube M2 in the first-stage amplifier circuit;

[0012] The second-stage amplifier circuit includes an NMOS tube M3 and an NMOS tube M4; the gate of the NMOS tube M3 is connected to one end of the output side of the transformer T2 in the inter-stage matching circuit; the gate of the NMOS tube M4 is connected to the other end of the output side of the transformer T2 in the inter-stage matching circuit;

[0013] The gate of the NMOS tube M3 is connected to one end of the capacitor Cn3, and the other end of the capacitor Cn3 is connected to the drain of the NMOS tube M4;

[0014] The gate of the NMOS tube M4 is connected to one end of the capacitor Cn4, and the other end of the capacitor Cn4 is connected to the drain of the NMOS tube M3;

[0015] The output matching circuit includes a transformer T3, one end of the input side of the transformer T3 is connected to the drain of the NMOS tube M3 in the second stage amplifier circuit, and the other end of the input side of the transformer T3 is connected to the drain of the NMOS tube M4 in the second stage amplifier circuit;

[0016] One end of the input side of the transformer T3 is connected to the radio frequency signal output interface RFout, and the other end of the input side of the transformer T3 is grounded.

[0017] As a further solution of the present invention: the tap on the output side of the transformer T1 is connected to the bias voltage Vb.

[0018] As a further solution of the present invention: the tap on the input side of the transformer T2 is connected to the power supply voltage Vdd; the tap on the output side of the transformer T2 is connected to the bias voltage Vb.

[0019] As a further solution of the present invention: the tap on the input side of the transformer T3 is connected to the power supply voltage Vdd.

[0020] As a further solution of the present invention: the source of the NMOS tube M1 and the source of the NMOS tube M2 in the first-stage amplifier circuit are both grounded.

[0021] As a further solution of the present invention: the source of the NMOS tube M3 and the source of the NMOS tube M4 in the second-stage amplifier circuit are both grounded.

[0022] As a further solution of the present invention: in the input matching circuit, the two ends of the input side of the transformer T1 are connected in parallel with the two ends of the capacitor C1; the two ends of the output side of the transformer T1 are connected in parallel with the two ends of the capacitor C2.

[0023] As a further solution of the present invention: in the inter-stage matching circuit, capacitors C3 are connected in parallel at both ends of the input side of the transformer T2; capacitors C4 are connected in parallel at both ends of the output side of the transformer T2.

[0024] As a further solution of the present invention: in the output matching circuit, capacitors C5 are connected in parallel at both ends of the input side of the transformer T3; capacitors C6 are connected in parallel at both ends of the output side of the transformer T3.

[0025] As a further solution of the present invention: the power supply voltage Vdd is 1V, and the bias voltage Vb is 0.6V.

[0026] As a further solution of the present invention: the capacitors Cn1, Cn2, Cn3 and Cn4 are all neutral capacitors, which are 15fF, and the model parameters of the NMOS tubes M1, M2, M3 and M4 are the same.

[0027] As a further solution of the present invention:

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention reduces synthesis loss. Power synthesis and output matching are achieved at the same time, reducing the chip area. The present invention is a wideband low-noise amplifier in the Ka band based on CMOS technology. The frequency band of the present invention covers the entire Ka band, achieves good performance indicators in the frequency range of 20GHz-40GHz, achieves broadband characteristics, and has a high degree of integration using CMOS technology. The present invention uses 65nm CMOS technology to realize a low-noise amplifier that works in the Ka band. A two-stage differential common source topology structure is adopted, combined with the input, output, inter-stage transformer matching network and neutralizing capacitor technology of embedded capacitors, and the low-noise amplifier realized has the characteristics of wideband, high gain and low noise. It has good application prospects in satellite communication systems and millimeter wave communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The present invention is a schematic diagram of the circuit structure of a wide-band low-noise amplifier based on the CMOS process Ka band disclosed in an embodiment.

[0031] Figure 2 The present invention is a schematic diagram of the structure of the first-stage amplification circuit of a wide-band low-noise amplifier based on the CMOS process Ka-band disclosed in an embodiment.

[0032] Figure 3 The present invention is a schematic diagram of a small signal equivalent circuit of a wide-band low-noise amplifier based on the CMOS process Ka-band and having a neutralizing capacitor differential common source structure disclosed in an embodiment.

[0033] Figure 4 The present invention discloses a layout of an input matching circuit in a wide-band low-noise amplifier based on the CMOS process Ka band according to an embodiment.

[0034] Figure 5 The present invention discloses a layout of an inter-stage matching circuit in a wide-band low-noise amplifier based on the CMOS process Ka-band.

[0035] Figure 6 The present invention discloses a layout of an output matching circuit in a wide-band low-noise amplifier based on the ka-band of a CMOS process according to an embodiment.

[0036] Figure 7 This is a diagram of post-simulation results of a wide-band low-noise amplifier based on the CMOS process Ka-band disclosed in an embodiment. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", and "connected" should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, or an indirect connection through an intermediate medium, or the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] At present, in terms of LNA process manufacturing, LNAs manufactured using advanced complementary metal oxide semiconductor (CMOS) processes have performance indicators similar to those of bipolar complementary metal oxide semiconductor (BiCMOS) processes using silicon germanium (SiGe), but the cost of CMOS processes is lower. Therefore, LNAs using CMOS technology have significant advantages.

[0040] See also Figure 1-7 , a wide-band low-noise amplifier based on CMOS process ka band, comprising an input matching circuit, a first-stage amplifying circuit, an inter-stage matching circuit, a second-stage amplifying circuit and an output matching circuit;

[0041] The input matching circuit includes a transformer T1, a capacitor C1 and a capacitor C2, one end of the input side of the transformer T1 is connected to the radio frequency signal input interface RFin, and the other end of the input side of the transformer T1 is grounded;

[0042] Capacitor C1 is connected in parallel to both ends of the input side of transformer T1; capacitor C2 is connected in parallel to both ends of the output side of transformer T1;

[0043] The tap on the output side of transformer T1 is connected to bias voltage Vb;

[0044] The first-stage amplifier circuit includes an NMOS tube M1 and an NMOS tube M2; the gate of the NMOS tube M1 is connected to one end of the output side of the transformer T1 in the input matching circuit; the gate of the NMOS tube M2 is connected to the other end of the output side of the transformer T1 in the input matching circuit;

[0045] The gate of the NMOS tube M1 is connected to one end of the capacitor Cn1, and the other end of the capacitor Cn1 is connected to the drain of the NMOS tube M2;

[0046] The gate of the NMOS tube M2 is connected to one end of the capacitor Cn2, and the other end of the capacitor Cn2 is connected to the drain of the NMOS tube M1;

[0047] The source of the NMOS tube M1 and the source of the NMOS tube M2 are both grounded;

[0048] In the first stage amplifier circuit, the gate of NMOS1 (M1) is connected to the drain of NMOS2 through a capacitor, and the gate of NMOS2 (M2) is connected to the drain of NMOS1 (M1) through a capacitor. The output end is located at the drain of NMOS1 (M1) and NMOS2 (M2), and is connected to the inter-stage matching circuit. The voltage bias Vb of the input matching circuit is located at the rear tap of the input transformer, providing a voltage bias for the gate of the NMOS tube, and the source of the differential pair is connected to the source degenerate ground.

[0049] The inter-stage matching circuit includes a transformer T2, a capacitor C3 and a capacitor C4, one end of the input side of the transformer T2 is connected to the drain of the NMOS tube M1 in the first-stage amplifier circuit, and the other end of the input side of the transformer T2 is connected to the drain of the NMOS tube M2 in the first-stage amplifier circuit;

[0050] Capacitor C3 is connected in parallel to both ends of the input side of transformer T2; capacitor C4 is connected in parallel to both ends of the output side of transformer T2;

[0051] The tap on the input side of the transformer T2 is connected to the power supply voltage Vdd; the tap on the output side of the transformer T2 is connected to the bias voltage Vb;

[0052] The second-stage amplifier circuit includes an NMOS tube M3 and an NMOS tube M4; the gate of the NMOS tube M3 is connected to one end of the output side of the transformer T2 in the inter-stage matching circuit; the gate of the NMOS tube M4 is connected to the other end of the output side of the transformer T2 in the inter-stage matching circuit;

[0053] The gate of the NMOS tube M3 is connected to one end of the capacitor Cn3, and the other end of the capacitor Cn3 is connected to the drain of the NMOS tube M4;

[0054] The gate of the NMOS tube M4 is connected to one end of the capacitor Cn4, and the other end of the capacitor Cn4 is connected to the drain of the NMOS tube M3;

[0055] The source of the NMOS tube M3 and the source of the NMOS tube M4 are both grounded;

[0056] The output matching circuit includes a transformer T3, a capacitor C5 and a capacitor C6. One end of the input side of the transformer T3 is connected to the drain of the NMOS tube M3 in the second-stage amplifier circuit, and the other end of the input side of the transformer T3 is connected to the drain of the NMOS tube M4 in the second-stage amplifier circuit.

[0057] Capacitor C5 is connected in parallel to both ends of the input side of transformer T3; capacitor C6 is connected in parallel to both ends of the output side of transformer T3;

[0058] One end of the input side of the transformer T3 is connected to the radio frequency signal output interface RFout, and the other end of the input side of the transformer T3 is grounded;

[0059] The tap on the input side of the transformer T3 is connected to the power supply voltage Vdd;

[0060] Both the first-stage amplifier circuit and the second-stage amplifier circuit adopt a differential common source structure, which effectively suppresses common-mode noise, and the two-stage cascade can further improve the gain. A neutralizing capacitor Cn is introduced to effectively reduce the Miller effect generated by the gate-drain capacitance of the transistor and improve the stability of the entire circuit.

[0061] like Figure 2-3 As shown, compared with the conventional common source structure, the amplifier circuit of the present invention has a parasitic capacitor C between the gate and drain of the transistor. gd , the circuit will form negative feedback (Miller effect). The formation of negative feedback reduces the isolation and power gain of the circuit. In order to offset the influence of the Miller effect, a differential common source structure with a neutralizing capacitor can be developed at low power consumption to meet the requirements of input impedance matching and low noise digital index at low power consumption. Where Cn is the neutralizing capacitor, C GS , C DG , C DB are the gate, drain and drain parasitic capacitance of the transistor respectively, R gis the gate parasitic resistance, R d is the equivalent resistance between the drain and the source, g m For the transconductance, we get the Y parameter:

[0062]

[0063] The stability coefficient K and maximum gain G of the circuit of the wideband low noise amplifier in the ka band of the CMOS process are further obtained. max :

[0064]

[0065] Under the condition of circuit stability, Vdd is the power supply voltage of 1V, Vb is the bias voltage of 0.6V, Cn is the neutral capacitance of 15fF, and the NMOS tube parameters are the same: the single gate width is 3μm, and the gate index is 20.

[0066] like Figure 4-6 As shown, they are the layout of the input matching circuit, the layout of the inter-stage matching circuit and the layout of the output matching circuit in the low noise amplifier, and the layout is designed based on CMOS technology.

[0067] A wideband low noise amplifier based on CMOS process ka band is composed of five cascaded parts, namely input matching circuit, first stage amplification circuit, interstage matching circuit, second stage amplification circuit and output matching circuit. The input matching circuit, interstage matching circuit and output matching circuit are composed of differential transformer and coupling capacitor; the first stage amplification circuit and the second stage amplification output circuit both have two NMOS tubes to form a differential common source structure, and the NMOS tube parameters are single gate width of 3μm, gate index of 20, Cn is neutral capacitance of 15fF; the secondary tap of the input matching transformer is connected to bias voltage Vb, the primary tap of the interstage matching transformer is connected to working voltage Vdd, the secondary tap is connected to bias voltage Vb, and the primary tap of the output matching transformer is connected to working voltage Vdd.

[0068] The present invention reduces synthesis loss, realizes power synthesis and output matching, and reduces chip area.

[0069] The invention is a wideband low noise amplifier in the Ka band based on CMOS technology. The frequency band of the invention covers the entire Ka band, achieves good performance indicators in the frequency range of 20GHz-40GHz, achieves broadband characteristics, and has a high degree of integration using CMOS technology.

[0070] Under the working voltage of 1V and the bias voltage of 0.6V, the maximum S21 gain of the present invention is 21.2dB, the 3dB bandwidth frequency range is 19.5GHz-41.5GHz, the bandwidth reaches 73%, and the entire Ka band is covered at the same time; the minimum noise factor NF of the low noise amplifier of the present invention is 2.8dB, and the noise factor in the entire frequency band is within 4.4dB. The present invention uses 65nm CMOS technology to realize a low noise amplifier working in the Ka band. The low noise amplifier realized by adopting a two-stage differential common source topology structure, combined with the input, output, interstage transformer matching network and neutralizing capacitor technology of embedded capacitors, has the characteristics of wide bandwidth, high gain and low noise. It has good application prospects in satellite communication systems and millimeter wave communications.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive from any point of view. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention, and any reference numerals in the claims should not be considered as limiting the claims involved.

[0072] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A wideband low noise amplifier based on CMOS process ka-band, characterized in that: It includes an input matching circuit, a first-stage amplifying circuit, an inter-stage matching circuit, a second-stage amplifying circuit and an output matching circuit; The input matching circuit includes a transformer T1, one end of the input side of the transformer T1 is connected to the radio frequency signal input interface RFin, and the other end of the input side of the transformer T1 is grounded; The first-stage amplifier circuit includes an NMOS tube M1 and an NMOS tube M2; the gate of the NMOS tube M1 is connected to one end of the output side of the transformer T1 in the input matching circuit; the gate of the NMOS tube M2 is connected to the other end of the output side of the transformer T1 in the input matching circuit; The gate of the NMOS tube M1 is connected to one end of the capacitor Cn1, and the other end of the capacitor Cn1 is connected to the drain of the NMOS tube M2; The gate of the NMOS tube M2 is connected to one end of the capacitor Cn2, and the other end of the capacitor Cn2 is connected to the drain of the NMOS tube M1; The inter-stage matching circuit includes a transformer T2, one end of the input side of the transformer T2 is connected to the drain of the NMOS tube M1 in the first-stage amplifier circuit, and the other end of the input side of the transformer T2 is connected to the drain of the NMOS tube M2 in the first-stage amplifier circuit; The second-stage amplifier circuit includes an NMOS tube M3 and an NMOS tube M4; the gate of the NMOS tube M3 is connected to one end of the output side of the transformer T2 in the inter-stage matching circuit; the gate of the NMOS tube M4 is connected to the other end of the output side of the transformer T2 in the inter-stage matching circuit; The gate of the NMOS tube M3 is connected to one end of the capacitor Cn3, and the other end of the capacitor Cn3 is connected to the drain of the NMOS tube M4; The gate of the NMOS tube M4 is connected to one end of the capacitor Cn4, and the other end of the capacitor Cn4 is connected to the drain of the NMOS tube M3; The output matching circuit includes a transformer T3, one end of the input side of the transformer T3 is connected to the drain of the NMOS tube M3 in the second stage amplifier circuit, and the other end of the input side of the transformer T3 is connected to the drain of the NMOS tube M4 in the second stage amplifier circuit; One end of the input side of the transformer T3 is connected to the radio frequency signal output interface RFout, and the other end of the input side of the transformer T3 is grounded.

2. A wideband low noise amplifier based on CMOS process ka band according to claim 1, characterized in that: The tap on the output side of the transformer T1 is connected to the bias voltage Vb.

3. A wideband low noise amplifier based on CMOS process ka band according to claim 2, characterized in that: The tap on the input side of the transformer T2 is connected to the power supply voltage Vdd; the tap on the output side of the transformer T2 is connected to the bias voltage Vb.

4. The wideband low noise amplifier based on CMOS process Ka band according to claim 3, characterized in that: The tap on the input side of the transformer T3 is connected to the power supply voltage Vdd.

5. The wideband low noise amplifier based on CMOS process Ka band according to claim 4, characterized in that: The source of the NMOS tube M1 and the source of the NMOS tube M2 in the first stage amplifier circuit are both grounded.

6. The wideband low noise amplifier based on CMOS process Ka band according to claim 5, characterized in that: The source of the NMOS tube M3 and the source of the NMOS tube M4 in the second stage amplifier circuit are both grounded.

7. The wideband low noise amplifier based on CMOS process Ka band according to claim 6, characterized in that: In the input matching circuit, two ends of the input side of the transformer T1 are connected in parallel with two ends of the capacitor C1; and two ends of the output side of the transformer T1 are connected in parallel with two ends of the capacitor C2.

8. The wideband low noise amplifier based on CMOS process Ka band according to claim 7, characterized in that: In the inter-stage matching circuit, capacitors C3 are connected in parallel at both ends of the input side of the transformer T2; capacitors C4 are connected in parallel at both ends of the output side of the transformer T2.

9. The wideband low noise amplifier based on CMOS process Ka band according to claim 8, characterized in that: In the output matching circuit, capacitors C5 are connected in parallel at both ends of the input side of the transformer T3; capacitors C6 are connected in parallel at both ends of the output side of the transformer T3.

10. The wideband low noise amplifier based on CMOS process Ka band according to claim 9, characterized in that: The power supply voltage Vdd is 1V, and the bias voltage Vb is 0.6V.

11. The wideband low noise amplifier based on CMOS process Ka band according to claim 10, characterized in that: The capacitors Cn1, Cn2, Cn3, and Cn4 are all neutral capacitors, which are 15fF. The model parameters of the NMOS tubes M1, M2, M3, and M4 are the same.

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