High-precision phase shift unit for realizing 5.625 degrees, 2.8125 degrees and 1.40625 degrees and phase shifter

Abstract

The invention relates to a high-precision phase shift unit for realizing 5.625 degrees, 2.8125 degrees and 1.40625 degrees and a phase shifter, belongs to the technical field of radio frequency integrated circuits, and solves the problems of low resolution and poor phase shift precision of the phase shift unit in the prior art. According to the high-precision phase shift unit, a first low-pass structure and a second low-pass structure are connected in parallel; the first low-pass structure comprises an NMOS transistor and a first inductor L1 which are connected in series; the source electrode of the NMOS transistor serves as the input end of the first low-pass structure and also serves as the signal input end of the high-precision phase shift unit; the drain electrode of the NMOS transistor is connected with one end of the first inductor L1; the other end of the first inductor L1 serves as the output end of the first low-pass structure and also serves as the signal output end of the high-precision phase shift unit; the phase shift flatness regulation and control unit is connected in parallel between the source electrode and the drain electrode of the NMOS tube; the grid electrode of the NMOS transistor is connected with a control voltage. The phase shift unit for realizing 5.625 degrees, 2.8125 degrees and 1.40625 degrees, which is higher in resolution ratio and higher in phase shift precision, is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a high-precision phase shift unit and a phase shifter for realizing 5.625°, 2.8125° and 1.40625°. Background Art

[0002] With the continuous development of communication technology, at the military level, phased array radars are gradually replacing traditional mechanical radars with slow scanning speeds and inflexible scanning directions due to their strong anti-interference capabilities and high reliability. At the same time, with the continuous breakthroughs in 5G technology, the application of automotive radar systems in driverless technology is becoming more and more popular. Among these technologies, phased array radar systems are a very important link. In phased array radar systems, T / R (Transmitter and Receiver) transceiver components are the core architecture, among which the phase shifter is an important component of the T / R transceiver component, which directly affects the performance of the entire phased array system, such as phase accuracy, insertion loss, etc. The entire phased array system has thousands of T / R transceiver components, and each T / R transceiver component requires at least one phase shifter, and the phase shifter also occupies a considerable area in the T / R transceiver component.

[0003] The existing technology for realizing phase shift units of 5.625°, 2.8125° and 1.40625° includes T-type structure, band / low-pass structure and high / low-pass topology structure. With the development of science and technology, these phase shift units are increasingly unable to meet the requirements of accuracy and resolution.

[0004] Therefore, there is an urgent need for a phase shift unit with higher resolution and higher phase shift accuracy for achieving phase shifts of 5.625°, 2.8125°, and 1.40625°. Summary of the invention

[0005] In view of the above analysis, an embodiment of the present invention aims to provide a high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625°, so as to solve the problems of low resolution and poor phase shift accuracy of the phase shift unit in the prior art.

[0006] On the one hand, an embodiment of the present invention provides a high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625°, wherein the high-precision phase shift unit includes a first low-pass structure, a second low-pass structure and a phase shift flatness control unit;

[0007] The first low-pass structure is connected in parallel with the second low-pass structure; the first low-pass structure includes an NMOS transistor and a first inductor L1 connected in series;

[0008] The source of the NMOS transistor serves as the input terminal of the first low-pass structure and also serves as the signal input terminal of the high-precision phase shift unit;

[0009] The drain of the NMOS transistor is connected to one end of the first inductor L1; the other end of the first inductor L1 serves as the output end of the first low-pass structure and also serves as the signal output end of the high-precision phase shift unit;

[0010] The phase shift flatness control unit is connected in parallel between the source and drain of the NMOS tube;

[0011] The gate of the NMOS transistor is connected to a control voltage.

[0012] Based on the further improvement of the above high-precision phase shift unit, the second low-pass structure includes a second inductor L2;

[0013] One end of the second inductor L2 is connected to the source of the NMOS tube, and the other end of the second inductor L2 is connected to the other end of the first inductor L1;

[0014] By adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2, phase shifts of 5.625°, 2.8125°, and 1.40625° can be achieved.

[0015] Based on the further improvement of the above-mentioned high-precision phase shift unit, the phase shift flatness control unit includes an adjustment resistor R1;

[0016] One end of the regulating resistor R1 is connected to the source of the NMOS transistor;

[0017] The other end of the regulating resistor R1 is connected to the drain of the NMOS transistor and one end of the first inductor L1 at the same time;

[0018] By changing the resistance value of the adjusting resistor R1, the flatness of the phase shift of the high-precision phase shift unit is adjusted.

[0019] Based on the further improvement of the above high-precision phase shift unit, the first low-pass structure further includes an isolation resistor R2;

[0020] One end of the isolation resistor R2 is connected to the gate of the NMOS transistor, and the other end of the isolation resistor R2 is connected to the control voltage;

[0021] The isolation resistor R2 is used to increase the isolation of the high-precision phase shift unit.

[0022] Based on the further improvement of the above high-precision phase shift unit, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1 are determined in the following manner:

[0023] Determine the circuit equivalent models of the NMOS transistor in the on and off states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state;

[0024] According to any one of the phase shifts of 5.625°, 2.8125° and 1.40625° to be achieved as needed, combined with the amplitude ratio of the output signal to the input signal in the two states and the phase change between the output signal and the input signal, a constraint equation is constructed under the phase shift, and the constraint equation is solved to obtain the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjusting resistor R1.

[0025] Based on the further improvement of the above-mentioned high-precision phase shift unit, the method of determining the amplitude ratio of the output signal to the input signal in each state and the phase change of the output signal to the input signal according to the circuit equivalent model in each state includes:

[0026] Determine the cascade matrix of the circuit equivalent model in the on state and the off state respectively, and convert the cascade matrix into the admittance matrix in the on state and the off state;

[0027] Determining insertion losses in the on and off states according to the admittance matrix in the on and off states;

[0028] According to the insertion loss in the on and off states, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on and off states, and the phase change amount of the output signal and the input signal are determined.

[0029] Based on the further improvement of the above high-precision phase shift unit, the amplitude ratio of the output signal to the input signal of the NMOS transistor in the on and off states, as well as the phase change of the output signal to the input signal are determined by the following formula:

[0030]

[0031]

[0032]

[0033]

[0034] Among them, phase and phase' respectively represent the phase change between the output signal and the input signal in the on and off states, S21 dB , S21′ dBRespectively represent the ratio of the output signal to the input signal in the on and off states, S21 real , S21′ real Represents the real part of the insertion loss in the on and off states, S21 imag , S21′ imag Represent the imaginary part of the insertion loss in the on and off states respectively.

[0035] Based on the further improvement of the above high-precision phase shift unit, the constraint equation constructed under the phase shift amount includes:

[0036] phase-phase′=x;

[0037] S21 dB =1;

[0038] S21' dB =1;

[0039] Here, x represents any phase shift of 5.625°, 2.8125°, and 1.40625°.

[0040] Based on the further improvement of the above high-precision phase shift unit, the cascade matrix of determining the circuit equivalent model in the on and off states includes:

[0041] Determine the cascade matrix of the circuit equivalent model in the on state:

[0042]

[0043] Wherein, A1 represents the cascade matrix of the first inductor L1 in the on state, A2 represents the cascade matrix of the second inductor L2 in the on state, j is an imaginary unit, w represents the angular frequency of the input signal, L1 and L2 represent the inductive reactance values ​​of the first inductor L1 and the second inductor L2 respectively;

[0044] Determine the cascade matrix of the circuit equivalent model in the off state:

[0045]

[0046]

[0047] Among them, B1 represents the cascade matrix of the regulating resistor R1 and the first inductor L1 in the off state, and B1 represents the cascade matrix of the second inductor L2 in the off state.

[0048] On the other hand, an embodiment of the present invention provides a phase shifter based on the above-mentioned high-precision phase shift unit, wherein the phase shifter includes two of the above-mentioned high-precision phase shift units, and by controlling the on and off of NMOS tubes in the two high-precision phase shift units, the two high-precision phase shift units generate phase shifts of 5.625°, 2.8125° and 1.40625°.

[0049] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0050] 1. Phase shifts of 5.625°, 2.8125° and 1.40625° are achieved by connecting the first low-pass structure and the second low-pass structure in parallel. At the same time, a phase shift flatness control unit is added to adjust the flatness during phase shift, so that when the phase shifts of 5.625°, 2.8125° and 1.40625° are achieved, the resolution is higher and the phase shift accuracy is higher.

[0051] 2. By determining the circuit equivalent model of the NMOS transistor in the on and off states, the amplitude ratio of the output signal to the input signal in each state, and the phase change between the output signal and the input signal are determined according to the circuit equivalent model in each state, and a constraint equation is constructed according to any one of the phase shifts of 5.625°, 2.8125° and 1.40625° that needs to be achieved, and the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1 are solved, so that when the phase shifts of 5.625°, 2.8125° and 1.40625° are achieved, the resolution is higher and the phase shift accuracy is higher.

[0052] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0054] Figure 1 A schematic diagram of the structure of a high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625° provided in an embodiment of the present invention;

[0055] Figure 2A circuit equivalent model of an NMOS transistor in a conducting state for realizing a high-precision phase shift unit of 5.625°, 2.8125° and 1.40625° provided in an embodiment of the present invention;

[0056] Figure 3 A circuit equivalent model of an NMOS transistor in an off state for realizing a high-precision phase shift unit of 5.625°, 2.8125° and 1.40625° provided in an embodiment of the present invention;

[0057] Figure 4 A schematic diagram of an actual phase shift of 1.40625° provided in an embodiment of the present invention;

[0058] Figure 5 A schematic diagram of return loss at a phase shift of 1.40625° provided in an embodiment of the present invention;

[0059] Figure 6 A schematic diagram of insertion loss at a phase shift of 1.40625° provided in an embodiment of the present invention;

[0060] Figure 7 A schematic diagram of an actual phase shift of 2.8125° provided in an embodiment of the present invention;

[0061] Figure 8 A schematic diagram of return loss at a phase shift of 2.8125° provided in an embodiment of the present invention;

[0062] Fig. 9 A schematic diagram of insertion loss at a phase shift of 2.8125° provided in an embodiment of the present invention;

[0063] Fig.10 A schematic diagram of an actual phase shift of 5.625° provided in an embodiment of the present invention;

[0064] Fig.11 A schematic diagram of return loss at a phase shift of 5.625° provided in an embodiment of the present invention;

[0065] Fig.12 A schematic diagram of insertion loss at a phase shift of 5.625° provided in an embodiment of the present invention.

[0066] Reference numerals:

[0067] 10 - a first low-pass structure; 20 - a second low-pass structure; 30 - a phase shift flatness control unit. DETAILED DESCRIPTION

[0068] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0069] On the one hand, a specific embodiment of the present invention discloses a high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625°, such as Figure 1 As shown, the high-precision phase shift unit includes a first low-pass structure 10, a second low-pass structure 20 and a phase shift flatness control unit 30;

[0070] The first low-pass structure 10 is connected in parallel with the second low-pass structure 20; the first low-pass structure 10 includes an NMOS transistor and a first inductor L1 connected in series;

[0071] The source of the NMOS transistor serves as the input terminal of the first low-pass structure 10 and also serves as the signal input terminal of the high-precision phase shift unit;

[0072] The drain of the NMOS transistor is connected to one end of the first inductor L1; the other end of the first inductor L1 serves as the output end of the first low-pass structure 10 and also as the signal output end of the high-precision phase shift unit;

[0073] The phase shift flatness control unit 30 is connected in parallel between the source and drain of the NMOS tube;

[0074] The gate of the NMOS transistor is connected to a control voltage.

[0075] Specifically, Figure 1 As shown, the first low-pass structure 10 includes an NMOS transistor and a first inductor L1 connected in series, the gate of the NMOS transistor is connected to a control voltage, and the state of the NMOS transistor is controlled by the control voltage, so that the high-precision phase shift unit achieves different phase shifts when the NMOS transistor is in the on and off states. For example: when the control voltage is at a low level, the NMOS transistor is turned off, and the signal passes through the phase shift flatness control unit 30, the first inductor L1 and the second low-pass structure 20 at the same time. At this time, the state can be used as the standard state of the high-precision phase shift unit; when the control voltage is at a high level, the NMOS transistor is turned on, and the signal passes through the first inductor L1 of the first low-pass structure 10 and the second low-pass structure 20 at the same time. At this time, the state can be used as the phase shift amount state of the high-precision phase shift unit.

[0076] It is understandable that in a phased array system, the phase shifter plays a key role in the quality and steering capability of beamforming, especially the resolution and phase accuracy of the phased array system, which mainly depend on the resolution and phase shift accuracy of the phase shifter. When a high-precision phase shift unit is used, two high-precision phase shift units are included in the phase shifter, and the on and off states of the NMOS transistor in each high-precision phase shift unit are controlled to achieve a phase shift of 5.625°, 2.8125° or 1.40625°.

[0077] Specifically, when the NMOS transistor is turned on and off, the signal generates two different phase shifts through the high-precision phase shift unit. In the 14GHz to 18GHz frequency band, when the NMOS transistor is turned on and off, a phase shift of 5.625°, 2.8125° or 1.40625° is achieved, and all have extremely high phase shift accuracy.

[0078] Preferably, if Figure 1 As shown, the second low-pass structure 20 includes a second inductor L2;

[0079] One end of the second inductor L2 is connected to the source of the NMOS tube, and the other end of the second inductor L2 is connected to the other end of the first inductor L1;

[0080] By adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2, phase shifts of 5.625°, 2.8125°, and 1.40625° can be achieved.

[0081] Specifically, Figure 1 As shown, the second low-pass structure 20 includes a second inductor L2, and two ends of the second inductor L2 serve as an input end and an output end of the second low-pass structure 20. It can be understood that no matter whether the NMOS transistor is in an on state or an off state, the signal passes through the second low-pass structure 20, that is, through the second inductor L2.

[0082] Specifically, by adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2, the phase shifts of 5.625°, 2.8125° and 1.40625° are achieved, that is, when the phase shifts are different, the inductive reactance values ​​of the first inductor L1 and the second inductor L2 are different. It can be understood that when the inductive reactance values ​​of the first inductor L1 and the second inductor L2 are determined, the component can only be used to achieve a phase shift of 5.625°, 2.8125° or 1.40625°.

[0083] Preferably, if Figure 1 As shown, the phase shift flatness control unit 30 includes an adjustment resistor R1;

[0084] One end of the regulating resistor R1 is connected to the source of the NMOS transistor;

[0085] The other end of the regulating resistor R1 is connected to the drain of the NMOS transistor and one end of the first inductor L1 at the same time;

[0086] By changing the resistance value of the adjusting resistor R1, the flatness of the high-precision phase shift unit during phase shifting is adjusted.

[0087] Specifically, the phase shift flatness control unit 30 includes an adjustment resistor R1, and the two ends of the adjustment resistor R1 are connected to the drain and source of the NMOS transistor. The phase shift flatness control unit 30 can adjust the flatness of the phase shift amounts of 5.625°, 2.8125° and 1.40625° to achieve higher resolution, higher accuracy and better design freedom.

[0088] It is understandable that after the resistance value of the adjusting resistor R1 is determined, the flatness of the high-precision phase shift unit is determined when the phase shift amount is 5.625°, 2.8125° or 1.40625°. The resistance value of the adjusting resistor R1 and the inductive reactance value of the first inductor L1 are reasonably selected according to the specific situation, so that the difference between the inductive reactance value after the adjusting resistor R1 and the first inductor L1 are connected in series and the inductive reactance value of the first inductor L1 itself is not too large. If the resistance value of the adjusting resistor R1 is too large, it will affect the impedance matching of the circuit as a whole, and the signal shunting ability will be weakened, reducing the ability to adjust the phase shift flatness.

[0089] Preferably, if Figure 1 As shown, the first low-pass structure also includes an isolation resistor R2;

[0090] One end of the isolation resistor R2 is connected to the gate of the NMOS transistor, and the other end of the isolation resistor R2 is connected to the control voltage;

[0091] The isolation resistor R2 is used to increase the isolation of the high-precision phase shift unit.

[0092] Specifically, Figure 1 As shown, connecting an isolation resistor R2 to the gate of the NMOS transistor can increase the isolation of the high-precision phase shift unit, making the control of the high-precision phase shift unit more precise, and further making the phase shift of 5.625°, 2.8125° or 1.40625° more precise.

[0093] Specifically, the resistance value of the isolation resistor R2 may be 10KΩ. Compared with the inductive reactance values ​​of the adjustment resistor R1, the first inductor L1, and the second inductor L2, the isolation resistor R2 is a large resistance.

[0094] For example, when a phase shift of 1.40625° is achieved, the inductive reactance value of the first inductor L1 is 335pH, the inductive reactance value of the second inductor L2 is 188pH, the resistance value of the adjusting resistor R1 is 36.5Ω, and the resistance value of the isolation resistor R2 is 10KΩ; when a phase shift of 2.8125° is achieved, the inductive reactance value of the first inductor L1 is 316pH, the inductive reactance value of the second inductor L2 is 243pH, the resistance value of the adjusting resistor R1 is 50.5Ω, and the resistance value of the isolation resistor R2 is 10KΩ; when a phase shift of 5.625° is achieved, the inductive reactance value of the first inductor L1 is 370pH, the inductive reactance value of the second inductor L2 is 370pH, the resistance value of the adjusting resistor R1 is 85.7Ω, and the resistance value of the isolation resistor R2 is 10KΩ.

[0095] It is worth noting that in the prior art, T-type structures, band / low-pass structures and high / low-pass topologies are generally used to achieve a phase shift of 5.625°, 2.8125° or 1.40625°. The high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625° provided in the embodiment of the present invention adopts two parallel low-pass structures, combined with a phase shift flatness control unit, so that the phase shift of 5.625°, 2.8125° and 1.40625° has a higher resolution and higher phase shift accuracy.

[0096] Specifically, when the control voltage is at a high level, the NMOS transistor is turned on, and the signal passes through the first inductor L1 and the second inductor L2 at the same time. Figure 2 As shown, the circuit equivalent model of the NMOS transistor in the on state.

[0097] Specifically, when the control voltage is at a low level, the NMOS transistor is turned off, and the signal passes through the adjustment resistor R1, the first inductor L1, and the second inductor L2 at the same time. Figure 3 As shown, the circuit equivalent model of the NMOS transistor in the off state.

[0098] It is worth noting that in the two states of NMOS transistor on and off, the signal produces two different phase shifts. By changing the size of the first inductor L1 and the second inductor L2, the phase shifts of 5.625°, 2.8125° and 1.40625° can be achieved; at the same time, by changing the size of the adjustment resistor R1, the flatness of the high-precision phase shift unit during phase shift can be adjusted. By reasonably adjusting the size of the first inductor L1, the second inductor L2 and the adjustment resistor R1, in the 14GHz to 18GHz frequency band, in the two states of NMOS transistor on and off, a phase shift of 5.625°, 2.8125° or 1.40625° can be achieved, and all three phase shift states have extremely high phase shift accuracy.

[0099] Preferably, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the regulating resistor R1 are determined in the following manner:

[0100] Determine the circuit equivalent models of the NMOS transistor in the on and off states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state;

[0101] According to any one of the phase shifts of 5.625°, 2.8125° and 1.40625° to be achieved as needed, combined with the amplitude ratio of the output signal to the input signal in the two states and the phase change between the output signal and the input signal, a constraint equation is constructed under the phase shift, and the constraint equation is solved to obtain the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjusting resistor R1.

[0102] Preferably, determining the amplitude ratio of the output signal to the input signal in each state and the phase change between the output signal and the input signal according to the circuit equivalent model in each state includes:

[0103] Determine the cascade matrix of the circuit equivalent model in the on state and the off state respectively, and convert the cascade matrix into the admittance matrix in the on state and the off state;

[0104] Determining insertion losses in the on and off states according to the admittance matrix in the on and off states;

[0105] According to the insertion loss in the on and off states, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on and off states, and the phase change amount of the output signal and the input signal are determined.

[0106] Specifically, Figure 2 As shown, the circuit equivalent model of the NMOS transistor in the on state, at this time the signal passes through the first inductor L1 and the second inductor L2, the cascade matrix of the circuit equivalent model in the on state:

[0107]

[0108] Among them, A1 represents the cascade matrix of the first inductor L1 in the on state, A2 represents the cascade matrix of the second inductor L2 in the on state, j is an imaginary unit, w represents the angular frequency of the input signal, and L1 and L2 represent the inductive reactance values ​​of the first inductor L1 and the second inductor L2 respectively.

[0109] Specifically, the cascade matrix of the circuit equivalent model in the on state is converted into the admittance matrix in the on state:

[0110]

[0111]

[0112] Y = Y1 + Y2;

[0113] Among them, A1(1,1), A1(1,2), A1(2,1) and A1(2,2) are four parameters of the cascade matrix A1, A2(1,1), A2(1,2), A2(2,1) and A2(2,2) are four parameters of the cascade matrix A2, Y1 represents the admittance matrix of the first inductor L1 in the on state, Y2 represents the admittance matrix of the second inductor L2 in the on state, and Y represents the admittance matrix in the on state.

[0114] Specifically, the insertion loss in the on state is determined according to the admittance matrix in the on state:

[0115]

[0116] Among them, S21 represents the insertion loss in the on state, Z represents the characteristic impedance parameter of the circuit network, and Y(1,1), Y(1,2), Y(2,1) and Y(2,2) are the four parameters of the admittance matrix in the on state.

[0117] Specifically, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on state, and the phase change of the output signal and the input signal are determined by the following formula:

[0118]

[0119]

[0120] Among them, phase represents the phase change between the output signal and the input signal in the on state, S21 dB Indicates the ratio of the amplitude of the output signal to the input signal in the on state, S21 real represents the real part of the insertion loss in the on state, S21 imag Represents the imaginary part of the insertion loss in the on state.

[0121] Similarly, if Figure 3 As shown, the circuit equivalent model of the NMOS transistor in the off state determines the cascade matrix of the circuit equivalent model in the off state:

[0122]

[0123]

[0124] Among them, B1 represents the cascade matrix of the regulating resistor R1 and the first inductor L1 in the off state, and B1 represents the cascade matrix of the second inductor L2 in the off state.

[0125] Specifically, the cascade matrix of the circuit equivalent model in the off state is converted into the admittance matrix in the off state:

[0126]

[0127]

[0128] Y′=Y3+Y4;

[0129] Among them, B1(1,1), B1(1,2), B1(2,1) and B1(2,2) are four parameters of the cascade matrix B1 respectively, B2(1,1), B2(1,2), B2(2,1) and B2(2,2) are four parameters of the cascade matrix B2 respectively, Y3 represents the admittance matrix of the regulating resistor R1 and the first inductor L1 in the off state, Y3 represents the admittance matrix of the second inductor L2 in the off state, and Y' represents the admittance matrix in the off state.

[0130] Specifically, according to the admittance matrix in the off state, the insertion loss in the off state is determined:

[0131]

[0132] Wherein, S21' represents the insertion loss in the off state, Z represents the characteristic impedance parameter of the circuit network, and Y'(1,1), Y'(1,2), Y'(2,1) and 'Y(2,2) are the four parameters of the admittance matrix in the off state.

[0133] Specifically, the amplitude ratio of the output signal to the input signal of the NMOS transistor in the off state, and the phase change of the output signal to the input signal are determined by the following formula:

[0134]

[0135]

[0136] Wherein, phase′ represents the phase change between the output signal and the input signal in the off state, S21′ dB They represent the ratio of the amplitude of the output signal to the input signal in the off state, S21′ realThey represent the real part of the insertion loss in the off state, S21′ imag They represent the imaginary part of the insertion loss in the off state respectively.

[0137] Specifically, the high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625° provided in the embodiment of the present invention can be used to achieve any phase shift of 5.625°, 2.8125° and 1.40625°. A phase shift is selected, and the amplitude ratio of the output signal to the input signal in the two states and the phase change of the output signal and the input signal are combined to construct a constraint equation under the phase shift.

[0138] Preferably, the constraint equation constructed under the phase shift includes:

[0139] phase-phase'=x;

[0140] S21 dB =1;

[0141] S21′ dB =1;

[0142] Here, x represents any phase shift of 5.625°, 2.8125°, and 1.40625°.

[0143] Specifically, when S21 dB =1, it means that the output signal in the on state has the same amplitude as the input signal, and there is no loss; similarly, when S21′ dB =1, it means that the output signal in the shutdown state has the same amplitude as the input signal and there is no loss.

[0144] Specifically, the constraint equation is solved to obtain the inductive reactance value of the first inductor L1 , the inductive reactance value of the second inductor L2 , and the resistance value of the adjustment resistor R1 .

[0145] It is worth noting that the process of solving constraint equations is to solve multi-objective problems. Through the particle swarm algorithm, the final solution of the problem can be selected from the non-inferior solution set according to the actual problem. In addition, the ant colony algorithm, distribution estimation algorithm, co-evolution algorithm or evolutionary algorithm can also be used to solve constraint equations.

[0146] Specifically, when a phase shift of 1.40625° is achieved, the inductive reactance value of the first inductor L1 obtained by solving the constraint equation is 335pH, the inductive reactance value of the second inductor L2 is 188pH, and the resistance value of the regulating resistor R1 is 36.5Ω, as shown in FIG. Figure 4 , Figure 5 and Figure 6As shown, the actual phase shift, return loss and insertion loss simulation when the phase shift is 1.40625°.

[0147] When a phase shift of 2.8125° is achieved, the inductive reactance value of the first inductor L1 obtained by solving the constraint equation is 316pH, the inductive reactance value of the second inductor L2 is 243pH, and the resistance value of the regulating resistor R1 is 50.5Ω, as shown in FIG. Figure 7 , Figure 8 and Fig. 9 As shown, the actual phase shift, return loss and insertion loss simulation are shown when the phase shift is 2.8125°.

[0148] When a phase shift of 5.625° is achieved, the inductive reactance value of the first inductor L1 obtained by solving the constraint equation is 370pH, the inductive reactance value of the second inductor L2 is 370pH, and the resistance value of the regulating resistor R1 is 85.7Ω. Fig.10 , Fig.11 and Fig.12 As shown, the actual phase shift, return loss and insertion loss simulation when the phase shift is 5.625°.

[0149] In summary Figure 4-Figure 12 As shown, the high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625° provided by the embodiment of the present invention has higher resolution and higher precision when achieving phase shift amounts of 5.625°, 2.8125° and 1.40625°.

[0150] On the other hand, an embodiment of the present invention provides a phase shifter based on the above-mentioned high-precision phase shift unit, wherein the phase shifter includes two of the above-mentioned high-precision phase shift units, and by controlling the on and off of NMOS tubes in the two high-precision phase shift units, the two high-precision phase shift units generate phase shifts of 5.625°, 2.8125° and 1.40625°.

[0151] Specifically, after determining the phase shifts of 5.625°, 2.8125°, and 1.40625°, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2, and the resistance value of the adjustment resistor R1 are calculated and determined, and the resistance value of the preset isolation resistor R2 is used. At this time, a high-precision phase shift unit that determines the phase shift of 5.625°, 2.8125°, or 1.40625° can be obtained. In the phase shifter, the NMOS tubes of the two high-precision phase shift units are respectively in the off and on states by controlling the voltage, and further the phase shift of the signals output by the two high-precision phase shift units is the determined phase shift of 5.625°, 2.8125°, or 1.40625°.

[0152] Compared with the prior art, the high-precision phase shift unit for realizing 5.625°, 2.8125° and 1.40625° provided in this embodiment realizes the phase shifts of 5.625°, 2.8125° and 1.40625° by connecting the first low-pass structure and the second low-pass structure in parallel, and at the same time, a phase shift flatness control unit is added to adjust the flatness during the phase shift, so that when the phase shifts of 5.625°, 2.8125° and 1.40625° are realized, the resolution is higher and the phase shift accuracy is higher; at the same time, by determining the NMOS transistor is turned on and off A circuit equivalent model in two states is defined, and an amplitude ratio of an output signal to an input signal and a phase change between the output signal and the input signal in each state are determined according to the circuit equivalent model in each state. A constraint equation is constructed according to any one of the phase shifts of 5.625°, 2.8125° and 1.40625° to be achieved. The inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjusting resistor R1 are solved, so that when the phase shifts of 5.625°, 2.8125° and 1.40625° are achieved, the resolution is higher and the phase shift accuracy is higher.

[0153] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-precision phase shift unit for achieving 5.625°, 2.8125° and 1.40625°, characterized in that: The high-precision phase shift unit includes a first low-pass structure, a second low-pass structure and a phase shift flatness control unit; The first low-pass structure is connected in parallel with the second low-pass structure; the first low-pass structure includes an NMOS transistor and a first inductor L1 connected in series; The source of the NMOS transistor serves as the input terminal of the first low-pass structure and also serves as the signal input terminal of the high-precision phase shift unit; The drain of the NMOS transistor is connected to one end of the first inductor L1; the other end of the first inductor L1 serves as the output end of the first low-pass structure and also serves as the signal output end of the high-precision phase shift unit; The phase shift flatness control unit is connected in parallel between the source and drain of the NMOS tube; The gate of the NMOS transistor is connected to a control voltage.

2. The high-precision phase shift unit according to claim 1, characterized in that: The second low-pass structure includes a second inductor L2; One end of the second inductor L2 is connected to the source of the NMOS tube, and the other end of the second inductor L2 is connected to the other end of the first inductor L1; By adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2, phase shifts of 5.625°, 2.8125°, and 1.40625° can be achieved.

3. The high-precision phase shift unit according to claim 2, characterized in that: The phase shift flatness control unit includes an adjustment resistor R1; One end of the regulating resistor R1 is connected to the source of the NMOS transistor; The other end of the regulating resistor R1 is connected to the drain of the NMOS transistor and one end of the first inductor L1 at the same time; By changing the resistance value of the adjusting resistor R1, the flatness of the high-precision phase shift unit during phase shifting is adjusted.

4. The high-precision phase shift unit according to claim 1, characterized in that: The first low-pass structure further includes an isolation resistor R2; One end of the isolation resistor R2 is connected to the gate of the NMOS transistor, and the other end of the isolation resistor R2 is connected to the control voltage; The isolation resistor R2 is used to increase the isolation of the high-precision phase shift unit.

5. The high-precision phase shift unit according to claim 3, characterized in that: The inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjusting resistor R1 are determined in the following manner: Determine the circuit equivalent models of the NMOS transistor in the on and off states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state; According to any one of the phase shifts of 5.625°, 2.8125° and 1.40625° to be achieved as needed, combined with the amplitude ratio of the output signal to the input signal in the two states and the phase change between the output signal and the input signal, a constraint equation is constructed under the phase shift, and the constraint equation is solved to obtain the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjusting resistor R1.

6. The high-precision phase shift unit according to claim 5, characterized in that: The determining, according to the circuit equivalent model in each state, the amplitude ratio of the output signal to the input signal in the state, and the phase change amount between the output signal and the input signal, comprises: Determine the cascade matrix of the circuit equivalent model in the on state and the off state respectively, and convert the cascade matrix into the admittance matrix in the on state and the off state; Determining insertion losses in the on and off states according to the admittance matrix in the on and off states; According to the insertion loss in the on and off states, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on and off states, and the phase change amount of the output signal and the input signal are determined.

7. The high-precision phase shift unit according to claim 6, characterized in that: The amplitude ratio of the output signal to the input signal of the NMOS transistor in the on and off states, as well as the phase change between the output signal and the input signal are determined by the following formula: Where phase and phase′ represent the phase change between the output signal and the input signal in the on and off states, respectively. S21 dB , S21′ dB Respectively represent the ratio of the output signal to the input signal in the on and off states, S21 real , S21′ real Represents the real part of the insertion loss in the on and off states, S21 imag , S21′ imag Represent the imaginary part of the insertion loss in the on and off states respectively.

8. The high-precision phase shift unit according to claim 7, characterized in that: The constraint equation constructed under the phase shift includes: phase-phase′=x; S21 dB ＝1； S21′ dB ＝1； Here, x represents any phase shift of 5.625°, 2.8125°, and 1.40625°.

9. The high-precision phase shift unit according to claim 6, characterized in that: The cascade matrix of determining the circuit equivalent model in the on and off states includes: Determine the cascade matrix of the circuit equivalent model in the on state: Wherein, A1 represents the cascade matrix of the first inductor L1 in the on state, A2 represents the cascade matrix of the second inductor L2 in the on state, j is an imaginary unit, w represents the angular frequency of the input signal, L1 and L2 represent the inductive reactance values ​​of the first inductor L1 and the second inductor L2 respectively; Determine the cascade matrix of the circuit equivalent model in the off state: Among them, B1 represents the cascade matrix of the regulating resistor R1 and the first inductor L1 in the off state, and B1 represents the cascade matrix of the second inductor L2 in the off state.

10. A phase shifter based on the high-precision phase shift unit according to any one of claims 1 to 9, characterized in that: The phase shifter comprises two high-precision phase shift units. By controlling the on and off of NMOS tubes in the two high-precision phase shift units, the two high-precision phase shift units generate phase shifts of 5.625°, 2.8125° and 1.40625°.

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