Phase shift device for reducing phase error based on phase shift compensation unit and design method

Abstract

The invention relates to a phase shifting device for reducing phase errors based on a phase shifting compensation unit and a design method, belongs to the technical field of radio frequency integrated circuits, and solves the problem that in the prior art, errors are large when a phase shifter achieves phase shifting. The phase shifting device comprises at least one phase shifting compensation unit and a phase shifter. The phase shifter comprises at least one phase shifting unit which is connected in series. When the phase shifter is used, the phase shift compensation unit is connected to the phase shift unit in series, and the phase shift compensation unit is used for compensating the phase of the phase shifter, so that the phase shift precision of the phase shifter is improved. The phase shifter is higher in phase precision during phase shifting.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a phase shifting device and a design method for reducing phase error based on a phase shift compensation unit. Background Art

[0002] With the continuous development of communication technology, at the military level, phased array radars are gradually replacing traditional mechanical radars with slow scanning speeds and inflexible scanning directions due to their strong anti-interference capabilities and high reliability. At the same time, with the continuous breakthroughs in 5G technology, the application of automotive radar systems in driverless technology is becoming more and more popular. Among these technologies, phased array radar systems are a very important link. In phased array radar systems, T / R (Transmitter and Receiver) transceiver components are the core architecture, among which the phase shifter is an important component of the T / R transceiver component, which directly affects the performance of the entire phased array system, such as phase accuracy, insertion loss, etc. The entire phased array system has thousands of T / R transceiver components, and each T / R transceiver component requires at least one phase shifter, and the phase shifter also occupies a considerable area in the T / R transceiver component.

[0003] In the prior art passive switching phase shifter, a capacitor-based or inductor-based T-type structure is usually used. In the capacitor-based T-type topology, the signal flows through the bandpass and low-pass structures respectively. When the signal flows through the bandpass circuit, the frequency band in which the signal resonates is usually close to the operating frequency band of the phase shifter, thereby causing the phase shifter to produce a large phase error.

[0004] Therefore, a new phase shifting scheme is urgently needed to reduce the phase error. Summary of the invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide a phase shifting device and a design method for reducing phase error based on a phase shift compensation unit, so as to solve the problem of large error when the phase shifter realizes phase shift in the prior art.

[0006] On the one hand, an embodiment of the present invention provides a phase shifting device for reducing phase error based on a phase shift compensation unit, wherein the phase shifting device includes at least one phase shift compensation unit and a phase shifter, wherein the phase shifter includes at least one phase shifting unit connected in series;

[0007] When in use, the phase shift compensation unit is connected in series with the phase shift unit, and the phase shift compensation unit is used to compensate for the phase of the phase shifter so as to improve the phase shift accuracy of the phase shifter.

[0008] Based on the further improvement of the above phase shifting device, the phase shift compensation unit includes a first low-pass structure, a second low-pass structure and a phase shift flatness control unit;

[0009] The first low-pass structure is connected in parallel with the second low-pass structure; the first low-pass structure includes an NMOS transistor and a first inductor L1 connected in series; the source of the NMOS transistor serves as the input end of the first low-pass structure and also as the signal input end of the phase shift compensation unit;

[0010] The drain of the NMOS transistor is connected to one end of the first inductor L1; the other end of the first inductor L1 serves as the output end of the first low-pass structure and also serves as the signal output end of the phase shift compensation unit;

[0011] The phase shift flatness control unit is connected in parallel between the source and drain of the NMOS transistor; the gate of the NMOS transistor is connected to a control voltage.

[0012] Based on the further improvement of the above phase shifting device, the second low-pass structure includes a second inductor L2;

[0013] One end of the second inductor L2 is connected to the source of the NMOS tube, and the other end of the second inductor L2 is connected to the other end of the first inductor L1;

[0014] The phase shift compensation amount of the phase shift compensation unit is achieved by adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2.

[0015] Based on the further improvement of the above phase shifting device, the phase shift flatness control unit includes an adjustment resistor R1;

[0016] One end of the regulating resistor R1 is connected to the source of the NMOS transistor;

[0017] The other end of the regulating resistor R1 is connected to the drain of the NMOS transistor and one end of the first inductor L1 at the same time;

[0018] By changing the resistance value of the adjusting resistor R1, the flatness of the phase shift compensation unit during phase shift is adjusted.

[0019] On the other hand, an embodiment of the present invention provides a design method based on the above-mentioned phase shifting device, the design method comprising:

[0020] Adjusting the center frequency of the phase shifter until a preset center frequency is reached to obtain a center frequency offset;

[0021] Determining a phase shift compensation amount of the phase shift compensation unit according to the center frequency offset;

[0022] According to the phase shift compensation amount of the phase shift compensation unit, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1 are calculated.

[0023] Based on the further improvement of the above design method, the phase shift compensation amount of the phase shift compensation unit is determined by the following formula:

[0024] △X=Q*△f+θ;

[0025] Among them, △X represents the phase shift compensation amount of the phase shift compensation unit, Q represents the phase shift parameter of the phase shift unit of the phase shifter, θ represents the frequency offset error of the phase shift unit of the phase shifter, and △f represents the center frequency offset.

[0026] Based on the further improvement of the above design method, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the regulating resistor R1 are determined in the following manner:

[0027] Determine the circuit equivalent models of the NMOS transistor of the phase shift compensation unit in the on and off states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state;

[0028] According to the phase shift compensation amount of the phase shift compensation unit, combined with the amplitude ratio of the output signal to the input signal in the two states and the phase change amount between the output signal and the input signal, a constraint equation is constructed, and the constraint equation is solved to obtain the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1.

[0029] Based on the further improvement of the above design method, the determination of the amplitude ratio of the output signal to the input signal in each state and the phase change of the output signal to the input signal in each state according to the circuit equivalent model in each state includes:

[0030] Determine the cascade matrix of the circuit equivalent model in the on state and the off state respectively, and convert the cascade matrix into the admittance matrix in the on state and the off state;

[0031] Determining insertion losses in the on and off states according to the admittance matrix in the on and off states;

[0032] According to the insertion loss in the on and off states, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on and off states, and the phase change amount of the output signal and the input signal are determined.

[0033] Based on the further improvement of the above design method, the amplitude ratio of the output signal to the input signal of the NMOS transistor in the on and off states, as well as the phase change of the output signal to the input signal are determined by the following formula:

[0034]

[0035]

[0036]

[0037]

[0038] Where phase and phase′ represent the phase change between the output signal and the input signal in the on and off states, respectively. S21 dB , S21′ dB Respectively represent the ratio of the output signal to the input signal in the on and off states, S21 real , S21′ real Represents the real part of the insertion loss in the on and off states, S21 imag , S21′ imag Represent the imaginary part of the insertion loss in the on and off states respectively.

[0039] Based on the further improvement of the above design method, the constraint equation constructed under the phase shift includes:

[0040] phase-phase′=ΔX;

[0041] S21 dB =1;

[0042] S21′ dB =1.

[0043] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0044] 1. By connecting at least one phase shift compensation unit in series in at least one phase shift unit included in the phase shifter, the phase of the phase shifter is compensated by the phase shift compensation unit, thereby improving the phase accuracy of the phase shifter;

[0045] 2. By combining the first low-pass structure, the second low-pass structure and the phase shift flatness control unit included in the phase shift compensation unit, the phase shift compensation unit can achieve a small phase shift in the working frequency band, thereby reducing the error of the phase shift amount achieved by the entire phase shifting device and improving the phase accuracy of the phase shifter.

[0046] 3. By adjusting the center frequency of the phase shifter until it reaches the preset center frequency, the center frequency offset is obtained, and the phase shift compensation amount of the phase shift compensation unit is determined according to the center frequency offset. The inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1 in the phase shift compensation unit are further determined. That is, the phase shift device of the present invention can determine the phase shift compensation amount according to the center frequency offset, thereby improving the applicability of the phase shift compensation unit.

[0047] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0049] Figure 1 It is a schematic diagram of the variation of the phase shift error superposition when the 11.25° and 22.5° phase shift units are cascaded in the prior art;

[0050] Figure 2 A schematic diagram showing the change of the actual phase shift amount of a 22.5° phase shift unit in the prior art;

[0051] Figure 3 A schematic diagram of the structure of a phase shifting device for reducing phase error based on a phase shift compensation unit provided in an embodiment of the present invention;

[0052] Figure 4 A schematic diagram of the structure of a phase shift compensation unit provided by an embodiment of the present invention;

[0053] Figure 5 A circuit equivalent model of an NMOS transistor in a conducting state of a phase shift compensation unit provided by an embodiment of the present invention;

[0054] Figure 6 A circuit equivalent model of an NMOS transistor in an off state of a phase shift compensation unit provided in an embodiment of the present invention;

[0055] Figure 7 A schematic flow chart of a design method based on a phase shifting device provided in an embodiment of the present invention;

[0056] Figure 8 (a) is a schematic diagram showing the change of the actual phase shift of the phase shifter with the working frequency band before the center frequency point of the phase shifter is adjusted;

[0057] Figure 8 (b) is a schematic diagram showing the change of the actual phase shift of the phase shifter with the working frequency band after the center frequency point of the phase shifter is adjusted;

[0058] Figure 8 (c) is a schematic diagram showing the variation of the actual phase shift of the phase shift compensation unit and the phase shifter with the operating frequency band;

[0059] Fig. 9 A schematic diagram showing the variation of the actual phase shift of the phase shift compensation unit provided by an embodiment of the present invention with the working frequency band;

[0060] Fig.10 A schematic diagram of the error variation of the actual phase shift amount of the phase shift device and the phase shifter provided by the embodiment of the present invention along with the working frequency band.

[0061] Reference numerals:

[0062] 10 - a first low-pass structure; 20 - a second low-pass structure; 30 - a phase shift flatness control unit. DETAILED DESCRIPTION

[0063] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0064] In the prior art passive switch-type phase shifters, the 11.25°, 22.5°, and 45° phase shift units mostly use a capacitor-based or inductor-based T-type structure. In the capacitor-based T-type topology, the signal flows through a bandpass structure and a low-pass structure, respectively.

[0065] When a signal flows through a bandpass circuit, the frequency band where the signal resonates is usually close to the operating frequency band, resulting in a larger phase error. In particular, when the 11.25° and 22.5° phase shift units are cascaded, the phase error caused by the resonant frequency being close to the operating frequency will be superimposed, resulting in a larger phase error, such as Figure 1 shown.

[0066] At the same time, in the process of phase shifter design, in order to minimize the phase error in the entire working frequency band, the phase of the phase shifter is often designed to be similar to the shape of the "smile curve", such as Figure 2 When the phase shift units are cascaded, the phase errors on the left and right sides of the smile curve tend to overlap to a certain extent.

[0067] In order to solve the above-mentioned phase error superposition problem, a specific embodiment of the present invention discloses a phase shifting device based on a phase shift compensation unit to reduce the phase error, such as Figure 3As shown, the phase shifting device includes at least one phase shift compensation unit and a phase shifter, and the phase shifter includes at least one phase shifting unit connected in series;

[0068] When in use, the phase shift compensation unit is connected in series with the phase shift unit, and the phase shift compensation unit is used to compensate for the phase of the phase shifter so as to improve the phase shift accuracy of the phase shifter.

[0069] Specifically, Figure 3 As shown, in the phase shifting device for reducing phase error based on the phase shift compensation unit, at least one phase shift compensation unit is included. The phase shift compensation unit is connected in series with the phase shift unit in the phase shifter. The position of the series connection is not limited. For example, the phase shift compensation unit can be connected in series to the signal input end of the existing phase shifter, that is, connected in series with the first phase shift unit in the phase shifter. The phase shift compensation unit can also be connected in series to the signal output end of the phase shifter, that is, connected in series with the last phase shift unit in the phase shifter. The phase shift compensation unit can also be connected in series between two phase shift units in the phase shifter, for example, the phase shift compensation unit is connected in series between phase shift unit 1 and phase shift unit 2. In the phase shifting device, the phase shift compensation unit can change the phase of the signal, thereby compensating for the phase of the phase shifter, reducing the phase error of the phase shifter, and improving the phase shifting accuracy of the phase shifter.

[0070] It is worth noting that the present invention does not limit the number of phase shift units included in the phase shifter. For example, the phase shifter may include one phase shift unit or multiple phase shift units. At the same time, the type of phase shift unit of the phase shift amount included in the phase shifter is not limited, and multiple phase shift units of multiple phase shift amounts may be included. For example, the phase shifter only includes a phase shift unit of 11.25°, or the phase shifter includes phase shift units of 11.25°, 25°, etc.

[0071] Specifically, after the phase shifting device is formed, the phase shift compensation unit and each phase shift unit in the phase shifter simultaneously change the phase of the signal, and the phase shift compensation unit compensates the phase of the phase shifter, thereby improving the phase shifting accuracy of the phase shifter.

[0072] Preferably, if Figure 4 As shown, the phase shift compensation unit includes a first low-pass structure 10, a second low-pass structure 20 and a phase shift flatness control unit 30;

[0073] The first low-pass structure 10 is connected in parallel with the second low-pass structure 20; the first low-pass structure 10 includes an NMOS transistor and a first inductor L1 connected in series; the source of the NMOS transistor serves as the input end of the first low-pass structure 10 and also as the signal input end of the phase shift compensation unit;

[0074] The drain of the NMOS transistor is connected to one end of the first inductor L1; the other end of the first inductor L1 serves as the output end of the first low-pass structure 10 and also as the signal output end of the phase shift compensation unit;

[0075] The phase shift flatness control unit 30 is connected in parallel between the source and drain of the NMOS transistor; the gate of the NMOS transistor is connected to a control voltage.

[0076] Specifically, Figure 4 As shown, the first low-pass structure 10 includes an NMOS transistor and a first inductor L1 connected in series, the gate of the NMOS transistor is connected to a control voltage, and the state of the NMOS transistor is controlled by the control voltage, so that the phase shift compensation unit realizes different phase shifts of the signal when the NMOS transistor is in the on and off states. For example: when the control voltage is at a low level, the NMOS transistor is turned off, and the signal passes through the phase shift flatness control unit 30, the first inductor L1 and the second low-pass structure 20 at the same time, and the state at this time can be used as the standard state of the phase shift compensation unit; when the control voltage is at a high level, the NMOS transistor is turned on, and the signal passes through the first inductor L1 of the first low-pass structure 10 and the second low-pass structure 20 at the same time, and the state at this time can be used as the phase shift amount state of the phase shift compensation unit.

[0077] Specifically, when the NMOS transistor is turned on and off, the signal generates two different phase shifts through the phase shift compensation unit. In the 14GHz to 18GHz frequency band, when the NMOS transistor is turned on and off, the phase shift required to be compensated by the phase shifter is achieved, and both have extremely high phase shift accuracy.

[0078] Preferably, if Figure 4 As shown, the second low-pass structure 20 includes a second inductor L2;

[0079] One end of the second inductor L2 is connected to the source of the NMOS tube, and the other end of the second inductor L2 is connected to the other end of the first inductor L1;

[0080] The phase shift compensation amount of the phase shift compensation unit is achieved by adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2.

[0081] Specifically, Figure 4 As shown, the second low-pass structure 20 includes a second inductor L2, and two ends of the second inductor L2 serve as an input end and an output end of the second low-pass structure 20. It can be understood that no matter whether the NMOS transistor is in an on state or an off state, the signal passes through the second low-pass structure 20, that is, through the second inductor L2.

[0082] Specifically, by adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2, the phase shift amount that needs to be compensated in the phase shifter is realized, that is, when the phase shift amounts are different, the inductive reactance values ​​of the first inductor L1 and the second inductor L2 are different. It can be understood that when the inductive reactance values ​​of the first inductor L1 and the second inductor L2 are determined, the component can only be used to realize the phase shift amount that needs to be compensated in the phase shifter.

[0083] Preferably, if Figure 4 As shown, the phase shift flatness control unit 30 includes an adjustment resistor R1;

[0084] One end of the regulating resistor R1 is connected to the source of the NMOS transistor;

[0085] The other end of the regulating resistor R1 is connected to the drain of the NMOS transistor and one end of the first inductor L1 at the same time;

[0086] By changing the resistance value of the adjusting resistor R1, the flatness of the phase shift compensation unit during phase shift is adjusted.

[0087] Specifically, the phase shift flatness control unit 30 includes an adjustment resistor R1, and the two ends of the adjustment resistor R1 are connected to the drain and source of the NMOS transistor. The phase shift flatness control unit 30 can adjust the flatness of the phase shift amount that needs to be compensated in the phase shifter, thereby achieving higher resolution, higher accuracy and better design freedom.

[0088] It is understandable that when the resistance value of the adjusting resistor R1 is determined, the flatness of the phase shift amount of the phase shift compensation unit is determined. The resistance value of the adjusting resistor R1 and the inductive reactance value of the first inductor L1 are reasonably selected according to the specific situation, so that the difference between the inductive reactance value after the adjusting resistor R1 and the first inductor L1 are connected in series and the inductive reactance value of the first inductor L1 itself is not too large. If the resistance value of the adjusting resistor R1 is too large, it will affect the impedance matching of the circuit as a whole, and the signal shunting ability will be weakened, reducing the ability to adjust the phase shift flatness.

[0089] Preferably, if Figure 4 As shown, the first low-pass structure 10 further includes an isolation resistor R2;

[0090] One end of the isolation resistor R2 is connected to the gate of the NMOS transistor, and the other end of the isolation resistor R2 is connected to the control voltage;

[0091] The isolation resistor R2 is used to increase the isolation of the phase shift compensation unit.

[0092] Specifically, Figure 4As shown, connecting an isolation resistor R2 to the gate of the NMOS transistor can increase the isolation of the phase shift compensation unit, making the control of the phase shift compensation unit more precise, and further making the phase shift amount to be compensated by the implemented phase shifter more precise.

[0093] Specifically, the resistance value of the isolation resistor R2 may be 10KΩ. Compared with the inductive reactance values ​​of the adjustment resistor R1, the first inductor L1, and the second inductor L2, the isolation resistor R2 is a large resistance.

[0094] Specifically, when the control voltage is at a high level, the NMOS transistor is turned on, and the signal passes through the first inductor L1 and the second inductor L2 at the same time. Figure 5 As shown, the circuit equivalent model of the NMOS transistor in the on state.

[0095] Specifically, when the control voltage is at a low level, the NMOS transistor is turned off, and the signal passes through the adjustment resistor R1, the first inductor L1, and the second inductor L2 at the same time. Figure 6 As shown, the circuit equivalent model of the NMOS transistor in the off state.

[0096] It is worth noting that when the NMOS transistor is turned on and off, the signal produces two different phase shifts. The phase shift amount that the phase shifter needs to compensate is achieved by changing the size of the first inductor L1 and the second inductor L2; at the same time, by changing the size of the adjustment resistor R1, the flatness of the phase shift compensation unit during phase shift can be adjusted. By reasonably adjusting the size of the first inductor L1, the second inductor L2 and the adjustment resistor R1, the phase shift amount that the phase shifter needs to compensate is achieved in the 14GHz to 18GHz frequency band, when the NMOS transistor is turned on and off, and it has extremely high phase shift accuracy.

[0097] Specifically, when in use, the NMOS transistor conduction state is controlled to be consistent with the phase shift state of the phase shifter, and the off state is controlled to be consistent with the standard state of the phase shifter. For example, the phase shift device includes a phase shift compensation unit and an 11.25° phase shift unit, and the phase shift compensation unit in one phase shift device is controlled to be in the NMOS transistor conduction state and the 11.25° phase shift unit is in the 11.25° phase shift state, while the phase shift compensation unit in another phase shift device is controlled to be in the NMOS transistor off state and the 11.25° phase shift unit is in the standard state of 0°, so that the output signal phase difference of the two phase shift devices is 11.25° of the phase shift amount, and the phase shift accuracy is higher.

[0098] Compared with the prior art, the phase shifting device for reducing phase error based on a phase shift compensation unit provided in the present embodiment improves the phase accuracy of the phase shifter by connecting at least one phase shift compensation unit in series in at least one phase shift unit included in the phase shifter, and compensating the phase of the phase shifter through the phase shift compensation unit; at the same time, through the combination of the first low-pass structure, the second low-pass structure and the phase shift flatness control unit included in the phase shift compensation unit, the phase shift compensation unit realizes a small phase shift in the working frequency band, thereby reducing the error of the phase shift amount realized by the entire phase shifting device and improving the phase accuracy of the phase shifter.

[0099] Another specific embodiment of the present invention discloses a design method based on the above-mentioned phase shifting device, such as Figure 7 As shown, the design method includes:

[0100] Step S101: adjusting the center frequency of the phase shifter until it reaches a preset center frequency, and obtaining a center frequency offset;

[0101] Step S102: determining the phase shift compensation amount of the phase shift compensation unit according to the center frequency offset;

[0102] Step S103: calculating the inductive reactance value of the first inductor L1 , the inductive reactance value of the second inductor L2 , and the resistance value of the adjusting resistor R1 according to the phase shift compensation amount of the phase shift compensation unit.

[0103] Specifically, Figure 7 As shown, in step S101, the center frequency of the phase shifter is adjusted, for example, Figure 2 In a phase shifter including only one 22.5° phase shift unit, the actual phase shift of the 22.5° phase shift unit has a center frequency of 1.6E+10. If the preset center frequency is 1.5E+10, the 1.6E+10 center frequency of the 22.5-degree phase shifter needs to be adjusted to 1.5E+10 center frequency to obtain the center frequency offset. At this time, the center frequency offset of the 22.5° phase shifter is 0.1E+10.

[0104] like Figure 8 As shown, (a) is a schematic diagram showing the change of the actual phase shift of the phase shifter with the working frequency band before the center frequency point is adjusted; (b) is a schematic diagram showing the change of the actual phase shift of the phase shifter with the working frequency band after the center frequency point is adjusted.

[0105] Specifically, Figure 7 As shown, in step S102, the phase shift compensation amount of the phase shift compensation unit is determined according to the center frequency offset.

[0106] Preferably, the phase shift compensation amount of the phase shift compensation unit is determined by the following formula:

[0107] △X=Q*△f+θ;

[0108] Among them, △X represents the phase shift compensation amount of the phase shift compensation unit, Q represents the phase shift parameter of the phase shift unit of the phase shifter, θ represents the frequency offset error of the phase shift unit of the phase shifter, and △f represents the center frequency offset.

[0109] Specifically, Q and θ are fixed parameters of the phase shifter. After knowing the center frequency offset, the phase shift compensation ΔX of the phase shift compensation unit is calculated by the above formula ΔX=Q*Δf+θ.

[0110] Specifically, in step S103, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2, and the resistance value of the adjustment resistor R1 are calculated according to the phase shift compensation amount ΔX of the phase shift compensation unit.

[0111] It is worth noting that, when the phase shifting device for reducing phase error based on the phase shift compensation unit provided in the embodiment of the present invention includes only one phase shift compensation unit, then the phase shift compensation amount of the phase shift compensation unit is △X, and the phase shift compensation unit is connected in series with other phase shift units; when the phase shifting device for reducing phase error based on the phase shift compensation unit provided in the embodiment of the present invention includes two or more phase shift compensation units, the sum of the phase shift compensation amounts of the two or more phase shift compensation units is △X, the phase shift compensation amount of each phase shift compensation unit can be the same or different, and can be set as needed, and is not limited here. The phase shift compensation unit and the phase shift unit in the phase shifting device are connected in series with each other.

[0112] Preferably, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the regulating resistor R1 are determined in the following manner:

[0113] Determine the circuit equivalent models of the NMOS transistor of the phase shift compensation unit in the on and off states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state;

[0114] According to the phase shift compensation amount of the phase shift compensation unit, combined with the amplitude ratio of the output signal to the input signal in the two states and the phase change amount between the output signal and the input signal, a constraint equation is constructed, and the constraint equation is solved to obtain the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1.

[0115] Preferably, determining the amplitude ratio of the output signal to the input signal in each state, and the phase change amount between the output signal and the input signal in each state according to the circuit equivalent model in each state includes:

[0116] Determine the cascade matrix of the circuit equivalent model in the on state and the off state respectively, and convert the cascade matrix into the admittance matrix in the on state and the off state;

[0117] Determining insertion losses in the on and off states according to the admittance matrix in the on and off states;

[0118] According to the insertion loss in the on and off states, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on and off states, and the phase change amount of the output signal and the input signal are determined.

[0119] Specific, concrete, such as Figure 5 As shown, the circuit equivalent model of the NMOS transistor in the on state, at this time the signal passes through the first inductor L1 and the second inductor L2, the cascade matrix of the circuit equivalent model in the on state:

[0120]

[0121] Among them, A1 represents the cascade matrix of the first inductor L1 in the on state, A2 represents the cascade matrix of the second inductor L2 in the on state, j is an imaginary unit, w represents the angular frequency of the input signal, and L1 and L2 represent the inductive reactance values ​​of the first inductor L1 and the second inductor L2 respectively.

[0122] Specifically, the cascade matrix of the circuit equivalent model in the on state is converted into the admittance matrix in the on state:

[0123]

[0124]

[0125] Y = Y1 + Y2;

[0126] Among them, A1(1,1), A1(1,2), A1(2,1) and A1(2,2) are four parameters of the cascade matrix A1, A2(1,1), A2(1,2), A2(2,1) and A2(2,2) are four parameters of the cascade matrix A2, Y1 represents the admittance matrix of the first inductor L1 in the on state, Y2 represents the admittance matrix of the second inductor L2 in the on state, and Y represents the admittance matrix in the on state.

[0127] Specifically, according to the admittance matrix in the on state, the insertion loss in the on state is determined:

[0128]

[0129] Among them, S21 represents the insertion loss in the on state, Z represents the characteristic impedance parameter of the circuit network, and Y(1,1), Y(1,2), Y(2,1) and Y(2,2) are the four parameters of the admittance matrix in the on state.

[0130] Specifically, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on state, and the phase change of the output signal and the input signal are determined by the following formula:

[0131]

[0132]

[0133] Among them, phase represents the phase change between the output signal and the input signal in the on state, S21 dB Indicates the ratio of the amplitude of the output signal to the input signal in the on state, S21 real represents the real part of the insertion loss in the on state, S21 imag Represents the imaginary part of the insertion loss in the on state.

[0134] Similarly, if Figure 5 As shown, the circuit equivalent model of the NMOS transistor in the off state determines the cascade matrix of the circuit equivalent model in the off state:

[0135]

[0136]

[0137] Among them, B1 represents the cascade matrix of the regulating resistor R1 and the first inductor L1 in the off state, and B1 represents the cascade matrix of the second inductor L2 in the off state.

[0138] Specifically, the cascade matrix of the circuit equivalent model in the off state is converted into the admittance matrix in the off state:

[0139]

[0140]

[0141] Y′=Y3+Y4;

[0142] Among them, B1(1,1), B1(1,2), B1(2,1) and B1(2,2) are four parameters of the cascade matrix B1, B2(1,1), B2(1,2), B2(2,1) and B2(2,2) are four parameters of the cascade matrix B2, Y3 represents the admittance matrix of the regulating resistor R1 and the first inductor L1 in the off state, Y3 represents the admittance matrix of the second inductor L2 in the off state, and Y' represents the admittance matrix in the off state.

[0143] Specifically, according to the admittance matrix in the off state, the insertion loss in the off state is determined:

[0144]

[0145] Wherein, S21' represents the insertion loss in the off state, Z represents the characteristic impedance parameter of the circuit network, and Y'(1,1), Y'(1,2), Y'(2,1) and 'Y(2,2) are the four parameters of the admittance matrix in the off state.

[0146] Specifically, the amplitude ratio of the output signal to the input signal of the NMOS transistor in the off state, and the phase change of the output signal to the input signal are determined by the following formula:

[0147]

[0148]

[0149] Wherein, phase′ represents the phase change between the output signal and the input signal in the off state, S21′ dB They represent the ratio of the amplitude of the output signal to the input signal in the off state, S21′ real They represent the real part of the insertion loss in the off state, S21′ imag They represent the imaginary part of the insertion loss in the off state respectively.

[0150] Specifically, according to the phase shift compensation amount △X of the phase shift compensation unit, combined with the amplitude ratio S21 of the output signal to the input signal in the two states dB , S21′ dB and the phase changes phase and phase′ between the output signal and the input signal, a constraint equation is constructed, and the constraint equation is solved to obtain the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1.

[0151] Preferably, the constraint equation constructed under the phase shift includes:

[0152] phase-phase′=ΔX;

[0153] S21 dB =1;

[0154] S21′ dB =1.

[0155] Specifically, when S21 dB =1, it means that the output signal in the on state has the same amplitude as the input signal, and there is no loss; similarly, when S21′ dB =1, it means that the output signal in the shutdown state has the same amplitude as the input signal and there is no loss.

[0156] It is worth noting that the process of solving constraint equations is to solve multi-objective problems. Through the particle swarm algorithm, the final solution of the problem can be selected from the non-inferior solution set according to the actual problem. In addition, the ant colony algorithm, distribution estimation algorithm, co-evolution algorithm or evolutionary algorithm can also be used to solve constraint equations.

[0157] Specifically, the constraint equation is solved to obtain the inductive reactance value of the first inductor L1 , the inductive reactance value of the second inductor L2 , and the resistance value of the adjustment resistor R1 .

[0158] For example, when the center frequency offset △f is 0.1E+10, the calculated phase shift compensation amount of the phase shift compensation unit is 0.3°, the inductive reactance value of the first inductor L1 is 138pH, the inductive reactance value of the second inductor L2 is 2nH, and the resistance value of the adjustment resistor R1 is 233Ω.

[0159] Specifically, after determining the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2, and the resistance value of the adjusting resistor R1, the actual phase shift amount of the phase shift compensation unit in the working frequency band is as follows: Fig. 9 As shown, at this time, the phase shift amount achieved by the phase shift compensation unit changes with the working frequency band.

[0160] Specifically, Figure 8 (c) shows that the curved dotted line shows the curve of the compensation phase shift amount achieved by the phase shift compensation unit as the working frequency band changes. Fig. 9 The compensating phase shift achieved by the phase shift compensation unit is small, and its purpose is to compensate for the error phase of the phase shifter; the curved solid line represents the curve showing the change of the phase shift achieved by the phase shifter with the working frequency band, and the horizontal dotted line represents the standard phase shift achieved by the phase shifter.

[0161] As shown in Figure (8)(c), the actual phase shift produced by the phase shifter and the standard phase shift are first a negative error and then a positive error within the working frequency band. The error is equal to the phase difference between the curved solid line and the horizontal dotted line. The curved dotted line produced by the phase shift compensation unit is used for phase compensation, so that the error of the phase shift finally achieved by the phase shifting device is reduced, thereby improving the phase accuracy of the phase shifter when performing phase shifting.

[0162] Specifically, Fig.10 As shown, the error variation curve diagram of the actual phase shift amount of the phase shifter in the prior art and the phase shifting device based on the phase shift compensation unit to reduce the phase error provided by the embodiment of the present invention, from which it can be seen that the phase shifting device provided by the embodiment of the present invention has higher phase shifting accuracy.

[0163] Compared with the prior art, the design method provided in this embodiment adjusts the center frequency of the phase shifter until it reaches a preset center frequency, obtains the center frequency offset, determines the phase shift compensation amount of the phase shift compensation unit according to the center frequency offset, and further determines the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1 in the phase shift compensation unit, that is, the phase shift device of the present invention can determine the phase shift compensation amount according to the center frequency offset, thereby improving the applicability of the phase shift compensation unit.

[0164] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0165] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A phase shifting device for reducing phase error based on a phase shift compensation unit, characterized in that: The phase shifting device comprises at least one phase shift compensation unit and a phase shifter, wherein the phase shifter comprises at least one phase shifting unit connected in series; When in use, the phase shift compensation unit is connected in series with the phase shift unit, and the phase shift compensation unit is used to compensate for the phase of the phase shifter so as to improve the phase shift accuracy of the phase shifter.

2. The phase shifting device according to claim 1, characterized in that: The phase shift compensation unit includes a first low-pass structure, a second low-pass structure and a phase shift flatness control unit; The first low-pass structure is connected in parallel with the second low-pass structure; the first low-pass structure includes an NMOS transistor and a first inductor L1 connected in series; the source of the NMOS transistor serves as the input end of the first low-pass structure and also as the signal input end of the phase shift compensation unit; The drain of the NMOS transistor is connected to one end of the first inductor L1; the other end of the first inductor L1 serves as the output end of the first low-pass structure and also serves as the signal output end of the phase shift compensation unit; The phase shift flatness control unit is connected in parallel between the source and drain of the NMOS transistor; the gate of the NMOS transistor is connected to a control voltage.

3. The phase shifting device according to claim 2, characterized in that: The second low-pass structure includes a second inductor L2; One end of the second inductor L2 is connected to the source of the NMOS tube, and the other end of the second inductor L2 is connected to the other end of the first inductor L1; The phase shift compensation amount of the phase shift compensation unit is achieved by adjusting the inductive reactance values ​​of the first inductor L1 and the second inductor L2.

4. The phase shifting device according to claim 3, characterized in that: The phase shift flatness control unit includes an adjustment resistor R1; One end of the regulating resistor R1 is connected to the source of the NMOS transistor; The other end of the regulating resistor R1 is connected to the drain of the NMOS transistor and one end of the first inductor L1 at the same time; By changing the resistance value of the adjusting resistor R1, the flatness of the phase shift compensation unit during phase shift is adjusted.

5. A design method for a phase shifting device according to any one of claims 1 to 4, characterized in that: The design method comprises: Adjusting the center frequency of the phase shifter until a preset center frequency is reached to obtain a center frequency offset; Determining a phase shift compensation amount of the phase shift compensation unit according to the center frequency offset; According to the phase shift compensation amount of the phase shift compensation unit, the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1 are calculated.

6. The design method according to claim 5, characterized in that: The phase shift compensation amount of the phase shift compensation unit is determined by the following formula: △X=Q*△f+θ; Among them, △X represents the phase shift compensation amount of the phase shift compensation unit, Q represents the phase shift parameter of the phase shift unit of the phase shifter, θ represents the frequency offset error of the phase shift unit of the phase shifter, and △f represents the center frequency offset.

7. The design method according to claim 5, characterized in that: The inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjusting resistor R1 are determined in the following manner: Determine the circuit equivalent models of the NMOS transistor of the phase shift compensation unit in the on and off states respectively; determine the amplitude ratio of the output signal to the input signal in each state, and the phase change amount of the output signal to the input signal according to the circuit equivalent model in each state; According to the phase shift compensation amount of the phase shift compensation unit, combined with the amplitude ratio of the output signal to the input signal in the two states and the phase change amount between the output signal and the input signal, a constraint equation is constructed, and the constraint equation is solved to obtain the inductive reactance value of the first inductor L1, the inductive reactance value of the second inductor L2 and the resistance value of the adjustment resistor R1.

8. The design method according to claim 7, characterized in that: The determining of the amplitude ratio of the output signal to the input signal in each state and the phase change between the output signal and the input signal in each state according to the circuit equivalent model in each state includes: Determine the cascade matrix of the circuit equivalent model in the on state and the off state respectively, and convert the cascade matrix into the admittance matrix in the on state and the off state; Determining insertion losses in the on and off states according to the admittance matrix in the on and off states; According to the insertion loss in the on and off states, the amplitude ratio of the output signal and the input signal of the NMOS transistor in the on and off states, and the phase change amount of the output signal and the input signal are determined.

9. The design method according to claim 8, characterized in that: The amplitude ratio of the output signal to the input signal of the NMOS transistor in the on and off states, as well as the phase change between the output signal and the input signal are determined by the following formula: Where phase and phase′ represent the phase change between the output signal and the input signal in the on and off states, respectively. S21 dB , S21′ dB Respectively represent the ratio of the output signal to the input signal in the on and off states, S21 real , S21′ real Represents the real part of the insertion loss in the on and off states, S21 imag , S21′ imag Represent the imaginary part of the insertion loss in the on and off states respectively.

10. The design method according to claim 9, characterized in that: The constraint equation constructed under the phase shift includes: phase-phase′=ΔX; S21 dB ＝1； S21′ dB ＝1。

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