Negative reactive synthesizer

Abstract

The invention provides a negative reactance synthesizer. The negative reactance synthesizer comprises a direct-current power supply; the first converter is configured to realize input current shaping under an alternating current input voltage with a given peak value and convert a variable direct current voltage into a fixed direct current voltage; a second converter configured to convert the fixed DC voltage into a superimposed DC voltage greater than a peak value of the AC input voltage, and to superimpose the superimposed DC voltage on the AC input voltage to form a variable DC voltage; a first control circuit configured to generate a first gate driver signal and a first complementary gate drive signal for controlling the first converter; and a second control circuit configured to generate a second gate driver signal and a second complementary gate drive signal for controlling the second converter. The invention provides a simple and low-cost solution to simulate independent negative reactance.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 588,780 filed on October 9, 2023, and the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention generally relates to the synthesis of desired independent negative reactances. More specifically, the present invention relates to the synthesis of independent negative inductances and independent negative capacitances. Background Art

[0003] Reactive power compensation is a common technique used in AC power transmission systems and wireless power transfer (WPT) systems to improve power factor and efficiency. In practice, compensation is usually achieved by adding capacitors to offset unwanted inductive effects or adding inductors to offset unwanted capacitive effects. However, the use of inductors / capacitors for compensation requires additional design considerations, which often complicates system design. For power systems, the use of capacitors may change the inductive or capacitive harmonic impedance of the system. In addition, for specific harmonic frequencies, capacitors may resonate with the system, resulting in the amplification of harmonic currents, which not only poses a risk to the capacitors, but also endangers electrical equipment in the grid. In severe cases, this may cause damage or even interrupt the normal operation of the grid. For WPT systems, accurate compensation by inserting inductors / capacitors can only be achieved at a specific frequency point (resonant frequency), which is affected by parameter changes, so a fairly complex design is required to allow performance to be maintained under changes in parameters (such as the inductance of the resonant coil and the distance between the resonant coils). Despite the known drawbacks of the above resonance-based compensation applications, using capacitors to offset excess inductance or inductors to offset excess capacitance remains the only practical solution to achieve reactive power compensation in the absence of negative reactance.

[0004] Some methods attempt to synthesize negative reactance that does not exist in the real world to directly eliminate the unwanted reactance. For example, a two-terminal network called a gyrator has been developed to synthesize negative reactance with small-signal characteristics. However, circuits based on gyrators can only achieve negative reactance characteristics within a very narrow frequency range, which does not manifest as true negative inductance or negative capacitance. In addition, gyrators are built using operational amplifiers or transconductance amplifiers, which are limited by voltage supply. Therefore, the negative reactance achieved by gyrators is only suitable for certain signal processing applications, but not for power transmission applications.

[0005] So far, there has been no realization of negative reactance that exists independently. The closest manifestation of negative reactance is through indirect verification. In this experiment, when a reactor is connected to an additional circuit, the reactance value of the entire circuit is smaller than the reactance value when the reactor is measured alone, which indirectly proves that the additional circuit has the characteristic of negative reactance. Obviously, this realization is difficult to apply to applications such as compensation mentioned above, because this requires that the additional circuit that realizes the negative reactance characteristic must be part of the original system, while in fact the excess reactance is independently generated by the inherent physical characteristics of the equipment (such as leakage inductance in transformers). Summary of the invention

[0006] The object of the present invention is to provide an independent negative reactance synthesizer to solve the above technical problems.

[0007] According to a first aspect of the present invention, a negative reactance synthesizer is provided. The negative reactance synthesizer comprises: a DC power supply, a first converter configured to implement input current shaping under an AC input voltage with a given peak value E, and convert a variable DC voltage into a fixed DC voltage U o ; The second converter is used to convert the fixed DC voltage U o Converted to superimposed DC voltage V E ; wherein the superimposed DC voltage V E The voltage is greater than the peak value E of the AC input voltage and is superimposed on the AC input voltage to form a variable DC voltage; a first control circuit for generating a first gate drive signal V for controlling the first converter d1 and the first complementary gate drive signal V 1-d1 ; and a second control circuit for generating a second gate drive signal V d2 and the second complementary gate drive signal V 1-d2 , used to control the second converter.

[0008] In the present invention, considering the simulation of power reactance in power electronic circuits capable of processing power, the input impedance of the converter is designed as a pure resistor to achieve a high input power factor. Appropriate control is used to shape the input current to ensure that the input current and input voltage meet the required phase difference, thereby obtaining a universal negative reactance.

[0009] The present invention overcomes the inherent instability of negative reactance due to power imbalance and provides a simple and low-cost solution for simulating independent negative reactance. By controlling the arrangement of the circuit, the topology can be simulated as a pure negative inductance or a pure negative capacitance. In addition, the present invention can achieve the cancellation of positive reactance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments of the present invention are described in more detail below with reference to the accompanying drawings, wherein:

[0011] Figure 1 A framework diagram of a negative reactance synthesizer according to an embodiment of the present invention is shown.

[0012] Figure 2 The definition of system input impedance is shown;

[0013] Figure 3 shows a circuit diagram of a first converter according to an embodiment of the present invention;

[0014] Figure 4 FIG. 4 shows a circuit diagram of a second converter according to an embodiment of the present invention.

[0015] Figure 5 A current loop for current shaping control is shown to achieve the desired amplitude and phase relationship between input voltage and input current;

[0016] Figure 6 A circuit diagram of a first control circuit according to an embodiment of the present invention is shown.

[0017] Fig. 7A A circuit diagram of an active filter for synthesizing independent negative inductance according to an embodiment of the present invention is shown.

[0018] Figure 7B A circuit diagram of an active filter for synthesizing independent negative capacitance according to another embodiment of the present invention is shown.

[0019] Figure 8 FIG. 4 is a circuit diagram of a second control circuit according to an embodiment of the present invention.

[0020] Fig.9A and Fig. 9B The waveforms of the input voltage and input current of the synthetic independent negative inductor at frequencies of 50 Hz and 100 Hz are shown respectively.

[0021] Fig.10 shows the magnitude and angle of the synthetic independent negative inductive impedance measured in the frequency range of 50 Hz to 400 Hz;

[0022] Fig.11 A circuit for verifying the use of a synthetic independent negative inductor to cancel a positive inductor is shown;

[0023] Fig. 12A The waveforms of the input voltage and the input current at a frequency of 50 Hz are shown when the circuit does not include a synthetic independent negative inductor.

[0024] Fig. 12B The waveforms of the input voltage and input current at a frequency of 50 Hz are shown when the circuit includes a synthetic independent negative inductor.

[0025] Fig.13AThe waveforms of the input voltage and the input current are shown at a frequency of 100 Hz without synthetic negative inductance.

[0026] Fig. 13B The waveforms of input voltage and input current in the presence of synthetic independent negative inductance at a frequency of 100 Hz are shown;

[0027] Fig.14A and Fig. 14B The waveforms of the input voltage and input current of the synthesized independent negative capacitor at frequencies of 50 Hz and 100 Hz are shown respectively;

[0028] Fig.15 shows the impedance magnitude and phase angle of the synthetic independent negative capacitive impedance measured in the frequency range of 50 Hz to 400 Hz;

[0029] Fig.16 A circuit for verifying the use of a synthetic independent negative capacitor to cancel a positive capacitor is shown;

[0030] Fig.17A shows the waveforms of input voltage and input current at 50 Hz frequency without synthesizing independent negative capacitance;

[0031] Fig. 17B shows the waveforms of input voltage and input current in the presence of a synthetic independent negative capacitor at a frequency of 50 Hz;

[0032] Fig.18A shows the waveforms of input voltage and input current at a frequency of 100 Hz without synthetic negative capacitance; and

[0033] Fig.18B The waveforms of input voltage and input current in the presence of a synthetic independent negative capacitance at a frequency of 100 Hz are shown. DETAILED DESCRIPTION

[0034] In the following description, the details of the present invention will be described as preferred embodiments. It will be apparent to those skilled in the art that modifications including additions and / or substitutions may be made without departing from the scope and spirit of the present invention. Specific details may be omitted in order not to obscure the present invention; however, the disclosure is written to enable those skilled in the art to practice the teachings herein without undue experimentation.

[0035] Independent negative inductance L n The definition is as follows: Among them, L n <0,v in and i in are the input voltage and input current respectively.

[0036] In the frequency domain, equation (1) can be expressed as: V in (s) = s·L n I in (s), (2)

[0037] Where s = jω, ω = 2πf in , and f in is the frequency of the input AC voltage.

[0038] Equations (1) and (2) show that the impedance of a negative inductor increases linearly with frequency, while the voltage phase lags the current phase by 90°. In other words, the magnitude-frequency response of a negative inductor is the same as that of a positive inductor, while the phase-frequency response of a negative inductor is the same as that of a positive capacitor. Therefore, the characteristics of a negative inductor are different from those of a positive capacitor.

[0039] Independent negative capacitance C n The definition is as follows: Among them, C n <0,v in and i in are the input voltage and input current respectively.

[0040] In the frequency domain, equation (3) can be expressed as: I in (s)=s·C n ·V in (s), (4)

[0041] Where s = jω, ω = 2πf in , and f in is the frequency of the input AC voltage.

[0042] Equations (3) and (4) show that the impedance of a negative capacitor decreases as the frequency increases, while the current phase lags the voltage phase by 90°. In other words, the amplitude-frequency response of a negative capacitor is the same as that of a positive capacitor, while the phase-frequency response of a negative capacitor is the same as that of a positive inductor. Therefore, the characteristics of a negative capacitor are different from those of a positive inductor.

[0043] Figure 1 FIG. 1 is a block diagram of a negative reactance synthesizer 100 according to an embodiment of the present invention. As shown in the figure, the negative reactance synthesizer includes a DC power supply (not shown), a first converter 101 , a second converter 102 , a first control circuit 103 and a second control circuit 104 .

[0044] The DC power supply is used to achieve power balance to avoid abnormal or unstable operation of the synthesizer due to power imbalance caused by the power consumption of the AC voltage source in actual situations.

[0045] The first converter 101 is configured to convert an input current i from an AC input voltage having a peak voltage E in To shape and convert the variable DC voltage into a fixed DC voltage U o The first converter has an input terminal In1 for receiving an AC input voltage and a DC voltage U o The output terminal Out1.

[0046] The second converter 102 is configured to convert the fixed DC voltage U o Converted to superimposed DC voltage V E , superimposed DC voltage V E The second converter 102 has a function of receiving a fixed DC voltage U o The input terminal In2 is used to transmit the superimposed DC voltage V E The output terminal Out2, where the DC voltage V E It must be higher than E to ensure that the input voltage of the first converter 101 is positive.

[0047] Specifically, the first converter 101 may be a direct current-to-direct current (DC-DC) converter capable of converting a variable DC voltage into a fixed DC voltage and having a voltage conversion ratio k subject to the following constraints: 1 :

[0048] The second converter 102 may be a DC-DC converter capable of converting a fixed DC voltage into another fixed DC voltage and having a voltage conversion ratio k subject to the following constraints: 2 :

[0049] The limits on both conversion ratios (the choice of DC-DC converter) depend on U o There are four different cases. E +E>V E >V E -E>U o , the first converter acts as a buck converter and the second converter acts as a boost converter. If V E +E>V E >U o >V E -E, the first converter acts as a buck / boost converter and the second converter acts as a boost converter. E +E>U o >V E >V E-E, the first converter acts as a buck / boost converter and the second converter acts as a buck converter. o >V E +E>V E >V E -E, the first converter acts as a step-up converter and the second converter acts as a step-down converter.

[0050] For example, when E is 5V, V E is 10V and U o When the voltage is 20 V, the first converter 101 is configured as a boost converter, and the second converter 102 is configured as a buck converter.

[0051] The first control circuit 103 is configured to generate a duty cycle d 1 The first gate drive signal V d1 and a duty cycle of 1-d 1 The first complementary gate drive signal V 1-d1 , used to control the first converter.

[0052] The second control circuit 104 is configured to generate a duty cycle d 2 The second gate drive signal V d2 and a duty cycle of 1-d 2 The second complementary gate drive signal V 1-d2 , used to control the second converter.

[0053] Figure 2 shows the definition of the input impedance of a system. The impedance seen from the terminals of a given circuit is defined as the ratio of the voltage across the terminals to the current flowing into and out of the terminals. In the frequency domain, the impedance can be expressed as: Where V in (s) and I in (s) are the input voltage and input current respectively. Therefore, in this equation, Z in (s) is the impedance to be synthesized.

[0054] The first converter 101 and the second converter 102 may be isolated DC-DC converters or non-isolated DC-DC converters.

[0055] Figure 3 FIG. 1 shows a circuit diagram of a first converter 101 according to an embodiment of the present invention. Figure 3 As shown, the first converter 101 includes: a sampling resistor R sense , whose first end is connected to the positive electrode In1+ of the input end of the first converter; a current limiting resistor r L1 , whose first end is connected to the sampling resistor R senseThe second end of the inductor L 1 , whose first end is connected to the current limiting resistor r L1 The second end of the field effect transistor S 1 , whose gate receives the first gate drive signal V d1 , the drain is connected to the inductor L 1 The second end of the field effect transistor S is connected to the negative electrode In1- of the input terminal of the first converter; 2 , whose gate is used to receive the first complementary gate drive signal V 1-d1 , the drain is connected to the positive electrode Out1+ of the output terminal of the first converter, and the source is connected to the inductor L 1 The second end of the first output coupling capacitor C o1 , a first end of which is connected to the positive electrode Out1+ of the output end of the first converter, and a second end of which is connected to the negative electrode Out1- of the output end of the first converter.

[0056] Figure 4 FIG. 4 shows a circuit diagram of a second converter 102 according to an embodiment of the present invention. Figure 4 As shown, the second converter 102 includes: a field effect transistor S 3 , whose gate is used to receive the second gate drive signal V d2 , the drain is connected to the positive electrode In2+ of the input terminal of the second converter; the field effect transistor S 4 , whose gate is used to receive the second complementary gate drive signal V 1-d2 , the drain is connected to the field effect transistor S 3 The source of the inductor L is connected to the negative electrode In2- of the input terminal of the second converter; 2 , whose first end is connected to the field effect transistor S 3 The source of the field effect transistor S 4 The drain of the current limiting resistor r L2 , whose first end is connected to the inductor L 2 The second end of the second output coupling capacitor C is connected to the positive electrode Out2+ of the output end of the second converter; o2 , whose first end is connected to the positive pole Out2+ of the output end of the second converter, and the second end is connected to the negative pole Out2- of the output end of the second converter. The positive pole In2+ of the input end of the second converter is connected to the positive pole Out1+ of the output end of the first converter. The negative pole In2- of the input end of the second converter is connected to the negative pole Out1- of the output end of the first converter. The negative pole Out2- of the output end of the second converter is connected to the negative pole In1- of the input end of the first converter.

[0001] Figure 5The current loop for current shaping control is shown to achieve the desired input voltage and input current amplitude and phase relationship. in The current reference i ref Should come from the input AC voltage v in In the complex frequency domain, i ref and v in The relationship between can be expressed as: I ref (s) = N·V in (s)·G(s), (8) Where N is the sampling gain of the input voltage and G(s) is the transfer function from the sampled input voltage to the current loop reference value.

[0057] If the sampling current M·i in Able to follow with v in The relevant reference signal i ref , then the relationship between the sampling current and the reference signal can be written as follows: M.I in (s)=K(s)·I ref (s), (9) Where M is the sampling gain of the input current.

[0058] In general, K(s) depends on the converter response. However, if the bandwidth of the converter response is much higher than the applied voltage V in bandwidth, we can assume that K(s) is a constant equal to the constant value K, that is, i in with i ref Directly proportional.

[0002] Combining equations (7), (8) and (9), the relationship between the input parameters (input voltage and input current) and the control signal is:

[0059] The first control circuit 103 and the second control circuit 104 may be implemented using general or dedicated analog devices and / or computing devices.

[0060] Figure 6 FIG. 1 is a circuit diagram of a first control circuit 103 according to an embodiment of the present invention. As shown in the figure, the first control circuit 103 includes: a voltage sampler 301, whose gain is N, for sampling an input AC voltage v in Sampling is performed to generate a sampling voltage V sample Active filter 302, having a transfer function G (s), for sampling voltage V sample Determine the type of reactance to be synthesized and generate the input analog signal V g; Multiplier 303, used to input analog signal V g With the first reference signal V ref1 Multiply to generate control signal i ref Current sensor 304, whose gain is N, is used to sense the input current i in To generate the sensing current i sense Current amplifier 305, used to amplify the sensed current i sense With control signal i ref The difference between the two generates the first output signal V o1 ; A first controller 306, for based on the first output signal V o1 Generate a first gate drive signal V d1 ; A first driver 307, for driving a gate based on a first gate drive signal V d1 Generate a first complementary gate drive signal V 1-d1 .

[0061] The current amplifier 305 includes: an error amplifier 308 having a positive input terminal, a negative input terminal and an output terminal; a resistor R 1_a1 , whose first end is connected to the negative input terminal of the error amplifier 308; capacitor C 1_a1 , whose first end is connected to the resistor R 1_a1 The second end of the capacitor C is connected to the output end of the error amplifier 308; 1_a2 , a first end of which is connected to the negative input terminal of the error amplifier 308 , and a second end of which is connected to the output terminal of the error amplifier 308 .

[0062] The first control circuit 103 further includes a resistor R connected between the current sensor 304 and the negative input terminal of the current amplifier 305. 1_f1 and a resistor R connected between the multiplier 303 and the positive input terminal of the current amplifier 305 1_f2 .

[0063] The impedance of an independent negative inductor can be expressed as: Z(s)=s·L n , (11) Where L n is the negative inductance to be synthesized and L n <0.

[0064] Combining equations (10) and (11), the required G(s) is:

[0065] Fig. 7AThe circuit diagram of an active filter 302a for synthesizing an independent negative inductor according to an embodiment of the present invention is shown. As shown in the figure, the active filter 302a has an input terminal and an output terminal, and includes: an error amplifier 3021a having a positive input terminal, a negative input terminal and an output terminal; a resistor R 1 , a first end of which is connected to the input end of the active filter 302a, and a second end of which is connected to the negative input end of the error amplifier; a resistor R 2 , a first end of which is connected to the negative input terminal of the error amplifier, and a second end of which is connected to the output terminal of the error amplifier; and a capacitor C 1 , which is connected to the resistor R 2 in parallel.

[0066] Assumption C 1 and R 2 The value of satisfies: |s·C 1 ·R 2 |>>1. (13)

[0067] Then, G(s) can be expressed as:

[0068] Therefore, the synthetic independent negative inductance (L n ) can be expressed as:

[0069] The impedance of an independent negative capacitor can be expressed as: Among them C n is the negative capacitance to be synthesized, and C n <0.

[0070] Combining equations (10) and (11), the required G(s) is:

[0071] Figure 7B FIG. 3 is a circuit diagram of an active filter 302b for synthesizing an independent negative capacitor according to another embodiment of the present invention. As shown in the figure, the active filter 302b has an input terminal and an output terminal, and includes: an error amplifier 3021b having a positive input terminal, a negative input terminal and an output terminal; a resistor R 3 , a first end of which is connected to the input end of the active filter 302b, and a second end of which is connected to the negative input end of the error amplifier; a resistor R 4 , a first end of which is connected to the negative input terminal of the error amplifier, and a second end of which is connected to the output terminal of the error amplifier; and a capacitor C 2 , which is connected to the resistor R 3 in parallel.

[0072] Assumption C 2 and R 3 The value of satisfies: |s·C 2 ·R 3 |>>1. (18)

[0073] Then, G(s) can be expressed as: G(s)≈-s·C 2 ·R 4 .(19)

[0074] Therefore, the synthetic negative capacitance (C n ) can be expressed as:

[0075] Figure 8 FIG. 1 shows a circuit diagram of a second control circuit 104 according to an embodiment of the present invention. Figure 8 As shown, the second control circuit 104 includes: a voltage sensor 401 for sensing the superimposed DC voltage V E And generate and superimpose DC voltage V E Proportional to the sense voltage V sense ; Voltage amplifier 402, used to amplify the sensing voltage V sense and the second reference signal V ref2 The difference between the two generates a second output signal V o2 ; A second controller 403, for based on the second output signal V o2 Generate a second gate drive signal V d2 ; A second driver 404, for driving a second gate signal V d2 Generate a second complementary gate drive signal V 1-d2 .

[0076] The voltage sensor 401 includes: a first sensing resistor R 2_v1 , a first end of which is connected to the positive electrode of the output terminal of the second converter; and a second sensing resistor R 2_v2 , whose first end is connected to the first sensing resistor R 2_v1 In other words, the first sensing resistor R 2_v1 and the second sensing resistor R 2_v2 Connect in series. Sense voltage V sense The first sensing resistor R 2_v1 and the second sensing resistor R 2_v2 The connection nodes between them.

[0077] The voltage amplifier 402 includes: an error amplifier 405 having a positive input terminal, a negative input terminal and an output terminal; a resistor R 2_a1, whose first end is connected to the negative input terminal of the error amplifier 405; the capacitor C 2_a1 , whose first end is connected to the resistor R 2_a1 The second end of the second terminal is connected to the output end of the error amplifier 405.

[0078] The second control circuit also includes: a resistor R 2_f1 , connected to the reference signal V ref2 Between the negative input terminal of the voltage amplifier; resistor R 2_f2 Connect between the voltage sensor and the positive input of the voltage amplifier.

[0079] Performance Evaluation

[0080] The performance of the prototypes of the negative inductance synthesizer and the negative capacitance synthesizer constructed according to the embodiments of the present invention was evaluated. The key parameters are listed in Table I.

[0081] Table I: Key parameters of the evaluated prototypes

[0082] Fig.9A and 9B The relevant waveform of the synthesized independent negative inductance is shown. The synthesized independent negative inductance value is -29mH. Fig.9A shows the input voltage and input current when the input voltage frequency is 50Hz, and Fig. 9B The input voltage and input current are shown when the frequency of the input voltage is 100 Hz. The peak value of the input voltage is 5 V in both cases. It can be observed that the phase of the input current leads the phase of the input voltage by 90° in both cases.

[0083] Fig.10 The magnitude and phase of the synthetic independent negative inductor impedance measured in the frequency range of 50Hz to 400Hz are shown. The test input voltage peak is 5V. Fig.10 It can be seen that the magnitude of the impedance increases with increasing frequency, and despite the change in frequency, the input current still leads the input voltage by nearly 90°, which meets the definition of negative inductance.

[0084] Fig.11 A circuit is shown to verify the use of a synthetic independent negative inductor to cancel the positive inductor. Fig.11 In, R t1 and R t2 Both are 11Ω, L t1 and L t2 Both are 40mH. nIt is a synthetic independent negative inductor with a value of -29mH. The peak value and frequency of the input voltage are 5V and 50Hz respectively.

[0085] Fig. 12A shows that when the circuit does not contain the synthetic independent negative inductance L n The waveforms of input voltage and input current when V in Represents the input voltage. w Represents no L n When L is not added to the circuit n When , the impedance of the circuit is 16.7Ω and the phase angle is 48.8°. Fig. 12A It can be seen that i w The peak value is about 0.26A, v in Ahead w Nearly 49°, which is consistent with the theoretical analysis.

[0086] Fig. 12B shows that when the circuit contains a synthetic independent negative inductor L n The waveforms of input voltage and input current when V in Represents the input voltage. in Represents the existence of L n When L n With R t2 and L t2 When connected in series, due to L t2 Most of the reactance is L n The impedance of the circuit is 11.5Ω and the phase angle is 17.4°. Fig. 12A It can be seen that i in The peak value is about 0.45A, v in Ahead in This indicates that the synthesized independent negative inductance can successfully offset the positive inductance.

[0087] Fig.13A and Fig. 13B The input voltage and input current waveforms are shown when a synthetic independent negative inductor is used to cancel the positive inductor. Verify that the circuit and all inductor values ​​are consistent with Fig.11 Same as given in R t1 and R t2 Both are 20Ω, the synthetic independent negative inductor L n The peak value and frequency of the input voltage are 5V and 100Hz respectively.

[0088] Fig.13A The circuit shown does not include the synthetic negative inductance L n The waveforms of input voltage and input current under the condition of V in Represents the input voltage. wRepresents the existence of L n When L is not added to the circuit n When , the impedance of the circuit is 32.1Ω and the phase angle is 51.5°. Fig.13A It can be seen that i w The peak value is about 0.15A, v in Ahead w Nearly 50°, which is consistent with the theoretical analysis.

[0089] Fig. 13B shows that when the circuit contains a synthetic independent negative inductor L n The waveforms of input voltage and input current under the condition of V in Represents the input voltage. in Represents the existence of L n When L n With R t2 and L t2 When connected in series, due to L t2 Most of the reactance has been n The impedance of the circuit is 21.2Ω, and the phase angle is 19°. Fig. 13B As you can see, in The peak value is about 0.23A, v in Ahead in 19°. This indicates that the synthesized independent negative inductance can successfully cancel the positive inductance.

[0090] Fig.14A and 14B The waveform of the synthesized independent negative capacitance is shown. The synthesized independent negative capacitance value is -140μF. Fig.14A shows the input voltage and input current when the input voltage frequency is 50Hz, and Fig. 14B The input voltage and input current are shown when the frequency of the input voltage is 100 Hz. The peak value of the input voltage is 5 V in both cases. It can be observed that the phase of the input voltage leads the phase of the input current by 90° in both cases.

[0091] Fig.15 The impedance magnitude and phase angle of the synthetic independent negative capacitance impedance measured in the frequency range of 50Hz to 400Hz are shown. The test input voltage peak is 5V. Fig.15 It can be seen that the magnitude of the impedance decreases as the frequency increases, and despite the change in frequency, the phase of the input voltage still leads the phase of the input current by approximately 90°, which meets the definition of negative capacitance.

[0092] Fig.16 A circuit is shown for verifying the use of a synthetic independent negative capacitor to cancel a positive capacitor. Fig.16 In, Rt1 and R t2 Both are 25Ω, R s1 and R s2 Both are 2Ω, C t1 and C t2 The synthesized independent negative capacitor C n The peak value and frequency of the input voltage are 5V and 50Hz respectively.

[0093] Fig.17A shows that the independent negative capacitance C is not included in the synthesis n The waveforms of input voltage and input current under the condition of V in Represents the input voltage. w Represents the absence of C n When C is not added to the circuit n When the impedance of the circuit is about 17.7Ω, the phase angle is -45°. Fig.17A It can be seen that w The peak value is about 0.29A, i w Advance v in Nearly 45′, which is consistent with the theoretical analysis.

[0094] Fig. 17B shows the synthesis of independent negative capacitance C n The waveforms of input voltage and input current under the condition of V in Represents the input voltage. in Represents the existence of C n When C n With R t2 and C t2 When connected in parallel, due to C t2 Most of the reactance has been n The circuit impedance is about 27Ω and the phase angle is -3°. Fig. 17B It can be seen that in The peak value is about 0.2A, V in and i in The phases of are almost synchronized. This indicates that the synthesized independent negative capacitors can successfully offset the positive capacitors.

[0095] Fig.18A and Fig.18B The waveforms of the input voltage and input current are shown when a synthetic independent negative capacitor is used to cancel the positive capacitor. Verify that the circuit and the values ​​of all resistors and capacitors are the same as Fig.16 The synthesized independent negative capacitance C n is -140μF. The peak value and frequency of the input voltage are 5V and 100Hz respectively.

[0096] Fig.18Ashows that the independent negative capacitance C is not included in the synthesis n The waveforms of input voltage and input current under the condition of V in Represents the input voltage. w Represents the absence of C n When C is not added to the circuit n When , the impedance of the circuit is 10.9Ω and the phase angle is -57°. Fig.18A It can be seen that w The peak value is about 0.48A, i w Advanced V in Nearly 55°, which is consistent with the theoretical analysis.

[0097] Fig.18B shows the synthesis of independent negative capacitance C n The waveforms of input voltage and input current under the condition of V in Represents the input voltage. w Represents the absence of L n When C n With R t2 and Ct 2 When connected in parallel, due to Ct 2 Most of the reactance has been n The circuit impedance is 27Ω and the phase angle is -6°. Fig.18B It can be seen that in The peak value is about 0.2A, v in and i in The phases of are almost synchronized. This indicates that the synthesized independent negative capacitors can successfully offset the positive capacitors.

[0098] Although described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. The illustrations are not necessarily drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the illustrations of the present disclosure and the actual device. The present invention may also have other embodiments, which are not described in detail here. The embodiments of the present invention may be modified to adapt to the purpose and scope of the present disclosure in response to specific circumstances, materials, material compositions, methods or processes. All these modifications are within the scope of the attached claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless otherwise specified herein, the order and grouping of operations are not limited.

Claims

1. A negative reactance synthesizer, comprising: DC power supply; A first converter is configured to implement input current shaping at an AC input voltage with a given peak value E and convert a variable DC voltage into a fixed DC voltage U o ; The second converter is configured to convert the fixed DC voltage U o Converted to superimposed DC voltage V E ; wherein the superimposed DC voltage V E is greater than the peak value E of the AC input voltage and is superimposed on the AC input voltage to form the variable DC voltage; a first control circuit configured to generate a first gate drive signal and a first complementary gate drive signal for controlling the first converter; as well as a second control circuit configured to generate a second gate drive signal and a second complementary gate drive signal for controlling the second converter; as well as in: When V E +E>V E >V E -E>U o When the condition is , the first converter acts as a buck converter and the second converter acts as a boost converter; When V E +E>V E >U o >V E -E condition, the first converter acts as a buck-boost converter, and the second converter acts as a boost converter; When V E +E>U o >V E >V E -E, the first converter acts as a buck-boost converter and the second converter acts as a step-down converter; or When U is satisfied o >V E +E>V E >V E -E condition, the first converter acts as a boost converter and the second converter acts as a buck converter.

2. The negative reactance synthesizer according to claim 1, characterized in that The first converter has an input terminal for receiving the AC input voltage and a DC voltage U o The output terminal of the converter comprises: Sampling resistor R sense , a first end of which is connected to the positive electrode of the input end of the first converter; Current limiting resistor r L1 , whose first end is connected to the sampling resistor R sense The second end of The inductor L1 has its first end connected to the current limiting resistor r L1 The second end of a field effect transistor S1, whose gate is configured to receive the first gate driving signal, whose drain is connected to the second end of the inductor L1, and whose source is connected to the negative electrode of the input end of the first converter; a field effect transistor S2, whose gate is configured to receive the first complementary gate drive signal, whose drain is connected to the positive terminal of the output terminal of the first converter, and whose source is connected to the second terminal of the inductor L1; and Output coupling capacitor C o1 , a first end of which is connected to the positive electrode of the output end of the first converter, and a second end of which is connected to the negative electrode of the output end of the first converter.

3. The negative reactance synthesizer according to claim 1, characterized in that The second converter has a circuit for receiving the fixed DC voltage U o The input terminal is used to transmit the superimposed DC voltage V E The output terminal of the second converter comprises: a field effect transistor S3, whose gate is configured to receive the second gate driving signal and whose drain is connected to the positive electrode of the input terminal of the second converter; a field effect transistor S4, whose gate is configured to receive the second complementary gate drive signal, whose drain is connected to the source of the field effect transistor S3, and whose source is connected to the negative electrode of the input terminal of the second converter; an inductor L2, a first end of which is connected to the source of the field effect transistor S3 and the drain of the field effect transistor S4; Current limiting resistor r L2 , a first end of which is connected to the second end of the inductor L2, and a second end of which is connected to the positive electrode of the output end of the second converter; and Output coupling capacitor C o2 , a first end of which is connected to the positive electrode of the output end of the second converter, and a second end of which is connected to the negative electrode of the output end of the second converter.

4. The negative reactance synthesizer according to claim 1, characterized in that The first control circuit comprises: A voltage sampler having a gain of N and configured to sample an input AC voltage to generate a sampled voltage; an active filter having a transfer function and configured to determine the type of reactance to be synthesized based on the sampled voltage and generate an input analog signal; a multiplier configured to multiply the input analog signal by a first reference signal to generate a control signal; a current sensor having a gain of N and configured to sense the input current to generate a sense current; a current amplifier configured to amplify a difference between the sense current and the control signal to generate a first output signal; a first controller configured to generate the first gate driving signal based on the first output signal; The first driver is configured to generate the first complementary gate drive signal based on the first gate drive signal.

5. The negative reactance synthesizer according to claim 4, characterized in that The current amplifier comprises: Error amplifier; Resistor R 1_a1 , a first end of which is connected to the negative input terminal of the error amplifier; Capacitor C 1_a1 , whose first end is connected to the resistor R 1_a1 A second end of the error amplifier is connected to the output end of the error amplifier; Capacitor C 1_a2 , a first end of which is connected to the negative input terminal of the error amplifier, and a second end of which is connected to the output terminal of the error amplifier.

6. The negative reactance synthesizer according to claim 4, characterized in that The active filter comprises: Error amplifier; A resistor R1, a first end of which is connected to the input end of the active filter, and a second end of which is connected to the negative input end of the error amplifier; a resistor R2, a first end of which is connected to the negative input terminal of the error amplifier, and a second end of which is connected to the output terminal of the error amplifier; and A capacitor C1 is connected in parallel with the resistor R2.

7. The negative reactance synthesizer according to claim 4, characterized in that The active filter comprises: Error amplifier; A resistor R3, a first end of which is connected to the input end of the active filter, and a second end of which is connected to the negative input end of the error amplifier; a resistor R4, a first end of which is connected to the negative input terminal of the error amplifier, and a second end of which is connected to the output terminal of the error amplifier; and A capacitor C2 is connected in parallel with the resistor R3.

8. The negative reactance synthesizer according to claim 4, characterized in that The first control circuit further includes: Resistor R 1_f1 , which is connected between the current sensor and the negative input terminal of the current amplifier; and Resistor R 1_f2 , which is connected between the multiplier and the positive input terminal of the current amplifier.

9. The negative reactance synthesizer according to claim 1, characterized in that The second control circuit comprises: A voltage sensor configured to sense the superimposed DC voltage V E And generate a superimposed DC voltage V E Proportional sense voltage; a voltage amplifier configured to amplify a difference between the sensing voltage and a second reference signal and generate a second output signal; a second controller configured to generate the second gate driving signal based on the second output signal; A second driver is configured to generate the second complementary gate drive signal from the second gate drive signal.

10. The negative reactance synthesizer according to claim 9, characterized in that The voltage sensor comprises: Sense resistor R 2_v1 , a first end of which is connected to the positive electrode of the output end of the second converter; and Sense resistor R 2_v2 , whose first end is connected to the sensing resistor R 2_v1 the second end of The sensing voltage is generated across the sensing resistor R 2_v1 and the sensing resistor R 2_v2 The connection nodes between them.

11. The negative reactance synthesizer according to claim 9, characterized in that The voltage amplifier comprises: Error amplifier; Resistor R 2_a1 , a first end of which is connected to the negative input terminal of the error amplifier; Capacitor C 2_a1， Its first end is connected to the resistor R 2_a1 A second end thereof is connected to the output end of the error amplifier.

12. The negative reactance synthesizer according to claim 11, characterized in that The second control circuit further includes: Resistor R 2_f1 , which is connected between the second reference signal and the negative input terminal of the voltage amplifier; and Resistor R 2_f2 , which is connected between the voltage sensor and the positive input terminal of the voltage amplifier.

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