Digital filter structure based on FPGA

Abstract

The invention relates to the technical field of digital filters, and provides a digital filter structure based on an FPGA. According to the structure, a Radix-4Booth multiplier structure and a DA algorithm idea are combined, and the structure comprises a multiplier coding generator, a partial product generation superposition unit and a shift accumulator. Wherein the multiplier code generator generates a three-bit coefficient for generating a partial product; the partial product generation and superposition unit obtains a partial product according to the three-bit coefficient and the input data, and superposes the partial product with a previous-level intermediate result to obtain a current-level intermediate result; the shift accumulator achieves shift summation of the sum of the partial products. Compared with a traditional structure, the clock cycle number is shortened, hardware resources are reduced, and the comprehensive performance index advantage is obvious.

Description

Technical Field

[0001] The present invention relates to the technical field of digital filters, and in particular to a digital filter structure on an FPGA and a construction method thereof. Background Art

[0002] At present, digital filter is a key technology in the field of digital signal processing. It is mainly used to weaken useless information or enhance useful information from the input signal. With the development of information technology, digital filters are more and more widely used, such as in audio processing, image processing, communication systems, etc.

[0003] Digital filters can be divided into infinite impulse response (IIR) filters and finite impulse response (FIR) filters according to the properties of their impulse response. Compared with IIR filters, FIR filters have better linear phase characteristics, strong stability, and hardware implementation.

[0004] FPGA-based FIR filter is one of the more popular research directions in the field of digital signal processing. As important components of FIR filter, adder and multiplier, their speed, area and other performance directly affect the overall performance of the filter.

[0005] Distributed Algorithm (DA) is often used in the optimization design of FIR filters. This algorithm splits the input digital signal bit by bit and converts the multiplication and addition operation with fixed coefficients into a simple lookup table operation and shift-accumulation operation.

[0006] For an FIR filter consisting of N product terms, its output y is the product of the input x. k and coefficient w k The sum of the products of :

[0007] Among them, w k and x k (0≤k≤N-1) represent the kth coefficient and the corresponding input respectively; for a coefficient w with a bit width of L k , which can be expressed as:

[0008] w kl Yes k The value of the lth bit of . Therefore, the output y can be expanded as:

[0009] The partial product y in the above formula l There are N inputs x k And the corresponding coefficient w k The kth bit w klThe sum of the products of (k=0, 1...N-1), for the partial product y l Perform shift accumulation to obtain the output y.

[0010] The Booth multiplier is an efficient signed multiplier widely used in hardware design. Its basic principle is to combine multiple basic multiplication operations into a relatively more complex operation by encoding the multiplier, and reduce the number of required additions by reducing the number of partial products. The Radix-4Booth multiplier is an extension of the traditional Booth multiplier. It encodes the multiplier in groups of 3 bits. Taking 8-bit multiplication as an example, let the multiplier be B, and its expansion is:

[0011] According to the expansion of B above, we can get The partial product A×(-2b 2i+1 +b 2i +b 2i-1 ) and the multiplier code {b 2i+1 , b 2i , b 2i-1 The corresponding relationship of} is shown in Table 1: Table 1 Correspondence between multiplier coding and partial product Summary of the invention

[0012] The present invention proposes a novel digital filter structure that combines the Radix-4Booth multiplier structure with the DA algorithm concept, and implements it using the FPGA of Xilinx. The present invention shortens the number of clock cycles used by the traditional DA algorithm and reduces the required hardware resources.

[0013] The algorithm proposed in the present invention substitutes the Radix-4Booth expansion of the multiplier into the FIR filter output formula, and the specific formula is as follows:

[0014] Among them, N represents the number of product terms contained in the FIR filter, and M represents the coefficient w k The bit width, is the partial product x k ·(-2w k [2i+1]+w k [2i]+w k [2i-1]).

[0015] Figure 1 The structure diagram of the filter of the present invention is given;

[0016] like Figure 1 As shown, the present invention includes three parts: a multiplier code generator, a partial product generation and superposition unit, and a shift accumulator.

[0017] The multiplier code generator is used to generate the three-digit coefficient {w k [2i+1],w k [2i],w k [2i-1]};

[0018] The partial product generation and superposition unit consists of three coefficients {w k [2i+1],w k [2i],w k [2i-1]}、input data x k Get the partial product and compare it with the intermediate result y of the previous level k-1 The intermediate result y of this level is obtained by superposition k ;

[0019] Figure 1 As shown in n-1 It is the sum of the partial products;

[0020] The shift accumulator is used to implement the shift sum of the partial product sums. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural diagram of the FIR filter of the present invention;

[0022] Figure 2 It is a structural diagram of a multiplier code generator of the present invention;

[0023] Figure 3 A structural diagram of the superposition unit for partial product generation of the present invention. DETAILED DESCRIPTION

[0024] In order to make the structure, technical solution and advantages of the invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0025] Figure 2 The structural diagram of the three-digit coefficient generation part is given;

[0026] like Figure 2 As shown, two LUT6-2 (six-input and two-output lookup tables in Xilinx FPGA) are configured as two-output 32-bit shift registers, where Q is the output of the 0th bit of the shift register and Q31 is the output of the 32nd bit of the shift register. The number {{w k[2i+1]}, the shift register 2 stores the number of the even-numbered bits of the coefficient Therefore, the Q31 terminal of shift register 1 and the Q and Q31 ports of shift register 2 generate the required three-bit coefficient {w k [2i+1],w k [2i],w k [2i-1]}.

[0027] Figure 3 The structural diagram of the partial product generation superposition unit is given;

[0028] like Figure 3 As shown, the partial product generation and superposition unit is composed of multiple LUT6-2 and CARRY (carry chain structure in Xilinx FPGA); the input of LUT6-2 is three-bit coefficient, input x k [n] and the previous intermediate result y k-1 [n]; the output of CARRY is the intermediate result y of this level k [n] (where k represents the kth product term and n represents the nth bit of the input and output signals). The sum of partial products can be obtained by cascading multiple partial product generation superposition units (the number of cascaded FIR filters contains the number of product terms);

[0029] Because the three-bit coefficients are updated with each clock cycle, a new sum of partial products is obtained every clock cycle.

[0030] Figure 1 The shift accumulator in the previous clock cycle shifts the accumulated result right by two bits and then accumulates it with the sum of the partial products of the current clock cycle. The above process is repeated times until the final result is obtained, which is the output of the FIR filter.

[0031] In order to further demonstrate the advantages of the structure of the present invention, the structure proposed by the present invention and the formula in

[0006] are designed and implemented using hardware description language. The corresponding direct implementation structure is then synthesized to calculate a comprehensive performance indicator of "consumed LUT number * number of cycles used for operation * maximum path delay". Among them, the fewer LUTs consumed, the less hardware resources consumed, and the smaller the number of cycles used for operation and the smaller the maximum path delay, the faster the operation speed. Therefore, the smaller the "consumed LUT number * number of cycles used for operation * maximum path delay", the better the comprehensive performance of the corresponding circuit.

[0032] Table 2 summarizes the performance of the structure of the present invention for different numbers of product terms and filter coefficients (w k ) and input data (x k )-bit-width FIR filter realizes the comprehensive performance of the circuit ("the number of LUTs consumed * the number of cycles used for operation * the maximum path delay"). Table 2 Comprehensive performance of the circuit structure of the present invention

[0033] Table 3 summarizes the direct implementation structure of FIR filter for different numbers of product terms and filter coefficients (w k ) and input data (x k )-bit-width FIR filter realizes the comprehensive performance of the circuit ("the number of LUTs consumed * the number of cycles used for operation * the maximum path delay"). Table 3 Comprehensive performance of FIR filter direct implementation structure circuit

[0034] By comparing the statistical results in Table 2 and Table 3, it can be seen that the comprehensive performance of the structure proposed in the present invention has obvious advantages, and the advantages increase significantly with the increase of the order.

[0035] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A digital filter structure based on FPGA, characterized in that: The digital filter realizes a structure that combines the Radix-4Booth multiplier structure with the DA algorithm concept, and includes three parts: a multiplier code generator, a partial product generation and superposition unit, and a shift accumulator. Compared with the traditional structure, the digital filter structure uses fewer clock cycles, consumes less hardware resources, and has obvious advantages in comprehensive performance indicators.

2. The multiplier code generator according to claim 1, characterized in that: It consists of two LUT6-2 configured as 32-bit shift registers; it is used to generate three-bit coefficients used to generate partial products in the above structure.

3. The partial product generation and superposition unit according to claim 1, characterized in that: It is composed of multiple LUT6-2 and CARRY; Its function is to obtain partial products based on three-digit coefficients and input data, and to superimpose them with the intermediate results of the previous level; the sum of the partial products can be obtained by cascading multiple partial product generation superposition units.

4. The shift accumulator according to claim 1, characterized in that: It is used to accumulate the sum of the partial products of the accumulated result of the previous clock cycle after shifting it right by two bits with the current clock cycle.

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