Cmos-based large delay chip

Abstract

The application provides a CMOS-based large-delay chip, which comprises a substrate and a delay circuit. The delay circuit comprises at least one delay unit, a plurality of delay units are connected in turn in a binary weight cascade structure, a low-noise amplifier is connected between a target delay unit and a next delay unit, and the delay unit and the low-noise amplifier are arranged on the substrate. The delay unit comprises four transistors, a delay state and a reference state. The reference state comprises a first inductor, and the two ends of the first inductor are connected with a first transistor and a second transistor respectively. The delay state comprises a delay line, and the two ends of the delay line are connected with a third transistor and a fourth transistor respectively. The first transistor is connected with the third transistor, and the second transistor is connected with the fourth transistor. In the delay unit, the delay line of a low-delay unit is arranged in the body of the low-delay unit, and the delay line of a high-delay unit is arranged on the substrate. The delay time can be increased, the loss in the working frequency band can be reduced, and the problems of short delay time and large loss fluctuation of the delay chip are solved.

Description

Technical Field

[0001] This application relates to the field of delay technology, and in particular to a CMOS-based long delay chip. Background Technology

[0002] True-Time Delay (TTD) circuits have wide applications in fields such as electronic communications. For example, phased array radars need to control the beam direction by adjusting the delay of the signals transmitted by each array element. The main delay technologies for TTDs include non-silicon delay and silicon delay. Compared to non-silicon technologies such as gallium arsenide (GaAs), silicon-based delay chips have advantages such as mature technology, low cost, high integrability, and strong compatibility. However, due to its relatively low electron mobility and other drawbacks, it results in higher insertion loss and power consumption when implementing TTD circuits.

[0003] For example, in some delay structures based on Complementary Metal Oxide Semiconductor (CMOS) technology, signal delay is mainly adjusted by introducing single-pole double-throw (SPDT) switches or trombone structures, with delay units often composed of Artificial Transmission Lines (ATLs). One inherent drawback of the trombone structure is that loss increases with the selection of longer delay states, leading to variations in loss across different delay states. Therefore, each state switch requires an amplifier, increasing the delay chip area and power consumption. Furthermore, with relatively small TTD delays, ATL structures introduce more operating bandwidth limitations and greater in-band loss variability when facing larger delay requirements. Summary of the Invention

[0004] This application provides a CMOS-based long delay chip to solve the problems of short delay time and large loss fluctuation in delay chip.

[0005] This application provides a CMOS-based long delay chip, comprising: a substrate and a delay circuit, wherein the delay circuit includes at least one delay unit, and multiple delay units are sequentially connected in a binary weighted cascade structure, wherein a low-noise amplifier is connected between a target delay unit and the next delay unit, the target delay unit being the delay unit whose loss reaches a loss threshold, and the delay unit and the low-noise amplifier are disposed on the substrate;

[0006] The delay unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a delay state, and a reference state. The reference state includes a first inductor, with its two ends connected to the drain of the first transistor and the source of the second transistor, respectively. The delay state includes a delay line, with its two ends connected to the drain of the third transistor and the source of the fourth transistor, respectively. The source of the first transistor is connected to the source of the third transistor, and the drain of the second transistor is connected to the drain of the fourth transistor.

[0007] The delay unit includes a low delay unit and a high delay unit. The delay line of the low delay unit is disposed within the low delay unit body, and the delay line of the high delay unit is disposed on the substrate.

[0008] By placing the delay lines of the low-delay unit within the low-delay unit body, lower on-chip losses can be achieved. By placing the delay lines of the high-delay unit on the substrate, the delay time can be increased, thus generating different delays. By connecting multiple delay units using a binary weighted cascade structure, a longer delay time can be obtained. By placing the low-noise amplifier between the delay units, the overall loss of the delay circuit can be reduced. This solves the problems of short delay time and large loss fluctuations in delay chip.

[0009] In some feasible implementations, the number of delay units is seven, the target delay unit is the fourth delay unit, and the low-noise amplifier is disposed between the fourth and fifth delay units. When the number of delay units in the delay circuit is seven, a longer delay time can be achieved while minimizing signal loss, and the large delay chip can also be kept in a small size.

[0010] In some feasible implementations, the delay time of the low-latency unit is less than or equal to 24 ps, and the delay time of the high-latency unit is greater than or equal to 48 ps.

[0011] In some feasible implementations, the delay line includes a microstrip line and a stripline, wherein the delay line of the low-delay unit is the microstrip line, and the delay line of the high-delay unit is the stripline.

[0012] In some feasible implementations, the microstrip lines within the low-latency unit are disposed on an on-chip high-layer metal layer. By disposing the microstrip lines on an on-chip high-layer metal layer, the on-chip losses of the delay lines can be reduced.

[0013] In some feasible embodiments, the thickness of the substrate is 300μm to 310μm, the linewidth of the stripline on the substrate ranges from 30μm to 40μm, and the spacing between two adjacent striplines ranges from 30μm to 40μm. By reducing the thickness of the substrate and reducing the linewidth and spacing of the striplines, the loss of the delay circuit can be reduced, and the area of ​​the large delay chip can also be reduced.

[0014] In some feasible implementations, the substrate is made of a low-loss dielectric material, specifically HL972LFG-LD, to further reduce the losses of the delay circuit.

[0015] In some feasible implementations, the reference state further includes a resistor and a first capacitor. The first capacitor is connected in parallel across the two ends of the first inductor, and the resistor is also connected in parallel across the two ends of the first inductor. One end of the resistor is connected to the first inductor, and the other end of the resistor is connected to one end of the first capacitor. The other end of the first capacitor is grounded. By connecting the first capacitor in parallel across the first inductor, a π-shaped equalization circuit is formed, which can adjust the loss within the operating frequency band while ensuring impedance matching. The parallel first capacitor can also fix the DC operating level of the delay unit circuit and reduce the conduction loss of the transistor. Furthermore, by reducing the use of inductors, the area of ​​the large delay chip can also be reduced.

[0016] In some feasible implementations, the input and output terminals of the delay unit and the two ends of the delay line are respectively impedance matched; the delay state also includes a second inductor, and the two ends of the delay line are respectively connected to the second inductor, one end of one of the second inductors is connected to the drain terminal of the third transistor, and the other end is connected to the input terminal of the delay line; one end of the other second inductor is connected to the output terminal of the delay line, and the other end is connected to the source terminal of the fourth transistor, and the second inductor is used for impedance matching.

[0017] In some feasible implementations, the delay circuit further includes a second capacitor, and the second capacitor is provided between the input terminal of the delay circuit and the first delay unit, and between the output terminal of the delay circuit and the last delay unit.

[0018] This application provides a CMOS-based long-delay chip, comprising: a substrate and a delay circuit. The delay circuit includes at least one delay unit, and multiple delay units are sequentially connected in a binary weighted cascade structure. A low-noise amplifier is connected between the target delay unit and the next delay unit. The delay units and the low-noise amplifier are disposed on the substrate. Each delay unit includes four transistors, a delay state, and a reference state. The reference state includes a first inductor, with its two ends connected to the drain of the first transistor and the source of the second transistor, respectively. The delay state includes a delay line, with its two ends connected to the drain of the third transistor and the source of the fourth transistor, respectively. The source of the first transistor is connected to the source of the third transistor, and the drain of the second transistor is connected to the drain of the fourth transistor. The delay unit includes low-delay units and high-delay units. The delay line of the low-delay unit is disposed within the low-delay unit body, and the delay line of the high-delay unit is disposed on the substrate. By cascading multiple delay units, setting the delay lines of high-delay units on the substrate, and placing a low-noise amplifier between the target delay unit and the next delay unit, the delay time can be increased and the loss within the operating frequency band can be reduced. Attached Figure Description

[0019] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a CMOS-based long-delay chip structure provided in an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the delay unit circuit provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram illustrating the delay fluctuations generated by different gear positions in an embodiment of this application.

[0023] Figure 4 A schematic diagram of a delay chip structure based on GaAs technology provided in an embodiment of this application;

[0024] Figure 5 A schematic diagram of a delay chip structure based on 28nm CMOS technology provided for an embodiment of this application;

[0025] Figure 6 A schematic diagram of a delay chip structure based on 40nm bulk CMOS technology provided for an embodiment of this application.

[0026] Illustration:

[0027] Among them, 100-substrate; 201-low delay unit; 202-high delay unit; 203-delay line; 300-low noise amplifier. Detailed Implementation

[0028] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application as detailed in the claims.

[0029] In some CMOS-based delay structures, signal delay is primarily adjusted by introducing single-pole double-throw (SPDT) switches or trombone structures, with delay units often composed of ATLs (Automatic Time Limiters). One inherent drawback of the trombone structure is that loss increases with longer delay states, leading to variations in loss across different delay states. Therefore, each state switch requires an amplifier, increasing the delay chip area and power consumption. Furthermore, TTD (Time Limit Tolerant) delays are relatively small, and ATL structures introduce more operating bandwidth limitations and greater in-band loss variability when facing larger delay requirements.

[0030] To address the issues of short delay times and large power consumption fluctuations in delay chip solutions, this application provides a CMOS-based long delay chip. (See also...) Figure 1 , Figure 1 Taking seven delay units as an example, the large delay chip is illustrated. The large delay chip includes a substrate 100 and a delay circuit. The delay circuit includes at least one delay unit. Multiple delay units are connected in sequence using a binary weighted cascade structure. A low-noise amplifier 300 is connected between the target delay unit and the next delay unit. The delay unit and the low-noise amplifier 300 are disposed on the substrate 100.

[0031] During the delay process, each delay unit incurs signal loss. When the loss reaches a threshold, compensation amplification is required. Therefore, the target delay unit is the delay unit where the loss reaches the threshold. A low-noise amplifier (LNA) is used to amplify weak signals and minimize the input-output signal-to-noise ratio. Thus, a low-noise amplifier 300 is placed between the target delay unit and the next delay unit to compensate for the losses incurred by each delay unit and reduce the overall loss of the delay circuit.

[0032] A binary weighted cascaded structure refers to a structure that sequentially connects multiple delay units with different delay times. The output of each delay unit is connected to the input of the next delay unit, thus forming a structure with multiple delay times. These delay times are arranged in binary, such as 6ps, 12ps, 24ps, 48ps, 96ps, etc. Cascading means connecting these delay units in a specific order to add their delay times together. It can be understood that the first delay unit (delay unit 1) is the first-level delay unit, the second delay unit (delay unit 2) is the second-level delay unit, and the Nth delay unit is the Nth-level delay unit.

[0033] In some embodiments, the delay unit may be a delay chip, see [reference needed]. Figure 2 The delay unit includes a first transistor Sr1, a second transistor Sr2, a third transistor Sr3, a fourth transistor Sr4, a delay state, and a reference state. For example... Figure 2 As shown in the dashed box, the reference state includes a first inductor L1, with its two ends connected to the drain of a first transistor Sr1 and the source of a second transistor Sr2, respectively. The delay state includes a delay line 203, with different lengths of delay lines 203 in different delay units to provide different levels of delay time. The two ends of delay line 203 are connected to the drain of a third transistor Sr3 and the source of a fourth transistor Sr4, respectively. The source of the first transistor Sr1 is connected to the source of the third transistor Sr3, and the drain of the second transistor Sr2 is connected to the drain of the fourth transistor Sr4. In some embodiments, the first transistor Sr1, the second transistor Sr2, the third transistor Sr3, and the fourth transistor Sr4 may be MOS switches based on a 65nm CMOS process.

[0034] Figure 2 In this context, Vc is the control signal for the transistor switch; a low level indicates the reference state is on, and a high level indicates the delayed state is on. This is the reverse. By turning on different transistors, the delay state or reference state can be turned on or off. By turning on the delay states of different levels of delay units, different delay times can be obtained. When the delay states of all delay units are turned on, the delay time of the large delay chip reaches its maximum value.

[0035] The delay unit includes a low-delay unit 201 and a high-delay unit 202. The delay line 203 of the low-delay unit 201 is disposed within the body of the low-delay unit 201, and the delay line 203 of the high-delay unit 202 is disposed on the substrate 100. See again. Figure 1The delay lines 1 of the first-level delay unit, 2 of the second-level delay unit, and 3 of the third-level delay unit are all located within the low-delay unit 201, i.e., on-chip. The delay lines 4 of the fourth-level delay unit to 7 of the seventh-level delay unit are located on the substrate 100, i.e. off-chip.

[0036] The large delay chip provided in this application embodiment achieves lower on-chip losses by placing the delay line 203 of the low delay unit 201 within the low delay unit 201 itself. Conversely, by placing the delay line 203 of the high delay unit 202 on the substrate 100, the delay time can be increased, thus generating different delays. By connecting multiple delay units using a binary weighted cascade structure, the delay time can be maximized when all delay units are in their delay states. Furthermore, by placing a low-noise amplifier 300 between the delay units, the overall delay circuit losses can be reduced. This solves the problems of short delay times and large loss fluctuations in delay chip solutions.

[0037] In some embodiments, the number of delay units is seven, and the delay units are connected in a seven-level binary weighted cascade structure. The delay time of the first-level delay unit is 6 ps, the delay time of the second-level delay unit is 12 ps, the delay time of the third-level delay unit (Delay3) is 24 ps, and the delay times of the fourth, fifth, sixth, and seventh-level delay units are 48 ps, 96 ps, 192 ps, and 384 ps, respectively. Adding the delay times of the first-level delay unit to the seventh-level delay unit yields a total delay time of 762 ps.

[0038] Since a delay greater than 6 ps cannot meet the minimum angular resolution requirement of radar phased arrays, and a delay less than 6 ps would be insufficient to achieve a delay time of 6 ps × 127 = 762 ps even with the minimum number of delay stages (7 stages in total, 127 stages). Therefore, the delay time of the first stage delay unit is 6 ps. With a delay time of 762 ps, the electromagnetic wave can travel 2.286 m, meeting the maximum size of the radar antenna that can be manufactured for the specific application scenario. Therefore, the number of delay stages must be at least seven, with a total delay time of 762 ps. While a delay greater than seven stages would increase the total delay time, it would also result in an excessive number of transistors used in the control delay units, leading to excessive signal loss. Experimental data shows that when the number of delay units in the delay circuit is seven, a longer delay time can be achieved with minimal signal loss, while also maintaining a small size for the large delay chip.

[0039] When there are seven delay units, the placement of the low-noise amplifier 300 is problematic. Amplifying too early would cause the signal to become too large and distorted midway, while amplifying too late would cause the signal to attenuate too much, making it more susceptible to noise interference. Therefore, the low-noise amplifier 300 is placed after the delay unit where the loss reaches the loss threshold. In some embodiments, a low-noise amplifier 300 with a gain of 25dB in the 17GHz–22GHz range can be used to compensate for the losses of each delay unit, reducing the impact on the circuit's noise performance and suppressing the 27GHz–32GHz frequency band. Simulation tests show that the performance of the low-noise amplifier 300 precisely meets the loss (20dB) caused by the first four delay units. Therefore, the low-noise amplifier 300 is placed between the fourth and fifth delay units, i.e., the target delay unit is the fourth delay unit.

[0040] In some embodiments, the delay time of the low-latency unit 201 is less than or equal to 24 ps, and the delay time of the high-latency unit 202 is greater than or equal to 48 ps. It is understood that in the embodiments of this application, the first-level delay unit, the second-level delay unit, and the third-level delay unit are low-latency units 201, and the fourth to seventh-level delay units are high-latency units 202.

[0041] The delay line 203 includes microstrip lines and striplines. The delay line 203 of the low-delay unit 201 is a microstrip line, meaning the on-chip delay line 203 is a microstrip line. Compared to striplines, microstrip lines have higher losses. By placing the microstrip line within the low-delay unit 201, the required delay time can be achieved while reducing losses. The microstrip line within the low-delay unit 201 is placed on the on-chip high-layer metal, which is the high-layer metal of the delay chip wafer. By placing the microstrip line on the on-chip high-layer metal, the on-chip loss of the delay line 203 can be reduced. The delay line 203 of the high-delay unit 202 is a stripline, meaning the off-chip delay line 203 is a stripline. Compared to microstrip lines, striplines can provide better signal transmission performance. Therefore, striplines can be placed on the substrate 100 to provide a longer delay time.

[0042] Since placing striplines on substrate 100 increases losses, to reduce the losses of the delay lines in the high-delay cell 202, the thickness of substrate 100 can be reduced to 300μm–310μm, the linewidth of the striplines on substrate 100 reduced to 30μm–40μm, the spacing between adjacent striplines reduced to 30μm–40μm, and the center-to-center distance of the pins can also be reduced. Because the thickness of substrate 100 is reduced, the linewidth and spacing are also reduced, thereby reducing the area of ​​the high-delay chip.

[0043] In some embodiments, the low-loss dielectric material HL972LFG-LD may also be used as the material of the substrate 100 to maintain low insertion loss and good in-band loss flatness while achieving a greater delay time.

[0044] See you again Figure 2 Impedance matching is performed at the input and output terminals of the delay unit and at both ends of the delay line 203 to reduce loss and loss fluctuation. In some embodiments, the impedance matching resistance is 50Ω. Impedance matching at both ends of the delay line 203 can reduce the loss and loss fluctuation caused by the delay line itself. Impedance matching at the input and output terminals of the delay unit can reduce signal reflection in the delay unit circuit. For example, it can make the input reflection coefficient S11 and the output reflection coefficient S22 less than or equal to -15dB, improve signal quality and transmission efficiency, reduce loss and loss fluctuation in the operating frequency band, and also improve the DC operating level of the delay unit circuit. Furthermore, since the external input is adjustable, the conduction loss of the first transistor, the second transistor, the third transistor, and the fourth transistor can also be reduced.

[0045] In some embodiments, the reference state further includes a resistor R and a first capacitor C1. The first capacitor C1 is connected in parallel across the two ends of the first inductor L1, and a resistor R is also connected in parallel across the two ends of the first inductor L1. One end of the resistor R is connected to the first inductor L1, and the other end of the resistor R is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is grounded. By connecting the first capacitor C1 in parallel across the first inductor L1, a π-shaped equalization circuit is formed. This allows adjustment of the loss within the operating frequency band while ensuring 50Ω impedance matching, making it comparable to the loss of the delay state within the operating frequency band. The parallel first capacitor C1 also fixes the DC operating level of the delay unit circuit, reducing the transistor's conduction loss. Furthermore, by reducing the use of inductors, the area of ​​the large delay chip can be reduced.

[0046] The delay state also includes a second inductor L2. The two ends of the delay line 203 are connected to the second inductor L2. One end of one second inductor L2 is connected to the drain of the third transistor Sr3, and the other end is connected to the input of the delay line 203. One end of the other second inductor L2 is connected to the output of the delay line 203, and the other end is connected to the source of the fourth transistor Sr4. As can be seen from the foregoing embodiments, the delay line 203 of the high-delay unit 202 is disposed on the substrate 100. In some embodiments, the delay line 203 and the second inductor L2 can be connected by wire bonding. It is understood that the second inductor L2 is used for impedance matching, and the impedance matching resistance is 50Ω. It should also be noted that the values ​​of the second inductor L2, the resistor R, and the first capacitor C1 are all obtained through electromagnetic modeling simulation.

[0047] See you again Figure 1The delay circuit also includes a second capacitor C2. The second capacitor C2 is provided between the input terminal of the delay circuit and the first delay unit, and between the output terminal of the delay circuit and the last delay unit. The second capacitor C2 can be a voltage-stabilizing capacitor to maintain the stability of the input and output voltages. In some embodiments, a third inductor L3 can also be provided across the second capacitor C2 to more effectively filter out noise and fluctuations in the input and output voltages.

[0048] Refer to Table 1, which shows the delay fluctuation values ​​of the large delay chip under different frequencies and switching states. In Table 1, the numbers 0000000 or 1111111 in each column of the first row represent the switching states from the seventh-level delay unit to the first-level delay unit from left to right, where 0 represents the reference state on and 1 represents the delay state on. Table 1 shows nine typical switching states: 0000000 indicates all delay units are off in their delay states; 0000001 indicates only the first-level delay unit is on in its delay state; 0000010 indicates only the second-level delay unit is on in its delay state; and 1111111 indicates all delay units from the first to the seventh level are on in their delay states. Therefore, it can be understood that 0000000 represents the minimum delay time, and 1111111 represents the maximum delay time.

[0049] Table 1. Delay fluctuation values ​​of long-delay chips under different frequencies and switching states.

[0050]

[0051] As shown in Table 1, the maximum latency fluctuation of the high-latency chip provided in this application embodiment is 3.5 ps. See also... Figure 3 , Figure 3 This diagram illustrates the time delay fluctuations caused by different gear positions. Figure 3 In the table, G0-G127 correspond to the nine switching states in Table 1. G0 corresponds to 0000000, G127 corresponds to 1111111, and G8, G16, G32, and G64 correspond to the delay states where only the fourth, fifth, sixth, and seventh level delay units are activated, respectively. Figure 3 As can be seen from this, the large delay chip of this application can generate a relatively small delay fluctuation when the delay time is large. The smaller the delay fluctuation, the higher the delay accuracy and the more accurate the obtained delay time.

[0052] See Figures 4-6 , Figure 4 The delay chip structure is based on GaAs technology and consists of a cascaded TTD delay unit, a broadband amplifier, and a programmable attenuator. It achieves a 255ps delay with a step size of 1ps in the 6-18GHz range and provides 8-bit delay control. The high-order delay path in the TTD unit is formed by cascaded ATLs. Figure 5The delay chip structure is based on 28nm CMOS technology. A 4-bit broadband switching line TTD operating in the range of 3 to 30 GHz is proposed, which achieves a delay of 4.6-68.5 ps. Cascaded coupled all-pass network (CAPN) and uncoupled all-pass network (NCAPN) are used as delay elements. Figure 6 The delay chip structure is based on 40nm bulk CMOS technology, employing a trombone structure design for a TTD circuit operating in the 5–23 GHz frequency band, with a delay range of 125 ps and a resolution of 3 bits. Each delay unit consists of two ATL segments. Figure 4 The structure is used as comparative example 1. Figure 5 The structure is used as comparative example 2. Figure 6 The structure shown is used as Comparative Example 3, and compared with the large delay chip of this application. See Table 2, which compares the large delay chip containing 7 delay units with delay chip chips of different structures.

[0053] Table 2 Comparison of large delay chips and delay chip chips with different structures

[0054] Large delay chip Comparative Example 1 Comparative Example 2 Comparative Example 3 Frequency (GHz) 17-22 6-18 3-30 5-23 Delay range / steps (ps) 762 / 6 255 / 1 68.5 / * 125 / 17.85 <![CDATA[Chip area (mm 2 )]]> 1.44 20 0.34 0.85

[0055] The large delay chip provided in this application embodiment, when the number of delay units is seven, has a delay step size of 6ps / step in the operating frequency range of 17GHz to 22GHz, and a delay accuracy of ≤±1.75ps under full-state and full-bandwidth conditions. Including position 0, the number of positions can reach 128, with a total delay time of approximately 762ps. Through simulation testing, the loss in the full-position operating frequency band is within the range of -17 to -22.5dB, the loss error is <±3dB under full-state and full-bandwidth conditions, and both the input reflection coefficient S11 and the output reflection coefficient S22 are less than -14dB. The overall die size of the chip is 2mm × 0.72mm (3.3mm × 2.9mm after packaging). As shown in Table 2, compared with the delay chip structure in the comparative example, the large delay chip provided in this application embodiment can maintain a small size while significantly improving the delay time.

[0056] As can be seen from the above technical solutions, this application provides a CMOS-based long-delay chip, including: a substrate 100 and a delay circuit. The delay circuit includes at least one delay unit, and multiple delay units are connected sequentially in a binary weighted cascade structure. A low-noise amplifier 300 is connected between the target delay unit and the next delay unit. The delay unit and the low-noise amplifier 300 are disposed on the substrate 100. The delay unit includes four transistors, a delay state, and a reference state. The reference state includes a first inductor, with its two ends connected to the drain of the first transistor and the source of the second transistor, respectively. The delay state includes a delay line, with its two ends connected to the drain of the third transistor and the source of the fourth transistor, respectively. The source of the first transistor is connected to the source of the third transistor, and the drain of the second transistor is connected to the drain of the fourth transistor. The delay unit includes a low-delay unit 201 and a high-delay unit 202. The delay line of the low-delay unit 201 is disposed within the low-delay unit body, and the delay line of the high-delay unit 202 is disposed on the substrate 100. By cascading multiple delay units, setting the delay line of the high delay unit 202 on the substrate 100, and setting a low noise amplifier 300 between the target delay unit and the next delay unit, the delay time can be increased and the loss in the operating frequency band can be reduced.

[0057] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.

Claims

1. A CMOS-based large delay chip, characterized by, The application relates to a time delay circuit, comprising: a substrate and a time delay circuit, the time delay circuit comprising at least one time delay unit, a plurality of the time delay units being connected in sequence in a binary weight cascade structure, wherein a low noise amplifier is connected between a target time delay unit and a next time delay unit, the target time delay unit being the time delay unit whose loss reaches a loss threshold, the time delay unit and the low noise amplifier being arranged on the substrate; the time delay unit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a delay state and a reference state, the reference state comprising a first inductor, a resistor and a first capacitor, two ends of the first inductor being connected with a drain end of the first transistor and a source end of the second transistor respectively, the two ends of the first inductor being connected with the first capacitor in parallel respectively, the two ends of the first inductor being further connected with the resistor in parallel respectively, one end of the resistor being connected with the first inductor, the other end of the resistor being connected with one end of the first capacitor, the other end of the first capacitor being grounded; the delay state comprising a delay line and a second inductor, two ends of the delay line being connected with a drain end of the third transistor and a source end of the fourth transistor respectively, an input end and an output end of the time delay unit and the two ends of the delay line being impedance matched respectively, the two ends of the delay line being connected with the second inductor respectively, one end of one of the second inductor being connected with the drain end of the third transistor, the other end of the second inductor being connected with the input end of the delay line; one end of the other of the second inductor being connected with the output end of the delay line, the other end of the second inductor being connected with the source end of the fourth transistor, the second inductor being used for impedance matching; a source end of the first transistor being connected with a source end of the third transistor, a drain end of the second transistor being connected with a drain end of the fourth transistor; the time delay unit comprising a low time delay unit and a high time delay unit, the delay line of the low time delay unit being arranged in the low time delay unit body, the delay line of the high time delay unit being arranged on the substrate.

2. The CMOS-based large delay chip of claim 1, wherein, The number of the time delay units is seven, the target time delay unit is the fourth time delay unit, and the low noise amplifier is arranged between the fourth time delay unit and the fifth time delay unit.

3. The CMOS-based large delay chip of claim 1, wherein, The delay time of the low time delay unit is less than or equal to 24ps, and the delay time of the high time delay unit is greater than or equal to 48ps.

4. The CMOS-based large delay chip of claim 1, wherein, The delay line comprises a microstrip line and a strip line, the delay line of the low time delay unit is the microstrip line, and the delay line of the high time delay unit is the strip line.

5. The CMOS-based large delay chip of claim 4, wherein, The microstrip line in the low time delay unit is arranged on an in-die high-layer metal.

6. The CMOS-based large delay chip of claim 4, wherein, The thickness of the substrate is 300-310 mu m, the line width of the strip line on the substrate ranges from 30 mu m to 40 mu m, and the interval between two adjacent strip lines ranges from 30 mu m to 40 mu m.

7. The CMOS-based large delay chip of claim 1, wherein, The material of the substrate is a low-loss dielectric material, and the low-loss dielectric material is HL972LFG-LD.

8. The CMOS-based large delay chip of claim 1, wherein, The delay circuit further comprises a second capacitor, and the second capacitor is arranged between the input end of the delay circuit and the first delay unit and between the output end of the delay circuit and the last delay unit.

Images