High-voltage high-speed push-pull comparator circuit and application thereof

Abstract

The invention discloses a high-voltage high-speed push-pull comparator circuit and application thereof. An input protection circuit is connected with an external input signal, processes the external input signal and then is connected with a differential pre-amplifier; the pre-amplifier is used for primarily amplifying an input signal, converting a high-voltage signal into a low-voltage signal and connecting the high-voltage signal to the low-voltage amplifier; the low-voltage amplifier amplifies the input signal for the second time to generate two output signals; the current feedback circuit is connected with the second output of the low-voltage operational amplifier, generates two signals after processing, and performs feedback control on the NMOS control circuit and the PMOS control circuit respectively; the LDO generates an LVDD and an HGND, the potential of the HGND is connected with the PMOS control circuit, and the LVDD is connected with the low-voltage operational amplifier and the NMOS control circuit. The PMOS control circuit and the NMOS control circuit process output signals of the two-stage operational amplifier circuit into digital logic signals, and the digital signals are processed by the output logic control circuit to control on and off of the PMOS push-pull tube and the NMOS push-pull tube.

Description

Technical Field

[0001] The invention relates to a comparator circuit, in particular to a high-voltage and high-speed push-pull comparator circuit and application thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] High voltage comparators have a wide operating voltage range and voltage comparison range, and are widely used in power management, analog-to-digital conversion, and signal conditioning. They also have important applications in industrial control, automotive electronics, and communications.

[0003] The high-voltage comparator has the function of a low-voltage comparator, that is, by comparing the voltage values ​​of the two input ports, it gives the correct high and low level logic signals at the output stage. In addition, the high-voltage comparator has a wider operating voltage range, and the maximum operating voltage depends on the device's allowable withstand voltage value; the high-voltage comparator also has a wider input common mode range and differential mode signal comparison range, which mainly depends on the power supply voltage value.

[0004] However, the traditional high voltage comparator still has some disadvantages. The traditional high voltage comparator is mainly based on the open drain output structure, such as Figure 1 As shown, an external pull-up resistor is required. Since the open-drain output can only drive the load in the low-level state, the external pull-up resistor provides a high level for charging the output port in the high-level state, which will slow down the rising and falling edge response time of the signal. Under the condition of selecting a suitable pull-up resistor, the output response result of the high-voltage open-drain comparator is as follows Figure 2 As shown. When the output is high, the output DENMOS tube is turned off, and the power supply charges the output port through the pull-up resistor. As the output potential increases, the charging speed slows down and the output potential rising slope decreases; when the output is low, the DENMOS tube is turned on, the gate level is fixed, and the power supply charges the DENMOS through the pull-up resistor. As the output potential decreases, the current passing through the DENMOS increases, causing the falling edge slope to slow down. During the output switching process, since the output stage DENMOS is always in the on state when the output is low, a large current needs to be consumed in high-frequency application scenarios. The specific value of the consumed current depends on the size of the pull-up resistor, so the power consumption utilization rate is reduced.

[0005] In addition, traditional high-voltage comparators generally use a high-voltage device unipolar op amp structure, that is, a unipolar high-voltage op amp plus control logic. Under the same gain conditions, the response bandwidth of the unipolar op amp itself is smaller than that of the multi-stage op amp, and the response speed is slower; and the high-voltage device itself is larger than the low-voltage device, and the parasitic effect is more obvious, making it more difficult to achieve high speed under the same power consumption conditions. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a high-voltage and high-speed push-pull comparator circuit and its application, which can quickly respond to changes in input signals, realize push-pull output, and improve the speed and power consumption utilization of the high-voltage comparator.

[0007] The present invention adopts the following technical solutions to solve the above technical problems:

[0008] A high-voltage and high-speed push-pull comparator circuit comprises: an input protection circuit, a first-stage differential pre-amplifier circuit, a second-stage low-voltage amplifier circuit, a current feedback circuit, a low-dropout linear regulator, a PMOS control circuit, an NMOS control circuit and an output logic control circuit;

[0009] The input protection circuit is connected to two external input signals, and after performing input protection processing on the external input signals, two output signals are obtained and sent to the first-stage differential pre-amplifier circuit; the first-stage differential pre-amplifier circuit preliminarily amplifies the input signal after the input protection processing, and converts the preliminarily amplified signal from high voltage to low voltage, and sends the converted low voltage signal to the second-stage low voltage amplifier circuit; the second-stage low voltage amplifier circuit performs a second amplification on the low voltage signal to obtain two output signals, wherein the first output signal is simultaneously connected to the PMOS control circuit and the NMOS control circuit, and the second output signal is connected to the current feedback circuit;

[0010] The current feedback circuit processes the second output signal and generates two feedback control signals CFB_P and CFB_N, sends CFB_P to the PMOS control circuit to perform feedback control on the PMOS control circuit, and sends CFB_N to the NMOS control circuit to perform feedback control on the NMOS control circuit; the low-voltage difference linear regulator generates a low-voltage power supply potential LVDD with driving capability and higher than the ground potential GND, and provides it to the second-stage low-voltage amplifier circuit and the NMOS control circuit; the low-voltage difference linear regulator also generates a high-voltage domain power supply potential H with driving capability and lower than the power supply voltage VDD GND, and provide it to the PMOS control circuit; the power supply voltage VDD is connected to the PMOS control circuit, and the ground potential GND is connected to the NMOS control circuit; the PMOS control circuit processes the first output signal, obtains a PMOS push-pull output control signal and sends it to the output logic control circuit; the NMOS control circuit processes the first output signal, obtains an NMOS push-pull output control signal and sends it to the output logic control circuit; the output logic control circuit performs logic processing on the PMOS and NMOS push-pull output control signals, and then controls the conduction and shutdown of the PMOS and NMOS push-pull tubes.

[0011] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0012] 1. The present invention uses a two-stage operational amplifier circuit to amplify the input over-drive voltage, including a first-stage high-voltage differential pre-amplifier circuit and a second-stage low-voltage amplifier circuit. Compared with the traditional unipolar high-voltage operational amplifier, the two-stage operational amplifier itself has a larger bandwidth and a faster speed.

[0013] 2. The first output terminal of the second-stage low-voltage amplifier circuit of the present invention controls the on and off of MN10 and MN11 at the same time, and the current feedback circuit controlled by the second output terminal controls the current mirror of the PMOS control circuit and the current mirror of the NMOS control circuit to have the same path length, so that the output logic response time of the PMOS control circuit and the output logic response time of the NMOS control circuit are the same. This avoids the formation of a current path from the power supply to the ground when the output logic is reversed due to the asynchronous response of the gate potential of the push-pull output PMOS and NMOS tubes, thereby increasing the dynamic power consumption of the push-pull comparator.

[0014] 3. The second-stage low-voltage amplifier circuit of the present invention adopts a low-voltage structure. Compared with traditional DEMOS devices, the low-voltage device has a smaller size, smaller parasitic capacitance, and higher characteristic frequency under the same gm. It is easier to achieve high-speed amplification effect under the same power consumption, so the response speed is faster.

[0015] 4. The present invention uses LDO to generate HGND and LVDD potentials, and separates the working voltage domains of the output push-pull tubes PMOS and NMOS. First, the logic signal voltage domain is separated so that the logic signal swings within a small range, which improves the speed of the logic signal flip response, thereby improving the speed of the comparator. Secondly, since the output tube DEMOS uses a thin gate oxide device, the gate control potential needs to be below 5V, and the smaller logic level swing ensures that the output tube push-pull output control signal operates within the safe range of the output tube gate withstand voltage.

[0016] 5. The present invention uses a current feedback circuit to control the PMOS control circuit and the NMOS control circuit. When the first output logic of the secondary operational amplifier is at a high or low level, the second output logic controls the current mirror current to decrease or increase. The current mirror MN12 of the PMOS control circuit and the current mirror MN7 of the NMOS control circuit are reduced or increased through the current mirror image, thereby improving the utilization rate of the internal power consumption of the comparator under high-speed working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a traditional high voltage open drain comparator structure;

[0018] Figure 2 It is the output response of a traditional high voltage open drain comparator;

[0019] Figure 3 It is a structural block diagram of a high-voltage and high-speed push-pull comparator of the present invention;

[0020] Figure 4This is a circuit diagram of a high-voltage and high-speed push-pull comparator of the present invention;

[0021] Figure 5 It is the output response of the high-voltage and high-speed push-pull comparator of the present invention. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0023] like Figure 3 As shown, the present invention provides a high-voltage and high-speed push-pull comparator, including: an input protection circuit, a first-stage high-voltage differential amplifier circuit, a second-stage low-voltage amplifier circuit, a current feedback circuit, a low-dropout linear regulator (LDO), a PMOS control circuit, an NMOS control circuit, and an output logic control circuit.

[0024] The input protection circuit is connected to the external input signal, and after processing the input signal, it is connected to the first-stage high-voltage differential pre-amplifier circuit; the pre-amplifier circuit initially amplifies the input signal and converts the high-voltage signal into a low voltage, and the output signal is connected to the second-stage low-voltage amplifier circuit; the low-voltage amplifier circuit amplifies the input signal for the second time, and the first output signal is simultaneously connected to DENMOS10 and DENMOS11, and the second output signal is connected to the current feedback module; the source electrodes of DENMOS10 and DENMOS11 are connected to a fixed current mirror, and the drain output signals are respectively connected to the PMOS control circuit and the NMOS control circuit, and the low The output signal of the low-voltage operational amplifier is transmitted to the output control terminal; the input terminal of the current feedback circuit is connected to the second output terminal of the low-voltage operational amplifier, and two signals CFB_N and CFB_P are generated after processing, which respectively perform feedback control on the NMOS control circuit and the PMOS control circuit; the LDO circuit generates a low-voltage power supply potential LVDD with driving capability, which is higher than the fixed value of GND, and a high-voltage domain low potential HGND, which is lower than the fixed value of VDD; the HGND potential is connected to the PMOS control circuit to provide it with a high-voltage domain power supply potential, and LVDD is connected to the third part of the low-voltage operational amplifier and the NMOS control circuit to provide power supply potential for the two modules. The PMOS control circuit and the NMOS control circuit are used to process the output signal of the two-stage operational amplifier circuit into a digital logic signal. The digital signals of the two modules are processed by the output logic control circuit and reach the high-voltage push-pull output stage, thereby controlling the conduction and shutdown of DEPMOS22 and DENMOS19.

[0025] The circuit structure of the high-voltage and high-speed push-pull comparator of the present invention is as follows: Figure 4 shown.

[0026] The input signal is processed by the input protection circuit and reaches the input end of the first-stage differential pre-amplifier, that is, the gate of MP1 and MP2. The drain of MP1 and MP2 is connected to one end of the load resistors R1 and R2, and the source is connected to the current mirror composed of MP19 and DEMOS MP20 to form a differential amplifier circuit. Resistors R1 and R2 are used to adjust the common mode and provide gain impedance. The second-stage low-voltage amplifier is composed of MP3, MP4, MN1, MN2, and MP21. MP3 and MP4 are input pairs of tubes. The gate of MP3 is connected to one end of the resistor R1, and the gate of MP4 is connected to one end of the resistor R2. The sources of MP4 and MP3 are connected to the MP21 current mirror. MN1 and MN2 are of the same size and convert the drain output signals of MP3 and MP4 into single-ended signals. The drain of MN2 is the first output signal, which is connected to the gates of DEMOS MN10 and MN11 to control the conduction and shutdown of the two tubes; the gate of MN2 is the second output signal, and the second output signal is connected to the gates of the current feedback circuits MN15, MN3, and MN4 to control the current passing through MN15, MN3, and MN4 in different states, thereby improving the power consumption utilization of the comparator.

[0027] In the current feedback circuit, the sources of MN3 and MN4 are connected to the drains of MN5 and MN6 respectively, and the drains are connected to the sources of MN8 and MN9 to form a high-voltage common-source common-gate structure. The drains of MN8, MN10, MN9 and MN11 are connected to the self-biased current mirrors composed of MP5 and PM8 and the self-biased current mirrors composed of MP11 and MP3 respectively; MN15 and MN14 are self-biased current mirrors, and MN16 provides them with variable current. On the one hand, this current is mirrored through MN16 and MN18 to control the current mirror tube MN7 of the NMOS control circuit. On the other hand, the current mirror controls the current mirror MP7 of the PMOS control circuit.

[0028] LDO generates LVDD and HGND potentials, which are connected to Figure 4 The HGND and LVDD ports in the circuit become the low-voltage power supply for the low-voltage operational amplifier and NMOS control circuit and the high-voltage domain ground potential for the PMOS control circuit.

[0029] In the PMOS control circuit, the gate of MP6 is connected to the self-biased current mirror gate composed of MP5 and MP8, which is used to mirror the current of MP5. The gate of MP7 is connected to the self-biased current mirror gate composed of MP15 and MP17, which is used to mirror the current of MP15. The size ratio of MN12 and MN13 is 1:1. MN12 is connected to the drain of MP9, and the drain of MN13 is connected to the drain of MP10, which is equivalent to comparing the current passing through MP5 with the current passing through MP15. The logic level in the high-voltage domain is obtained at the drain of MN12; the output logic level is connected to the input port of the Schmitt trigger, and the output result is transmitted to the output logic control module.

[0030] The structure of the NMOS control circuit is the same as that of the PMOS control circuit. The MP12 tube mirrors the current generated by the self-biased current mirrors of MP11 and MP13, and the MN7 tube mirrors the current generated by the self-biased current mirrors of MN16 and MN18, which is equivalent to comparing the current passing through MP15 with the current passing through MP11. A logic level signal in the low-voltage domain is obtained at the drain of MN6, and then the logic signal is output to the input of the Schmitt trigger, and the output result is connected to the push-pull output logic control module.

[0031] The output results of the PMOS control circuit and the NMOS control circuit are processed by the signal of the output logic control circuit, and the gate potentials of the DEMOS MP22 and MN19 are controlled in two voltage domains respectively to obtain high-speed high-voltage push-pull output results.

[0032] The working principle of the high-voltage high-speed comparator of the present invention is as follows:

[0033] The input protection circuit is used to limit the input of large differential mode signals and limit the potential of the input port of the first-stage high-voltage differential amplifier to a safe operating range. This prevents the gate of the first-stage high-voltage differential amplifier input pair from being broken down when a high-voltage large differential mode signal is input.

[0034] The first-stage high-voltage differential amplifier performs the first-stage amplification on the input differential-mode signal and converts the high-voltage input common-mode signal into a low-voltage domain common-mode signal. The low-voltage domain common-mode signal is I 19 / 2*R1(or R2). MP1 and MP2 are input pairs, using DEMOS, with the same size; load resistors R1 and R2 have the same area and resistance, and MP19 provides tail current for the first stage amplifier. The first stage needs to select a suitable tail current value and load resistor value to ensure that the output common mode signal makes the second stage op amp input pair work in the normal saturation area.

[0035] The second-stage op amp is a typical five-tube op amp. The power supply potential of the second-stage op amp is provided by the LVDD of the LDO, which is a low-voltage domain. At the same time, the first-stage high-voltage op amp converts the changing input common-mode voltage signal into a low-voltage domain signal. Therefore, the second-stage op amp uses low-voltage NMOS and low-voltage PMOS. Compared with DEMOS, it has a smaller area, smaller parasitic capacitance, higher characteristic frequency, and is easier to achieve high bandwidth and high speed effects. The second-stage op amp performs secondary amplification on the output result of the first-stage fully differential amplifier to ensure that the gain of the comparator amplifier part is high enough to improve the accuracy of the comparator.

[0036] The input pair tubes MP3 and MP4 have the same size, and the gate is connected to the input terminal of the first-stage high-voltage differential operational amplifier, forming a two-stage operational amplifier structure. The first output terminal of the second-stage operational amplifier, namely the drain of MN2, controls the gates of DEMOS MN10 and MN11. MN10 and MN11, as switch tubes, need to be set to a smaller size to control the on and off of the MN5 and MN6 current mirrors, so that the PMOS control module self-biased current mirrors MP5 and MP11 respond simultaneously.

[0037] When the first output potential of the second-stage op amp increases, the MN5 and MN6 current mirrors are turned on, and the two currents simultaneously control the gate potential of the self-biased current mirrors MP5 and MP11 to decrease, and then the currents of MP6 and MP12 are increased simultaneously through the current mirrors. When the second output potential of the second-stage op amp decreases, the current flowing through MN16 decreases, which raises the gate potential of the self-biased current mirror MP15, and finally reduces the current flowing through MN12 and MN7. The two currents are compared respectively, and the drains of MN12 and MN7 become logical high levels. Correspondingly, when the second-stage op amp outputs a low level, the currents of the MP7 and MP12 mirrors decrease, and the currents of the MN12 and MN7 mirrors increase, and the output is a logical low level. Therefore, it is necessary to reasonably set the ratios of MP6, MN12 and MP12, MN6 to ensure that the output potential logic is quickly and correctly flipped.

[0038] When the logic of the first output of the second stage is low, MN10 and MN11 are turned off, MN3, MN4 current mirror tubes and MN8, MN9 common gate tubes, MN1 and MN3 / MN4 ratio is M:1, M is set according to demand. At this time, MN3 and MN4 mirror the MN1 current to ensure that there is a certain current in the MP5, MP11 self-biased current mirror, to prevent the current mirror from being completely turned off, resulting in a slow response speed when the logic is flipped.

[0039] For the current feedback circuit, the second output terminal of the second-stage operational amplifier controls the current change of the MN16 current mirror, which is mirrored by the MP16 and MP7 tubes through the MP15 self-biased current mirror, and finally controls the current of the PMOS control logic MN12 tube and the NMOS control logic MN7 tube, while ensuring the synchronization of the signals reaching the PMOS and NMOS control circuits through the current feedback path. In the specific implementation process, the ratio of MP16 to MP7 can be set to 1:1; MN16 to MN7 to 1:1; MN12 to MN13 to 1:1; the ratio of MP11 and MP12 is set to be the same as that of MP5 and MP6, and the ratio of MN5 to MN6 is equal, to ensure that the current response of the two modules is the same and the path delay is equal.

[0040] In the specific implementation process, an LDO circuit is required to generate LVDD (less than 5V) higher than the ground potential and HGND (greater than HGND-5V) lower than the power supply voltage. On the one hand, for most high-voltage processes, the gate of the high-voltage tube withstands 5.5V. During the processing of the low-voltage comparator, the high voltage of the output signal is the power supply voltage, and the low voltage is the ground potential, but in the high-voltage structure, it will cause the gate of the output tube to break down. LDO is required to separate the voltage domain to protect the output tube. On the other hand, in the process of designing a high-speed comparator, limiting the logic voltage swing can effectively improve the response speed of the comparator. Therefore, the use of HGND and LVDD improves the speed performance and safety of the high-voltage high-speed comparator. In addition, in order to ensure that the current mirror responds quickly enough, the present invention sets MN3, MN4 current mirror tubes and MN8, MN9 common-gate tubes, and the ratio of MN1 to MN3 / MN4 is M:1, and M is set according to demand. Its purpose is to ensure that when MN10 and MN11 are completely closed, a certain current is ensured in MP5 and MP11 to prevent the current mirror from being completely turned off, resulting in a slow response speed when the logic is flipped.

[0041] In the specific implementation method, the PMOS control circuit and the NMOS control circuit are set to use the same device type, that is, the PMOS control circuits MN12 and MN13 use isolated NMOS tubes, and correspondingly, the NMOS control circuits MN7 and MN16 use isolated NMOS tubes. Ensure that the parasitics of the two paths are the same and the response delay is synchronized. The PMOS control circuit and the NMOS control circuit use Schmitt triggers to process the logic level to prevent oscillation caused by logic disorder.

[0042] Finally, the output logic control circuit performs logic processing on the synchronously responding PMOS push-pull output control signal and NMOS push-pull output control signal, firstly improving the ability of the logic signal to drive the push-pull output, and secondly delaying the push-pull signal to avoid the push-pull NMOS and PMOS being turned on at the same time, which increases meaningless dynamic power consumption. The processed signal reaches the gate of the push-pull output tube, completing the implementation process of the high-voltage and high-speed push-pull comparator. The output response of the high-voltage and high-speed push-pull comparator is as follows: Figure 5 shown.

[0043] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A high-voltage and high-speed push-pull comparator circuit, characterized in that: include: An input protection circuit, a first-stage differential pre-amplifier circuit, a second-stage low-voltage amplifier circuit, a current feedback circuit, a low-voltage dropout linear regulator, a PMOS control circuit, an NMOS control circuit, and an output logic control circuit; The input protection circuit is connected to two external input signals, and after performing input protection processing on the external input signals, two output signals are obtained and sent to the first-stage differential pre-amplifier circuit; the first-stage differential pre-amplifier circuit preliminarily amplifies the input signal after the input protection processing, and converts the preliminarily amplified signal from high voltage to low voltage, and sends the converted low voltage signal to the second-stage low voltage amplifier circuit; the second-stage low voltage amplifier circuit performs a second amplification on the low voltage signal to obtain two output signals, wherein the first output signal is simultaneously connected to the PMOS control circuit and the NMOS control circuit, and the second output signal is connected to the current feedback circuit; The current feedback circuit processes the second output signal and generates two feedback control signals CFB_P and CFB_N, sends CFB_P to the PMOS control circuit to perform feedback control on the PMOS control circuit, and sends CFB_N to the NMOS control circuit to perform feedback control on the NMOS control circuit; the low-voltage difference linear regulator generates a low-voltage power supply potential LVDD with driving capability and higher than the ground potential GND, and provides it to the second-stage low-voltage amplifier circuit and the NMOS control circuit; the low-voltage difference linear regulator also generates a high-voltage domain power supply potential H with driving capability and lower than the power supply voltage VDD GND, and provide it to the PMOS control circuit; the power supply voltage VDD is connected to the PMOS control circuit, and the ground potential GND is connected to the NMOS control circuit; the PMOS control circuit processes the first output signal, obtains a PMOS push-pull output control signal and sends it to the output logic control circuit; the NMOS control circuit processes the first output signal, obtains an NMOS push-pull output control signal and sends it to the output logic control circuit; the output logic control circuit performs logic processing on the PMOS and NMOS push-pull output control signals, and then controls the conduction and shutdown of the PMOS and NMOS push-pull tubes.

2. The high-voltage and high-speed push-pull comparator circuit according to claim 1, characterized in that: The first-stage differential preamplifier circuit includes first to second DEPMOS tubes, a nineteenth PMOS tube, a twentieth DEPMOS tube and first to second resistors; the first output signal of the input protection circuit is connected to the gate of the first DEPMOS tube, and the second output signal of the input protection circuit is connected to the gate of the second DEPMOS tube; the drain of the first DEPMOS tube is connected to the ground potential GND via the first resistor, and the drain of the second DEPMOS tube is connected to the ground potential GND via the second resistor; the source of the first DEPMOS tube and the source of the second DEPMOS tube are respectively connected to the drain of the twentieth DEPMOS tube, the source of the twentieth DEPMOS tube is connected to the drain of the nineteenth PMOS tube, the source of the nineteenth PMOS tube is connected to the power supply voltage VDD, the gate of the nineteenth PMOS tube is connected to the external current mirror VPB1, and the gate of the twentieth DEPMOS tube is connected to the external bias potential VPB3.

3. The high-voltage and high-speed push-pull comparator circuit according to claim 2, characterized in that: The second-stage low-voltage amplifier circuit includes third to fourth PMOS tubes, a twenty-first PMOS tube, and first to second NMOS tubes; the gate of the third PMOS tube is connected to the drain of the first DEPMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the second DEPMOS tube; the source of the third and fourth PMOS tubes are respectively connected to the drain of the twenty-first PMOS tube, the source of the twenty-first PMOS tube receives the low-voltage power supply potential LVDD generated by the low-voltage difference linear regulator, and the gate of the twenty-first PMOS tube is connected to the external current mirror bias potential VPB2; The output signal of the drain of the third PMOS tube is used as the second output signal of the second-stage low-voltage amplifier circuit and is connected to the current feedback circuit; the output signal of the drain of the fourth PMOS tube is used as the first output signal of the second-stage low-voltage amplifier circuit and is connected to the PMOS control circuit and the NMOS control circuit; The gate of the first NMOS tube is connected to the drain of the first NMOS tube, the drain of the third PMOS tube and the gate of the second NMOS tube; the gates of the first and second NMOS tubes are both connected to the current feedback circuit; the sources of the first and second NMOS tubes are both connected to the ground potential GND; the drain of the fourth PMOS tube is connected to the drain of the second NMOS tube.

4. The high-voltage and high-speed push-pull comparator circuit according to claim 3, characterized in that: The current feedback circuit includes fifteenth to sixteenth PMOS tubes, seventeenth to eighteenth DEPMOS tubes, third to fourth NMOS tubes, eighth to ninth DENMOS tubes, fourteenth to sixteenth NMOS tubes and seventeenth to eighteenth DENMOS tubes; the source electrodes of the fifteenth and sixteenth PMOS tubes are both connected to the power supply voltage VDD; the gate electrode of the fifteenth PMOS tube is connected to the gate electrode of the sixteenth PMOS tube, the drain electrode of the fifteenth PMOS tube is connected to the source electrode of the seventeenth DEPMOS tube, the drain electrode of the sixteenth PMOS tube is connected to the source electrode of the eighteenth DEPMOS tube, and the gate electrodes of the seventeenth and eighteenth DEPMOS tubes are both connected to the external bias potential VPB3; The drain of the seventeenth DEPMOS tube is connected to the drain of the seventeenth DENMOS tube, and the output signal of the drain of the seventeenth DEPMOS tube is used as the feedback control signal CFB_P generated by the current feedback circuit and connected to the PMOS control circuit; the drain of the eighteenth DEPMOS tube is connected to the drain of the eighteenth DENMOS tube, and the output signal of the drain of the eighteenth DEPMOS tube is used as the feedback control signal CFB_N generated by the current feedback circuit and connected to the NMOS control circuit; The gates of the seventeenth and eighteenth DENMOS tubes are both connected to the external bias voltage VNB2, and VNB2 makes the fourteenth to sixteenth NMOS tubes in the normal saturation region; the source of the seventeenth DENMOS tube is connected to the drain of the fifteenth NMOS tube and the drain of the fourteenth NMOS tube, the source of the eighteenth DENMOS tube is connected to the drain of the sixteenth NMOS tube, and the sources of the fourteenth, fifteenth and sixteenth NMOS tubes are all connected to the ground potential GND; the gate of the fourteenth NMOS tube is connected to the external current mirror bias potential VNB1, the gate of the fifteenth NMOS tube is connected to the gate of the first NMOS tube and the gate of the second NMOS tube, and the gate of the sixteenth NMOS tube is connected to the drain of the eighteenth DENMOS tube; The gates of the eighth and ninth DENMOS tubes are both connected to the external bias voltage VNB3, and VNB3 puts the third to fourth NMOS tubes in a normal saturation region; the drain of the eighth DENMOS tube is connected to the PMOS control circuit, and the drain of the ninth DENMOS tube is connected to the NMOS control circuit; the source of the eighth DENMOS tube is connected to the drain of the third NMOS tube, and the source of the ninth DENMOS tube is connected to the drain of the fourth NMOS tube; the source of the third NMOS tube is connected to the PMOS control circuit, and the source of the fourth NMOS tube is connected to the NMOS control circuit.

5. The high-voltage and high-speed push-pull comparator circuit according to claim 4, characterized in that: The PMOS control circuit includes fifth to seventh PMOS tubes, eighth to tenth DEPMOS tubes, a fifth NMOS tube, a tenth DENMOS tube, twelfth to thirteenth NMOS tubes and a first Schmitt trigger; the source electrodes of the fifth, sixth and seventh PMOS tubes and the first power supply end of the first Schmitt trigger are all connected to the power supply voltage VDD, the gate electrode of the fifth PMOS tube is connected to the gate electrode of the sixth PMOS tube and the drain electrode of the eighth DEPMOS tube, the drain electrode of the fifth PMOS tube is connected to the source electrode of the eighth DEPMOS tube, and the drain electrode of the sixth PMOS tube is connected to the source electrode of the eighth DEPMOS tube. The gates of the eighth, ninth and tenth DEPMOS tubes are connected to the external bias potential VPB4; the drain of the eighth DEPMOS tube is connected to the drain of the tenth DENMOS tube and the drain of the eighth DENMOS tube, the gate of the tenth DENMOS tube is connected to the drain of the fourth PMOS tube, the source of the tenth DENMOS tube is connected to the source of the third NMOS tube and the drain of the fifth NMOS tube, the gate of the fifth NMOS tube is connected to the external current mirror bias potential VNB1, and the source of the fifth NMOS tube is connected to the ground potential GND; The gate of the seventh PMOS tube is connected to the drain of the seventeenth DEPMOS tube, and the drain of the seventh PMOS tube is connected to the source of the tenth DEPMOS tube; the drain of the ninth DEPMOS tube is connected to the input end of the first Schmitt trigger and the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube is connected to the gate of the thirteenth NMOS tube and the drain of the thirteenth NMOS tube, the source of the twelfth NMOS tube, the source of the thirteenth NMOS tube and the second power supply end of the first Schmitt trigger are all connected to the high-voltage domain power supply potential HGND; the drain of the tenth DEPMOS tube is connected to the drain of the thirteenth NMOS tube, and the output end of the first Schmitt trigger is connected to the output logic control circuit.

6. The high-voltage and high-speed push-pull comparator circuit according to claim 5, characterized in that: The NMOS control circuit comprises eleventh to twelfth PMOS tubes, thirteenth to fourteenth DEPMOS tubes, sixth to seventh NMOS tubes, eleventh DENMOS tube and a second Schmitt trigger; the source of the eleventh PMOS tube, the source of the twelfth PMOS tube and the first power supply end of the second Schmitt trigger are all connected to the low voltage power supply potential LVDD, the gate of the eleventh PMOS tube is connected to the gate of the twelfth PMOS tube, the drain of the thirteenth DEPMOS tube and the drain of the ninth DENMOS tube, the drain of the eleventh PMOS tube is connected to the gate of the thirteenth DEPMOS tube The gates of the thirteenth and fourteenth DEPMOS tubes are connected to the external bias potential VPB5, the drain of the thirteenth DEPMOS tube is connected to the drain of the eleventh DENMOS tube, the gate of the eleventh DENMOS tube is connected to the drain of the fourth PMOS tube, the source of the eleventh DENMOS tube is connected to the source of the tenth NMOS tube and the drain of the sixth NMOS tube, the gate of the sixth NMOS tube is connected to the external current mirror bias potential VNB1, and the source of the sixth NMOS tube, the source of the seventh NMOS tube and the second power supply end of the second Schmitt trigger are all connected to the ground potential GND; The drain of the twelfth PMOS tube is connected to the source of the fourteenth DEPMOS tube, the drain of the fourteenth DEPMOS tube and the drain of the seventh NMOS tube are both connected to the input end of the second Schmitt trigger, the gate of the seventh NMOS tube is connected to the gate of the sixteenth NMOS tube, the drain of the eighteenth DENMOS tube and the drain of the eighteenth DEPMOS tube, and the output end of the second Schmitt trigger is connected to the output logic control circuit.

7. The high-voltage and high-speed push-pull comparator circuit according to claim 6, characterized in that: The output logic control circuit performs logic processing on the PMOS and NMOS push-pull output control signals, thereby controlling the on and off of the PMOS and NMOS push-pull tubes. The gate of the PMOS push-pull tube and the gate of the NMOS push-pull tube are both connected to the output end of the output logic control circuit, the source of the PMOS push-pull tube is connected to the power supply voltage VDD, the source of the NMOS push-pull tube is connected to the ground potential GND, and the drain of the PMOS push-pull tube is connected to the drain of the NMOS push-pull tube.

8. The high-voltage and high-speed push-pull comparator circuit according to claim 7, characterized in that: The first DEPMOS tube and the second DEPMOS tube have the same size, the first resistor and the second resistor have the same area and resistance value, the third PMOS tube and the fourth PMOS tube have the same size, the sixteenth PMOS tube and the seventh PMOS tube have the same size, the sixteenth NMOS tube and the seventh NMOS tube have the same size, the twelfth NMOS tube and the thirteenth NMOS tube have the same size, the fifth NMOS tube and the sixth NMOS tube have the same size, the size ratio of the eleventh PMOS tube and the twelfth PMOS tube is equal to the size ratio of the fifth PMOS tube and the sixth PMOS tube, and the ratio of the first NMOS tube to the third NMOS tube or the fourth NMOS tube is M:1, where M is a preset value.

9. A chip circuit, characterized in that: The chip circuit includes the high-voltage and high-speed push-pull comparator circuit according to any one of claims 1 to 8.

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