Digital-to-analog converter system

Abstract

The invention discloses a digital-to-analog converter system. A digital-to-analog converter (100) for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter comprising: (i) a first switched resistor network (200) having a first configuration and for converting a first input differential signal to a first analog output in response to a first set of bits of the plurality of bits; and (ii) a second switched resistor network (300) coupled to the first switched resistor network, the second switched resistor network having a second configuration different from the first configuration, and configured to convert a second input differential signal to a second analog output in response to a second set of bits of the plurality of bits.

Description

[0001] This application is a divisional application of Chinese patent application 201880090652.5, whose application date is January 5, 2018 and whose name is “Digital-to-Analog Converter System”. Technical Field

[0002] Preferred embodiments relate to digital-to-analog converters and systems including such converters. Background Art

[0003] A digital-to-analog converter ("DAC") is a device or configuration that receives a digital input and provides an output voltage proportional to the digital input value. The digital values ​​may follow a standard binary representation or a Gray code value, where each successive value is represented by only a single bit change relative to its previous value. Various DAC architectures are currently used in the art, and the choice of a particular architecture may depend on the application and on certain performance and design considerations, such as power consumption, speed, glitch amplitude and energy, the area required to implement the device, and so on.

[0004] Therefore, although existing methods have been feasible in certain applications, the present inventors have sought to improve upon the existing technology, as further described below. Summary of the invention

[0005] In one embodiment, there is a digital-to-analog converter for generating an analog output voltage in response to a digital value including multiple bits, the converter comprising: (i) a first switch resistor network having a first configuration and for converting a first input differential signal to a first analog output in response to a first group of bits among the multiple bits; and (ii) a second switch resistor network coupled to the first switch resistor network, the second switch resistor network having a second configuration different from the first configuration and for converting a second input differential signal to a second analog output in response to a second group of bits among the multiple bits.

[0006] Many other inventive aspects are also disclosed and claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An electrical and functional block diagram of a digital-to-analog converter (DAC) system is shown in accordance with a preferred embodiment.

[0008] Figure 2 Shown from Figure 1 Electrical block diagram and schematic diagram of the MSB level of the system.

[0009] Figure 3A Shown from Figure 1 The ISB level electrical block diagram and schematic diagram of the system.

[0010] Figure 3B Shows Figure 3AThe ISB stage has a switch position in response to the ISB Gray code being 00000.

[0011] Figure 3C Shows Figure 3B The ISB stage has the equivalent resistance of the last sub-stage.

[0012] Figure 3D Shows Figure 3B The ISB stage has the equivalent resistance of the last two sub-stages.

[0013] Figure 3E Shows Figure 3B An ISB level with equivalent resistance of all sub-levels.

[0014] Figure 4A Shown from Figure 1 The electrical block diagram and schematic diagram of the system at the LSB level.

[0015] Figure 4B shows a switch position with a response to an LSB sequence of 0000. Figure 4A The equivalent resistance of LSB level.

[0016] Figure 4C Shows Figure 4A The equivalent resistance of LSB level.

[0017] Figure 5 Shown from Figure 1 An electrical block diagram and schematic diagram of an alternative preferred embodiment of the LSB level of the system.

[0018] Figure 6 Shows Figure 1 A DAC system having an additional output buffer and an offset cancellation circuit incorporated into the LSB stage.

[0019] Figure 7 A schematic diagram of a first offset cancellation circuit incorporated into the LSB stage is shown.

[0020] Figure 8 A schematic diagram of a second alternative offset cancellation circuit incorporated into the LSB stage is shown.

[0021] Fig. 9 shows the use of Figure 7 A preferred embodiment of an offset cancellation circuit that implements offset cancellation using a Voc signal.

[0022] Fig.10 shows the use of Figure 8 A preferred embodiment of an offset cancellation circuit that implements offset cancellation using differential Voc_H and Voc_L signals. DETAILED DESCRIPTION

[0023] Figure 1 1 shows an electrical and functional block diagram of a digital-to-analog converter (DAC) system 100 according to a preferred embodiment. As an introduction, the system 100 converts a digital binary value dac_bin into a proportional analog output voltage Vdac_out, where Figure 1 In the example of (and subsequent figures), dac_bin has a total of 12 bits and is therefore shown as dac_bin<11:0> by conventional convention. 12 bits are used as an example because various inventive concepts can be applied to other numbers of binary values. Therefore, in this example, for dac_bin<11:0>=000000000000, the analog signal of Vdac_out will be relatively low (e.g., equal to or close to a relatively low power supply voltage, such as ground), and for dac_bin<11:0>=1111111111111, the analog signal of Vdac_out will be relatively high (e.g., equal to or close to a high power supply voltage of system 200).

[0024] In a preferred embodiment, the system 100 includes at least two stages, and preferably in a preferred embodiment includes three different stages, each stage being responsive to a subset of the digital binary values ​​dac_bin. Figure 1As shown, the preferred embodiment of the three stages includes: (i) a most significant bit (MSB) stage 200; (ii) an intermediate significant bit (ISB) stage 300; and (iv) a least significant bit (LSB) stage 400. The MSB stage 200 is biased between voltage rails VrefH and VrefL and receives the MSBs of dac_bin<11:0>, where the number of MSBs is equal to three in the example shown. In response to those (e.g., three) MSBs dac_bin<11:9>, the MSB stage 200 outputs different rail signals V(Rtop) and V(Rbot) to the ISB stage 300, where the magnitudes of V(Rtop) and V(Rbot) are proportional to the digital value of dac_bin<11:9>. Therefore, the ISB stage 300 is biased between voltage rails V(Rtop) and V(Rbot) and receives the ISBs of dac_bin<11:0>, where the number of ISBs so received is equal to 5 in the example shown. In response to those (e.g., five) ISB dac_bin<8:4>, the ISB stage 300 outputs different rail signals VH and VL to the LSB stage 400, wherein the magnitudes of VH and VL are proportional to the digital value of dac_bin<8:4>, and thus further proportional to the single MSB stage 200 preceding the ISB stage 300. Thus, the LSB stage 400 is biased between the voltage rails VH and VL, and receives the LSBs of dac_bin<11:0>, wherein the number of ISBs so received is equal to four in this example. In response to those (e.g., four) LSB dac_bin<3:0>, the LSB stage 400 outputs a system output voltage Vdac_out, which will be proportional to the digital value of dac_bin<3:0>, and thus further proportional to the two stages preceding the LSB stage 400, namely the MSB stage 200 and the ISB stage 300. Each of these three stages will be further described in detail below.

[0025] Figure 2An electrical block diagram and schematic diagram of the MSB stage 200 is shown in more detail. Each of the voltage rails VrefH and VrefL is connected to a respective node 202 and 204, and a switch decoding / control block 205 receives the MSB, i.e., dac_bin<11:9>. As further understood below, the stage 200 includes a plurality of switches, wherein each switch is preferably implemented in the same form, such as via one or more transistors, etc. The opening and closing of each switch is responsive to a control signal from the switch decoding / control block 205, as generally shown by the dashed arrows. As further described in detail below, the selective closing of the switches is preferably closing only one switch in a group of eight switches connected to the node 202 at a time, and closing only one switch in a group of eight switches connected to the node 204 at the same time. As also understood below, the stage 200 includes a plurality of resistors, and thus the selective closing of the switches effectively changes the overall realized (or achievable) equivalent resistance of the stage 200 as a whole, thereby changing the stage division effect between the voltage rails VrefH and VrefL. To further understand the selectivity or changing effective resistance of stage 200, it is noted that nodes 208 and 210 are also loaded by the equivalent resistance from ISB stage 300 and LSB stage 400 driven by those nodes, where as described in detail below, the resistance of the stage is twice the unit resistance, so Figure 2 The resistor indicated in the figure is 2R.

[0026] In conjunction with node 202, first terminals of seven even-numbered switches 208SW1 to 220SW1 are connected to node 202, and second terminals of the seven switches are connected to first terminals of corresponding resistors of even-numbered resistors 204R1 to 216R1, wherein the second terminal of each of the resistors 204R1 to 216R1 is connected to node 208. A first node of an eighth switch 222SW1 is connected to node 202, and a second node of switch 222SW1 is connected to node 208. Node 208 also provides the rail voltage V(Rtop) described above. It is noted that the resistance values ​​of the resistors in stage 200 (and subsequent stages) are described relative to a unit resistance 1R, which means that each resistor has an integer multiple of the nominal unit value, where the nominal value may be 20 kΩ, for example, in which case it is intended that the resistors of resistance 1R have the same resistance of 20 kΩ, the resistors of resistance 2R have twice that resistance, i.e., 40 kΩ, and so on. It is also noted that the resistance value will depend on the total resistance, drive current, and reference voltage, so, for example, a 1R unit resistance may be in the range of 1 kΩ to 40 kΩ. With this in mind, in the preferred embodiment shown, the multi-unit resistance of each of the seven resistors having a terminal connected to node 208 is as shown in Table 1 below:

[0027] Resistors Unit resistance 204R1 14R 206R1 12R 208R1 10R 210R1 8R 212R1 6R 214R1 4R 216R1 2R

[0028] Table 1

[0029] In conjunction with node 204, first terminals of seven even-numbered switches 210SW2 to 222SW2 are connected to node 204, and second terminals of the seven switches are connected to first terminals of corresponding resistors of even-numbered resistors 206R2 to 218R2, wherein the second terminal of each of the resistors 206R2 to 218R2 is connected to node 210. A first node of the eighth switch 208SW2 is connected to node 204, and a second node of the switch 208SW2 is connected to node 210. Node 210 also provides the rail voltage V(Rbot) introduced above. In addition, after the introduction of the unit resistor 1R, in the preferred embodiment shown, the multi-unit resistance of each of the seven resistors having a terminal connected to node 210 is shown in Table 2 below:

[0030] Resistors Unit resistance 206R2 2R 208R2 4R 210R2 6R 212R2 8R 214R2 10R 216R2 12R 218R2 14R

[0031] Table 2

[0032] The operation of the MSB stage 200 is now described in more detail. The MSB dac_bin<11:9> is input to block 205, and in response, one or both of the voltages V(Rtop) and V(Rbot) are adjusted to provide a second differential ΔV2 that is proportional to the value of the MSB and as a function of the differential voltage ΔV1 between VrefH and VrefL. As described above, the three MSBs cause only one switch in a set of switches connected to node 202 and one switch in a set of switches connected to node 204 to be closed simultaneously, so that each resistor in the first set of resistors (204R1 to 216R1) can be selectively switched to be connected between node 202 and node 208, and each resistor in the second set of resistors (206R2 to 218R2) can be selectively switched to be connected between node 204 and node 210. It is now noted that the first three integers used in the reference numbers of these switches are intended to indicate that similarly numbered switches are closed simultaneously, for example, if the MSB causes switch 208SW1 to be closed, then those same MSBs cause switch 208SW2 to be closed simultaneously. Continuing with the example of switch 208SW1 being closed (simultaneously with switch 208SW2 being closed), it will therefore be understood by those skilled in the art that VrefH is thereby connected to node 208 through resistor 204R1 having a resistance of 14R, thereby producing a series connection of the ISB / LSB equivalent resistance of 2R from the 14R resistor 204R1 for a total series resistance of 16R, and due to the voltage division, the 14R resistor 204R1 has 7 / 8 of VrefH across it (i.e., 14R / 16R=7 / 8), while the 2R equivalent resistance of the ISB / LSB stage has the remaining 1 / 8 of VrefH across it (i.e., 2R / 16R=1 / 8), so the output is V(Rtop). Also in the example where switch 208SW2 is closed (at the same time as switch 208SW1 is closed), VrefL is thereby directly connected to node 210, in which case the voltage at node 210 is equal to VrefL, which as a lower rail voltage may be equal to ground. Having provided an example of simultaneous closure of similarly numbered switches and the resulting voltages at V(Rtop) and V(Rbot), Table 3 below shows all possible cases for the three MSBs, and the corresponding switch pairs are closed by block 205 in response to those MSBs and the resulting voltages at V(Rtop) and V(Rbot) by decoding / control, where those voltages are shown as VrefH, VrefL, or proportional to the differential voltage of VrefH-VrefL=ΔV1:

[0033]

[0034] Table 3

[0035] In view of the foregoing and the values ​​in Table 3, it can be generally observed that at the MSB maximum value (i.e., MSB = dac_bin<12:9> = 111), V(Rtop) is eight (i.e., 3 2 =8)MSB combination, i.e., V(Rtop) is equal to the total differential of ΔV1 (i.e., VrefH-VrefL)+VrefL, while V(Rbot) is [(7 / 8)*ΔV1]+VrefL, i.e., (1 / 8)*ΔV1 below V(top). Moreover, with each successive decrement of the MSB (e.g., 111, 110, 101, ...), each of the nodes 208 and 210 decreases by (1 / 8)*ΔV1. Thus, for changes in the MSB, the difference between V(Rtop) and V(Rbot) remains constant, while each corresponding rail V(Rtop) and V(Rbot) decreases by (1 / 8)*ΔV1 for each sequential decrement. Furthermore, when the combined MSB reaches a minimum value (i.e., MSB=dac_bin<12:9>=000), V(Rbot) is the lowest achievable output of the eight MSB combination, i.e., V(Rbot) is equal to RrefL, and V(Rtop) is again 1 / 8*ΔV1 higher than V(Rbot). In all cases, the adjustable rail voltage with a common voltage difference is thus presented to the next stage, i.e., to the ISB stage 300, as discussed further below.

[0036] FIG3 shows an electrical block diagram and schematic diagram of the ISB stage 300 in more detail. By way of introduction, the stage 300 includes an R-2R resistor ladder, which in certain previous implementations was the only method of converting a digital signal to an analog signal, and in this regard, the configuration is referred to as a ladder, which is used to include a plurality of sub-stages, whereby each sub-stage includes a first resistor and a second resistor, wherein an intermediate node between the two resistors or a terminal of the second resistor provides a switchable input to the next sub-stage. In fact, as described later, the preferred embodiment of the multiple stages produces a significant improvement over this approach, particularly in reducing the resistor values ​​required for ADC conversion. Also by way of introduction, additional information regarding ADC R-2R resistor ladders can be found in U.S. Patent 4,591,826, issued to Seiler on May 27, 1986, which is incorporated herein by reference in its entirety.

[0037] ISB stage 300 receives a voltage V(Rtop) connected to node 302 and a voltage V(Rbot) connected to node 304. A double-pole double-throw (DPDT) switch 306 is connected from nodes 302, 304 to switch between those nodes and a corresponding pair of nodes 308 and 310, wherein switch 306 is shown by dashed lines; thus, switch 306 in a first position connects node 302 to node 308 while connecting node 304 to node 310, and switch 306 in a second position connects node 302 to node 310 while connecting node 304 to node 308. In response to Gray code bit B <4> , controlling the switch 306 to any of these positions. In further regard, the system 300 includes a binary to Gray code converter 312 that receives the five ISBs dac_bin<8:4> and converts them into an equivalent five-bit Gray code B<4:0>, wherein it is known that Gray codes provide an increasing sequence of bits wherein only a single bit changes in the code for each incremental value compared to the immediately preceding bit code. In further regard, each bit in the Gray code B<4:0> operates a corresponding switch in the stage 300, as further described below, and thus the nature of the Gray code allows only one bit to switch state at a time will correspondingly cause only one switch in the stage 300 to change state at a time, thereby improving performance (e.g., reducing switching-induced node and power consumption). Thus, bit B <4> Switch 306 is controlled as described above, and furthermore, when B <4> = 0, the first position is reached, and when B <4> =1, the above-mentioned second position is reached.

[0038] Continuing with the devices and connections in stage 300, node 308 is also connected to a first terminal of a resistor 314 having a unit resistance of 1R and having a second terminal connected to node 316. Node 316 is also connected to a first terminal of a resistor 318 having a unit resistance of 2R and having a second terminal connected to node 310. The relationship of the 1R resistance of resistor 314 to the 2R resistance of resistor 318 is consistent with the configuration being an R-2R configuration. The connection from nodes 316, 310 is made by Gray code bit B. <3> The DPDT switch 320 is controlled to switch between those nodes and a corresponding pair of nodes 322 and 324. Node 322 is also connected to a first terminal of a resistor 326 having a unit resistance of 1R and having a second terminal connected to a node 328. Node 328 is also connected to a first terminal of a resistor 330 having a unit resistance of 2R and having a second terminal connected to node 324. A Gray code bit B is connected from nodes 328 and 324. <2> DPDT switch 332 is controlled to switch between those nodes and a corresponding pair of nodes 334 and 336. Node 334 is also connected to a first terminal of a resistor 338 having a unit resistance of 1R and having a second terminal connected to node 340. Node 340 is also connected to a first terminal of a resistor 342 having a unit resistance of 2R and having a second terminal connected to node 336. A Gray code bit B is connected from nodes 340, 336. <1> DPDT switch 344 is controlled to switch between those nodes and a corresponding pair of nodes 346 and 348. Node 346 is also connected to a first terminal of a resistor 350 having a unit resistance of 1R and having a second terminal connected to node 352. Node 352 is also connected to a first terminal of a resistor 354 having a unit resistance of 2R and having a second terminal connected to node 348. A Gray code bit B is connected from nodes 352, 348. <0> DPDT switch 344 is controlled to switch between those nodes and a corresponding pair of nodes 358 and 360. Node 358 is also connected to a first terminal of resistor 362, which has a unit resistance of 1R and has a second terminal connected to node 364. Finally, nodes 364 and 360 provide corresponding rail voltages VH and VL to LSB stage 400 (see Figure 1 and Figure 4A ), and as shown in FIG. 3 , this stage provides an equivalent resistance load of 1R to the MSB stage 300.

[0039] The operation of the ISB stage 300 will now be described in more detail. As described above, when the ISBs (e.g., dac_bin<8:4>) are input to the system 100, they are converted by the converter 312 to Gray code B<4:0>, where the conversion is shown in the first two columns of Table 4 below:

[0040]

[0041]

[0042] Table 4

[0043] Thus, the two left columns of Table 4 illustrate the above-mentioned properties of Gray code, namely, as the five MSBs in the binary code dac_bin are incremented, the corresponding Gray code is provided, and only one bit is changed at a time. For example, consider increasing the binary code dac_bin from 00011 to 00100. In the binary sense, all three less significant bits in the sequence are changing; however, the corresponding Gray code transition provides a sequence from 00010 to 00110, in which case only the third bit has changed, that is, from 0 to 1. In addition, it can be seen from Figure 3 that the third bit is bit B. <2> , so in this case, only switch 332 changes position, while the other four switches do not change. In addition, the switch changes connect node 328 to node 336, and node 324 to node 334, thereby causing a change in the voltage division from stage 300, as will be further understood below.

[0044] The voltage division and selective changes in node connectivity achieved by the various resistors in stage 300 through switches 306, 320, 332, 344, and 356 are now further described. As an example, consider the case where dac_bin<8:4>=00000, as shown in Table 4, and the corresponding Gray code B<4:0> is therefore also=00000. In this case, Figure 3A Each switch in the figure is connected along the horizontal dashed line as shown, so as to establish Figure 3B The resistor ladder shown, i.e., has four sub-stages, which means that a 1R resistor is connected to a combination of a 2R resistor, wherein the intermediate node between the resistors provides the output for the next sub-stage, and wherein the ladder basically includes a resistor 362 which can be characterized as a 1R resistor and a last fifth sub-stage of a 1R equivalent resistor at the LSB level connected to nodes 364 and 360. In this configuration, from a circuit analysis point of view, the 1R resistor 362 and the 1R equivalent resistor at the LSB level can be considered to be an equivalent 2R total series resistance Req1, which is therefore connected in parallel with the 2R resistance of resistor 354, as shown Figure 3C Therefore, Figure 3D As shown, two parallel resistors of the same value 2R (i.e., resistor 354 and equivalent resistor Req1) continue to produce an equivalent resistor Req2 of 1R between nodes 352 and 348. Therefore, similar to Figure 3A, the rightmost end of the equivalent network again has two 1R resistors connected in series, here resistor 350 and equivalent resistor Req2, which are connected in parallel with a 2R resistor, here resistor 342. Based on these observations, one skilled in the art should be able to easily confirm that this impedance equivalence can continue for each successive sub-stage, ultimately producing Figure 3E The equivalent resistance is shown. Specifically, Figure 3E The final equivalent resistance diagram is shown, in which a resistor 314 having a resistance of 1R and a 1R equivalent resistance Req3 are connected between the input rail voltage, an output node 316 between the two resistors and another output node 304 at the end of the two resistors connected, thereby generating a differential output voltage across the 1R equivalent resistance Req3. In addition, because the resistance of the resistor 314 and the equivalent resistance Req3 are equal (for example, 1R), a 1 / 2 input voltage divider is generated, that is, the output voltage of the equivalent resistance is (1 / 2)*ΔV2.

[0045] It has been proved above that the single-stage equivalent resistance of output = (1 / 2) * (input differential voltage) should be pointed out that the same principle also applies to Figure 3B Each sub-stage in (i.e., in response to dac_bin<8:4>=B<4:0>=00000). Therefore, when switching to the 3B configuration, each stage multiplies its input by 1 / 2, so a total of five stages are generated Returning to Table 4, it should be noted that, corresponding to the case of dac_bin<8:4>=B<4:0>=00000, the first data row therefore provides an upper rail output VH of [(1 / 32)*ΔV2]+V(Rbot); FIG. 3A to FIG. 3E It can be easily seen that the same switching configuration connects V(Rbot) directly to VL, as also shown in the first data row of Table 4. Finally, given the first row and Figures 3A to 3E , a person skilled in the art can easily perform a similar / comparable analysis for each other row by evaluating the achieved equivalent resistance and the achieved resulting voltage division of each sub-stage, thereby confirming the remaining indications in Table 4. In all cases, the adjustable rail voltages of VH and VL will have a common voltage difference of (1 / 32)*ΔV2, but it is noted that in some cases, the DPDT switch allows VH>VL or VL>VH, and in any case, the difference will thereby be presented to the next stage, i.e., to the LSB stage 400, in the form of ΔV3, as further discussed below.

[0046] Figure 4AThe electrical block diagram and schematic of LSB stage 400 are shown in more detail. Each of the voltage rails VH and VL (outputs from ISB stage 300) is connected to corresponding nodes 402 and 404, and the switch decoding / control block 406 receives the LSB, i.e., dac_bin<3:0>. Similar to block 205 in stage 200, block 406 converts bits, which are here four LSB bits, into controls to selectively close one switch of sixteen even-numbered switches 408SW to 438SW at a time. Specifically, each of switches 408SW to 438SW has a first terminal connected to output node 440 and a second terminal connected to a first terminal of a corresponding resistor of resistors 408RR to 438RR of even-numbered 1R unit resistors, wherein resistors 408RR to 438RR form a series string of resistors connected between node 402 and node 404. In the series connection of resistors 408RR to 438RR, the second terminal of each resistor of resistors 410RR to 438RR is connected to the first terminal of the corresponding resistor below it, where, for example, the second terminal of resistor 438R is connected to the first terminal of resistor 436RR, the second terminal of resistor 436R is connected to the first terminal of resistor 434RR, and so on, but the second terminal of the last series-connected resistor 408RR is connected to node 404. Resistor 438RR is also one of 16 1R unit resistance resistors, all connected as part of resistor group 442, each connected in parallel, i.e., between node 402 and node 444. Finally, an additional resistor 446 having a single unit resistance of 1R is connected between node 444 and node 404.

[0047] The operation of the LSB stage 400 will now be described in more detail. As described above, when LSBs (e.g., dac_bin<3:0>) are input to the system 100, they are converted into control signals to close switches 408SW to 438SW one at a time, where the selected closed switch and the corresponding LSB bit that causes such closure are shown in the first two columns of Table 5 below:

[0048]

[0049]

[0050] Table 5

[0051] Thus, the left two columns of Table 5 illustrate the change in the LSB and the corresponding single selected switch that is closed in response, while the third column indicates the resulting voltage division in response to the closed switch. This voltage division achieved by the various resistors and switches in stage 400 is now further described. As an example, consider the case where dac_bin<0:0>=0000, and as shown in Table 5, switch 408SW is closed, so the effective resulting circuit can be as follows Figure 4B Towards the top of the figure, the equivalent resistance of the resistors of the 16 parallel 1R unit resistors in group 444 connected between nodes 402 and 444 is shown, i.e., R / 16. Below node 444 is the same single 1R unit resistor of resistor 446, and in parallel with it are 14 series connected 1R unit resistors 410RR to 436RR (so the total resistance is 14R), and further in series with a single 1R unit resistor 408RR. Finally, it is noted that by closing switch 408SW in the present example (see Figure 4A ), the output node 440 is located between the 1R unit resistors 410RR to 436RR of the 14R resistor and the single 1R unit resistor 408RR.

[0052] Figure 4C Shows Figure 4B The equivalent resistance of , which takes into account the connection between nodes 444 and 404. Specifically, if Figure 4B As shown, between these nodes is a parallel connection of 1R resistors (from 446) and a series connection of 15R resistors (from 408RR to 436RR). The resulting equivalent resistance Req4 from this parallel connection is shown in the following formula 1:

[0053]

[0054] Therefore, if Figure 4C As shown, stage 400 is reduced to an equivalent resistance of R / 16 above node 444 and 15R / 16 below node 444, that is, a voltage divider is formed by [(1 / 16)*(VH-VL)]+VL above node 444 and [(15 / 16)*(VH-VL)]+VL below node 444. In addition, it should be noted that the lower [(15 / 16)*(VH-VL)]+VL can be further divided by 15 resistors and corresponding switches below node 444, as shown in FIG. Figure 4A For example, therefore, if switch 408SW is closed, the lower [[15 / 16)*(VH-VL)]+VL below node 444 is divided by one of the 15 resistors (i.e., resistor 408RR) connected to output node 444 via the closed switch, thereby providing a resulting output voltage as shown in the following formula 2:

[0055]

[0056] Thus, Equation 2 confirms the first data row entry in Table 15, i.e., in the case of dac_bin<3:0>=0000, switch 408SW is closed and the output is the differential input divided by 16, plus VL. Furthermore, those skilled in the art should now appreciate that as the LSB (i.e., dac_bin<3:0>) is incremented, the next upper switch in the set of 16 switches will be closed, each switch connected to a corresponding series-connected resistor, thereby connecting an additional 1 / 15 resistance between node 404 and the output, thereby increasing the output by an additional (1 / 16)*VΔ3, as shown in Table 5.

[0057] Combination Figure 4A The Level 400 also considers various alternatives. For example, although Figure 4A A 16-bit voltage divider is shown, but other variations, such as powers of 2, may be implemented in alternative preferred embodiments. In the example shown or such alternatives, for voltages that follow Figure 4A The same general schematic N-bit voltage divider has N number of parallel resistors in group 444, N number of switches, and N-1 number of series resistors between nodes 444 and 404. In this manner, for example, an N=8-bit voltage divider may be constructed with 8 parallel resistors between nodes 402 and 444, 7 series resistors between nodes 444 and 404, and 8 switches, each connected from a respective first terminal of the resistor to output node 440. As another variation, it can be seen from Table 5 that since this configuration does not facilitate a connection directly from node 404 to node 440, a minimum voltage above VL (e.g., (1 / 16)*VΔ3) can be achieved, and therefore, the minimum achievable output is the voltage across the bottom resistor 408RR (i.e., via switch 408SW) in the series string of output resistors. Therefore, in an alternative preferred embodiment, a switch may be added from node 404 to node 440, while the switch from node 402 to node 440 is removed; in this configuration, the lowest achievable output will be VL, although as a compromise, the highest achievable output will no longer be VH because a direct connection from node 402 to node 440 cannot be made, and therefore the highest such output voltage will be (15 / 16)*VΔ3, i.e., the voltage across the N-1 resistor between node 444 and node 404.

[0058] Figure 5 In more detail, it is shown that Figure 4A The electrical block diagram and schematic diagram of an alternative preferred embodiment of the LSB stage 400 and the LSB stage 500 are shown in FIG. Figure 4AIn the stage 400, one terminal of each of the 16 switches is directly connected to the output node 440. As a result, parasitic capacitance from such switches may cause speed limitations on the signal swing at this node and potential glitches in the output signal. Therefore, the LSB stage 500 provides an alternative in which such considerations may be ameliorated, particularly for situations in which the number of LSBs exceeds a design threshold (e.g., greater than four LSBs).

[0059] The LSBs of stage 500, i.e., dac_bin<3:0>, are divided into two groups, one for the less significant bits of those bits and the other for the more significant bits of those bits. The less significant bits of the LSBs, i.e., dac_bin<1:0>, are connected to a decoder which will be referred to herein as a snake decoder 502, as will be described later, the reason for its naming being that those bits are decoded into the following pattern: responsive to successive increments in dac_bin<1:0>, and further responsive to dac_bin <2> , the output of decoder 502 is such that, rather than wrapping around from its maximum value of 3 to 0 as a typical 2-bit binary decoder would, it tracks up to its maximum value, repeats that maximum value, then decrements back to its minimum value, repeats that value, and then back again in the opposite direction (e.g., 0, 1, 2, 3, 3, 2, 1, 0, 0, 1, 2, ...), for reasons that will become more apparent later on to account for the serpentine array pattern. Thus, further to this point, for each 2-bit input to decoder 502, 1 of the 4 outputs of serpentine decoder 502 outputs the corresponding column C0 to C3 is thereby selected. The more significant bits of the LSB (i.e., dac_bin<3:2>) are connected to binary decoder 504, which operates in standard binary conversion, such that in response to successive increments in dac_bin<3:2>, the output of binary encoder 504 simply increments up to its maximum value, then repeats from its minimum value (e.g., 0, 1, 2, 3, 3, 0, 1, 2, 3, ...), also for reasons that will become more apparent later on. Therefore, further to this point, for each 2-bit input, 1 of the 4 outputs of the binary decoder 504 selects the corresponding row R0 to R3.

[0060] Each of the voltage rails VH and VL (outputs from the ISB stage 300) is connected to a respective node 506 and 508. Between nodes 508 and 506 is a series resistor string consisting of 16 even-numbered resistors 510RR to 540RR. The first terminal of each of the resistors 510RR to 540RR, closer to the node 506, is connected to the drain of the respective even-numbered switching transistor 510T to 540T, and the source of each of the switching transistors 510T to 540T is connected to one of the four columns C0 to C3, as shown in Table 6 below:

[0061] List Connect the transistor source C0 510T,524T,526T,540T C1 512T,522T,528T,538T C2 514T,520T,530T,536T C3 516T, 518T, 532T, 534T

[0062] Table 5

[0063] In addition, the gate of each of the switch transistors 510T to 540T is connected to one of the four rows R0 to R3 as shown in Table 6 below:

[0064] OK Connect the transistor source R0 510T, 512T, 514T, 516T R1 518T, 520T, 522T, 524T R2 526T, 528T, 530T, 532T R3 534T, 536T, 538T, 540T

[0065] Table 6

[0066] Therefore, from Tables 5 and 6 and from Figure 5 , the series resistor string of resistors 510RR to 540RR and the corresponding transistors connected to each resistor are connected in a serpentine fashion, i.e., as one traverses a row of resistors, e.g., from left to right, all are coupled to corresponding transistors having gates controlled by a single row line, providing the end of a row at the last column, and instead of wrapping around to the first column of the next row (e.g., the left column), the pattern is serpentine so as to end at the first column of a row and then begin the next row at the same column. For example, consider the top row R3 of transistors 540T to 534T and their corresponding resistors 540TT to 534RR, which move from left (i.e., from node 506 and column C0) to right. At the right end of row R3 is resistor 534RR and its corresponding transistor 534T coupled to column C3, but continuing in the series path of resistors, the next series connected resistor 532RR is not at the left end of the next row R2 (i.e., column C0), but is located at the right end of the next row R2, and the transistor 532T connected to this next resistor 532RR is again connected to selectively output to column C3, i.e., the same column to which the previous resistor 534RR may be connected. In fact, then continuing from column C3 to the right and then continuing to the left along row R2, the same serpentine pattern repeats at the left end of row R2, ending with resistor 526RR switchably connected to column C0 through corresponding transistor 526T, and then series connected resistor 524RR, which is located in the next row R1, but at the left end and has a corresponding transistor 524TT for switchably connecting resistor 524RR to the same column C0, and similarly for the rightmost end of row R1. In view of these connections, the decoding table of the snake decoder 502 is constructed to match the snake connectivity so that the increase of the binary bit sequence dac_bin<1:0> is correctly mapped from the column at one end of the row to the same column of the next consecutive row; and, in order to accomplish this operation, it is further noted that in addition to the two LSBs dac_bin<1:0> connected to the decoder 502, the next more significant bit dac_bin<1:0> is also connected to the decoder 502. <2> Also, to enable the following

[0067] The decoding is shown in Table 7:

[0068]

[0069]

[0070] Table 7

[0071] Thus, Table 7 illustrates that the enabled columns follow the serpentine nature of the resistor string, for example, when the LSB dac_bin<2:0> increases from 000 to 111, the serpentine effect occurs in the transition from dac_bin<2:0>=011 to dac_bin<2:0>=100, since both cases result in the selection of column C3. In addition, it is noted that when dac_bin<2:0> increases from 000 to 111, the serpentine effect occurs in the transition from dac_bin<2:0>=011 to dac_bin<2:0>=100, since both cases result in the selection of column C3. <3> Table 7 also applies when dac_bin<3:0>=0111 to dac_bin<3:0>=1000, for example, note that in the transition from dac_bin<3:0>=0111 to dac_bin<3:0>=1000, for Table 7, both bits of the bit set cause column C0 to be enabled, again preserving the serpentine nature of the column addressing to match the serpentine configuration of the row / column / resistor / transistor layout of stage 500. In fact, it is contemplated in connection with the preferred embodiment that by accessing the same column twice during the rise or fall of dac_bin in this manner, a lower glitch rate and / or amplitude will be achieved as opposed to other approaches.

[0072] Combination Figure 5 The Level 500 also considers various alternatives. For example, although Figure 5 A 16-bit voltage divider is shown, but other variations, such as powers of 2, may be implemented in alternative preferred embodiments. In fact, for N>16, this approach may be better than Figure 4A 400, since the latter will increase the capacitance by increasing N therein. To obtain more bits in stage 500, if N has the square root of an integer, then this method (such as Figure 5 The method in Line and columns; however, this method can still be implemented if N does not have an integer square root Figure 5 The serpentine nature of the resistor divider shown, but with a different number of rows than columns.

[0073] Figure 6 Again, it shows Figure 1 DAC system 100 and adds additional aspects thereto. Figure 6In the embodiment of the present invention, the analog output terminal Vdac_out of the system 100 is coupled to the buffer 600, which can be configured as an amplifier in a negative feedback configuration. In this regard, the output of the buffer 600 provides a corresponding analog signal output Vdac_out_buff, and the signal output is fed back to the inverting input terminal of the buffer 600, while Vdac_out is connected to the non-inverting input terminal of the buffer 600.

[0074] In another preferred aspect, it is noted that, as is known in the art, buffer 600 may experience some level of DC offset. In the present context, it is further noted that the offset may exceed the resolution obtained by the three stages of system 100. For example, consider the case where VrefH = 3.0V and VrefL is grounded, and recall stages 200, 300, and 400 together provide a 16-bit DAC. Thus, the DAC provides 2 16 = 4,096 different divisions of the differential voltage input 3.0V, so the available resolution is 3.0V / 4096 = 0.732 millivolts. However, a device such as buffer 600 may have a DC offset in the range of ±3 millivolts, with a total swing of 6 millivolts. In other words, the DC offset is approximately 8 times the resolution achievable by stages 200, 300, and 400, so the available resolution may be overwhelmed by the considerable error caused by the 6 millivolt swing in the buffer DC offset. Therefore, further in this regard, in a preferred embodiment, the LSB stage 400 or a portion thereof is further enhanced so that the LSB stage 400 provides both the output Vdac_out described and, in addition, provides a voltage offset cancellation signal Voc coupled to the offset control input of the buffer 600 so as to correct (i.e., adjust to reduce) the DC offset within the resolution achievable by the DAC, as further described below. Further in this regard, Figure 6 Also shown is an offset cancellation control signal OCCS having four bits (i.e., OCCS<3:0>) as input to the LSB stage 400 and to facilitate offset cancellation. The OCCS bits may come from a separate circuit, such as a processor or controller that the DAC 100 serves or is part of, and where the signal may be established during manufacturing, startup, etc., and then stored in memory for subsequent DC offsetting of the buffer 600.

[0075] Figure 7 Schematic diagram of offset cancellation circuit 602 is shown. In a preferred embodiment, as described above with respect to Figure 6As introduced, it is incorporated into the LSB level 400. Continuing with the example of the previous paragraph, in this example, the buffer DC offset is approximately 8 times the resolution achievable by the ADC, then the same 8 times swing of that resolution can be achieved by using the voltage across 8 series string resistors, where, since the voltage across any one of these resistors represents the lowest resolution of the DAC, the voltage across 8 of these resistors is approximately the same voltage as the DC offset swing of the buffer 600. Furthermore, according to a preferred embodiment, it is preferred that the voltage across each of those resistors is further subdivided into a plurality of equal steps to provide additional resolution or granularity to adjust the offset of the buffer 600 via Voc. Therefore, in Figure 7 In the example of , this additional resolution is four sections for each series string resistor, that is, circuit 602 provides what is known as a 1 / 4 step divider, meaning that the circuit is configured and operable to divide its differential rail voltage into 1 / 4 steps (e.g., 0, 1 / 4, 2 / 4, 3 / 4), as further understood below.

[0076] See in more detail Figure 7 , the offset cancellation circuit 602 preferably replaces the lowest resistor 408RR in stage 400 with a 1 / 4 step circuit output to serve as the voltage offset cancellation Voc from node 604, while also providing a switchable voltage from output node 408RUN to node 440. By replacing only a single resistor (e.g., resistor 408RR) with a 1 / 4 step circuit, such an implementation provides only a 1 / 4 step for the voltage swing across resistor 408RR (i.e., (VH-VL) / 4096). Therefore, if additional voltage swing options for offset cancellation are desired, multiple additional resistors in the series string containing resistors 408RR to 438RR can likewise be replaced by the circuit of the configuration of circuit 602.

[0077] Then looking at circuit 602 in more detail, the circuit is shown between nodes 408RUN and 404, at stage 400. Figure 7 Note that nodes 408RUN and 404 are nodes at the upper and lower terminals of resistor 408RR, respectively. Figure 6The offset cancellation control signal OCCS has four bits (i.e., OCCS<3:0>), and each of the four bits controls a corresponding one of the four switches 606, 608, 610, and 612 in the circuit 602. If each bit in OCCS<3:0> is enabled, a corresponding one of the four switches 606, 608, 610, and 612 is selectively closed at a time to provide a selected voltage from the other terminal of the closed switch to the output node 604, thereby providing the offset voltage Voc to the buffer 600. In particular, each of the switches 604, 606, and 608 has a first terminal connected to the output node 604 and a second terminal connected to a first terminal of a corresponding one of the resistors 614 to 618 of even-numbered 1R unit resistances; in addition, the switch 612 has a first terminal connected to the output node 604 and a second terminal connected to a node 620, wherein four unit 1R resistors 622, 624, 626, and 628 are connected in parallel between the node 620 and the node 408RUN. Finally, an additional resistor 630 having a single unit resistance 1R is connected between the node 620 and the node 404.

[0078] In view of the above, the reader should appreciate the various similarities of the structure of circuit 602 to the other arrangements described above, as well as the equivalent resistance that can be obtained by selecting the closure of any one of switches 606 , 608 , 610 , and 612 . Therefore, in general: (i) the four parallel resistors 622, 624, 626 and 628 provide an equivalent resistance of (R / 4); and (ii) the parallel connection of resistor 630 with the series-connected resistors 614, 616 and 618 provides an equivalent resistance of (3R / 4), and therefore, items (i) and (ii) are connected in series to evenly divide 3 / 4 of the voltage between nodes 408RUN between nodes 620 and 404 so that: (A) the voltage of node 404 can be selected by switch 606; (B) 1 / 4 of the voltage between nodes 404 and 408RUN can be selected by switch 608; (C) 2 / 4 of the voltage between nodes 404 and 408RUN can be selected by switch 610; and (D) 3 / 4 of the voltage between nodes 404 and 408RUN can be selected by switch 612. Furthermore, as described above, OCCS<3:0> may be determined earlier and stored to select one of such switches, again providing a resolution of (1 / 4)*(1 / 4096)*(VH-VL), and thus, Voc may be switchably selected to be any of VL, (1 / 4)*(1 / 4096)*(VH-VL), (2 / 4)*(1 / 4096)*(VH-VL), or (3 / 4)*(1 / 4096)*(VH-VL). Moreover, those skilled in the art should now also appreciate that, as described above, the other resistors in the series string of stage 400 may likewise be replaced with structures similar / comparable to circuit 602, wherein additional increments of this resolution may be provided (e.g., (4 / 4)*(1 / 4096)*(VH-VL), (5 / 4)*(1 / 4096)*(VH-VL), etc.). Additionally, while the above example shows a 1 / 4 step size, various design considerations, etc. may result in different step sizes, in which case, in view of the teachings of this document, circuit 602 is readily modified to provide more or fewer resistors in the series string and connected to the top node (or possibly the bottom node) in a parallel combination to achieve different desired step sizes.

[0079] Figure 8 A schematic diagram showing an alternative preferred embodiment of an offset cancellation circuit 802 as described above with respect to FIG. Figure 6 described and similar to Figure 7, is alternatively incorporated into the LSB stage 400. Specifically, as is known in the art, some buffer / amplifier circuits allow for DC offset adjustment via differential inputs and interpolation between those inputs, such as by including multiple (e.g., 16) differential transistor pairs responsive to the differential inputs. An example of such an approach can be found in U.S. Patent 6,707,404 issued to Yilmaz on March 16, 2004, which is commonly owned by the assignee of the present patent application and is hereby incorporated herein by reference. Therefore, in this regard, Figure 8 The circuit 802 is Figure 7 A modification is provided to circuit 602 that provides a differential output voltage signal pair including Voc_H and Voc_L, wherein the pair is connected to buffer 600 for DC offset cancellation by interpolation, which may be incorporated into buffer 600 as described above.

[0080] Looking at circuit 802 in more detail, circuit 802 includes the same connections as circuit 602 and generally has the same name, except that the letter "L" is added to a group of switches, thereby designating switches 606L, 608L, 610L, and 612L, all with their first terminals connected to node 604L, where all of these items are in Figure 7 , but without the "L" designation. Figure 7 In , these terms provide a single output Voc, while in Figure 8 In the embodiment, the first node 604H is connected to the first node 604H for providing the second differential signal (i.e., Voc_H) of the two differential signals; in addition, the second terminal of each of the four switches 606H, 608H, 610H, and 612H is connected to the corresponding higher potential across each corresponding resistor, i.e.: (i) the second terminal of the switch 606H is connected to the resistor 614H connected to the resistor 614L connected to the switch 606H; and (ii) the second terminal of the switch 606H is connected to the resistor 614H connected to the switch 606L. (ii) a second terminal of switch 608H is connected to a terminal of resistor 616 opposite to the terminal of resistor 616 connected to switch 608L; (iii) a second terminal of switch 610H is connected to a terminal of resistor 618 opposite to the terminal of resistor 618 connected to switch 610L; and (iv) a second terminal of switch 612H is connected to a terminal of a parallel resistor of even-numbered resistors 622 to 628 opposite to the terminal of the parallel resistor connected to switch 612L.

[0081] In view of the above, the operation of circuit 802 should be easy to Figure 6 and 7For circuit 802, when OCCS<3:0> specifies one of the four switches, Figure 8 , each having the same first three digit reference number. For example, if OCCS<3:0>=0000, then switches 606L and 606H are both closed, wherein switch 606L thereby connects node 404 to node 606L and provides a first voltage as Voc_L, and switch 606H thereby connects the potential between resistors 614 and 616 to node 604H and provides a second voltage as Voc_H, the two output voltages providing differential DC offset correction inputs to buffer 600. Furthermore, the resistor voltage division teachings of this document will therefore facilitate those skilled in the art to understand the various voltage divisions thereby switchably selected for output in the case of DC offset correction.

[0082] Fig. 9 shows the use of Figure 7 A preferred embodiment of an offset cancellation circuit 902 for implementing offset cancellation in the buffer 600 is provided by a Voc signal. The circuit 902 includes a first differential PMOS transistor pair, the first differential PMOS transistor pair including a PMOS transistor 904 and a PMOS transistor 906, each of the PMOS transistors having a source connected to an output of a first current source 908, the first current source 908 receiving a power supply voltage (e.g., a power supply to the entire DAC 100) VPS. The gate of the PMOS transistor 904 is connected from Figure 7 902 receives the Vdac_out signal (i.e., from node 440). The drain of PMOS transistor 904 is connected to node 910, and the drain of PMOS transistor 906 is connected to node 912. Node 910 is also connected to the non-inverting input of amplifier 914 and to the drain of NMOS transistor 916, the source of which is grounded. Node 912 is also connected to the inverting input of amplifier 914 and to the drain of NMOS transistor 918, the source of which is grounded, and node 912 is also connected to the gates of both NMOS transistors 916 and 918. Circuit 902 also includes a second differential PMOS transistor pair, which includes a PMOS transistor 920 and a PMOS transistor 922, each of which has a source connected to a current source 924, which is connected to receive a voltage VPS. The drain of PMOS transistor 920 is connected to node 912, and the drain of PMOS transistor 922 is connected to node 910. The gate of PMOS transistor 920 is connected to receive the Figure 7 The Voc signal, and the gate of the PMOS transistor 922 is connected to the Figure 7 Node 404, which recalls is also connected to the lower rail voltage VL.

[0083] The operation of circuit 902 will now be described. First, it is noted that the output signal Vdac_out_buff of amplifier 914 represents the buffered / amplified / converted output from the three stages of system 100, with further offset cancellation provided by circuit 902. Thus, Vdac_out_buff includes any offset voltage introduced by the buffer / amplifier, but is also reduced (preferably toward zero) by the offset cancellation voltage controlled by Voc. Thus, further in this regard, it is noted that the difference between Voc and VL applied to the gates of PMOS pair 920 and 922 provides a first differential signal or current to nodes 910 and 912, and then the feedback connection from the output of amplifier 914 (as provided to the gate of PMOS transistor 906 and as a differential to Vdac_out applied to the gate of PMOS transistor 904) further adjusts the differential signal at nodes 910 and 912. Thus, as described above, the feedback operates toward canceling the DC offset of the amplifier.

[0084] Fig.10 shows the use of Figure 8 A preferred embodiment of an offset cancellation circuit 1002 for implementing offset cancellation in buffer 600 is provided by differential Voc_H and Voc_L signals. The various components and connections in circuit 1002 are similar to Fig. 9 1002 is identical to the circuit 902 in 1002, so it is assumed that the reader is familiar with those aspects. In addition, the circuit 1002 includes a switch matrix 1004 that receives a number B of interpolation offset cancellation bits IOCB, where in the example shown, B=4, and such bits are correspondingly shown as IOCB<3:0>. From Figure 8 The differential Voc_H and Voc_L signals of the offset cancellation circuit 802 are also input to the switch matrix 1004. The switch matrix 1004 is connected to output these signals to the 2 B The corresponding gates of the PMOS transistor pairs, so for the example shown, there are a total of 2 B =2 4=16 PMOS transistor pairs TP1, ..., TP15, TP16, wherein these pairs include PMOS pair 920 and 922 indicated as pair TP16. Each of these PMOS transistor pairs is configured in a similar / comparable manner to PMOS pairs 920 and 922, that is, the sources of the pair of PMOS transistors are connected to the corresponding current sources, the connected drains of the pair of transistors switchably receive Voc_H at their gates connected to node 912, and the connected drains of the pair of transistors switchably receive Voc_L at their gates connected to node 910.

[0085] The operation of circuit 1002 is comparable to the operation of circuit 902, with the additional operability to linearly interpolate between Voc_H and Voc_L in response to the IOCB<3:0> bits, which select a plurality of transistor pairs to provide voltages to nodes 910 and 912. Specifically, the number of PMOS transistor pairs having inputs connected to Voc_H at one time is equal to the decimal value of the IOCB<3:0> bits applied to switch matrix 1004. For example, if the IOCB<3:0> bits are equal to 0, then all (+) inputs of PMOS transistor pairs TP1 to TP16 are connected to Voc_L, and then the output Vdac_out_buff of amplifier 914 will be equal to Voc_L. If the digital input IOCB<3:0> bits are equal to 0001, then the (+) input of one of the PMOS transistor pairs TP1 to TP16 is connected to Voc_H, while the other (+) input is connected to Voc_L. Since one of the 16 (+) inputs is connected to Voc_H, the PMOS transistor pair adds an offset cancellation voltage of (1)(Voc_H-Voc_L) / 16 to the amplifier 914. Similarly, with each increase in the digital input IOCB<3:0> bit, the numerator multiplier of the generated offset voltage also increases, so, for example, if IOCB<3:0>=0010 (i.e., a decimal value of 2), then Voc_H is connected to the (+) gate inputs of the corresponding two pairs of PMOS transistors, in which case the two pairs of PMOS transistors together add an offset cancellation voltage of (2)(Voc_H-Voc_L) / 16 to the buffer 914. As another example, if IOCB<3:0>=0011 (i.e., a decimal value of 3), Voc_H is connected to the (+) gate input terminals of the corresponding three pairs of PMOS transistors, in which case the three pairs of PMOS transistors together add an offset cancellation voltage of (3)(Voc_H-Voc_L) / 16 to the buffer 914. Therefore, in general, the amount of the offset voltage can be expressed as the following formula 3:

[0086]

[0087] Thus, circuit 1002 provides an additional level of interpolation for the purpose of counteracting the DC offset of buffer 914 .

[0088] In summary, various preferred embodiments provide circuits and systems, which include digital-to-analog conversion with two or more stages having a variable resistor / switch configuration. In addition, it has been shown that the preferred embodiments have many benefits, and various embodiments have been provided. For example, the preferred embodiments can be implemented based on, for example, a unit resistor, wherein the resistance value of the unit resistor is much lower than the traditional ladder-only network. In addition, the preferred embodiments can produce improved performance in terms of speed and reduced output glitches. Another benefit is that various modifications have been described, and those skilled in the art can think of or discern other modifications, such as different divisions of the number of digital bits in the total digital quantity to different stages of the converter, and different step sizes of the resistor configurations described herein. Therefore, although various alternatives have been provided according to the disclosed embodiments, other solutions can also be envisioned, and other solutions can be determined. Therefore, in view of the foregoing, it should be further understood by those skilled in the art that although some embodiments have been described in detail, various replacements, modifications or changes can be made to the above description without departing from the scope of the invention defined by the appended claims.

Claims

1. A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter comprising: a first switched resistor network having a first configuration and configured to convert a first input differential signal to a first analog output in response to a first set of bits of the plurality of bits; as well as A second switched resistor network is coupled to the first switched resistor network, has a second configuration different from the first configuration, and is used to convert a second input differential signal to a second analog output in response to a second set of bits in the plurality of bits.

2. The converter according to claim 1, further comprising: a third switched resistor network coupled to the first switched resistor network and the second switched resistor network, having a third configuration different from the first configuration and the second configuration, and for converting a third input differential signal to a third analog output in response to a third group of bits in the plurality of bits.

3. The converter according to claim 1, wherein: The first switched resistor network comprises: a first node, the first node being used to receive a first reference voltage; a second node, wherein the second node outputs a first output voltage; a third node, the third node being used to receive a second reference voltage; a second node, the second node outputting a second output voltage; a first set of resistors switchably selectable to be connected between the first node and the second node; a second set of resistors switchably selectable to be connected between the first node and the second node; and A control circuit is configured to simultaneously select a first resistor in the first set of resistors and a second resistor in the second set of resistors in response to the first set of bits.

4. The converter according to claim 3, further comprising: a first switch operable to directly connect the first node to the second node; a second switch operable to directly connect the third node to the fourth node; and The control circuit is further used to simultaneously select only one of the first switch that directly connects the first node to the second node or the second switch that directly connects the third node to the fourth node, and is simultaneously used to switchably connect the first resistor in the first group of resistors or the second resistor in the second group of resistors in response to the first group of bits.

5. The converter according to claim 3, wherein: The control circuit is configured to simultaneously select a first resistor in the first set of resistors and a second resistor in the second set of resistors in response to the first set of bits, wherein the first resistor and the second resistor have different resistance values.

6. The converter according to claim 3, wherein: The first group of bits includes the most significant bits of the plurality of bits.

7. The converter according to claim 3: in, Each resistor in the first set of resistors has a different resistance value than all other resistors in the first set of resistors; and Wherein each resistor in the second set of resistors has a resistance value different from all other resistors in the second set of resistors.

8. The converter according to claim 3, wherein: The second switched resistor network includes a resistor ladder network.

9. The converter according to claim 8, wherein: The second group of bits includes middle significant bits of the plurality of bits.

10. The converter according to claim 8: in, The resistor ladder network includes a plurality of sub-stages; and Each sub-stage includes a resistor pair, wherein the resistor pair includes: a first resistor having a first terminal connected to the first resistor string node and a second terminal connected to the intermediate node; a second resistor having a third terminal connected to the intermediate node and a fourth terminal connected to a second resistor string node; and A first switch, wherein the first switch is used for: In a first switch position, the first resistor string node is selectively connected to the middle node of a previous sub-stage resistor pair, and the second resistor string node is selectively connected to the fourth terminal of the second resistor in the previous sub-stage resistor pair; and In a second switch position, the first resistor string node is selectively connected to a fourth terminal of the second resistor in the previous sub-stage resistor pair, and the fourth terminal of the resistor in the sub-stage is selectively connected to an intermediate node of the previous sub-stage resistor pair.

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