BCH parallel coding and decoding algorithm suitable for eMMC

Abstract

The invention discloses a BCH parallel coding and decoding algorithm suitable for eMMC. The BCH parallel coding and decoding algorithm comprises a BCH coding algorithm and a BCH decoding algorithm. The BCH coding algorithm determines a corresponding generator polynomial through a given error correction capability and effective data bits, and further constructs a corresponding BCH code; a BCH decoding algorithm calculates a syndrome to solve an error position polynomial coefficient, and then a root of an error polynomial is solved by using Chien search, so that an error position is obtained and corrected. The BCH coding algorithm adopts an 8-bit parallel coding mode to process the data, so that the coding efficiency is improved; according to the BCH decoding algorithm, a parallel processing syndrome solving module and a Chien search module are adopted, and a block decoding mode of a two-stage pipeline structure is adopted, so that the decoding time is shortened, and the decoding efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a BCH parallel encoding and decoding algorithm suitable for eMMC. Background Art

[0002] With the rapid development of the digital information age, the demand for large-capacity data storage is growing rapidly. As one of the embedded non-volatile memories, eMMC has gradually become one of the important media for embedded non-volatile storage due to its compactness, high efficiency and easy integration, and has been widely used.

[0003] eMMC integrates NAND Flash and flash controller, and its core is NAND Flash technology, which is a high-density non-volatile memory suitable for storing large amounts of data. Flash memory has fast read and write speeds and relatively low costs. Due to the particularity of the physical structure of NAND Flash, when data is stored on NAND Flash, individual bits may flip, resulting in errors in the stored data. Therefore, in order to improve the reliability of the data, the data needs to be properly encoded before storage to ensure that when the data is wrong, the system can correct it.

[0004] Error correction code technology (ECC) based on storage applications can effectively solve the above problems. Commonly used error correction code technologies generally include Hamming code, RS algorithm, LDPC algorithm and BCH algorithm. The binary BCH error correction algorithm has gradually become the mainstream error correction algorithm in eMMC storage due to its strong error correction capability, configurable error correction capability and high flexibility. Summary of the invention

[0005] The object of the present invention is to provide a BCH parallel encoding and decoding algorithm suitable for eMMC to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a BCH parallel encoding and decoding algorithm suitable for eMMC, including: a BCH encoding algorithm and a BCH decoding algorithm;

[0007] The BCH coding algorithm determines the corresponding generating polynomial through the given error correction capability and valid data bits, and then constructs the corresponding BCH code;

[0008] The BCH decoding algorithm calculates the syndrome to obtain the error position polynomial coefficients, and then uses Qian search to solve the roots of the error polynomial, thereby obtaining the error position and correcting it.

[0009] In one embodiment, the BCH code is a cyclic code in a linear block code, whose codeword remains a valid codeword after cyclic shift, and whose codeword polynomial is defined by the root of a generating polynomial in a finite field; the encoded BCH code is composed of information bits and check bits, the information bits are valid information codewords to be transmitted, and the check bits are used by the decoder to calculate the number and position of errors in the information bits during transmission and to correct them.

[0010] In one embodiment, the exact form of the generator polynomial depends on the code length and error correction capability of the BCH code. α, α are calculated based on the given error correction capability t. 2 ,…,α t-1 The minimum polynomial of , where α is a finite field GF(2 m ), calculate the least common multiple of these minimal polynomials to get the generating polynomial, so each specific BCH code will have a specific generating polynomial.

[0011] In one embodiment, the BCH encoding algorithm uses a multi-bit parallel encoding method to balance the master control rate and the encoding rate. The page storage data of the NAND Flash in the eMMC device is transmitted in bytes. The BCH encoding algorithm uses an 8-bit parallel encoding method to process the data. At the same clock frequency, it has a higher data throughput rate than serial encoding, thereby improving encoding efficiency.

[0012] In one embodiment, the BCH decoding algorithm includes three steps: calculating the syndrome from the received codeword, judging whether there is an error code according to the value of the syndrome, if there is an error code, finding the error position polynomial according to the syndrome, then solving the root of the error position polynomial, obtaining the error position according to the Qian search algorithm, and correcting it.

[0013] In one embodiment, the syndrome is used to determine whether the received data has an error during the transmission process. By solving the syndrome, if the value is 0, it means that there is no error in the received data, and the decoded data is directly output; otherwise, an error occurs, and the next step of error position search is performed.

[0014] In one implementation, the error location polynomial is used to find the location of data errors, the coefficients of the error location polynomial are determined according to the value of the companion equation, the coefficient values ​​are solved to determine the error location polynomial, and the roots of the polynomial are solved to obtain the error location.

[0015] In one implementation, the Qian search algorithm is used to solve the error position polynomial, obtain each root of the error position polynomial by iterative exhaustive method, and then obtain the error position and correct it.

[0016] In one implementation, the BCH decoding algorithm uses a block decoding method with a two-stage pipeline structure to shorten the decoding time.

[0017] The present invention provides a BCH parallel encoding and decoding algorithm suitable for eMMC, which has the following features:

[0018] Beneficial effects:

[0019] (1) The maximum error correction capability is 110 bits of error correction for every 2048 bytes of data. It supports self-configuration of data length within 2048 bytes and error correction capability within 110 bits.

[0020] (2) The BCH coding algorithm uses 8-bit parallel coding to process data. At the same clock frequency, it can have a higher data throughput than serial coding, thus improving coding efficiency.

[0021] (3) The block decoding method with a two-stage pipeline structure shortens the decoding time and improves the decoding efficiency;

[0022] (4) Compared with the traditional serial BCH encoding and decoding algorithm, it has faster data processing speed, higher encoding and decoding efficiency, supports autonomous configuration of data length and error correction capabilities, and has higher flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a functional structure diagram of a BCH parallel encoding and decoding algorithm suitable for eMMC provided by the present invention.

[0024] Figure 2 The present invention provides a coding flow chart of a BCH parallel encoding and decoding algorithm suitable for eMMC.

[0025] Figure 3 The present invention provides a decoding flow chart of a BCH parallel encoding and decoding algorithm suitable for eMMC. DETAILED DESCRIPTION

[0026] The following is a further detailed description of a BCH parallel encoding and decoding algorithm suitable for eMMC proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] The present invention provides a BCH parallel encoding and decoding algorithm suitable for eMMC, and its functional structure is as follows: Figure 1 As shown, it includes a BCH encoding module and a BCH decoding module.

[0028] The operation process of the BCH encoding module is as follows Figure 2 As shown, according to the above description of BCH code, binary BCH code consists of information bits and check bits. For a binary BCH code with error correction capability of t, code length of n, and information bits of k, the following conditions must be met:

[0029] (1) Code length: n = 2 m -1(where m≥3)

[0030] (2) Check bit: nk≤m*t

[0031] (3) Minimum Hamming distance: d m ≥2t+1

[0032] The encoding process is as follows Figure 2 As shown, first convert the information code into information polynomial form, that is:

[0033] w(x)=w0+w1x+w2x 2 +···+w k-1 x k-1

[0034] The coefficients of the polynomial w i That is the information code, i is 0, 1, 2, ..., k-1.

[0035] Then shift the information polynomial right by nk positions to get w(x)*x n-k , divide the formula by the generating polynomial g(x), and take the remainder r(x), that is:

[0036] r(x)=Rem(w(x)*x n-k ) g(x)

[0037] where Rem(a(x)) b(x) Represents the remainder after dividing the polynomial a(x) by the polynomial b(x).

[0038] The remainder r(x) is the polynomial corresponding to the BCH code check bit. Combining it with the information bit can obtain the polynomial C(x) corresponding to the BCH code, that is:

[0039] C(x)=w(x)*x n-k +Rem(w(x)*x n-k ) g(x)

[0040] The exact form of the generating polynomial depends on the code length and error correction capability of the BCH code. Based on the given error correction capability t, α, α can be calculated. 2 ,…,α t-1 The minimum polynomial of , where α is a finite field GF(2m ), and the generating polynomial can be obtained by calculating the least common multiple of these minimal polynomials. From this, the derivation process of the generating polynomial can be summarized as follows:

[0041] (1) Determine the finite field GF(2 m ) and a code length of n = 2 m -1 and error correction capability t;

[0042] (2) Determine the finite field GF(2 m ) on the primitive polynomial p(x), so that p(α) = 0. The primitive polynomial can be obtained by looking up the table;

[0043] (3) Generate the GF(2 m ) domain;

[0044] (4) The root {α,α 2 ,…,α t-1}In GF(2 m ) is divided into conjugate root groups;

[0045] (5) Determine the minimum polynomial m based on the conjugate root group i (x);

[0046] (6) Generating polynomial g(x) = m1(x)*m3(x)*···m 2t-1 (x).

[0047] Figure 3 The BCH decoding module mainly includes three modules: syndrome calculation module, error position polynomial module and money search module. After receiving the data, the BCH decoding module first enters the syndrome calculation module, that is, calculates the correction subvector S i Is the value of 0? If S i If all the values ​​of S are 0, it is considered that no error occurred during the transmission of the information; i If the value of is not all 0, it is considered that an error has occurred in the information transmission process. The specific calculation process of the syndrome is as follows:

[0048] Assume that the codeword polynomial sent by the transmitter is:

[0049] C(x)=c0+c1x+c2x 2 +···+c n-1 x n-1

[0050] The code element polynomial received by the receiver is:

[0051] R(x)=r0+r1x+r2x 2 +···+r n-1x n-1

[0052] The error polynomial is:

[0053] E(x)=e0+e1x+e2x 2 +···+e n-1 x n-1

[0054] Then we have:

[0055] R(x)=C(x)+E(x)

[0056] Let α i (i=0,1,2…2t) is the root of the generating polynomial g(x), where t is the maximum number of error correction bits. i Substitute the received codeword polynomial R(x) to find R(α i ), that is, S i =R(α i ).

[0057] If S i If the value of is not all 0, it means that an error has occurred in the transmission process. Enter the error position polynomial module, solve the key equation, and obtain the error polynomial. The specific solution process is as follows:

[0058] Assume the error location polynomial is:

[0059] σ(x)=1+σ1x+σ2x 2 +···+σ t x t

[0060] The purpose of the error location polynomial module is to find the coefficients σ of the error location polynomial i (i=1,2,…t).

[0061] Let the adjoint polynomial be:

[0062] S(x)=1+S1x+S2x 2 +···+S t x t

[0063] The error value polynomial is:

[0064] ω(x)=1+ω1x+ω2x 2 +···+ω i x i +···

[0065] The key equation is:

[0066] S(x)*σ(x)=ω(x)modx 2t+1

[0067] Solving this key equation gives the coefficients σ of the error position polynomial: i (i=1,2,…t), the key equation can be solved by using BM iterative algorithm, the specific solution process will not be derived in detail here, and is well known to those skilled in the art.

[0068] After the error position polynomial is found, the module enters the Chien search module, which uses the Chien search algorithm to find the root of the error position polynomial, thereby obtaining the specific location of the error and correcting it. The core idea of ​​the Chien search algorithm is to start from the position α n-1 Start checking until the entire element space is traversed. If you want to determine whether the ni position is an error position, just verify α -(n-i) Is it a root of σ(x) = 0? If so, the nith bit is wrong, otherwise it is correct. After traversing the entire element space, all the error positions can be obtained. After correcting all the error positions, the correct information code can be obtained, and the decoding is completed.

[0069] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A BCH parallel encoding and decoding algorithm suitable for eMMC, characterized in that: include: BCH encoding algorithm, BCH decoding algorithm; The BCH coding algorithm determines the corresponding generating polynomial through the given error correction capability and valid data bits, and then constructs the corresponding BCH code; The BCH decoding algorithm calculates the syndrome to obtain the error position polynomial coefficients, and then uses Qian search to solve the roots of the error polynomial, thereby obtaining the error position and correcting it.

2. The BCH parallel encoding and decoding algorithm suitable for eMMC as claimed in claim 1, characterized in that: The BCH code is a cyclic code in linear block codes, and its codeword is still a valid codeword after cyclic shift. Its codeword polynomial is defined by the root of the generator polynomial in a finite field; the encoded BCH code is composed of information bits and check bits, the information bits are valid information codewords to be transmitted, and the check bits are used by the decoder to calculate the number and position of errors in the information bits during transmission and correct them.

3. The BCH parallel encoding and decoding algorithm suitable for eMMC as claimed in claim 2, characterized in that: The exact form of the generating polynomial depends on the code length and error correction capability of the BCH code. α, α are calculated based on the given error correction capability t. 2 ,…,α t-1 The minimum polynomial of , where α is a finite field GF(2 m ), calculate the least common multiple of these minimal polynomials to get the generating polynomial, so each specific BCH code will have a specific generating polynomial.

4. The BCH parallel encoding and decoding algorithm suitable for eMMC as claimed in claim 1, characterized in that: The BCH encoding algorithm adopts a multi-bit parallel encoding method to balance the master control rate and the encoding rate. The page storage data of the NAND Flash in the eMMC device is transmitted in bytes. The BCH encoding algorithm uses an 8-bit parallel encoding method to process the data. It has a higher data throughput rate than serial encoding at the same clock frequency, thereby improving the encoding efficiency.

5. The BCH parallel encoding and decoding algorithm applicable to eMMC as claimed in claim 1, characterized in that: The BCH decoding algorithm includes three steps: calculating the syndrome from the received codeword, judging whether there is an error code according to the value of the syndrome, if there is an error code, finding the error position polynomial according to the syndrome, then solving the root of the error position polynomial, obtaining the error position according to the Qian search algorithm, and correcting it.

6. The BCH parallel encoding and decoding algorithm suitable for eMMC as claimed in claim 1, characterized in that: The syndrome is used to determine whether the received data has errors during transmission. By solving the syndrome, if the value is 0, it means that there is no error in the received data, and the decoded data is directly output; Otherwise, an error occurs and the next step is to search for the error location.

7. The BCH parallel encoding and decoding algorithm suitable for eMMC as claimed in claim 1, characterized in that: The error location polynomial is used to find the location of data errors. The coefficients of the error location polynomial are determined according to the value of the companion equation. The coefficient values ​​are solved to determine the error location polynomial. The roots of the polynomial are solved to obtain the error location.

8. The BCH parallel encoding and decoding algorithm applicable to eMMC as claimed in claim 1, characterized in that: The Qian search algorithm is used to solve the error position polynomial, obtain each root of the error position polynomial by iterative exhaustive method, and then obtain the error position and correct it.

9. The BCH parallel encoding and decoding algorithm applicable to eMMC as claimed in claim 1, characterized in that: The BCH decoding algorithm adopts a block decoding method with a two-stage pipeline structure to shorten the decoding time.

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