RS232 receiver circuit applied to multi-protocol communication interface chip
By introducing a shutdown control circuit and an input switching resistor circuit into the RS232 receiver circuit of the multi-protocol communication interface chip, the problem of large current of the RS232 receiver in the shutdown mode in the multi-protocol communication interface chip is solved, and an ultra-low shutdown current design is realized.
Patent Information
- Application Number
- CN202510028358.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-08
- Publication Date
- 2025-04-11
AI Technical Summary
The RS232 receiver in the existing multi-protocol communication interface chip cannot achieve ultra-low shutdown current in the shutdown mode, resulting in a large current, which cannot meet the needs of the multi-protocol communication interface chip.
An RS232 receiver circuit applied to a multi-protocol communication interface chip is designed. The working state of the RS232 receiver circuit is controlled by a protocol selection signal inside the chip, and the shutdown control circuit and an input switching resistor circuit are used to achieve an ultra-low shutdown current on the multi-protocol interface chip.
In the shutdown mode of the multi-protocol communication interface chip, the ultra-low shutdown current of the RS232 receiver solves the problem that the existing RS232 receiver cannot achieve low shutdown current in the multi-protocol communication interface circuit.
Smart Images
Figure CN119814061A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of multi-protocol communication interface chip interface circuits, and in particular relates to an RS232 receiver circuit applied to a multi-protocol communication interface chip. Background Art
[0002] RS232 communication standard is the standard for data serial communication. This standard is mainly applicable to point-to-point data communication between data terminal equipment, data communication equipment, and intelligent instruments and meters. RS422 standard is developed from RS232 standard. It is a unidirectional, balanced transmission communication interface standard for single-machine transmission and multi-machine reception. RS485 standard is formulated on the basis of RS422. RS485 adds multi-point transmission and two-way communication functions, that is, it allows multiple transmitters to connect to the same bus for communication, while expanding the bus common mode range, enhancing noise suppression ability, increasing data transmission rate, increasing communication distance, and improving communication reliability. Usually, data devices such as computers are only equipped with RS232 interface. If RS485 bus data is to communicate with the computer, it needs to be converted through RS232 / RS485 to realize the two-way communication of data between RS485 bus interface and RS232 serial interface.
[0003] With the rise of Industry 4.0, industrial control systems are developing towards intelligence, and the demand for multi-protocol communication interface chips is growing rapidly. The development of intelligent communication interface chips that are compatible with RS232 / RS422 / RS485 standards, can provide multiple communication interfaces separately or simultaneously, and support mutual conversion has a wide range of market applications and the urgency of customer needs. RS232 is a one-to-one communication, so two or more channels are usually used for data communication at the same time when applied, while RS485 communication can support up to 256 devices in the network. When combining the two, it is necessary to consider the problems caused by the communication interference between different communication modules of the chip, especially the abnormal shutdown current and excessive power consumption caused by the mutual influence of different modules in the chip shutdown mode.
[0004] For independent RS485 chips, in shutdown mode, the transmitter can be completely turned off, and the differential receiver can also be completely turned off. For independent RS232 chips, in shutdown mode, the transmitter can be completely turned off, and the RS232 receiver is single-ended input, and the input common mode voltage is usually between ±30V, and the receiver threshold is around 1V. Therefore, due to the particularity of this receiver circuit, the receiver will be specially designed for ±30V high input voltage and low threshold voltage. The receiver circuit structure does not have a shutdown function. The circuit shutdown is to ensure that the input of the receiver is low voltage through the 5KΩ resistor that pulls down the receiver input to GND, so that the RS232 receiver will not have any current.
[0005] For multi-protocol communication interface chips, due to the characteristics of multi-protocol and multi-channel selectability, there will be multiple multiplexing of RS232 and RS485 receiver ports and transmitter ports. The RS232 receiver input port has a pull-down resistor, and the RS485 port has a weak pull-up resistor and a receiving end common mode resistor. In the case of port multiplexing, firstly, when RS485 communicates normally, the RS232 receiver input resistance will affect the normal function of RS485 communication. Secondly, when the chip is in shutdown mode, the receiver's pull-down resistor and the RS485's weak pull-up resistor will form a conduction path, causing the shutdown current to be too large. Therefore, the input resistance of the RS232 receiver of the multi-protocol communication interface chip needs to be controlled by a switch, that is, when in non-RS232 communication mode, the RS232 receiver's pull-down resistor will be disconnected. In the shutdown mode of the multi-protocol communication interface chip, when the input resistor of the RS232 receiver port is disconnected, the weak pull-up resistor of the RS485 transmitter port will work. Due to the existence of the clamp circuit inside the RS232 receiver port, the interaction between the weak pull-up resistor and the clamp circuit will cause the voltage of the input port inside the RS232 receiver to be in an intermediate state. The intermediate voltage at the input end will cause the receiver to generate an abnormal conduction current in the shutdown mode. When the existing communication interface chip RS232 receiver is used in the multi-protocol interface chip, its current in the shutdown mode cannot meet the requirements of the multi-protocol communication interface chip, and no related technology has proposed a design method for ultra-low shutdown current of the RS232 receiver for the multi-protocol communication interface chip. Summary of the invention
[0006] In view of the problems existing in the prior art, the present invention provides an RS232 receiver circuit applied to a multi-protocol communication interface chip, which can meet the requirements of the multi-protocol communication interface chip in the current under shutdown mode.
[0007] To solve the above technical problems, the present invention provides the following technical solutions: an RS232 receiver circuit applied to a multi-protocol communication interface chip, comprising an upper clamping circuit, a lower clamping circuit, a protection resistor circuit, an input switch resistor circuit, and a Schmitt trigger circuit respectively connected to a protection resistor circuit, and also comprising a shutdown control circuit connected to the Schmitt trigger circuit;
[0008] When the chip works in RS232 mode, the receiver transmits RS232 protocol signals normally; when the chip works in RS485 or shutdown mode, the inverter in the shutdown control circuit controls the NMOS tube and the PMOS tube to be turned on or off, so that the path from the Schmitt trigger circuit to the power supply VCC and GND is disconnected, thereby realizing ultra-low shutdown current of the chip with multi-protocol interface.
[0009] Furthermore, the aforementioned input switch resistor circuit includes: a resistor R1 and a switch K1; one end of the switch K1 is grounded, and the other end is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the signal input end of the RS232 receiver circuit as the output end of the switch resistor circuit.
[0010] Furthermore, the aforementioned protection resistor circuit includes: a resistor R2 and a resistor R3; one end of the resistor R2 is connected to the input signal end, and the other end of the resistor R2 is connected to one end of the resistor R3 and the lower clamping circuit; the other end of the resistor R3 is connected to the upper clamping circuit input end and the Schmitt trigger circuit respectively.
[0011] Furthermore, the aforementioned lower clamping circuit includes: a first NMOS tube M1, a second NMOS tube M2, and a third NMOS tube M3;
[0012] The drain of the first NMOS tube M1 is connected to the gate and one end of the resistor R3; the source of the first NMOS tube M1 is connected to the drain and gate of the second NMOS tube M2; the source of the second NMOS tube M2 is connected to the drain and gate of the third NMOS tube M3, and the source of the third NMOS tube M3 is grounded.
[0013] Furthermore, the upper clamping circuit includes: a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, and a resistor R4;
[0014] The gate of the fourth NMOS tube M4 is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded; the source of the fourth NMOS tube M4 is connected to the other end of the resistor R3 and the Schmitt trigger circuit; the drain of the fourth NMOS tube M4 is connected to the drain of the fifth PMOS tube M5, the gate of the fifth PMOS tube M5, the gate of the sixth PMOS tube M6, and the gate of the seventh PMOS tube M7; the source of the seventh PMOS tube M7 is connected to the voltage terminal VCC;
[0015] The source of the fifth PMOS tube M5 is connected to the drain of the sixth PMOS tube M6 , and the source of the sixth PMOS tube M6 is connected to the drain of the seventh PMOS tube M7 .
[0016] Furthermore, the aforementioned Schmitt trigger circuit includes: a first inverter INV1, an eighth NMOS tube M8, a ninth NMOS tube M9, a tenth PMOS tube M10, an eleventh PMOS tube M11, a twelfth PMOS tube M12, and a thirteenth PMOS tube M13;
[0017] The gate of the eighth PMOS tube M8 is connected to the gate of the ninth PMOS tube M9, the gate of the tenth PMOS tube M10, the gate of the eleventh PMOS tube M11, the other end of the resistor R3, and the source of the fourth NMOS tube M4;
[0018] The source of the eighth PMOS tube M8 is connected to the first input terminal of the shutdown control circuit, the drain of the eighth PMOS tube M8 is connected to the source of the ninth PMOS tube M9 and the source of the twelfth PMOS tube M12, and the drain of the twelfth PMOS tube M12 is connected to the power supply terminal VCC;
[0019] The drain of the ninth NMOS tube M9 is connected to the drain of the tenth PMOS tube M10, the gate of the twelfth PMOS tube M12, the gate of the thirteenth PMOS tube M13, the input end of the first inverter INV1, and the second input end of the shutdown control circuit; the output end of the first inverter INV1 serves as the output end of the receiver circuit;
[0020] The source of the tenth PMOS tube is connected to the drain of the eleventh PMOS tube M11 and the source of the thirteenth PMOS tube M13, and the drain of the thirteenth PMOS tube M13 is grounded;
[0021] The source of the eleventh PMOS tube M11 is connected to the third input terminal of the shutdown control circuit.
[0022] Furthermore, the aforementioned shutdown control circuit includes: a second inverter INV2, a third inverter INV3, a fourteenth NMOS tube M14, a fifteenth NMOS tube M15, and a sixteenth PMOS tube M16;
[0023] The input end of the second inverter INV2 is used to input the control signal CTL, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, the gate of the fifteenth NMOS transistor M15, and the gate of the sixteenth PMOS transistor M16;
[0024] The output end of the third inverter INV3 is connected to the gate of the fourteenth NMOS tube M14, and the drain of the fourteenth NMOS tube M14 is connected to the source of the eighth PMOS tube M8 as the first input end of the shutdown control circuit;
[0025] The drain of the fifteenth NMOS transistor M15 is connected to the input end of the first inverter INV1 as the second input end of the shutdown control circuit, and the source of the fifteenth NMOS transistor M15 is grounded;
[0026] The drain of the sixteenth PMOS tube M16 is connected to the source of the eleventh PMOS tube M11 as the third input terminal of the shutdown control circuit, and the source of the sixteenth PMOS tube M16 is connected to the power supply terminal VCC. Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:
[0027] The present invention controls the working state of the RS232 receiver circuit through the protocol selection signal inside the chip, and realizes the design of ultra-low shutdown current of the RS232 receiver in the shutdown mode of the multi-protocol communication interface chip. The problem that the existing RS232 receiver cannot realize low shutdown current in the multi-protocol communication interface circuit is solved. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It is the RS232 receiver circuit diagram of the traditional communication interface chip.
[0029] Figure 2 The present invention discloses an ultra-low shutdown current RS232 receiver circuit diagram of a protocol communication interface chip. DETAILED DESCRIPTION
[0030] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.
[0031] Various aspects of the invention are described herein with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the invention are not limited to those described in the accompanying drawings. It should be understood that the invention is implemented by any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed in the invention are not limited to any implementation. In addition, some aspects disclosed in the invention may be used alone or in any appropriate combination with other aspects disclosed in the invention.
[0032] refer to Figure 1 , Figure 1 The RS232 receiver circuit of the traditional communication interface chip is shown, including an upper clamp circuit, a lower clamp circuit, a protection resistor circuit, an input switch resistor circuit, and a Schmitt trigger circuit respectively connected to the protection resistor circuit. Among them, one end of the first resistor R1 is connected to GND, and the other end of the first resistor R1 is connected to one end of the second resistor R2 and the input terminal IN of the receiver.
[0033] The other end of the second resistor R2 is connected to the third resistor R3 and is also connected to the gate and drain of the first NMOS tube M1. The source of the first NMOS tube M1 is connected to the gate and drain of the second NMOS tube M2. The source M2 of the second NMOS tube is connected to the gate and drain of the third NMOS tube M3. The source of the third NMOS tube M3 is connected to GND. The other end of the third resistor R3 is connected to the source of the fourth NMOS tube M4 and is also connected to the gate of the eighth NMOS tube M8, the gate of the ninth NMOS tube M9, the gate of the tenth PMOS tube M10 and the gate of the eleventh PMOS tube M11. The gate of the fourth NMOS tube is connected to GND through the fourth resistor R4. The drain of the fourth NMOS tube M4 is connected to the gates of the fifth PMOS tube M5, the sixth PMOS tube M6 and the seventh PMOS tube M7. The source of the fifth PMOS tube M5 is connected to the drain of the sixth PMOS tube M6. The source of the sixth PMOS tube M6 is connected to the drain of the seventh PMOS tube M7. The source of the seventh PMOS tube M7 is connected to VCC. The drain of the eighth NMOS tube M8 is connected to the source of the ninth NMOS tube M9 and the source of the twelfth PMOS tube M12, the source of the eighth NMOS tube is connected to GND, the drain of the twelfth NMOS tube is connected to VCC, the source of the tenth PMOS tube M10 is connected to the drain of the eleventh PMOS tube M11 and the source of the thirteenth PMOS tube M13, the source of the eleventh PMOS tube is connected to VCC, the drain of the eleventh PMOS tube M11 is connected to VCC, the drain of the ninth NMOS tube M9 is connected to the drain of the tenth PMOS tube M10 and the gate of the twelfth PMOS tube M12 and the gate of the thirteenth PMOS tube M13, and is connected to the input end of the first inverter, and the output end of the first inverter is the output OUT end of the entire receiver.
[0034] This circuit is a conventional receiver input circuit in RS232 communication mode, where the IN terminal is the input port, the first resistor R1 is the input resistor, and the input signal of the IN terminal is provided to the Schmitt trigger composed of the eighth NMOS tube M8, the ninth NMOS tube M9, the tenth PMOS tube M10 and the eleventh PMOS tube M11 through the second resistor R2 and the third resistor R3. The threshold of the Schmitt trigger is the differential mode threshold voltage of the input port of RS232. When the IN port inputs a voltage of 30V, the first NMOS tube M1, the second NMOS tube M2 and the third NMOS tube M3 are turned on, which will clamp the input node voltage to ensure that the gate voltage of the Schmitt trigger does not exceed the 5V withstand voltage range, and the Schmitt trigger output is low. When the IN input voltage is -30V, the fourth NMOS tube M4 is turned on, which will clamp the input node voltage relative to GND to be not lower than the threshold voltage of the MOS tube, and the Schmitt trigger output is high. In shutdown mode, the 5KΩ pull-down resistor R1 at the RS232 receiver input ensures that the receiver input is a low voltage in a certain state, which makes the receiver almost non-existent.
[0035] In the multi-protocol communication interface chip, the IN end of the RS232 receiver will be multiplexed with each port of RS485. In shutdown mode, since the 5KΩ pull-down resistor R1 at the input end of the RS232 receiver is disconnected by the switch K1, the RS485 port is connected to a weak pull-up resistor, and there is a clamp circuit to GND inside the RS232 receiver input end. The interaction between the weak pull-up resistor of the RS485 transmitter and the clamp circuit inside the RS232 receiver may cause the potential of the RS232 receiver input end to be in an intermediate state. The intermediate voltage at the input end will cause the receiver to have additional on-current, that is, the shutdown current of the entire chip will be too large.
[0036] The embodiment of the present invention provides an RS232 receiver circuit applied to a multi-protocol communication interface chip, such as Figure 2 As shown, the circuit is compared with Figure 1 The existing RS232 receiver circuit is added with a shutdown control circuit, and a switch K1 is added to the input switch resistor circuit as a control switch from the resistor R1 to GND. One end of the switch K1 is grounded, and the other end is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the signal input end of the RS232 receiver circuit as the output end of the switch resistor circuit.
[0037] The protection resistor circuit includes: a resistor R2 and a resistor R3; one end of the resistor R2 is connected to the input signal end, and the other end of the resistor R2 is connected to one end of the resistor R3 and the lower clamping circuit; the other end of the resistor R3 is connected to the upper clamping circuit input end and the Schmitt trigger circuit respectively.
[0038] The lower clamping circuit includes: a first NMOS tube M1, a second NMOS tube M2, and a third NMOS tube M3; the drain of the first NMOS tube M1 is connected to the gate and one end of the resistor R3; the source of the first NMOS tube M1 is connected to the drain and gate of the second NMOS tube M2; the source of the second NMOS tube M2 is connected to the drain and gate of the third NMOS tube M3, and the source of the third NMOS tube M3 is grounded.
[0039] The upper clamping circuit includes: a fourth NMOS tube M4, a fifth PMOS tube M5, a sixth PMOS tube M6, a seventh PMOS tube M7, and a resistor R4;
[0040] The gate of the fourth NMOS tube M4 is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded; the source of the fourth NMOS tube M4 is connected to the other end of the resistor R3 and the Schmitt trigger circuit; the drain of the fourth NMOS tube M4 is connected to the drain of the fifth PMOS tube M5, the gate of the fifth PMOS tube M5, the gate of the sixth PMOS tube M6, and the gate of the seventh PMOS tube M7; the source of the seventh PMOS tube M7 is connected to the voltage terminal VCC;
[0041] The source of the fifth PMOS tube M5 is connected to the drain of the sixth PMOS tube M6 , and the source of the sixth PMOS tube M6 is connected to the drain of the seventh PMOS tube M7 .
[0042] The Schmitt trigger circuit includes: a first inverter INV1, an eighth NMOS tube M8, a ninth NMOS tube M9, a tenth PMOS tube M10, an eleventh PMOS tube M11, a twelfth PMOS tube M12, and a thirteenth PMOS tube M13.
[0043] The gate of the eighth PMOS tube M8 is connected to the gate of the ninth PMOS tube M9, the gate of the tenth PMOS tube M10, the gate of the eleventh PMOS tube M11, the other end of the resistor R3, and the source of the fourth NMOS tube M4;
[0044] The source of the eighth PMOS tube M8 is connected to the first input terminal of the shutdown control circuit, the drain of the eighth PMOS tube M8 is connected to the source of the ninth PMOS tube M9 and the source of the twelfth PMOS tube M12, and the drain of the twelfth PMOS tube M12 is connected to the power supply terminal VCC;
[0045] The drain of the ninth NMOS tube M9 is connected to the drain of the tenth PMOS tube M10, the gate of the twelfth PMOS tube M12, the gate of the thirteenth PMOS tube M13, the input end of the first inverter INV1, and the second input end of the shutdown control circuit; the output end of the first inverter INV1 serves as the output end of the receiver circuit;
[0046] The source of the tenth PMOS tube is connected to the drain of the eleventh PMOS tube M11 and the source of the thirteenth PMOS tube M13, and the drain of the thirteenth PMOS tube M13 is grounded;
[0047] The source of the eleventh PMOS tube M11 is connected to the third input terminal of the shutdown control circuit.
[0048] The shutdown control circuit includes: a second inverter INV2, a third inverter INV3, a fourteenth NMOS tube M14, a fifteenth NMOS tube M15, and a sixteenth PMOS tube M16;
[0049] The input end of the second inverter INV2 is used to input the control signal CTL, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, the gate of the fifteenth NMOS transistor M15, and the gate of the sixteenth PMOS transistor M16;
[0050] The output end of the third inverter INV3 is connected to the gate of the fourteenth NMOS tube M14, and the drain of the fourteenth NMOS tube M14 is connected to the source of the eighth PMOS tube M8 as the first input end of the shutdown control circuit;
[0051] The drain of the fifteenth NMOS transistor M15 is connected to the input end of the first inverter INV1 as the second input end of the shutdown control circuit, and the source of the fifteenth NMOS transistor M15 is grounded;
[0052] The drain of the sixteenth PMOS transistor M16 is connected to the source of the eleventh PMOS transistor M11 as the third input terminal of the shutdown control circuit, and the source of the sixteenth PMOS transistor M16 is connected to the power supply terminal VCC.
[0053] Below through Figure 1 and Figure 2 The comparison of the circuits illustrates the design idea of the circuit of the present invention.
[0054] Firstly, for Figure 1 Circuit, this circuit belongs to the existing conventional RS232 receiver circuit. The previous part has discussed the working principle of this RS232 receiver circuit, but when the chip works in shutdown mode, Figure 1 The IN port of the RS232 receiver circuit is left floating. At the same time, inside the multi-protocol communication interface chip, the IN port of the RS232 receiver circuit is multiplexed with the various ports of RS485. When the RS232 receiver input resistor R1 is disconnected, the weak pull-up resistor of the RS485 port and the clamping circuit inside the RS232 receiver interact with each other, causing the input end of the Schmitt trigger to be in an intermediate state voltage. The intermediate state voltage at the input end causes the Schmitt trigger to have an abnormal direct current, which will cause an abnormally large current to appear when the chip is turned off.
[0055] In order to solve the above problems, firstly, Figure 2 In the circuit shown, when the chip works in RS232 mode, the CTL signal is high, the second inverter and the third inverter control the fourteenth NMOS tube M14 to turn on, the fifteenth NMOS tube M15 to turn off, and the sixteenth PMOS tube M16 to turn on. At this time, the receiver normally transmits the RS232 protocol signal. When the chip works in RS485 or shutdown mode, the CTL signal is low, the second inverter and the third inverter control the fourteenth NMOS tube M14 to turn off, the fifteenth NMOS tube M15 to turn on, and the sixteenth PMOS tube M16 to turn off. In this way, the path from the Schmitt trigger to the power supply VCC and GND is disconnected, and it will not have normal signal transmission function, and the Schmitt trigger will not cause abnormal shutdown current because the input terminal is suspended in the intermediate state voltage. This module circuit realizes the ultra-low shutdown current design of the chip with a multi-protocol interface when the chip works in shutdown mode.
[0056] The present invention controls and designs the operating state and operating current of the RS232 receiver circuit of the multi-protocol communication interface chip, thereby solving the problem that the current of the multi-protocol communication interface chip is too large in shutdown mode due to the inability of the existing RS232 receiver to achieve ultra-low shutdown current. The present invention can realize the design of ultra-low shutdown current of the multi-protocol communication interface chip.
[0057] Although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the claims.
Claims
1. An RS232 receiver circuit for a multi-protocol communication interface chip, comprising an upper clamping circuit, a lower clamping circuit, a protection resistor circuit, an input switch resistor circuit, and a Schmitt trigger circuit respectively connected to a protection resistor circuit, characterized in that: Also included is a shutdown control circuit connected to the Schmitt trigger circuit; When the chip works in RS232 mode, the receiver transmits RS232 protocol signals normally; when the chip works in RS485 or shutdown mode, the inverter in the shutdown control circuit controls the NMOS tube and the PMOS tube to be turned on or off, so that the path from the Schmitt trigger circuit to the power supply VCC and GND is disconnected, thereby realizing ultra-low shutdown current of the chip with multi-protocol interface.
2. The RS232 receiver circuit for a multi-protocol communication interface chip according to claim 1, characterized in that: The input switch resistor circuit includes: a resistor R1 and a switch K1; one end of the switch K1 is grounded, and the other end is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the signal input end of the RS232 receiver circuit as the output end of the switch resistor circuit.
3. The RS232 receiver circuit for a multi-protocol communication interface chip according to claim 1, characterized in that: The protection resistor circuit includes: a resistor R2 and a resistor R3; one end of the resistor R2 is connected to the input signal end, and the other end of the resistor R2 is connected to one end of the resistor R3 and the lower clamping circuit; the other end of the resistor R3 is connected to the upper clamping circuit input end and the Schmitt trigger circuit respectively.
4. The RS232 receiver circuit for a multi-protocol communication interface chip according to claim 3, characterized in that: The lower clamping circuit includes: a first NMOS tube M1, a second NMOS tube M2, and a third NMOS tube M3; The drain of the first NMOS tube M1 is connected to the gate and one end of the resistor R3; the source of the first NMOS tube M1 is connected to the drain and gate of the second NMOS tube M2; the source of the second NMOS tube M2 is connected to the drain and gate of the third NMOS tube M3, and the source of the third NMOS tube M3 is grounded.
5. The RS232 receiver circuit for a multi-protocol communication interface chip according to claim 3, characterized in that: The upper clamping circuit includes: a fourth NMOS tube M4, a fifth PMOS tube M5, a sixth PMOS tube M6, a seventh PMOS tube M7, and a resistor R4; The gate of the fourth NMOS tube M4 is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded; the source of the fourth NMOS tube M4 is connected to the other end of the resistor R3 and the Schmitt trigger circuit; the drain of the fourth NMOS tube M4 is connected to the drain of the fifth PMOS tube M5, the gate of the fifth PMOS tube M5, the gate of the sixth PMOS tube M6, and the gate of the seventh PMOS tube M7; the source of the seventh PMOS tube M7 is connected to the voltage terminal VCC; The source of the fifth PMOS tube M5 is connected to the drain of the sixth PMOS tube M6 , and the source of the sixth PMOS tube M6 is connected to the drain of the seventh PMOS tube M7 .
6. The RS232 receiver circuit for a multi-protocol communication interface chip according to claim 3, characterized in that: The Schmitt trigger circuit includes: a first inverter INV1, an eighth NMOS tube M8, a ninth NMOS tube M9, a tenth PMOS tube M10, an eleventh PMOS tube M11, a twelfth PMOS tube M12, and a thirteenth PMOS tube M13; The gate of the eighth PMOS tube M8 is connected to the gate of the ninth PMOS tube M9, the gate of the tenth PMOS tube M10, the gate of the eleventh PMOS tube M11, the other end of the resistor R3, and the source of the fourth NMOS tube M4; The source of the eighth PMOS tube M8 is connected to the first input terminal of the shutdown control circuit, the drain of the eighth PMOS tube M8 is connected to the source of the ninth PMOS tube M9 and the source of the twelfth PMOS tube M12, and the drain of the twelfth PMOS tube M12 is connected to the power supply terminal VCC; The drain of the ninth NMOS tube M9 is connected to the drain of the tenth PMOS tube M10, the gate of the twelfth PMOS tube M12, the gate of the thirteenth PMOS tube M13, the input end of the first inverter INV1, and the second input end of the shutdown control circuit; the output end of the first inverter INV1 serves as the output end of the receiver circuit; The source of the tenth PMOS tube is connected to the drain of the eleventh PMOS tube M11 and the source of the thirteenth PMOS tube M13, and the drain of the thirteenth PMOS tube M13 is grounded; The source of the eleventh PMOS tube M11 is connected to the third input terminal of the shutdown control circuit.
7. The RS232 receiver circuit for a multi-protocol communication interface chip according to claim 6, characterized in that: The shutdown control circuit includes: a second inverter INV2, a third inverter INV3, a fourteenth NMOS tube M14, a fifteenth NMOS tube M15, and a sixteenth PMOS tube M16; The input end of the second inverter INV2 is used to input the control signal CTL, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, the gate of the fifteenth NMOS transistor M15, and the gate of the sixteenth PMOS transistor M16; The output end of the third inverter INV3 is connected to the gate of the fourteenth NMOS tube M14, and the drain of the fourteenth NMOS tube M14 is connected to the source of the eighth PMOS tube M8 as the first input end of the shutdown control circuit; The drain of the fifteenth NMOS transistor M15 is connected to the input end of the first inverter INV1 as the second input end of the shutdown control circuit, and the source of the fifteenth NMOS transistor M15 is grounded; The drain of the sixteenth PMOS transistor M16 is connected to the source of the eleventh PMOS transistor M11 as the third input terminal of the shutdown control circuit, and the source of the sixteenth PMOS transistor M16 is connected to the power supply terminal VCC.