Data transmission method of interface and communication device

Abstract

The embodiment of the invention provides a data transmission method of an interface and a communication device, relates to the technical field of communication, and can improve the bandwidth utilization rate of the interface. In the application, when a plurality of continuous first data units are transmitted between interfaces, each first data unit in at least one first data unit comprises n first data bits and first bits, n is an integer greater than or equal to 1, and the first bits are located behind the n first data bits in a time domain, the value of the first bit is opposite to the value of the nth first data bit in the n first data bits. The embodiment of the invention is used for data transmission between the interfaces.

Description

[0001] This application is a divisional application. The application number of the original application is 202410291171.8, and the original application date is March 13, 2024. The entire contents of the original application are incorporated into this application by reference.

[0002] This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office on October 8, 2023, with application number 202311300982.1 and application name “A data transmission method and communication device of an interface”, all contents of which are incorporated by reference in this application. Technical Field

[0003] The present application relates to the field of chip technology, and in particular to an interface data transmission method and a communication device. Background Art

[0004] Devices can be connected by cables to achieve signal transmission between devices, such as audio and video data transmission and charging. In order to meet various data transmission needs, the industry has defined various types of interconnection interface specifications for signal transmission between devices. These interconnection interfaces usually include high-speed links for transmitting business information and low-speed transmission links for transmitting control information. When data is transmitted on an interconnection interface without an accompanying clock, for example, when transmitting control information, the sending and receiving sides of the data often accumulate and increase the deviation during the data reception sampling process due to clock frequency deviation, jitter, etc., resulting in the inability of the receiving side to sample correctly.

[0005] In order to correct the sampling error on the receiving side, sufficient signal flipping is required on the line. In the current implementation, when the interconnection interface transmits data, the bits of a symbol include a start bit, a data bit, and an end bit. The start bit is used to indicate that the data carried by a symbol will start to be transmitted, and the end bit is used to indicate that the data transmission carried by this symbol is completed. Moreover, the signal flipping is achieved by the different levels of the start bit and the end bit in a symbol, and the signal flipping is achieved between two symbols by using different levels of the start bit and the end bit. It can be seen that in this implementation, the interconnection interface also needs to occupy the transmission time of the start bit and the end bit to transmit the data carried by a symbol, and the bandwidth utilization of the interface is low. Summary of the invention

[0006] The embodiments of the present application provide a data transmission method and a communication device for an interface, which can improve the bandwidth utilization of the interface.

[0007] In order to achieve the above-mentioned purpose, the embodiment of the present application adopts the following technical solution.

[0008] In a first aspect, a data transmission method of an interface is provided, comprising: generating at least one first data unit, wherein the at least one first data unit is continuous in the time domain, wherein each of the at least one first data unit comprises n first data bits and a first bit, n is an integer greater than or equal to 1, the first bit is located after the n first data bits in the time domain, and the value of the first bit is opposite to the value of the nth first data bit among the n first data bits; and sending at least one first data unit.

[0009] The embodiments of the present application can be applied in scenarios where devices are directly connected, or in scenarios where multiple devices are networked and connected via an intermediate routing device, and can be executed by an electronic device or an interface device. When executed by an electronic device, the electronic device includes an interface device, such as an interface chip, which can adapt the source data generated by the electronic device, obtain multiple first data units, and send multiple first data units. When the interface device includes the interface device, the interface device can be integrated inside the interface device or can be sold as a separate module.

[0010] The embodiments of the present application can be applied to signal transmission between interfaces of devices.

[0011] In the embodiment of the present application, when the data unit is a symbol, the first data unit is recorded as the first symbol.

[0012] Therefore, when the signal is transmitted between interfaces, considering that the deviation in the data receiving sampling process may accumulate and increase due to clock frequency deviation, jitter and other reasons when there is no accompanying clock, resulting in the inability of the receiving side to sample correctly, sampling correction can be performed by signal flipping. When the present application transmits multiple consecutive first symbols, each first symbol includes n first data bits and 1 first bit. When the value of the first bit is opposite to the value of the nth first data bit in the n first data bits, the first bit is a flip bit, which is used to achieve signal flipping. In this way, the bandwidth utilization rate of the interface when transmitting the signal is (n / (n+1)). Compared with the prior art in which each symbol includes a start bit, a data bit and an end bit, assuming that the data bit is n bits, the bandwidth utilization rate of the interface is (n / (n+2)), and the bandwidth utilization rate of the present application is higher. In this way, there are not only enough bits on the link to achieve signal flipping, which helps the receiving side to correct sampling errors, but also improves bandwidth utilization.

[0013] The bandwidth utilization rate can be understood as the ratio of valid data bits transmitted in a period of time. A period of time can be understood as multiple clock cycles for transmitting a data unit. When the transmission time of each bit is 1 clock cycle, it takes (n+1) clock cycles to transmit (n+1) bits. The valid data bits are the n first data bits, and the bandwidth utilization rate is n / (n+1).

[0014] In one possible design, the method also includes: generating a second data unit; sending the second data unit, the second data unit being located after at least one first data unit in the time domain; wherein the second data unit includes n second data bits and a second bit, the second bit being located after the n second data bits in the time domain, and the value of the second bit being the same as the value of the nth second data bit among the n second data bits.

[0015] In this way, for a burst transmission, when the second data unit transmitted is the last data unit in the time domain, it is equivalent to the second bit value in the second data unit being the same as the value of the nth second data bit in the n second data bits, indicating the end of a burst transmission. The second data unit is still similar to the first data unit, including n data bits and 1 second bit for indicating the end of the burst, and the bandwidth utilization rate of the link between the interfaces when transmitting the second data unit can also be increased to n / (n+1).

[0016] In a possible design, after the second data unit is sent, the idle state is restored. That is, after a burst transmission is received, the line can be restored to the idle state.

[0017] In a possible design, at least one first data unit and a second data unit are both data units belonging to a burst transmission. Compared with the prior art that requires 2 bits of flipping bits when transmitting each symbol, the present application only requires the last bit of each data unit in the time domain to implement signal flipping or indicate the end of burst transmission. In this way, in a burst transmission, among the at least one first data unit and the second data unit transmitted, the bandwidth utilization rate when transmitting each data unit is high.

[0018] In one possible design, the method also includes: generating a third data unit; sending the third data unit, the third data unit is located before at least one first data unit in the time domain and is used to indicate the start of a burst transmission; wherein the third data unit includes n+1 third bits and a fourth bit, the fourth bit is located after the n+1 third bits in the time domain, and the value of the fourth bit is opposite to the value of the n+1 third bits.

[0019] This is equivalent to the third data unit being (n+2) bits, and the fourth bit being the (n+2)th bit of the third data unit. Optionally, the value of the n+1 third bits is opposite to the value of the bit indicating the idle state, and the value of the fourth bit is the same as the value of the bit of the idle state. For example, if the bit value of the idle state is 1, the third data unit includes (n+1) bits of 0 and 1 bit of 1; if the bit of the idle state is 0, the third data unit includes (n+1) bits of 1 and 1 bit of 0. If the level of the link line is high in the idle state, the third data unit includes (n+1) clock cycles of low level and 1 clock cycle of high level. Alternatively, if the level of the link line is low in the idle state, the third data unit includes (n+1) clock cycles of high level and 1 clock cycle of low level. Compared with the prior art which uses a 1-bit flip bit opposite to the idle state level to indicate the start of a burst transmission, the receiving side may misjudge the start of a burst transmission due to disturbances and other reasons. The present application uses a third data unit with the same duration as the first data unit to indicate the start of a burst transmission, which can avoid the timing error of the receiving side at the start of a transmission and allow more time for error recovery and low-power wake-up.

[0020] In a possible design, the first data unit and the third data unit are both data units belonging to a burst transmission. In this way, not only can the bandwidth utilization rate of the link be higher when transmitting at least one first data unit, but the receiving side can also use the third data unit to start timing a transmission to avoid errors.

[0021] In one possible design, the method also includes: generating a fourth data unit; sending the fourth data unit, the fourth data unit including a fifth bit, the fourth data unit being located before at least one first data unit in the time domain and being used to indicate the start of a burst transmission, the value of the fifth bit being opposite to the value of the bit indicating an idle state, and at least one first data unit being a data unit belonging to a burst transmission.

[0022] In this way, when a burst transmission starts, when the level of the idle state before the burst transmission starts is a low level, the level of the fifth bit can be high to implement a signal flip to indicate the start of a burst transmission. When the level of the idle state before the burst transmission starts is a high level, the level of the fifth bit can be low to implement a signal flip to indicate the start of a burst transmission. In addition, in a burst transmission, the bandwidth utilization rate when transmitting at least one first data unit is high.

[0023] In a second aspect, a data transmission method of an interface is provided, comprising: receiving at least one first data unit, the at least one first data unit being continuous in the time domain, wherein each of the at least one first data unit comprises n first data bits and a first bit, n being an integer greater than or equal to 1, the first bit being located after the n first data bits in the time domain, and the value of the first bit being opposite to the value of the nth first data bit among the n first data bits; processing at least one first data unit to obtain first data.

[0024] The beneficial effects of the second aspect can be found in the description of the first aspect.

[0025] Moreover, for the receiving side, when processing at least one first data unit to obtain first data, taking into account the last bit of each first data unit in the time domain, that is, the first bit is the flipped bit of the previous bit of the first bit in the time domain, the effective first data obtained by the receiving side includes the data of n first data bits in each first data unit.

[0026] In one possible design, the method also includes: receiving a second data unit, the second data unit is located after at least one first data unit in the time domain and is used to indicate the end of a burst transmission; wherein the second data unit includes n second data bits and a second bit, the second bit is located after the n second data bits in the time domain, and the value of the second bit is the same as the value of the nth second data bit among the n second data bits; processing the second data unit to obtain second data.

[0027] Similar to the second aspect, the second data includes data of n first data bits in each first data unit, and data of n second data bits in each second data unit.

[0028] In a possible design, the first data and the second data are data belonging to a burst transmission. That is, when the second data unit is the last data unit of a burst transmission in the time domain, when the second data unit is received, the data of the burst transmission obtained by the receiving side includes the first data obtained from at least one first data unit and the second data from the second data unit.

[0029] In one possible design, before receiving at least one first data unit, the method also includes: receiving a third data unit, the third data unit is located before at least one first data unit in the time domain and is used to indicate the start of a burst transmission; wherein the third data unit includes n+1 third bits and a fourth bit, the fourth bit is located after the n+1 third bits in the time domain, and the value of the fourth bit is opposite to the value of the n+1 third bits.

[0030] In one possible design, the values ​​of the n+1 third bits are opposite to the bit value indicating the idle state, and the value of the fourth bit is the same as the bit value of the idle state; the third data unit is processed to obtain third data.

[0031] Considering that the third data unit is not used to carry valid data, when the receiving side receives the third data unit, it only recognizes the start of a burst transmission through the third data unit. When the idle state signal is at a high level, the third data is only a low level signal of n+1 clocks and a high level signal of 1 clock, or when the idle state signal is at a low level, the third data is only a high level signal of n+1 clocks and a low level signal of 1 clock, but the third data unit does not have valid data.

[0032] Moreover, for the receiving side, compared with the prior art which indicates the start of a burst transmission by using a 1-bit start bit, but is prone to disturbance, causing the receiving side to misjudge the start of a burst transmission, the present application indicates the start of a burst transmission by using a third data unit having the same transmission duration as the first data unit, which can prevent the receiving side from misjudging the start of a burst transmission due to disturbances and other reasons, avoid timing errors, and allow more time for error recovery and low-power wake-up.

[0033] In one possible design, for the receiving side, the line level is detected in the idle state, and when a change in the level is detected, the third data unit time is used as the low power consumption wake-up time.

[0034] In a possible design, the first data and the third data are data belonging to a burst transmission. For the receiving side, the first data includes data of n first data bits in each first data unit. There is no valid data in the third data.

[0035] In one possible design, the method also includes: receiving a fourth data unit, the fourth data unit including a fifth bit, the fourth data unit is located before at least one first data unit in the time domain and is used to indicate the start of a burst transmission, the value of the fifth bit is opposite to the value of the bit indicating the idle state, and the at least one first data unit is a data unit belonging to a burst transmission.

[0036] Among them, the fifth bit can also be called the start bit. The receiving side can recognize the start of a burst transmission based on the fifth bit, time the burst transmission, and improve the reliability of data transmission.

[0037] According to a third aspect, an interface device is provided, comprising: a processing module for generating at least one first data unit, wherein the at least one first data unit is continuous in the time domain, wherein each of the at least one first data unit comprises n first data bits and a first bit, n is an integer greater than or equal to 1, the first bit is located after the n first data bits in the time domain, and the value of the first bit is opposite to the value of the nth first data bit among the n first data bits; and a sending module for sending at least one first data unit.

[0038] In a fourth aspect, an interface device is provided, the interface device comprising: a receiving module, used to receive at least one first data unit, the at least one first data unit is continuous in the time domain, wherein each of the at least one first data unit comprises n first data bits and a first bit, n is an integer greater than or equal to 1, the first bit is located after the n first data bits in the time domain, and the value of the first bit is opposite to the value of the nth first data bit among the n first data bits; a processing module, used to process at least one first data unit to obtain first data.

[0039] According to a fifth aspect, an interface device is provided, comprising a module for executing the method as described in the first aspect and any one design of the first aspect, or the second aspect and any one design of the second aspect.

[0040] In a sixth aspect, an interface device is provided, which includes a processor and a memory, wherein the memory is used to store computer execution instructions. When the computer execution instructions are executed by the processor, the method described in the first aspect and any one of the designs of the first aspect, or the second aspect and any one of the designs of the second aspect is executed.

[0041] In the seventh aspect, a computer-readable storage medium is provided, in which computer instructions are stored. When the computer instructions are executed on an interface device, the interface device executes the method described in the first aspect and any one of the designs of the first aspect, or the second aspect and any one of the designs of the second aspect.

[0042] In an eighth aspect, a computer program product is provided, comprising computer instructions, which, when executed on an interface device, cause the interface device to execute the method described in the first aspect and any one of the designs of the first aspect, or the second aspect and any one of the designs of the second aspect.

[0043] In a ninth aspect, an electronic device is provided, the electronic device comprising the interface device in the fifth aspect and / or the sixth aspect.

[0044] In a tenth aspect, a chip is provided, the chip comprising the interface device in the fifth aspect and / or the sixth aspect.

[0045] It can be understood that any of the electronic devices, interface devices, chips, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0046] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of the architecture of a communication system for direct connection between devices provided in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of basic components of an electronic device provided in an embodiment of the present application;

[0049] Figure 3 A schematic diagram of transmission between interfaces provided in an embodiment of the present application;

[0050] Figure 4 A schematic diagram of transmission of multiple data bits provided in an embodiment of the present application;

[0051] Figure 5 A schematic diagram of symbol transmission for correcting sampling errors by flipping a signal in an auxiliary link provided in an embodiment of the present application;

[0052] Figure 6 A symbol transmission flow chart for correcting sampling errors by flipping signals provided in an embodiment of the present application;

[0053] Figure 7 A schematic diagram of transmitting multiple symbols provided in an embodiment of the present application;

[0054] Figure 8 A signal interaction flow chart of a data transmission method of an interface provided in an embodiment of the present application;

[0055] Fig. 9 A schematic diagram of a burst transmission provided in an embodiment of the present application;

[0056] Fig.10 A transmission schematic diagram of two burst transmissions provided in an embodiment of the present application;

[0057] Fig.11 A signal interaction flow chart of a data transmission method of an interface provided in an embodiment of the present application;

[0058] Fig.12 A transmission schematic diagram of a burst transmission provided in an embodiment of the present application;

[0059] Fig.13 A schematic diagram of the structure of an interface device provided in an embodiment of the present application;

[0060] Fig.14 A schematic diagram of the structure of an interface device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0062] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0063] The embodiments of the present application can be used in the scenario of signal transmission between devices. Devices can be directly connected to each other, or the connection between multiple devices can be completed through a routing device. Signals can be transmitted (sent and received) between devices by wired means, or by wireless means. Signals can be transmitted directly between devices, or signals can be transmitted between devices through an interface device, and the signal can be transmitted to the processing unit inside the device through a bus inside the device.

[0064] For example, Figure 1 (a) in FIG. 1 is a schematic diagram of the architecture of a communication system 10a in which devices are directly connected. Device 101 and device 102 are connected by a cable, and interface 1011 in device 101 and interface 1021 in device 102 are connected to realize signal transmission between device 101 and device 102, such as transmission of audio and video data and short-distance transmission of charging signals. For example, Figure 1 In (a), device 101 is a set-top box, device 102 is a TV, and audio and video data are transmitted between the interfaces of the set-top box and the TV via cables, or device 101 is a display, device 102 is a game controller, and control information is transmitted between the interfaces of the display and the game controller via cables.

[0065] Figure 1 (b) shows a schematic diagram of the architecture of a communication system 10b in which devices are connected through a routing device. Devices 103 to 105 are all connected to a routing device 106 through cables, and the interfaces between devices can transmit signals through the routing device, such as the transmission of audio and video data and short-distance transmission of charging signals. In this scenario, the interface of each device is connected to the interface of the routing device, and the signals transmitted between the interfaces of the devices must be transmitted through the interface of the routing device. For example, device 103 is a display, device 104 is a set-top box, and device 105 is an audio player. The interface of the set-top box 104 transmits audio and video data to the interface of the routing device 106, and the interface of the routing device 106 transmits audio and video data to the interface of the display 103. Alternatively, the interface of the display 103 transmits audio data to the interface of the audio player 105 through the interface of the routing device 106.

[0066] In the above two communication systems, the devices interconnected by the interface can be various electronic devices, such as personal computers, laptops, mobile phones, digital cameras, digital televisions, audio equipment, DVD players, set-top boxes, game consoles, printers, mice, keyboards and household appliances, etc. The transmitted signals can be audio signals, video signals, Internet data, Internet of Things data and charging signals, etc.

[0067] In order to meet various signal transmission requirements, the industry has defined various types of interface specifications for signal transmission between devices, such as universal serial bus (USB) interface specification, high definition multimedia interface (HDMI) interface specification, DisplayPort (DP) interface specification, unified multimedia interconnection (UMMI) interface specification, and peripheral component interconnect express (PCI-Express) interface specification, etc. Accordingly, the interface may be HDMI, miniHDMI, micro HDMI, Type-A, Type-B, Micro-B, Type-C, etc.

[0068] For example, in the above-mentioned short-distance transmission scenario interconnected by cables, the interface connection between the set-top box / speaker and the TV, or the interface connection between the game console and the TV, is connected through a USB cable, and the interface standard followed is the USB interface specification, or the connection method is connected through an HDMI cable, and the interface standard followed is the HDMI interface specification, or the connection method is connected through a DP cable, and the interface standard followed is the DisplayPort interface specification.

[0069] The embodiment of the present application also provides another interface standard that can replace the above interface standards (such as USB interface or HDMI interface): unified midia interconnecter (UMI) interface. The UMI interface can not only adapt the data transmission, but also realize the charging function. Of course, the UMI interface can also be other interface names. When the UMI interface is replaced with other interface names, the other interfaces can be used to realize the functions of the UMI interface in the present application.

[0070] In this application, the UMI interface also supports direct connection between devices, or multi-device networking connection (for example, devices are connected through routing devices, or devices are connected through docking stations). The device can be any electronic device or component. When the device is an electronic device, the electronic device is, for example, a personal computer, a display, an audio and video device, a digital device, a printer, a router, a game console, and a vehicle-mounted device, and the electronic device includes a UMI interface. When the device is a component, the component can be understood as any interface device (interface device / interface component), and the interface device is the UMI interface.

[0071] In this application, devices can transmit (send and receive) signals via wired or wireless means. Devices can transmit signals directly or through interface devices (such as interface devices of routing devices), and then transmit signals to the processing units inside the respective devices through the bus.

[0072] When the device is an electronic device, the devices can be interconnected through the UMI interface of the device. Figure 1 The scenario shown in (a) is similar to that shown in FIG. For example, the UMI interfaces of the set-top box and the TV are interconnected through cables for signal transmission.

[0073] When the device is an interface device, the device can be a chip, that is, the chips are interconnected, and the chip can be an interface chip on an electronic device / cable / dock / adapter / router. Among them, the docking station can be plugged with a gigabit network port, a video graphics array (VGA) interface, HDMI, a TF card (trans-flash card), an SD card (secure digital memory card), a charging interface, and a USB interface.

[0074] In this application, when the device is a chip, the chip may include an interface module, that is, the application may be applied to the interface module for interconnecting chips. The interface module may be understood as an IP integrated inside the chip. Alternatively, the interface module may also be sold separately as an IP.

[0075] For example, when the chip is a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), etc., the present application can be applied to the interface modules of chips such as SoC, CPU, and GPU. When the chip is a small chip such as a die, the interface module can be understood as the sending circuit and / or receiving circuit in the die, and the chip can also be an input / output (I / O) die that only includes interface functions.

[0076] In this application, when a device is an electronic device, such as Figure 2 The figure shows a schematic diagram of basic components of an electronic device 20. The electronic device 20 includes an interface chip 200 (UMI interface), the interface chip 200 includes one or more adapters 201, one or more management control adapters 202 and one or ports 203, or when the electronic device 20 is a routing device, the interface chip 200 only includes one or more ports 203. Each of the one or more adapters 201 can be coupled to an external component of the interface chip 200. One or management control adapters 202 can be coupled to a component used for management control outside the interface chip 200. The port 203 can be coupled to a connector 204 of the electronic device 20, and the connector 204 is used to couple an external device of the electronic device 20. Among them, one or more adapters 201 can be a sending / receiving adapter. For example, when the adapter 201 is used for adapting audio and video formats, the adapter 201 can be an audio and video sending / receiving adapter. When the adapter 201 is used for third-party protocol adaptation, the adapter 201 can be a third-party protocol adapter.

[0077] For example, when port 203 is a downlink port, the sending adapter can be used to adapt the service information to be sent into service information that can be transmitted on port 203 of the interface chip, and send the service information out through port 203. When port 203 is an uplink port, the receiving adapter 201 can be used to adapt the service information received from port 203 into service information to be processed internally by the electronic device 20 for internal processing. The management control adapter 202 can be used to adapt control information.

[0078] The basic components of different electronic devices 20 can be combined to form a variety of different device types. For example, the electronic device 20 includes a source device including at least one downstream port and at least one video and audio transmission adapter, or a source device including at least one upstream port and a video and audio receiving adapter, or a docking device including at least one upstream port, at least one video and audio receiving adapter and at least one traditional video and audio interface, or a routing device including at least one downstream port and at least one upstream port without a video and audio transmission adapter and a video and audio receiving adapter, or a composite device having both an upstream port and a downstream port.

[0079] like Figure 3 The figure shows a schematic diagram of an inter-interface transmission provided by an embodiment of the present application. In the UMI system, the uplink port and the downlink port between devices include a main link (ML) and an auxiliary link (SL), and further, a power bus link (PL) and a cable information link (CL). The cable information link can be used to transmit cable information, such as the cable model and cable capability information.

[0080] The main link is used for high-speed data transmission, such as the transmission of audio and video signals, while the auxiliary link is mainly used for management and control between devices, such as device discovery, capability query, device configuration, device control, etc. It can also be used for low-speed data transmission and control message transmission.

[0081] In some scenarios, the main link consists of one or more lanes, each of which supports only unidirectional transmission, and the auxiliary link consists of two single-ended lanes in different directions. Alternatively, part of the main link is a unidirectional channel, the other part is a bidirectional channel, and the auxiliary link is a bidirectional channel. A main link may include multiple channels, such as 2 / 5 / 9 channels. The more channels there are, the faster the data transmission speed.

[0082] In addition, whether it is an uplink port or a downlink port, it may include multiple pins, for example, a pin connected to a ground line, a pin connected to a power line, a pin connected to a main link channel, and a pin connected to an auxiliary link channel.

[0083] Usually, when transmitting data, if there is no accompanying clock, the data sending and receiving sides may have clock frequency deviation or jitter, which may cause the deviation to accumulate and increase during the data receiving sampling process. Figure 4 The figure shows a schematic diagram of the transmission of multiple data bits. Each bit includes a clock cycle. When sampling, the receiving end can obtain the bit data corresponding to each clock cycle according to the level information sampled in each clock cycle. In the process of transmitting bits 0 to 7, the corresponding bit data can also be sampled in the clock cycle. Due to clock deviation and other reasons, a lag occurs from bit 8, and the bit data starting from bit 8 cannot be sampled correctly.

[0084] In order to correct the sampling error, when transmitting data, there needs to be enough flip signals on the line to correct the sampling error. Therefore, a symbol consists of three parts: 1 bit of start bit data, multiple bits of data and 1 bit of end bit data. Among them, the different levels of the start bit and the end bit are used to achieve signal flipping, which can be called flip bits. In order to save power consumption, when there is no data transmission, the line of the link can be always at a high level without signal flipping to maintain low power consumption. When data transmission is to be performed, the start of data transmission is marked by a low-level start bit, and after the data bit is transmitted, the end bit of the high level is used to mark the end of the transmission. Alternatively, when there is no data transmission, the line of the auxiliary link can be always at a low level without signal flipping. When data transmission is to be performed, the start of data transmission is marked by a high-level start bit, and after the data bit is transmitted, the end bit of the low level is used to mark the end of the transmission. Thus, signal flipping is achieved between two symbols by using start bits and end bits of different levels.

[0085] like Figure 5 The figure shows a schematic diagram of symbol transmission of an auxiliary link correcting sampling errors by flipping signals. When N symbols are transmitted, N is an integer greater than or equal to 2, for example, each symbol in multiple symbols (such as the first symbol and the second symbol) includes 10 bits, including 1 start bit, 8 data bits (bits 0 to 7) and 1 end bit. Assuming that when the transmitting side is in an idle state, the line of the auxiliary link is always at a high level, when the first symbol is to be transmitted, a low-level start bit is transmitted first, then data bits 0 to 7 are transmitted, and then a high-level end bit is transmitted. When the second symbol is transmitted immediately, a low-level start bit is also transmitted first, then data bits 0 to 7 are transmitted, and then a high-level end bit is transmitted. In this way, N symbols of a data packet can be transmitted. Since each symbol has a flip bit, for the receiving side, even if there is a clock deviation in the receiving sampling process, due to the signal flip on the line, the receiving end can use the signal flip to correct the sampling error.

[0086] However, the above symbol transmission method is equivalent to that when transmitting each symbol, multiple bits of data require the transmission time of the start bit and the end bit, which makes the bandwidth utilization rate low. Figure 5 In the example of FIG. 1 , for each symbol, 10 bits of transmission time are required to transmit 8 bits of data, and the bandwidth utilization is 80%.

[0087] Therefore, the present application provides a data transmission method for an interface, in which, when transmitting each symbol, each symbol includes (n+1) bits, n is an integer greater than or equal to 1, and a 1-bit flip bit is introduced for every n data bits to achieve sampling error correction. In this way, the bandwidth utilization of the auxiliary link can be increased to n / (n+1). For example, each symbol includes 9 bits, the first 8 bits are data bits, and the last bit is a flip bit, and the bandwidth utilization is 88.9%. Compared with the prior art that 10 bits of transmission time are required to transmit 8 bits of data, the bandwidth utilization of the auxiliary link in the present application is improved.

[0088] The following is an introduction to the embodiments of the present application.

[0089] It should be noted that in the method of the present invention, data transmission between interfaces can be transmitted on an auxiliary link or on a main link, and the present invention does not limit this.

[0090] like Figure 6 The figure shows a signal interaction diagram of a data transmission method of an interface, which includes the following process.

[0091] 601. The sending side generates at least one first data unit, and the at least one first data unit is continuous in the time domain, wherein each of the at least one first data unit includes n first data bits and a first bit, n is an integer greater than or equal to 1, the first bit is located after the n first data bits in the time domain, and the value of the first bit is opposite to the value of the nth first data bit among the n first data bits.

[0092] In some embodiments, the transmitting side is an electronic device or an interface device or a port device or an interface chip. When the transmitting side is an electronic device, the electronic device may be, for example, a source device, a sink device, a routing device, a docking station, or a composite device. When the transmitting side is an interface device, the interface device may be, for example, an interface chip. The interface chip may be, for example, an interface chip of a source device, a sink device, a routing device, a docking station, or a composite device.

[0093] The source device, the sink device and the composite device are electronic devices such as personal computers, monitors, audio and video devices, digital devices, printers, routers, game consoles and vehicle-mounted devices.

[0094] In some embodiments, at least one first data unit is a plurality of symbols, that is, each first data unit is a symbol, and the plurality of symbols are continuous in the time domain. Each symbol in the plurality of symbols includes (n+1) bits, including n first data bits and a first bit. The first bit is located after the n first data bits in the time domain, that is, the first bit is the last bit of each symbol. When the value of the first bit is opposite to the value of the nth first data bit in the n first data bits, it is used to implement signal flipping during symbol transmission.

[0095] In some embodiments, at least one first data unit is obtained by line coding the data to be sent. For example, the at least one first data unit obtained by coding is a plurality of symbols, each symbol including (n+1) bits. In some embodiments, when the transmission time of 1 bit is 1 clock cycle, the transmission time of each symbol is (n+1) clock cycles.

[0096] 602. The sending side sends at least one first data unit.

[0097] Correspondingly, the receiving side receives at least one first data unit sent by the sending side.

[0098] In some embodiments, the transmitting side sends at least one first data unit to the interface of the receiving side through the interface of the transmitting side. The at least one first data unit is transmitted on a link between the interface of the transmitting side and the interface of the receiving side.

[0099] For example, when the present application can be applied to the communication scenario between multiple devices in the above-mentioned UMI system, the sending side is the source device, the receiving side is the sink device, the source device and the sink device are directly connected, or the interface of the source device and the interface of the sink device are directly connected. Alternatively, the sending side is a source device or a composite device, the receiving side is a routing device, and the interface of the source device or the composite device is connected to the interface of the routing device. Alternatively, the sending side is a routing device, and the receiving side is a sink device or a composite device. Alternatively, the sending side is a source device and the receiving side is a composite device. Alternatively, the sending side is a composite device and the receiving side is a sink device. Alternatively, the sending side is an expansion dock, and the receiving side is one of a sink device, a routing device, or a composite device. Alternatively, the sending side is one of a source device, a routing device, or a composite device, and the receiving side is an expansion dock.

[0100] In some embodiments, when the transmitting side and the receiving side are electronic devices, the interface is, for example, an interface device, and the interface device is an interface chip. Alternatively, the interface is an interface module in the chip. For example, when applied in the above-mentioned UMI system, the interface is the above-mentioned UMI interface.

[0101] In some embodiments, the transmitting side sends at least one first data unit to the receiving side, including: a downlink port on the interface chip of the transmitting side sends at least one first data unit to an uplink port on the interface chip of the receiving side. Specifically, the at least one first data unit may be sent from a pin / line of a link channel of the downlink port to a pin / line of a link channel of the uplink port.

[0102] Exemplarily, when the sending side is a source device and the receiving side is a sink device, it is equivalent to a downlink port on an interface chip of the source device sending at least one first data unit to an uplink port on an interface chip of the sink device. When the sending side is a source device and the receiving side is a routing device, it is equivalent to a downlink port on an interface chip of the source device sending at least one first data unit to an uplink port on an interface chip of the sink device.

[0103] 603. The receiving side processes at least one first data unit to obtain first data.

[0104] The first data is a sampling result of at least one first data unit. In the case where each first data unit includes (n+1) bits, each first data unit includes n data bits, and only 1 bit is a flip bit. The value of the flip bit is opposite to the value of the nth bit transmitted in the time domain, and the bandwidth utilization of the link between the transmitting side and the receiving side interface is n / (n+1). Compared with the prior art, if each data unit includes (n+1) bits, the bandwidth utilization is (n-1) / (n+1). The design of the first data unit in the present application can not only realize signal flipping during line transmission and correct data sampling errors, but also improve the bandwidth utilization of the link between interfaces.

[0105] Exemplarily, taking at least one first data unit in step 601, step 602 and step 603 as a plurality of symbols, a first bit is inserted every n bits, and the first bit is used as a flip bit of the symbol. For each symbol, the signal of the first bit is the flip of the signal of the nth bit. For example, for binary data, the flip of 0 is 1, and the flip of 1 is 0. Assuming that a low level is used to represent 0 and a high level is used to represent 1, the first bit in this application is a flip bit, which means that if the level of the nth bit in the time domain is a low level, the level of the first bit is a high level, and if the level of the nth bit is a high level, the level of the first bit is a low level. Assuming that a low level is used to represent 1 and a high level is used to represent 0, the first bit in this application is a flip bit, which means that if the level of the nth bit in the time domain of each symbol is a low level, the level of the first bit is a high level, and if the level of the nth bit in the time domain of each symbol is a high level, the level of the first bit is a low level.

[0106] In other words, if the duration of transmitting each bit is 1 clock cycle, (n+1) clock cycles are 1 symbol cycle. In the (n+1) clock cycles of a symbol cycle, the (n+1)th clock cycle signal is the flip of the nth clock cycle signal. The first n clock cycles are used to transmit the data of the above n first data bits, and the n+1th clock cycle is used to transmit the flip bit of the nth bit.

[0107] For example, Figure 7 The figure shows a schematic diagram of transmitting multiple symbols. When the number of multiple symbols is m, the m symbols are recorded as symbol 0 to symbol m-1. Each of the m symbols includes (n+1) bits, and the (n+1) bits are recorded as bit 0 to bit n, where bit 0 to bit n-1 are the first data bits, and bit n is the first bit, that is, the flip bit T. D i (n-1:0) represents bit 0 to bit n-1 of the i-th symbol, and the value range of i is 0 to m-1. The value of bit n of each symbol is opposite to the value of bit (n-1). For example, when the value of bit n-1 is 1, the value of bit n is 0, and when the value of bit (n-1) is 0, the value of bit n is 1. For the receiving side, by sampling these m symbols, the data transmitted by the first n data bits of each symbol in the m symbols can be obtained, that is, the first data.

[0108] Thus, assuming that n is 8, the bandwidth utilization of the interface link is about 88.9%. Compared with the prior art in which n is 8, the bandwidth utilization of the link is about 80%, and the bandwidth utilization of the present application is improved by 8.9% relative to the prior art. Moreover, the last bit of each of the multiple symbols is the flip bit of the previous bit in the time domain, which can ensure that there is a signal flip in each symbol or every n+1 clock cycles, which is beneficial to correcting sampling errors when the receiving side performs data sampling.

[0109] In order to distinguish different burst transmission data packets, in the present application, an end symbol may be introduced to indicate the end of a burst transmission.

[0110] Therefore, in some embodiments, Figure 8 The figure shows a signal interaction diagram of a data transmission method of an interface, and the method also includes the following process.

[0111] 604. The sending side generates a second data unit, the second data unit includes n second data bits and a second bit, the second bit is located after the n second data bits in the time domain, and the value of the second bit is the same as the value of the nth second data bit among the n second data bits.

[0112] In some embodiments, at least one first data unit and at least one second data unit are both data units belonging to one burst transmission.

[0113] Exemplarily, according to the above example, the second data unit is a symbol, denoted as symbol m, and a data packet of a burst transmission includes symbol 0 to symbol m-1 and symbol m, a total of (m+1) symbols, or (m+1) consecutive symbols are a burst transmission. Symbol m is the (m+1)th symbol in a data packet of a burst transmission, and symbol m includes n second data bits and a second bit. The second bit is the (n+1)th bit of symbol m in the time domain, and the second bit is located after the n second data bits in the time domain. The value of the second bit is the same as the value of the nth second data bit among the n second data bits.

[0114] 605. The sending side sends a second data unit, where the second data unit is located after at least one first data unit in the time domain and is used to indicate the end of a burst transmission.

[0115] Correspondingly, the receiving side receives the second data unit. The second data unit may also be referred to as an end of burst (EOB).

[0116] For example, Fig. 9 The following is a schematic diagram of a burst transmission. Figure 7 Based on the first m symbols shown, the transmitting side continues to send the m+1th symbol: symbol m. In the time domain, symbol m is after the mth symbol and is continuous with the mth symbol. Symbol m can be called EOB symbol. Among them, the first n bits of symbol m, that is, bit 0 to bit n-1, are data bits (D m (n-1:0)), the symbol m is located at the last bit in the time domain, that is, the n+1th bit (bit n) is recorded as bit K. The value of bit K is the same as the value of the nth bit of symbol m. For example, when the value of the nth bit (bit n-1) is 0, the value of bit K is also 0, and when the value of the nth bit is 1, the value of bit K is also 1.

[0117] In other words, if the duration of transmitting each bit is 1 clock cycle, (n+1) clock cycles are 1 symbol cycle. In a burst transmission, in the (n+1) clock cycle of the (m+1)th symbol transmitted, the (n+1)th clock cycle signal is the same as the signal of the nth clock cycle, or in other words, the level of the (n+1)th clock cycle is the same as the level of the nth clock cycle. The first n clock cycles are used to transmit the data of n second data bits, and the (n+1)th clock cycle is used to transmit the data of the (n+1)th bit / second bit, and the value of the second bit is the same as the value of the nth second data bit among the n second data bits.

[0118] In some embodiments, after the burst transmission is completed, the line returns to the idle state. For example, the idle state is high level, and the sending side transmits K bits, which means that the burst transmission is completed and the line returns to the idle state, that is, the line returns to the high level state (such as Fig. 9 Of course, the line can also be low level in idle state ( Fig. 9 (not shown in the figure), at this time, after the sending side transmits K bits, the line returns to a low level state.

[0119] 606. The receiving side processes the second data unit to obtain second data.

[0120] The second data is a sampling result of a second data unit. The first data and the second data are data belonging to one burst transmission.

[0121] Exemplary, reference Fig. 9 For example, for the receiving side, the end of a burst transmission can be identified based on K bits. That is, if the value of the (n+1)th bit of a symbol is the same as the value of the nth bit, it means that K bits are received, which means that a burst is over.

[0122] In some embodiments, after a burst transmission is received, the line can be restored to an idle state. For example, the idle state is a high level, and the receiving side receives K bits, which means that this burst transmission is over and the line is restored to an idle state, that is, the line returns to a high level state. Of course, the line can also be a low level in the idle state. In this case, after the receiving side receives K bits, the line returns to a low level state.

[0123] It should be noted that when the sending side performs line coding, the second data unit may be generated before the first data unit or after the second data unit. It is just that when the sending side sends data, in the time domain, the second data unit is sent after the first data unit.

[0124] In order to further improve the reliability of data transmission and avoid the receiving side from misjudging the start of a burst transmission due to disturbances and other reasons, in the present application, a third data unit can be introduced as a data unit indicating the start of a burst transmission, or as the first data unit transmitted in the time domain of a burst transmission, that is, it can be sent before at least one first data unit. The third data unit also includes (n+1) bits, but the difference is that the (n+1) bits here are not data bits, but bits used to indicate the start of a burst transmission. In this way, the error of not being able to correctly identify the start of a burst transmission caused by a K-bit detection error can be prevented. The present application can avoid the above-mentioned misjudgment problem by designing the transmission bits of the third data unit.

[0125] Therefore, if Figure 8As shown, the method may also include the following process.

[0126] 607. The sending side generates a third data unit, where the third data unit includes a third bit and a fourth bit, where the fourth bit is located after the third bit in the time domain, and a value of the fourth bit is opposite to a value of the third bit.

[0127] In some embodiments, the value of the third bit is opposite to the value of the bit indicating the idle state, and the value of the fourth bit is the same as the value of the bit indicating the idle state.

[0128] In some embodiments, at least one first data unit and a third data unit are both data units belonging to a burst transmission. In the present application, the third data unit is recorded as a start of burst (SOB).

[0129] In some embodiments, before sending at least one first data unit, the transmitting side generates a third data unit to indicate the start of a burst transmission.

[0130] Exemplarily, according to the above example, the third data unit is a symbol, and is (n+1) bits, when recorded as SOB, the SOB includes n third bits and fourth bits. The n third bits are the first n bits included in the SOB, and the fourth bit is the (n+1)th bit included in the SOB, and the fourth bit is located after the n third bits in the time domain. The value of the fourth bit is opposite to the value of the third bit. Optionally, the value of the n third bits is opposite to the value of the idle state, and the value of the fourth bit is the same as the value of the idle state. If the bit value of the idle state is 1, the value of the n third bits is 0, and the value of the fourth bit is 1. If the bit value of the idle state is 0, the value of the n third bits is 1, and the value of the fourth bit is 0. From the perspective of the signal, if the signal level of the idle state is high, the signal level of the clock cycle of the n third bits is low, and the signal level of the clock cycle of the fourth bit is high. If the signal level in the idle state is a low level, the signal level in the clock cycles of the n third bits is a high level, and the signal level in the clock cycle of the fourth bit is a low level.

[0131] In another embodiment, the third data unit is (n+2) bits, and when it is recorded as SOB, the SOB includes (n+1) third bits and a fourth bit. The (n+1) third bits are the first (n+1) bits included in the SOB, and the fourth bit is the (n+2)th bit included in the SOB, and the fourth bit is located after the (n+1) third bit in the time domain. The value of the fourth bit is opposite to the value of the third bit. The third data unit is (n+2) bits, and more time can be used for error recovery and low-power wake-up. Optionally, the value of the (n+1) third bits is opposite to the value of the idle state, and the value of the fourth bit is the same as the value of the idle state. If the bit value of the idle state is 1, the value of the (n+1) third bit is 0, and the value of the fourth bit is 1. If the bit value of the idle state is 0, the value of the (n+1) third bit is 1, and the value of the fourth bit is 0. From the perspective of the signal, if the signal level of the idle state is high, the signal level of the (n+1) third bit clock cycle is low, and the signal level of the fourth bit clock cycle is high. If the signal level of the idle state is low, the signal level of the (n+1) third bit clock cycle is high, and the signal level of the fourth bit clock cycle is low.

[0132] 608. The sending side sends a third data unit, where the third data unit is located before at least one first data unit in the time domain and is used to indicate the start of a burst transmission.

[0133] Accordingly, the receiving side receives the third data unit.

[0134] In some embodiments, a burst transmission includes a third data unit indicating the start of the burst transmission, at least one first data unit, and a second data unit indicating the end of the burst transmission.

[0135] For example, Fig. 9 (a) and (b) in the figure are schematic diagrams of a burst transmission. When the sending side transmits a burst transmission, the data packet of a burst transmission includes SOB and symbol 0 to symbol m, with a total of (m+2) symbols, or (m+2) consecutive symbols as the transmission time of a burst transmission. SOB is the first symbol in a burst transmission data packet, symbol 0 to symbol m are data symbols used to transmit the bits of the burst data packet, and symbol m is the (m+2)th symbol transmitted in the time domain. When symbol m is the above-mentioned EOB, it is used to indicate the end of a burst transmission.

[0136] When the third data unit is (n+1) bits, Fig. 9As shown in (a), when the state is idle before a burst transmission starts, and the idle state level is high, the level of the first n third bits of the SOB is low, and the level of the fourth bit is high, for example Fig. 9 As shown in (a), the first n third bits are examples for bit D SOB (n-1:0). Similarly, Fig. 9 As not shown in (a), when the state is idle before a burst transmission starts and the idle state level is low, the levels of the first n third bits of the SOB are high and the level of the fourth bit is low.

[0137] In other words, if the duration of transmitting each bit is 1 clock cycle, (n+1) clock cycles are the symbol period of 1 SOB. In a burst transmission, in the (n+1) clock cycles of the transmitted SOB, the first n clock cycles are used to transmit n third bits, and the (n+1)th clock cycle is used to transmit the fourth bit. The value of the third bit is opposite to the value of the idle state, and the value of the fourth bit is the same as the value of the idle state. The signal of the first n clock cycles is different from the signal of the clock cycle of the idle state, or in other words, the level of the first n clock cycles is opposite to the level of the signal of the clock cycle of the idle state. The signal of the (n+1)th clock cycle is the same as the signal of the clock cycle of the idle state, or in other words, the level of the n+1th clock cycle is the same as the level of the clock cycle of the idle state.

[0138] When the third data unit is (n+2) bits, Fig. 9 As shown in (b), when the state is idle before a burst transmission starts, and the idle state level is high, the level of the first n+1 third bits of the SOB is low, and the level of the fourth bit is high. Fig. 9 As shown in (b), the first n+1 third bits are for bit D SOB (n:0). Similarly, Fig. 9 As not shown in (b), when the state is idle before a burst transmission starts and the idle state level is low, the levels of the first n+1 third bits of the SOB are high and the level of the fourth bit is low.

[0139] In other words, if the duration of transmitting each bit is 1 clock cycle, (n+2) clock cycles are the symbol period of 1 SOB. In a burst transmission, in the (n+2) clock cycles of the transmitted SOB, the first n+1 clock cycles are used to transmit the n+1 third bits, and the (n+2)th clock cycle is used to transmit the fourth bit. The value of the third bit is opposite to the value of the idle state, and the value of the fourth bit is the same as the value of the idle state. The signal of the first n+1 clock cycles is different from the signal of the clock cycle of the idle state, or in other words, the level of the first n+1 clock cycles is opposite to the level of the signal of the clock cycle of the idle state. The signal of the (n+2)th clock cycle is the same as the signal of the clock cycle of the idle state, or in other words, the level of the n+2th clock cycle is the same as the level of the clock cycle of the idle state.

[0140] 609. The receiving side processes the third data unit to obtain third data.

[0141] The first data and the third data are data belonging to one burst transmission.

[0142] refer to Fig. 9 In the example in , the receiving side receives this burst transmission, in which the burst transmission includes an SOB symbol and symbol 0 to symbol m, where symbol 0 to symbol (m-1) are data symbols and symbol m is an EOB symbol. Since SOB is not a data symbol, the receiving result of this burst transmission includes first data, second data and third data, where the first data is the data of n first data bits of each symbol from symbol 0 to symbol (m-1), the second data is the data of n second data bits of symbol m, and the third data is ignored.

[0143] In some embodiments, the third data unit time may be used as a low-power wake-up time to wake up other circuits in the link for data reception and data processing, such as a management adapter.

[0144] In some embodiments, after a burst transmission ends, the next burst transmission may be transmitted, and there is no idle state between the two burst transmissions. That is, the EOB of the previous burst transmission is continuous with the SOB of the next burst transmission. In some implementation methods of the present invention, the first n bits of the SOB of the next burst transmission have the same value as the bits of the idle state, and the actual effect is also equivalent to that after the previous burst transmission ends, the line of the link between the interfaces returns to the idle state.

[0145] For example, Fig.10The figure shows a transmission diagram of two burst transmissions. The two consecutive burst transmissions sent by the transmitting side are recorded as burst0 (burst transmission 0) and burst1 (burst transmission 1). The symbols transmitted by burst0 include SOB0, symbol 0 to symbol m, and EOB0, and the symbols transmitted by burst1 include SOB1, symbol '0 to symbol 'm, and EOB 1. The number of symbols from symbol 0 to symbol m may be the same as the number of symbols from symbol '0 to symbol 'm, or it may be different. Fig.10 , SOB1 is continuous with EOB 0. Alternatively, if each symbol in the two burst transmissions includes (n+1) bits, it can also be said that the first bit of SOB1 is located after the (n+1)th bit of EOB0, and the first bit of SOB 1 is continuous with the (n+1)th bit of EOB 0.

[0146] In this way, if the second bit of EOB 0 transmitted in burst0 is erroneous due to clock frequency deviation, jitter, etc., for example, the second bit does not undergo signal inversion, and the level of the second bit is different from the level of the nth bit of EOB 0, the receiving side does not know the end of burst0 transmission when sampling. If burst1 does not transmit SOB 1, the receiving side cannot accurately identify the time when burst1 starts to transmit data symbols, which will cause the receiving side to make timing errors for burst1. However, if SOB 1 is transmitted first when burst1 starts to transmit, the receiving side can accurately identify the time when burst1 starts to transmit data symbols based on the bit data transmitted by SOB 1, avoiding the receiving side's timing errors for burst1 and improving the transmission reliability of the link between interfaces.

[0147] It is described above that the start of a burst transmission can be indicated by a third data unit of a burst transmission, and a burst transmission includes the third data unit. In some embodiments, the present application can also indicate the start of a burst transmission by a fourth data unit, and the fourth data unit includes 1 bit. This 1 bit can be understood as a start bit. Therefore, if Fig.11 The figure shows a signal interaction diagram of a data transmission method of an interface, which includes the following processes.

[0148] 111. The sending side generates a fourth data unit, the fourth data unit includes a fifth bit, the fourth data unit is located before at least one first data unit in the time domain, the value of the fifth bit is opposite to the value of the bit indicating the idle state, and the at least one first data unit is a data unit belonging to a burst transmission.

[0149] In some embodiments, at least one first data unit and a second data unit are both data units belonging to a burst transmission, and the fourth data unit is located before the at least one first data unit in the time domain and is used to indicate the start of a burst transmission.

[0150] Exemplarily, according to the above example, the fourth data unit includes a fifth bit. If the bit value of the idle state is 1, the value of the fifth bit is 0. If the bit value of the idle state is 0, the value of the fifth bit is 1.

[0151] In other words, in this implementation, when the fifth bit is used as the start bit, the start of a burst transmission is marked by flipping the idle state. The fifth bit is the flip of the line level in the idle state. If the line of the link is at a low level in the idle state, a high level of one clock cycle can be used to indicate the start of a burst transmission; if the line of the link is at a high level in the idle state, a high level of one clock cycle can be used to indicate the start of a burst transmission. That is, the bit of one clock cycle before a burst transmission is the flip of the line level of the link in the idle state.

[0152] 112. The sending side sends a fourth data unit.

[0153] Accordingly, the receiving side receives the fourth data unit.

[0154] 113. The receiving side recognizes the start of a burst transmission according to the fourth data unit.

[0155] In some embodiments, when the receiving side detects a signal flip, if the sending side and the receiving side execute steps 601 to 606 above, a burst transmission includes at least one first data unit and a second data unit indicating the end of the burst transmission, and the data of a burst transmission sampled by the receiving side includes the first data collected from at least one first data unit and the second data collected from the second data unit.

[0156] like Fig.12 The figure shows a transmission diagram of a burst transmission. Before the sending side transmits a burst transmission, it is assumed that the line level of the link is low in the idle state, such as Fig.12 As shown in , the transmitting side first transmits the fifth bit, the level of the fifth bit is high, and then transmits the symbol 0 after the fifth bit in the time domain, and the symbol 0 is continuous with the fifth bit. Similarly, Fig.12 Not shown in FIG, if the line level of the link is high in the idle state, the level of the fifth bit is low. Fig.12 As shown, when symbol m is EOB, if each symbol includes (n+1) bits, the receiving side recognizes that this burst transmission ends when sampling the (n+1)th bit (K bits) of symbol m.

[0157] In this way, when the transmitting side sends a burst transmission, not only can the bandwidth utilization rate be increased to n / (n+1), but the idle state can also be flipped through the fourth data unit to indicate the start of a burst transmission.

[0158] In some embodiments, if there is no data to be continuously sent after the EOB of a burst transmission, the line of the inter-interface link returns to an idle state.

[0159] In addition, in some embodiments of the present application, the value of n may be fixed, for example, n is 8, or other fixed values.

[0160] In some embodiments, the value of n can be set or configured according to the channel conditions of the link transmission signal between the interfaces. In one possible manner, the value of n is related to the clock period (or sampling clock period) of receiving and transmitting a 1-bit signal and the maximum offset of the receiving and transmitting clock in each clock period.

[0161] Exemplarily, the value of n is the smallest integer that satisfies the relationship shown in formula (1).

[0162]

[0163] Where Δ represents the maximum offset of the transmit and receive clocks in each symbol and each clock cycle, T UI Indicates the clock period (or sampling clock period) for sending and receiving 1 bit of signal in each symbol.

[0164] In this way, the calculation method of formula (1) can ensure that the sampling deviation at the receiving side reaches within one symbol. Previously, a bit flip occurred to correct the sampling deviation by bit flipping.

[0165] For example, T UI When the value is 800 nanoseconds (ns) and Δ is 50ns, the maximum value of n is 8. Thus, each symbol includes 9 bits, of which the first 8 bits in the time domain are data bits, and the last bit is a flip bit (in the case of a data symbol) or has the same level as the 8th bit (EOB symbol).

[0166] Therefore, in the present application, the number of data bits of each symbol is determined according to the clock cycle (or sampling clock cycle) for transmitting and receiving a 1-bit signal and the maximum offset of the receiving and transmitting clock in each clock cycle, and it is possible to ) before the sampling deviation is corrected in time by flipping the bits, thus improving the data transmission efficiency of the link between interfaces.

[0167] It is understandable that in order to implement the functions in the above embodiments, the sending side and the receiving side include hardware structures and / or software modules corresponding to the execution of each function. It should be easy for those skilled in the art to realize that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0168] Fig.13 and Fig.14 The following is a schematic diagram of the structure of possible interface devices provided in the embodiments of the present application. These interface devices can be used to implement the functions of the sending side or the receiving side in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. In the embodiments of the present application, the interface device can be as follows: Figure 1 One of the devices 1011 or 1021 shown in FIG. 1 may also be Figure 1 One of the devices 103 to 106 shown, or the above Figure 2 The devices shown may also be applied to interface modules (such as chips or chipsets) of these devices. The relevant interface devices are used to implement interface data transmission, for example, they may be used to implement the UMI interface functions described above.

[0169] like Fig.13 As shown, the interface device 130 includes a processing module 1310 and a transceiver module 1320. The interface device 130 is used to implement the above Figure 6 , Figure 8 and Fig.11 The functions of the sending side or the receiving side in the method embodiment shown in FIG.

[0170] When the interface device 130 is used to implement Figure 6 , Figure 8 and Fig.11 In the method embodiment shown, the functions of the sending side are: the processing module 1310 can be used to generate at least one first data unit, a second data unit, and a third data unit. Alternatively, the processing module 1310 can be used to generate at least one first data unit and a fourth data unit. The transceiver module 1320 is used to send at least one first data unit, a second data unit, and a third data unit. Alternatively, the transceiver module 1320 can be used to send at least one first data unit and a fourth data unit;

[0171] When the interface device 130 is used to implement Figure 6 , Figure 8 and Fig.11The functions of the receiving side in the method embodiment shown are as follows: the transceiver module 1320 is used to receive at least one first data unit, a second data unit and a third data unit. Alternatively, the transceiver module 1320 is used to receive at least one first data unit and a fourth data unit; the processing module 1310 is used to process at least one first data unit to obtain first data, to process the second data unit to obtain second data, and to process the third data unit to obtain third data; alternatively, the processing module 1310 is used to process at least one first data unit to obtain first data, and to process the fourth data unit to obtain fourth data.

[0172] For more detailed description of the processing module 1310 and the transceiver module 1320, please refer to Figure 6 , Figure 8 and Fig.11 The method embodiment shown is described in detail.

[0173] like Fig.14 As shown, the interface device 140 includes a processor 1410 and an interface circuit 1420. The processor 1410 and the interface circuit 1420 are coupled to each other. It is understood that the interface circuit 1420 can be a transceiver or an input-output interface. Optionally, the interface device 140 can also include a memory 1430 for storing instructions executed by the processor 1410 or storing input data required by the processor 1410 to execute instructions or storing data generated after the processor 1410 executes instructions.

[0174] When the interface device 140 is used to implement Figure 6 , Figure 8 and Fig.11 In the method shown, the processor 1410 is used to implement the functions of the processing module 1310, and the interface circuit 1420 is used to implement the functions of the transceiver module 1320. The interface circuit 1420 can be an interface chip or a separate IP module integrated in the interface chip.

[0175] When the interface device 140 is an interface chip applied to the sending side, the interface chip on the sending side implements the functions of the sending side in the above method embodiment. The interface chip on the sending side sends data to the receiving side, which can be understood as the data being first generated by other modules (such as source data components) on the sending side and then sent to the interface chip on the sending side by these modules.

[0176] When the interface device 140 is an interface chip applied to the receiving side, the interface chip on the receiving side implements the functions of the receiving side in the above method embodiment. The interface chip on the receiving side receives data from the sending side, which can be understood as the data is first received by the interface chip on the receiving side, and then sent by the interface chip on the receiving side to the data processing component on the receiving side.

[0177] In the present application, when entity A sends information to entity B, it can be that A sends it directly to B, or that A sends it to B indirectly through other entities. Similarly, when entity B receives information from entity A, it can be that entity B directly receives the information sent by entity A, or that entity B indirectly receives the information sent by entity A through other entities. The entities A and B here can be the sending side or the receiving side, or they can be modules inside the sending side or the receiving side. The sending and receiving of data can be the information interaction between the sending side and the receiving side, for example, the information interaction between the source device and the host device; the sending and receiving of data can also be the information interaction between different modules inside a device, for example, the information interaction between the interface chip on the sending side and the interface chip on the receiving side.

[0178] It is understandable that the processor in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0179] The method steps in the embodiments of the present application can be implemented in hardware or in software instructions that can be executed by a processor. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. The storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a base station or a terminal. The processor and the storage medium can also be present in a base station or a terminal as discrete components.

[0180] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc; it may also be a semiconductor medium, for example, a solid-state hard disk. The computer-readable storage medium may be a volatile or nonvolatile storage medium, or may include both volatile and nonvolatile types of storage media.

[0181] In the various embodiments of the present application, unless otherwise specified or provided for in any logical conflict, the terms and / or descriptions between the different embodiments are consistent and may be referenced to each other, and the technical features in the different embodiments may be combined to form new embodiments according to their inherent logical relationships.

[0182] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. In the text description of this application, the character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "Including at least one of A, B and C" can mean: including A; including B; including C; including A and B; including A and C; including B and C; including A, B and C.

[0183] It is understood that the various numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. The size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic.

Claims

1. A data transmission method for an interface, characterized in that: include: Generate at least one first data unit, each of the at least one first data unit is a data symbol, and the at least one first data unit is continuous in the time domain, wherein each of the at least one first data unit includes n first data bits and a first bit, n is an integer greater than or equal to 1, the first bit is located after the n first data bits in the time domain, and a value of the first bit is opposite to a value of an nth first data bit among the n first data bits; The at least one first data unit is sent.

2. The method according to claim 1, characterized in that The method further comprises: generating a second data unit, wherein the second data unit is a burst end EOB; Sending the second data unit, where the second data unit is located after the at least one first data unit in the time domain and is used to indicate the end of a burst transmission; The second data unit includes n second data bits and a second bit, the second bit is located after the n second data bits in the time domain, and the value of the second bit is the same as the value of the nth second data bit among the n second data bits.

3. The method according to claim 2, characterized in that The at least one first data unit and the second data unit are both data units belonging to the burst transmission.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: generating a third data unit, wherein the third data unit is a burst start SOB; Sending the third data unit, where the third data unit is located before the at least one first data unit in the time domain and is used to indicate the start of a burst transmission; Among them, the third data unit includes n+1 third bits and a fourth bit, the fourth bit is located after the n+1 third bits in the time domain, the value of the fourth bit is opposite to the value of the n+1 third bits, the value of the n+1 third bits is 0, and the value of the fourth bit is 1.

5. The method according to claim 4, characterized in that The first data unit and the third data unit are both data units belonging to the one burst transmission.

6. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: generating a fourth data unit; The fourth data unit is sent, the fourth data unit includes a fifth bit, the fourth data unit is located before the at least one first data unit in the time domain and is used to indicate the start of a burst transmission, the value of the fifth bit is opposite to the value of the bit indicating the idle state, and the at least one first data unit is a data unit belonging to the burst transmission.

7. A data transmission method for an interface, characterized in that: include: Receive at least one first data unit, each of the at least one first data unit is a data symbol, and the at least one first data unit is continuous in the time domain, wherein each of the at least one first data unit includes n first data bits and a first bit, n is an integer greater than or equal to 1, the first bit is located after the n first data bits in the time domain, and a value of the first bit is opposite to a value of an nth first data bit among the n first data bits; The at least one first data unit is processed to obtain first data.

8. The method according to claim 7, characterized in that The method further comprises: receiving a second data unit, where the second data unit is a burst end EOB, the second data unit is located after the at least one first data unit in the time domain and is used to indicate the end of a burst transmission; The second data unit includes n second data bits and a second bit, the second bit is located after the n second data bits in the time domain, and a value of the second bit is the same as a value of an nth second data bit among the n second data bits; The second data unit is processed to obtain second data.

9. The method according to claim 8, characterized in that The first data and the second data are data belonging to the one burst transmission.

10. The method according to any one of claims 7 to 9, characterized in that: Before receiving the at least one first data unit, the method further comprises: receiving a third data unit, wherein the third data unit is a burst start SOB, the third data unit is located before the at least one first data unit in the time domain and is used to indicate the start of a burst transmission; The third data unit includes n+1 third bits and a fourth bit, the fourth bit is located after the n+1 third bits in the time domain, the value of the fourth bit is opposite to the value of the n+1 third bits, the value of the n+1 third bits is 0, and the value of the fourth bit is 1; The third data unit is processed to obtain third data.

11. The method according to claim 10, characterized in that The first data and the third data are data belonging to the one burst transmission.

12. The method according to any one of claims 7 to 9, characterized in that: The method further comprises: A fourth data unit is received, wherein the fourth data unit includes a fifth bit, the fourth data unit is located before the at least one first data unit in the time domain and is used to indicate the start of a burst transmission, the value of the fifth bit is opposite to the value of the bit indicating the idle state, and the at least one first data unit is a data unit belonging to the burst transmission.

13. An interface device, characterized in that: The interface device comprises: a processing module, configured to generate at least one first data unit, each of the at least one first data unit being a data symbol, and the at least one first data unit being continuous in a time domain, wherein each of the at least one first data unit comprises n first data bits and a first bit, n being an integer greater than or equal to 1, the first bit being located after the n first data bits in the time domain, and a value of the first bit being opposite to a value of an nth first data bit among the n first data bits; The sending module is used to send the at least one first data unit.

14. An interface device, characterized in that: The interface device comprises: A receiving module, configured to receive at least one first data unit, each of the at least one first data unit is a data symbol, and the at least one first data unit is continuous in a time domain, wherein each of the at least one first data unit includes n first data bits and a first bit, n is an integer greater than or equal to 1, the first bit is located after the n first data bits in the time domain, and a value of the first bit is opposite to a value of an nth first data bit among the n first data bits; The processing module is used to process the at least one first data unit to obtain first data.

15. An interface device, characterized in that: The method comprises a module for executing the method as claimed in any one of claims 1 to 12.

16. An interface device, characterized in that: The interface device comprises a processor and a memory, wherein the memory is used to store computer-executable instructions. When the computer-executable instructions are executed by the processor, the method according to any one of claims 1 to 12 is executed.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and when the computer instructions are executed on the interface device, the interface device executes the method according to any one of claims 1 to 12.

18. A computer program product, characterized in that The method comprises computer instructions, which, when executed on an interface device, cause the interface device to execute the method according to any one of claims 1 to 12.

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