Multi-modal expandable high-performance homomorphic encryption system

Abstract

The invention discloses a multi-modal extensible high-performance homomorphic encryption system, and relates to the technical field of computer systems, the system comprises an upper-layer server software and drive architecture and a multi-modal homomorphic encryption hardware architecture realized based on an FPGA (Field Programmable Gate Array), which are in communication connection; the upper-layer server software and drive architecture comprises a multi-modal homomorphic encryption algorithm software library, a software memory scheduler, a modulo calculation module software drive and a floating point calculation module software drive; the multi-modal homomorphic encryption hardware architecture realized based on the FPGA comprises a communication data controller, a plurality of modulo calculation modules, a floating point calculation module, a data read-write bus and a high-bandwidth memory, and each modulo calculation module comprises a fast number theory transformation calculation unit. Through a software and hardware collaborative design scheme, the problem of low scheduling efficiency of ciphertext calculation tasks of different scales in hardware architecture design under multi-modal homomorphic encryption is solved, and the calculation efficiency is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of computer system technology, and in particular to a multi-modal scalable high-performance homomorphic encryption system. Background Art

[0002] Homomorphic encryption is an encryption technology that allows computing operations to be performed directly in the ciphertext state without decryption. Its main advantage is that it can process data while ensuring data privacy. This feature makes homomorphic encryption a hot topic in many application scenarios, such as data analysis in cloud computing, privacy protection of medical data, and secure computing of financial data. However, homomorphic encryption also has some disadvantages, including high computational complexity, high performance overhead, and the scheduling of multiple homomorphic encryption schemes (multimodal homomorphic encryption) in practical applications has become a challenge. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to propose a multi-modal scalable high-performance homomorphic encryption system to improve the computational efficiency of homomorphic encryption.

[0004] To achieve the above objectives, the embodiment of the present application proposes a multi-modal scalable high-performance homomorphic encryption system, the system comprising an upper-layer server software and driver architecture and a multi-modal homomorphic encryption hardware architecture based on FPGA;

[0005] Wherein, the upper server software and driver architecture are communicatively connected with the multi-modal homomorphic encryption hardware architecture implemented based on FPGA;

[0006] The upper server software and driver architecture includes a multimodal homomorphic encryption algorithm software library, a software memory scheduler, a modulus calculation module software driver, and a floating-point calculation module software driver;

[0007] The multi-modal homomorphic encryption hardware architecture based on FPGA includes a communication data controller, multiple modulus calculation modules, a floating-point calculation module, a data read-write bus and a high-bandwidth memory; each of the modulus calculation modules includes a fast number theory transformation calculation unit;

[0008] Among them, the communication data controller and the upper-level server software are communicatively connected to the drive architecture, and the communication data controller is also communicatively connected to each of the modulo calculation modules and the floating-point calculation modules respectively; the data read and write bus is communicatively connected to the communication data controller, each of the modulo calculation modules, the floating-point calculation module, and the high-bandwidth memory respectively.

[0009] In some embodiments, the multimodal homomorphic encryption algorithm software library is used to manage and schedule multimodal homomorphic encryption algorithms;

[0010] The software memory scheduler is used to manage and schedule memory resources;

[0011] The modulus calculation module software driver is used to control and drive each of the modulus calculation modules;

[0012] The floating-point calculation module software driver is used to control and drive the floating-point calculation module.

[0013] In some embodiments, the communication data controller is used to manage the interactive data between the upper-layer server software and the driver architecture and the multi-modal homomorphic encryption hardware architecture implemented based on FPGA;

[0014] Each of the modulo calculation modules is used for modulo calculation;

[0015] The floating point calculation module is used for floating point calculation;

[0016] The data read-write bus is used to transmit data;

[0017] The high bandwidth memory is used to store ciphertext data and intermediate calculation results.

[0018] In some embodiments, the upper server software and driver architecture are communicatively connected to the multi-modal homomorphic encryption hardware architecture implemented based on FPGA via a PCIe data communication interface;

[0019] The communication data controller adopts a PCIe data controller;

[0020] The PCIe data controller is respectively connected to the modulo calculation module and the floating-point calculation module through the calculation module control signaling data path.

[0021] In some embodiments, each of the modulo calculation module and the floating-point calculation module includes a memory array composed of a plurality of SRAM memory blocks, a data multiplexer, a memory block read / write address generator, a configurable parameter register, and a memory data read / write path;

[0022] Wherein, each of the SRAM memory blocks is used to store data;

[0023] The data multiplexer includes a data write path and a data read path, and the data multiplexer is used to read and write distribution data;

[0024] The memory block read / write address generator is used to generate the read / write address of each of the SRAM memory blocks;

[0025] The configurable parameter register is used to store configuration parameters, which are configured by the upper server software and the driver architecture through the computing module control signaling data path;

[0026] The memory data read / write path is connected to the high bandwidth memory, and the memory data read / write path is used to read and write data.

[0027] In some embodiments, each of the SRAM memory blocks is used to store intermediate data;

[0028] Wherein, each of the SRAM memory blocks includes a plurality of SRAM memory cells; each of the SRAM memory blocks includes a read / write interface with a width of 1024 bits;

[0029] The storage capacity of each of the SRAM memory cells is 4096 words of data, each word of data is 64 bits; the storage capacity of a single SRAM memory block is 65536 words of data.

[0030] In some embodiments, the memory array is provided with a data read and write channel A and a data read and write channel B;

[0031] The data read and write channel A is connected to each of the modulo calculation modules, and the data read and write channel B is connected to the floating-point calculation module.

[0032] In some embodiments, the fast number theoretic transformation computing unit is used to execute a homomorphic encryption algorithm through a plurality of the memory arrays operating in parallel.

[0033] In some embodiments, the upper server software and driver architecture are used to merge several physical blocks in the high bandwidth memory into a virtual block, thereby obtaining a plurality of virtual blocks; each virtual block corresponds to one modulus calculation module;

[0034] Each of the virtual blocks is divided into a plurality of virtual sub-blocks, and each of the virtual sub-blocks is used to store polynomial coefficients of different RNS bases.

[0035] In some embodiments, the multimodal homomorphic encryption algorithm software library includes a CKKS homomorphic encryption algorithm, a BFV homomorphic encryption algorithm, and a BGV homomorphic encryption algorithm.

[0036] The embodiments of the present application include at least the following beneficial effects:

[0037] The system of the present application includes an upper-layer server software and driver architecture and a multimodal homomorphic encryption hardware architecture based on FPGA; the upper-layer server software and driver architecture includes a multimodal homomorphic encryption algorithm software library, a software memory scheduler, a modulo calculation module software driver, and a floating-point calculation module software driver; the multimodal homomorphic encryption hardware architecture based on FPGA includes a communication data controller, multiple modulo calculation modules, a floating-point calculation module, a data read-write bus, and a high-bandwidth memory; each modulo calculation module includes a fast number theory transformation calculation unit. The present application solves the problem of inefficient scheduling of ciphertext calculation tasks of different scales under multimodal homomorphic encryption in hardware architecture design through a software-hardware collaborative design scheme, and significantly improves computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 An example structural diagram of a multi-modal, scalable, high-performance homomorphic encryption system provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of a high-speed SRAM memory block structure design provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of a data storage and transmission architecture based on a high-speed SRAM memory block provided in an embodiment of the present application;

[0042] Figure 4 An example diagram of memory distribution for software and hardware collaboration provided in an embodiment of the present application;

[0043] Figure 5 A flow chart of the pipeline scheduling for performing NTT calculations in the modulo calculation unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0045] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0046] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0048] Before describing the embodiments of the present application in detail, some related technologies that may be involved in the embodiments of the present application are first described as follows:

[0049] With the development of homomorphic encryption technology, the processing capacity of ciphertext data has been significantly improved. However, the existing homomorphic encryption system still faces many challenges in hardware architecture implementation, especially in the application scenarios of computing clusters of different sizes and homomorphic encryption of different modes. High-performance memory scheduling strategy is a key factor affecting the overall performance of the system.

[0050] Traditional ciphertext data reading and writing strategies, due to the lack of support for multimodal homomorphic encryption and optimization of ciphertext data of different sizes, cannot fully utilize memory bandwidth, limiting the reading and writing efficiency of ciphertext data in the system. This limitation further affects the computational efficiency of ciphertext and becomes a bottleneck for system performance optimization.

[0051] In order to improve system performance, how to effectively schedule and parallelize ciphertext data in memory has become an urgent problem to be solved. By optimizing the memory scheduling strategy and making the hardware computing module scalable, the efficiency of data reading and writing can be improved and the overall computing power of the system can be enhanced. This not only helps to improve the performance of the encryption system, but also enables the deployment of hardware platforms according to application scenarios of different scales.

[0052] In order to solve the problem of inefficient scheduling of homomorphic encryption ciphertext in hardware architecture design in the prior art, this application adopts a software-hardware collaborative design methodology to comprehensively improve system performance by integrating scheduling optimization at the software level with efficient computing at the hardware level.

[0053] The upper-layer software implements the multimodal homomorphic encryption algorithm library, and calls the underlying hardware resources through the hardware call interface function in the algorithm library to accelerate the upper-layer application of multimodal homomorphic encryption; the upper-layer software optimizes the scheduling strategy of ciphertext data through the scheduling algorithm program, and adopts the memory scheduling algorithm based on RNS (Residue Number System) to calculate by decomposing large integers into small moduli, and allocate ciphertext storage space and computing tasks according to the computing resources available in the hardware resources, thereby improving the parallelism and efficiency of data processing. Improve memory bandwidth utilization and data processing efficiency.

[0054] The underlying hardware integrates NTT (Number Theoretic Transform) computing units to efficiently process large integer polynomial multiplication operations required for homomorphic encryption, improving computing speed and accuracy; the underlying hardware introduces HBM (High Bandwidth Memory) memory and high-speed on-chip SRAM (Static Random-Access Memory) memory, using the multi-channel high bandwidth of HBM and the high read-write characteristics of SRAM to provide the system with high-throughput data transmission capabilities, combined with optimized scheduling algorithms, to fully utilize memory bandwidth and achieve efficient parallel processing of ciphertext data. The underlying memory scheduling circuit adopts a dynamic scheduling strategy to adjust the memory read and write order in real time according to the scale of ciphertext data to ensure the continuity and efficiency of data transmission; the underlying hardware introduces a high-performance double-precision floating-point processing module to provide hardware support for the underlying operators for multi-modal homomorphic encryption solutions. The computing module is an extensible architecture that can allocate different numbers of computing units according to application scenarios of different scales, and is fully compatible with homomorphic encryption applications in different scenarios.

[0055] Through the above technical means and measures, this application significantly improves the scheduling efficiency and computing performance of the homomorphic encryption hardware architecture, and solves the performance bottleneck problem caused by inefficient scheduling in the traditional architecture.

[0056] The embodiment of the present application provides a multi-modal scalable high-performance homomorphic encryption system, the system comprising an upper-layer server software and driver architecture and a multi-modal homomorphic encryption hardware architecture implemented based on FPGA;

[0057] Wherein, the upper server software and driver architecture are communicatively connected with the multi-modal homomorphic encryption hardware architecture implemented based on FPGA;

[0058] The upper server software and driver architecture includes a multimodal homomorphic encryption algorithm software library, a software memory scheduler, a modulus calculation module software driver, and a floating-point calculation module software driver;

[0059] The multi-modal homomorphic encryption hardware architecture based on FPGA includes a communication data controller, multiple modulus calculation modules, a floating-point calculation module, a data read-write bus and a high-bandwidth memory; each of the modulus calculation modules includes a fast number theory transformation calculation unit;

[0060] Among them, the communication data controller and the upper-level server software are communicatively connected to the drive architecture, and the communication data controller is also communicatively connected to each of the modulo calculation modules and the floating-point calculation modules respectively; the data read and write bus is communicatively connected to the communication data controller, each of the modulo calculation modules, the floating-point calculation module, and the high-bandwidth memory respectively.

[0061] Furthermore, the multimodal homomorphic encryption algorithm software library is used to manage and schedule the multimodal homomorphic encryption algorithm;

[0062] The software memory scheduler is used to manage and schedule memory resources;

[0063] The modulus calculation module software driver is used to control and drive each of the modulus calculation modules;

[0064] The floating-point calculation module software driver is used to control and drive the floating-point calculation module.

[0065] Furthermore, the communication data controller is used to manage the interactive data between the upper-layer server software and the driver architecture and the multi-modal homomorphic encryption hardware architecture implemented based on FPGA;

[0066] Each of the modulo calculation modules is used for modulo calculation;

[0067] The floating point calculation module is used for floating point calculation;

[0068] The data read-write bus is used to transmit data;

[0069] The high bandwidth memory is used to store ciphertext data and intermediate calculation results.

[0070] Furthermore, the upper server software and driver architecture are communicatively connected with the multi-modal homomorphic encryption hardware architecture implemented based on FPGA via a PCIe data communication interface;

[0071] The communication data controller adopts a PCIe data controller;

[0072] The PCIe data controller is respectively connected to the modulo calculation module and the floating-point calculation module through the calculation module control signaling data path.

[0073] Further, each of the modulo calculation module and the floating-point calculation module includes a memory array composed of a plurality of SRAM memory blocks, a data multiplexer, a memory block read-write address generator, a configurable parameter register and a memory data read-write path;

[0074] Wherein, each of the SRAM memory blocks is used to store data;

[0075] The data multiplexer includes a data write path and a data read path, and the data multiplexer is used to read and write distribution data;

[0076] The memory block read / write address generator is used to generate the read / write address of each of the SRAM memory blocks;

[0077] The configurable parameter register is used to store configuration parameters, which are configured by the upper server software and the driver architecture through the computing module control signaling data path;

[0078] The memory data read / write path is connected to the high bandwidth memory, and the memory data read / write path is used to read and write data.

[0079] As a more specific implementation, each of the SRAM memory blocks is used to store intermediate data;

[0080] Wherein, each of the SRAM memory blocks includes a plurality of SRAM memory cells; each of the SRAM memory blocks includes a read / write interface with a width of 1024 bits;

[0081] The storage capacity of each of the SRAM memory cells is 4096 words of data, each word of data is 64 bits; the storage capacity of a single SRAM memory block is 65536 words of data.

[0082] As a more specific implementation, the memory array is provided with a data read and write channel A and a data read and write channel B;

[0083] The data read and write channel A is connected to each of the modulo calculation modules, and the data read and write channel B is connected to the floating-point calculation module.

[0084] As a more specific implementation, the fast number theory transformation calculation unit is used to execute a homomorphic encryption algorithm through a plurality of parallel operating memory arrays.

[0085] Furthermore, the upper server software and driver architecture are used to merge several physical blocks in the high bandwidth memory into a virtual block, thereby obtaining a plurality of virtual blocks; each virtual block corresponds to one modulus calculation module;

[0086] Each of the virtual blocks is divided into a plurality of virtual sub-blocks, and each of the virtual sub-blocks is used to store polynomial coefficients of different RNS bases.

[0087] Furthermore, the multimodal homomorphic encryption algorithm software library includes CKKS homomorphic encryption algorithm, BFV homomorphic encryption algorithm and BGV homomorphic encryption algorithm.

[0088] Next, the solution of the embodiment of the present application will be introduced and explained in detail with reference to specific application examples.

[0089] See also Figure 1 , Figure 1 This is a schematic diagram of a multimodal homomorphic encryption computing system based on FPGA (Field Programmable Gate Array) provided in an embodiment of the present application, which includes an upper-layer server software and driver architecture and a multimodal homomorphic encryption hardware architecture based on FPGA. The upper-layer server software and driver architecture are connected to the multimodal homomorphic encryption hardware architecture based on FPGA through a PCIe (Peripheral Component Interconnect Express) data communication interface.

[0090] The upper-level server software and driver architecture includes a multimodal homomorphic encryption algorithm software library, a software memory scheduler, and a modulus and floating-point calculation module software driver.

[0091] Specifically, the multimodal homomorphic encryption algorithm software library is used to manage and schedule the multimodal homomorphic encryption algorithm. The software memory scheduler is responsible for managing and scheduling system memory resources. The modulus and floating-point calculation module software driver is used to control and drive the corresponding hardware modules. The PCIe data communication interface is used for high-speed data transmission between the upper-level server and the FPGA hardware.

[0092] Specifically, this system supports a variety of homomorphic encryption algorithms, including CKKS (Cheon-Kim-Kim-Song), BFV (Brakerski / Fan-Vercauteren) and BGV (Brakerski-Gentry-Vaikuntanathan) mainstream homomorphic encryption algorithms. The CKKS algorithm is mainly used for approximate number calculations and supports floating-point operations; the BFV algorithm is suitable for integer operations, and can keep the scale of the ciphertext unchanged during the ciphertext calculation process, with high computational efficiency; the BGV algorithm supports circuit evaluation of arbitrary depth and is suitable for complex encryption calculation tasks. By managing these different algorithms, the multimodal homomorphic encryption algorithm software library enables the system to select the most appropriate encryption scheme according to specific application requirements, thereby achieving efficient and flexible homomorphic encryption calculations.

[0093] The multimodal homomorphic encryption hardware architecture implemented based on FPGA includes a PCIe data controller, a computing module control signaling data path, a modulo computing module, a high-performance double-precision floating-point computing module, a data read and write bus, and a high-bandwidth HBM memory.

[0094] Among them, the PCIe data controller is responsible for managing the data transmission of the PCIe interface. The computing module control signaling data path is used to coordinate and schedule the work between various computing modules. The modulo computing module contains multiple modulo computing units, including NTT computing units. The high-performance double-precision floating-point computing module is used to perform high-precision floating-point operations. The data read and write bus connects various computing modules and memory to achieve efficient data transmission. The high-bandwidth HBM memory is used to store ciphertext data and intermediate calculation results.

[0095] See also Figure 2 , Figure 2 The schematic diagram of a high-speed SRAM memory block structure design provided by the embodiment of the present application is mainly used for intermediate data storage in the modulo / floating-point calculation module.

[0096] Specifically, the high-speed SRAM memory block is composed of multiple SRAM memory cells. Each SRAM memory cell can store 4096 words of data, each word of data is 64 bits. Multiple SRAM memory cells are combined into a memory block, and a single memory block can store a total of 65536 words of data. This design can effectively improve data storage density and access speed, and is compatible with ciphertext data of different sizes, providing good algorithm compatibility for upper-level applications.

[0097] Each memory block provides a total of 1024 bits of read and write interface width. This wide interface design can significantly improve data transmission efficiency and meet the needs of large-scale data processing in homomorphic encryption computing.

[0098] See also Figure 3 , Figure 3 The present invention provides a schematic diagram of a data storage and transmission architecture based on a high-speed SRAM memory block. The architecture is mainly used to optimize the data flow and storage management in the modulo / floating-point calculation module.

[0099] Specifically, the architecture based on SRAM memory implementation includes the following main components:

[0100] SRAM memory block: It is composed of multiple high-speed on-chip SRAM memories, and each high-speed memory array is composed of 4 high-speed on-chip SRAM memory blocks. This design provides large-capacity and high-speed on-chip data storage capabilities.

[0101] Data multiplexer: responsible for data read and write distribution, including data write path and data read path. Through the data multiplexer, the system can achieve efficient data read, write and transmission.

[0102] Memory block read and write address generator: used to generate the read and write addresses of the memory block to ensure that data can be stored and accessed correctly.

[0103] Configurable parameter registers: store system configuration parameters, which can be configured by the upper-layer server through the computing module control signaling data path. This design increases the flexibility and configurability of the system.

[0104] HBM memory data read and write path: connected to HBM memory for high-speed reading and writing of large-capacity data.

[0105] As the core design of this application, the memory array is provided with data read and write channels A and B, which are respectively connected to the modulus calculation module (including the NTT calculation unit) and the floating point calculation module. This design enables the system to support both integer operations and floating point operations, thereby meeting the requirements of different homomorphic encryption algorithms.

[0106] Specifically, the data stored in the SRAM memory array of the modulo calculation module can be quickly transferred to the modulo calculation circuit through the data read and write channel A or B to perform operations such as modular multiplication and modular addition, and then the data completed by the calculation is written back to the SRAM memory array through the data write-back channel A or B; the data stored in the SRAM memory array of the floating-point calculation module can be transferred to the floating-point calculation circuit through the data read and write channel A or B to perform operations such as addition and multiplication, and then the data completed by the calculation is written back to the SRAM memory array through the data write-back channel A or B. This direct data path design significantly reduces the delay of data transmission and improves the efficiency of integer operations. This bidirectional data flow design ensures that the calculation results can be stored in time to prepare for subsequent calculations or data transmission.

[0107] The architecture achieves efficient data storage and transmission through the design of multi-level storage and parallel data paths. The SRAM memory block provides fast on-chip data access, while the HBM memory provides large-capacity data storage. This design fully considers the needs of large-scale data processing in homomorphic encryption computing and can effectively improve the overall performance of the system.

[0108] As an improvement to the above solution, the number and capacity of SRAM memory blocks and the configuration of HBM memory can be adjusted according to specific computing requirements to optimize system performance and resource utilization.

[0109] Specifically, this data storage and transmission architecture can support the efficient execution of multiple homomorphic encryption algorithms such as CKKS, BFV and BGV. For example, when performing ciphertext calculations based on large integer polynomials, SRAM memory blocks can be used to store intermediate calculation results, and data can be quickly accessed and updated through data multiplexers, thereby accelerating the calculation process of ciphertext polynomials. HBM memory can be used to store large-scale ciphertext data, and the required data can be quickly called through a high-bandwidth interface.

[0110] See also Figure 4 , Figure 4 An example of memory distribution of software and hardware collaboration in the embodiment of the present application is shown. This design is mainly used to optimize the modulo operation in the homomorphic encryption algorithm, especially for efficient parallel processing of polynomials represented by the RNS residue number system.

[0111] Specifically, the memory distribution solution includes the following main components and features:

[0112] Modulo calculation module: Figure 4 8 modulo calculation modules (modulo calculation module 1 to modulo calculation module 8) are shown in FIG. These modules can perform modulo calculations in parallel, which significantly improves the calculation efficiency.

[0113] HBM memory: The physical memory space of HBM memory is divided into multiple virtual blocks, each of which corresponds to a modulo computing module. The capacity of each physical block is 256MB, and the physical blocks are secondary allocated in a software-defined manner. This division method enables each modulo computing module to access its corresponding memory space independently and in parallel, avoiding read and write blocking caused by multiple computing modules accessing a similar memory space at the same time.

[0114] Memory distribution strategy: The upper-layer software merges multiple physical blocks into one virtual block. This design increases the flexibility of memory management. Each virtual block is further divided to store polynomial coefficients of different RNS bases.

[0115] Polynomial storage method: The lower part of the figure shows how polynomials represented by the remainder number system are distributed in the HBM memory. Each virtual block stores a set of related polynomial coefficients. This distribution method takes into account the characteristics of the RNS modulus, allowing the modulus calculation unit to efficiently access the required data in parallel.

[0116] Parameter Description:

[0117] k: indicates the number of modules for modulo calculation;

[0118] n: represents the number of moduli of the remainder number system;

[0119] m = n / k: represents the number of moduli processed by each modulo calculation module;

[0120] The main advantages of this design are: multiple modulo calculation modules can perform operations simultaneously, greatly improving computing efficiency; each modulo calculation module has a dedicated HBM memory area, reducing memory access conflicts and improving data reading speed; the upper-level software can dynamically adjust memory allocation according to specific needs to adapt to different homomorphic encryption algorithms and parameter settings; the memory distribution method fully considers the characteristics of RNS, so that related polynomial coefficients can be quickly accessed and processed.

[0121] In specific implementation, for example, when executing a multimodal homomorphic encryption algorithm, the system can allocate the corresponding polynomial coefficients to different HBM virtual blocks according to the selected RNS basis. Each modular calculation module can simultaneously process the data in its corresponding virtual block and perform operations such as modular multiplication and modular addition. This parallel processing method can significantly improve the efficiency of large integer operations in homomorphic encryption.

[0122] See also Figure 5 , Figure 5 The pipeline scheduling process of performing NTT calculation in the modulus calculation unit in the embodiment of the present application is shown. This design is mainly used to optimize the NTT operation in the homomorphic encryption algorithm and improve the calculation efficiency through pipeline technology.

[0123] Specifically, the NTT calculation process utilizes multiple SRAM arrays working in parallel (such as SRAM arrays 1, 2, 3, 4, etc. in the figure) to achieve efficient pipeline calculation. The entire process is divided into multiple consecutive stages, and each stage is performed simultaneously in different SRAM arrays. For example, SRAM arrays 1 and 2 are responsible for reading the polynomials under the rotation factors ω0 and q0, respectively, and then performing NTT calculations internally. At the same time, SRAM arrays 3 and 4 have begun to prepare for the next round of NTT calculations, reading the polynomials under the rotation factors ω1 and q1, respectively. This design allows data reading, NTT calculations, and result writebacks to be performed in parallel, greatly improving the calculation efficiency.

[0124] The main advantage of this pipeline design is that it achieves efficient parallel processing and memory access optimization. The simultaneous operation of multiple SRAM arrays greatly improves the data processing speed, and dividing the NTT calculation process into multiple stages enables continuous data processing and reduces idle time. In particular, while performing NTT calculations, the system can perform data read and write operations in parallel, effectively saving overall calculation time. In addition, this design has good flexibility and can adapt to NTT calculation needs of different scales by adjusting the number and allocation of SRAM arrays.

[0125] In practical applications, this pipelined NTT calculation method can effectively support various homomorphic encryption algorithms. For example, when executing polynomial multiplication in a multimodal homomorphic encryption algorithm, while one set of data is undergoing NTT transformation, the next set of data has already been prepared and loaded, significantly reducing the total execution time of the algorithm.

[0126] Through this pipeline-scheduled NTT computing solution, the system can fully utilize the parallel computing capabilities of FPGA and the high-speed access characteristics of SRAM to provide powerful hardware acceleration support for homomorphic encryption algorithms, thereby achieving efficient and large-scale encryption computing. This optimization is of great significance to improving the overall performance of the homomorphic encryption system, enabling the system to better meet the performance requirements of practical applications.

[0127] based on Figures 1 to 5 Based on the information displayed, the overall workflow of this system can be described as follows:

[0128] The upper server sends the encrypted data and computing tasks to the FPGA hardware through the PCIe interface. After receiving the data, the PCIe data controller distributes the data to the corresponding computing module according to the task type. The computing module control signaling data path is responsible for coordinating the work of each computing module to ensure the coordination of the entire system operation.

[0129] During data processing, the system mainly relies on two core computing modules: the modulo computing module and the high-performance double-precision floating-point computing module. The modulo computing module plays a key role in homomorphic encryption algorithms such as CKKS, BGV, and BFV, and is mainly used to perform modular operations on polynomials, such as modular multiplication and modular addition. These operations are the basic computing steps in homomorphic encryption algorithms.

[0130] The main function of the high-performance double-precision floating-point computing module is to complete the RNS polynomial basis transformation operation, also known as base conversion. This operation plays a vital role in implementing ciphertext multiplication calculations for multimodal homomorphic encryption. Basis conversion allows ciphertext data to be efficiently converted between different RNS bases, which is necessary to manage the modulus growth of the ciphertext and maintain calculation accuracy.

[0131] By combining these two computing modules, the system can efficiently perform the complex calculations required by various homomorphic encryption algorithms. The modulus computing module handles basic polynomial operations, while the high-performance double-precision floating-point computing module handles the basis conversion operations that require high precision. The two work together to enable the system to support multiple homomorphic encryption schemes and flexibly switch between different encryption modes. This design not only improves the system's computing efficiency, but also enhances its flexibility and adaptability in handling various homomorphic encryption tasks.

[0132] The fast transmission of data between modules is achieved through an efficient data read and write bus. At the same time, the system adopts an innovative memory management strategy, using HBM memory to store a large number of intermediate results and final results. Figure 4 As shown in the figure, HBM is divided into multiple virtual blocks by the upper-level memory scheduler, and each block corresponds to a modulo calculation module. This design greatly improves the data access efficiency.

[0133] Specifically, the module calculation module uses the following Figure 5 The pipelined NTT calculation scheme shown in Figure 1. Multiple SRAM arrays work in parallel, achieving efficient parallel processing of data reading, NTT calculation, and result writing back, significantly improving system performance.

[0134] In addition, the system is designed with flexibility and scalability in mind. The modulo calculation module and high-performance double-precision floating-point calculation module can contain different numbers of modulo calculation units according to needs to adapt to computing tasks of different scales.

[0135] After the calculation is completed, the result is returned to the upper-level server through the PCIe interface. Throughout the process, the system fully utilizes the parallel computing capabilities of the FPGA, combined with optimized memory access strategies and pipeline design, to significantly improve the efficiency of homomorphic encryption operations. This hardware acceleration solution makes multimodal homomorphic encryption more feasible in practical applications of different computing scales, maintains good flexibility and scalability, and can perform functional updates and performance optimizations as needed.

[0136] In summary, the embodiments of the present application may include the following beneficial effects:

[0137] The embodiment of the present application achieves more efficient performance by combining software and hardware optimization design. The scheduling strategy of ciphertext data is optimized at the software level to ensure that the memory bandwidth is fully utilized, thereby improving the overall efficiency of data processing.

[0138] The embodiment of the present application integrates a fast number theory transformation circuit to make large integer polynomial operations more efficient. By accelerating the homomorphic encryption calculation process, the calculation speed and accuracy are improved, and the polynomial multiplication processing time is significantly shortened.

[0139] The embodiment of the present application adopts a fully pipelined computing circuit design to significantly improve the throughput of ciphertext computing. Through pipeline technology, the system can quickly process multiple data streams, greatly improving computing efficiency and processing speed.

[0140] The embodiment of the present application performs memory scheduling based on the principle of the remainder number system, decomposes large integers into small moduli for calculation, and uses the scheduling algorithm to fully call hardware resources to improve parallel processing capabilities. This method effectively enhances the processing efficiency of the system and improves the throughput of ciphertext calculations.

[0141] The embodiments of the present application introduce high-bandwidth memory, which provides high-throughput data transmission capabilities through its multi-channel characteristics, solves the problem of insufficient memory bandwidth, and supports efficient scheduling and processing of large-scale encrypted data.

[0142] The embodiment of the present application uses a dynamic scheduling strategy to adjust the memory read and write order in real time according to the size of the ciphertext data, thereby ensuring the continuity and efficiency of the data flow, optimizing the utilization of system resources, and improving the overall performance.

[0143] The embodiment of the present application introduces a high-performance double-precision floating-point processing module to provide hardware support for the underlying operators of the multimodal homomorphic encryption scheme, so that the system can simultaneously support different types of homomorphic encryption schemes, thereby improving the compatibility of the system.

[0144] The embodiment of the present application designs the computing module in a scalable manner, so that the proposed architecture can support homomorphic encryption application scenarios under different computing scales, thereby optimizing the cost of deploying the homomorphic encryption hardware platform.

[0145] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0146] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0147] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0148] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0149] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but the scope of the rights of the present application is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present application should be within the scope of the rights of the present application.

Claims

1. A multi-modal scalable high-performance homomorphic encryption system, characterized in that: The system includes an upper-layer server software and driver architecture and a multi-modal homomorphic encryption hardware architecture based on FPGA implementation; Wherein, the upper server software and driver architecture are communicatively connected with the multi-modal homomorphic encryption hardware architecture implemented based on FPGA; The upper server software and driver architecture includes a multimodal homomorphic encryption algorithm software library, a software memory scheduler, a modulus calculation module software driver, and a floating-point calculation module software driver; The multi-modal homomorphic encryption hardware architecture based on FPGA includes a communication data controller, multiple modulus calculation modules, a floating-point calculation module, a data read-write bus and a high-bandwidth memory; each of the modulus calculation modules includes a fast number theory transformation calculation unit; Among them, the communication data controller and the upper-level server software are communicatively connected to the drive architecture, and the communication data controller is also communicatively connected to each of the modulo calculation modules and the floating-point calculation modules respectively; the data read and write bus is communicatively connected to the communication data controller, each of the modulo calculation modules, the floating-point calculation module, and the high-bandwidth memory respectively.

2. A multi-modal scalable high-performance homomorphic encryption system according to claim 1, characterized in that: The multimodal homomorphic encryption algorithm software library is used to manage and schedule the multimodal homomorphic encryption algorithm; The software memory scheduler is used to manage and schedule memory resources; The modulus calculation module software driver is used to control and drive each of the modulus calculation modules; The floating-point calculation module software driver is used to control and drive the floating-point calculation module.

3. A multi-modal scalable high-performance homomorphic encryption system according to claim 1, characterized in that: The communication data controller is used to manage the interactive data between the upper-layer server software and the driver architecture and the multi-modal homomorphic encryption hardware architecture implemented based on FPGA; Each of the modulo calculation modules is used for modulo calculation; The floating point calculation module is used for floating point calculation; The data read-write bus is used to transmit data; The high bandwidth memory is used to store ciphertext data and intermediate calculation results.

4. A multi-modal scalable high-performance homomorphic encryption system according to claim 1, characterized in that: The upper server software and driver architecture are connected to the multi-modal homomorphic encryption hardware architecture based on FPGA through a PCIe data communication interface; The communication data controller adopts a PCIe data controller; The PCIe data controller is respectively connected to the modulo calculation module and the floating-point calculation module through the calculation module control signaling data path.

5. A multi-modal scalable high-performance homomorphic encryption system according to claim 1, characterized in that: Each of the modulo calculation module and the floating-point calculation module includes a memory array composed of a plurality of SRAM memory blocks, a data multiplexer, a memory block read-write address generator, a configurable parameter register and a memory data read-write path; Wherein, each of the SRAM memory blocks is used to store data; The data multiplexer includes a data write path and a data read path, and the data multiplexer is used to read and write distribution data; The memory block read / write address generator is used to generate the read / write address of each of the SRAM memory blocks; The configurable parameter register is used to store configuration parameters, which are configured by the upper server software and the driver architecture through the computing module control signaling data path; The memory data read / write path is connected to the high bandwidth memory, and the memory data read / write path is used to read and write data.

6. A multi-modal scalable high-performance homomorphic encryption system according to claim 5, characterized in that: Each of the SRAM memory blocks is used to store intermediate data; Wherein, each of the SRAM memory blocks includes a plurality of SRAM memory cells; each of the SRAM memory blocks includes a read / write interface with a width of 1024 bits; The storage capacity of each of the SRAM memory cells is 4096 words of data, each word of data is 64 bits; the storage capacity of a single SRAM memory block is 65536 words of data.

7. A multi-modal scalable high-performance homomorphic encryption system according to claim 5, characterized in that: The memory array is provided with a data read-write channel A and a data read-write channel B; The data read and write channel A is connected to each of the modulo calculation modules, and the data read and write channel B is connected to the floating-point calculation module.

8. A multi-modal scalable high-performance homomorphic encryption system according to claim 5, characterized in that: The fast number theory transformation calculation unit is used to execute a homomorphic encryption algorithm through a plurality of parallel operation memory arrays.

9. A multi-modal scalable high-performance homomorphic encryption system according to claim 1, characterized in that: The upper server software and driver architecture are used to merge several physical blocks in the high bandwidth memory into a virtual block, thereby obtaining a plurality of virtual blocks; each virtual block corresponds to one modulus calculation module; Each of the virtual blocks is divided into a plurality of virtual sub-blocks, and each of the virtual sub-blocks is used to store polynomial coefficients of different RNS bases.

10. A multi-modal scalable high-performance homomorphic encryption system according to any one of claims 1 to 9, characterized in that: The multimodal homomorphic encryption algorithm software library includes the CKKS homomorphic encryption algorithm, the BFV homomorphic encryption algorithm and the BGV homomorphic encryption algorithm.

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