A monoclinic analog-to-digital converter

Abstract

The application discloses a single-ramp analog-to-digital converter, and belongs to the field of image sensors. After a reset voltage of a pixel signal to be processed is quantized for the first time by a counting module, when the pixel signal to be processed is not greater than a preset voltage threshold (i.e. the pixel signal to be processed is generated under weak light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on a first counting parameter; when the pixel signal to be processed is greater than the preset voltage threshold (i.e. the pixel signal to be processed is generated under strong light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on a second counting parameter (i.e. the counting frequency is halved and the counting bit is reduced by one). That is, when the pixel signal to be processed corresponding to strong light is processed, the power consumption of the counting module is reduced by sacrificing the analog-to-digital conversion precision, so that the power consumption of the single-ramp analog-to-digital converter is reduced, and the power consumption of the CMOS image sensor is ultimately reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of image sensors, and particularly relates to a single-ramp analog-to-digital converter. BACKGROUND

[0002] As an important component of a CMOS (Complementary Metal Oxide Semiconductor) image sensor, the power consumption of an analog-to-digital converter also affects the overall power consumption of the CMOS image sensor, however, there is a lack of a mature single-ramp analog-to-digital converter in the related art, resulting in high power consumption of the related analog-to-digital converter, thereby causing the power consumption of the CMOS image sensor to be high.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. SUMMARY

[0004] The purpose of the present application is to provide a single-ramp analog-to-digital converter, after the reset voltage of a pixel signal to be processed is quantized for the first time by a counting module, when the pixel signal to be processed is not greater than a preset voltage threshold (i.e. the pixel signal to be processed is generated under weak light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on the original first counting parameter, when the pixel signal to be processed is greater than the preset voltage threshold (i.e. the pixel signal to be processed is generated under strong light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on the second counting parameter (counting frequency is halved and counting bit is reduced by one), that is, by sacrificing the analog-to-digital conversion accuracy when processing the pixel signal to be processed corresponding to strong light, the power consumption of the counting module is reduced, thereby reducing the power consumption of the single-ramp analog-to-digital converter, which is conducive to ultimately reducing the power consumption of the CMOS image sensor.

[0005] To solve the above technical problems, the present application provides a single-ramp analog-to-digital converter, comprising:

[0006] a comparator, configured to reset the first input end and the second input end of the comparator to a reset voltage when the comparator is reset, wherein the first input end is configured to input a pixel signal to be processed, and the second input end is configured to input a ramp signal;

[0007] The counting module is configured to quantize the reset voltage of the first input terminal of the comparator for the first time when the comparator is reset; and is further configured to, after the first quantization is completed, if the voltage value of the pixel signal to be processed is not greater than a preset voltage threshold, quantize the pixel signal to be processed for the second time based on a first counting parameter, wherein the voltage value of the pixel signal to be processed is a voltage difference of the pixel signal to be processed relative to the reset voltage, and the first counting parameter is that a counting frequency is a first frequency and a counting weight is 1; if the voltage value of the pixel signal to be processed is greater than the preset voltage threshold, quantize the pixel signal to be processed for the second time based on a second counting parameter, so that a difference between a result of the second quantization and a result of the first quantization is taken as a pixel digital signal corresponding to the pixel signal to be processed, wherein the second counting parameter is that a counting frequency is a second frequency, the first frequency is twice the second frequency, and a counting weight is 2.

[0008] In another aspect, the counting module comprises a clock control device and N cascaded sub-counters.

[0009] In the N cascaded sub-counters, an output terminal of a previous sub-counter is connected to a clock terminal of a next sub-counter, and the clock control device is connected to a clock terminal of the first sub-counter, an output terminal of the first sub-counter and a clock terminal of the second sub-counter, respectively.

[0010] The clock control device is configured to deliver a first counting clock signal to the clock terminal of the first sub-counter when the comparator outputs the first digital signal, and deliver a second counting clock signal to the clock terminal of the second sub-counter when the comparator outputs the second digital signal, wherein the frequency of the first counting clock signal is a first frequency, the frequency of the second counting clock signal is a second frequency, and the first frequency is twice the second frequency.

[0011] Any of the sub-counters is configured to count under the drive of a counting clock signal, wherein the counting clock signal comprises the first counting clock signal and the second counting clock signal.

[0012] In another aspect, the clock control device comprises a clock control module and a switch module.

[0013] The switch module is arranged between the output terminal of the first sub-counter and the clock terminal of the second sub-counter.

[0014] The clock control module is configured to, when the comparator outputs the first digital signal, realize electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module, and deliver the first counting clock signal to the clock end of the first-stage sub-counter; and when the comparator outputs the second digital signal, disconnect the electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module, and deliver the second counting clock signal to the clock end of the second-stage sub-counter.

[0015] In another aspect, the switch module comprises a first switch and a second switch.

[0016] The first switch is arranged between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter, and the clock control module is connected with the first end of the first switch, the control end of the first switch and the control end of the second switch, and the second end of the second switch is connected with the clock end of the second-stage sub-counter.

[0017] The clock control module is specifically configured to, when the comparator outputs the first digital signal, control the first switch to be turned on and the second switch to be turned off, and deliver the first counting clock signal to the clock end of the first-stage sub-counter; and when the comparator outputs the second digital signal, control the first switch to be turned off and the second switch to be turned on, and deliver the second counting clock signal to the input end of the second switch.

[0018] In another aspect, the clock control module comprises a signal generation module and a clock selection module.

[0019] The clock selection module is connected with the clock end of the first-stage sub-counter and the first end of the second switch respectively, and the output end of the signal generation module is connected with the control end of the first switch and the control end of the second switch respectively.

[0020] The signal generation module is configured to output a first switch control signal or a second switch control signal under control, wherein the first switch control signal is used to control the first switch to be turned on, and the second switch control signal is used to control the second switch to be turned on.

[0021] The clock selection module is configured to output the first counting clock signal under a first constraint condition, and output the second counting clock signal under a second constraint condition, wherein the first constraint condition comprises that the comparator outputs the first digital signal and the signal generation module outputs the first switch control signal, and the second constraint condition comprises that the comparator outputs the second digital signal and the signal generation module outputs the second switch control signal.

[0022] In another aspect, the first constraint condition further comprises that a counting enable signal is effective, and the second constraint condition further comprises that the counting enable signal is effective.

[0023] In another aspect, the clock selection module comprises a first AND gate and a second AND gate;

[0024] The input terminals of the first AND gate are connected to a first counting clock signal, a counting enable signal, an output terminal of the comparator, and a first switch control signal output terminal of the signal generation module, respectively; the output terminal of the first AND gate is connected to a clock terminal of the first stage sub-counter; the input terminals of the second AND gate are connected to a second counting clock signal, a counting enable signal, an output terminal of the comparator, and a second switch control signal output terminal of the signal generation module, respectively; and the output terminal of the second AND gate is connected to a first terminal of the second switch.

[0025] In another aspect, the sub-counter comprises an OR gate, a first NAND gate, a second NAND gate, a first inverter, a second inverter, a CMOS switch, a first signal inversion device, a second signal inversion device, and a third signal inversion device.

[0026] The input terminals of the OR gate are connected to a latch signal and a clock signal, respectively; the output terminal of the OR gate is connected to a first input terminal of the first NAND gate; the second input terminal of the first NAND gate is connected to a switching signal; the output terminal of the first NAND gate is connected to an enable terminal of the CMOS switch, an input terminal of the first inverter, and an enable terminal of the second signal inversion device, respectively; the output terminal of the first inverter is connected to an enable terminal of the first signal inversion device and an enable terminal of the third signal inversion device, respectively; the input terminal of the first signal inversion device, the output terminal of the second inverter, and the input terminal of the third signal inversion device together serve as an output terminal of the sub-counter; the output terminal of the first signal inversion device is connected to a second input terminal of the second NAND gate and an output terminal of the second signal inversion device, respectively; the first input terminal of the second NAND gate serves as a reset port of the sub-counter; the output terminal of the second NAND gate is connected to an input terminal of the second signal inversion device and a first terminal of the CMOS switch, respectively; and the second terminal of the CMOS switch is connected to an input terminal of the second inverter and an output terminal of the third signal inversion device, respectively.

[0027] The switching signal is used to cooperate with the latch signal to invert the count value of the sub-counter.

[0028] In another aspect, the sub-counter is further used to:

[0029] After completing the first quantization, the count value of the sub-counter is inverted.

[0030] The count value of the counting module after completing the second quantization is used as a pixel digital signal corresponding to the pixel signal to be processed.

[0031] Beneficial effects: the application provides a single slope analog-to-digital converter, considering that (1) the power of the analog-to-digital converter can be reduced by reducing the counting frequency and counting bit of the counting module, (2) the quantization noise introduced by a small decrease in the counting bit is negligible compared to the photon shot noise of the pixel signal to be processed generated under strong light, therefore, in the application, after the reset voltage of the pixel signal to be processed is quantized for the first time by the counting module, when the pixel signal to be processed is not greater than the preset voltage threshold (i.e. the pixel signal to be processed is generated under weak light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on the original first counting parameter, when the pixel signal to be processed is greater than the preset voltage threshold (i.e. the pixel signal to be processed is generated under strong light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on the second counting parameter (the counting frequency is halved and the counting bit is reduced by one), that is, by sacrificing the analog-to-digital conversion accuracy when processing the pixel signal to be processed corresponding to strong light, the power consumption of the counting module is reduced, thereby reducing the power consumption of the single slope analog-to-digital converter, which is beneficial to ultimately reducing the power consumption of the CMOS image sensor. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the application, the related art and the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0033] Figure 1 A structural schematic diagram of a single slope analog-to-digital converter provided by the application is shown in the figure.

[0034] Figure 2 A structural schematic diagram of a signal generation module provided by the application is shown in the figure.

[0035] Figure 3 A structural schematic diagram of a clock selection module provided by the application is shown in the figure.

[0036] Figure 4 A structural schematic diagram of an N-stage cascaded sub-counter provided by the application is shown in the figure.

[0037] Figure 5 A structural schematic diagram of a sub-counter provided by the application is shown in the figure.

[0038] Figure 6 An analog-to-digital conversion timing diagram of a weak light pixel signal provided by the application is shown in the figure.

[0039] Figure 7 An analog-to-digital conversion timing diagram of a strong light pixel signal provided by the application is shown in the figure. DETAILED DESCRIPTION

[0040] The core of the present application is to provide a single-ramp analog-to-digital converter, after a reset voltage of a pixel signal to be processed is quantized for the first time by a counting module, when the pixel signal to be processed is not greater than a preset voltage threshold (i.e. the pixel signal to be processed is generated under weak light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on a first counting parameter, and when the pixel signal to be processed is greater than the preset voltage threshold (i.e. the pixel signal to be processed is generated under strong light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on a second counting parameter (i.e. the counting frequency is halved and the counting bit is reduced by one), that is, by sacrificing the analog-to-digital conversion accuracy when processing the pixel signal to be processed corresponding to strong light, the power consumption of the counting module is reduced, thereby reducing the power consumption of the single-ramp analog-to-digital converter, which is conducive to ultimately reducing the power consumption of the CMOS image sensor.

[0041] To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0042] Reference is made to Figure 1 , Figure 1 A single-ramp analog-to-digital converter provided by the present application has the structure as shown in the figure, which comprises:

[0043] A comparator is configured to reset both a first input end and a second input end to a reset voltage when being reset, wherein the first input end is configured to input a pixel signal to be processed, and the second input end is configured to input a ramp signal;

[0044] A counting module is configured to quantize the reset voltage of the first input end of the comparator for the first time when the comparator is reset, and is further configured to, after the first quantization is completed, quantize the pixel signal to be processed for the second time based on a first counting parameter if a voltage value of the pixel signal to be processed is not greater than a preset voltage threshold, wherein the voltage value of the pixel signal to be processed is a voltage difference of the pixel signal to be processed relative to the reset voltage, and the first counting parameter is that the counting frequency is a first frequency and the counting weight is 1, and quantize the pixel signal to be processed for the second time based on a second counting parameter if the voltage value of the pixel signal to be processed is greater than the preset voltage threshold, so that a difference between a result of the second quantization and a result of the first quantization is taken as a pixel digital signal corresponding to the pixel signal to be processed, wherein the second counting parameter is that the counting frequency is a second frequency, the first frequency is twice the second frequency, and the counting weight is 2.

[0045] Specifically, in Figure 2 V RAMP : a ramp signal of an output of the ramp generator, PIEXL : an output signal of the pixel, RST: a comparator reset voltage signal, high level enable, comparator reset, Comp_out: a comparator output signal, IN+ V IN- , the comparator output is high level, otherwise low level, CLK[0]: a first counting clock signal, frequency FCLK[0]. CLK[1]: a second counting clock signal, frequency FCLK[1]=FCLK[0] / 2, wherein, the double frequency selectable N-bit counter is the counting module mentioned above, N is a positive integer, N and C P are coupling capacitors, used for coupling corresponding signals to the input end of the comparator, wherein, the lower plate of the first coupling capacitor C N is connected to the pixel signal V PIXEL to be processed, and the upper plate is connected to the inverting input end of the comparator, the lower plate of the second coupling capacitor C P is connected to the ramp voltage signal V RAMP , and the upper plate is connected to the non-inverting input end of the comparator.

[0046] Specifically, considering the technical problems in the background art above, and also considering (1) the power of the analog-to-digital converter can be reduced by reducing the counting frequency and counting bit of the counting module, (2) the quantization noise introduced by a small decrease in the counting bit is negligible compared to the photon shot noise of the pixel signal to be processed generated based on strong light, therefore, in the embodiment of the present application, the counting module in the single-ramp analog-to-digital converter can count in a low frequency and one less counting bit way when quantizing the "pixel signal to be processed generated based on strong light", thereby reducing the power consumption of the counting module when quantizing the "pixel signal to be processed generated based on strong light", therefore, in the embodiment of the present application, the single-ramp analog-to-digital converter is first controlled to perform a reset quantization stage, that is, after the comparator in the single-ramp analog-to-digital converter is reset, the reset voltage of the first input end of the comparator is quantized for the first time by the counting module in the single-ramp analog-to-digital converter.

[0047] Specifically, since the pixel digital signal can be regarded as the difference between the second quantization result of the count module for the pixel signal to be processed and the first quantization result of the reset voltage for the pixel signal to be processed, the second quantization action can be expanded in the embodiment of the present application. As the above idea is considered, the embodiment of the present application first determines whether the pixel signal to be processed is generated based on "strong light or weak light" by the preset voltage threshold. That is, when the voltage value of the pixel signal to be processed is not greater than the preset voltage threshold, it indicates that the pixel signal to be processed is generated based on weak light. At this time, the count module can be controlled to perform the second quantization on the pixel signal to be processed based on the first count parameter. The first count parameter can be regarded as the original count parameter, that is, the count parameter without change, which has the first frequency and the count weight of 1.

[0048] Specifically, when the voltage value of the pixel signal to be processed is greater than the preset voltage threshold, it indicates that the pixel signal to be processed is generated based on strong light. At this time, the count module can be controlled to perform the second quantization on the pixel signal to be processed based on the second count parameter. As the above idea is considered, the count bits are sacrificed when the pixel signal to be processed generated based on strong light is quantized in the embodiment of the present application. Therefore, the count weight of the second count parameter in the embodiment of the present application is 2, and the two quantization results are in the same dimension, and the count frequency is reduced by half.

[0049] Specifically, the difference between the second quantization result and the first quantization result can be regarded as the pixel digital signal corresponding to the pixel signal to be processed based on the idea of DCDS (Digital Correlated Double Sampling) in the embodiment of the present application.

[0050] Specifically, the embodiment of the present application can be applied to the design field of CCD (Charge-coupled Device Image Sensor) and CIS (CMOS Image Sensor) and related applications.

[0051] In addition, considering that the comparator in the single-ramp analog-to-digital converter can grade the voltage value of the pixel signal to be processed by setting the voltage of the ramp signal, in the embodiment of the present application, the voltage value of the ramp voltage signal received by the second input end of the comparator in the pre-comparison stage can be controlled as a preset voltage threshold, and then the level grade of the output of the comparator can represent the comparison result of the pixel signal to be processed and the preset voltage threshold, that is, if the first digital signal is output by the comparator in the pre-comparison stage, it is determined that the voltage value of the pixel signal to be processed is not greater than the preset voltage threshold, and if the second digital signal is output by the comparator in the pre-comparison stage, it is determined that the voltage value of the pixel signal to be processed is greater than the preset voltage threshold. In the embodiment of the present application, the comparison between the pixel signal to be processed and the preset voltage threshold can be realized based on the original comparator in the single-ramp analog-to-digital converter, without the need for additional devices or calculation actions, thereby further saving the cost and reducing the power consumption.

[0052] The preset voltage threshold can be set as the voltage value corresponding to the MSB (Most Significant Bit, highest significant bit), which is not limited in the embodiment of the present application.

[0053] The present application provides a single-ramp analog-to-digital converter. Considering that (1) the power of the analog-to-digital converter can be reduced by reducing the counting frequency and counting bit of the counting module, and (2) the quantization noise introduced by a small decrease in the counting bit can be ignored compared with the photon shot noise of the pixel signal to be processed generated under strong light, in the present application, after the reset voltage of the pixel signal to be processed is quantized for the first time by the counting module, when the pixel signal to be processed is not greater than a preset voltage threshold (that is, the pixel signal to be processed is generated under weak light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on the original first counting parameter, and when the pixel signal to be processed is greater than the preset voltage threshold (that is, the pixel signal to be processed is generated under strong light), the counting module is controlled to quantize the pixel signal to be processed for the second time based on the second counting parameter (counting frequency halved and counting bit reduced by one). That is, by sacrificing the analog-to-digital conversion accuracy when processing the pixel signal to be processed corresponding to strong light, the power consumption of the counting module is reduced, thereby reducing the power consumption of the single-ramp analog-to-digital converter, which is conducive to reducing the power consumption of the CMOS image sensor.

[0054] On the basis of the above embodiment:

[0055] As an optional embodiment, the counting module comprises a clock control device and N cascaded sub-counters.

[0056] The output end of the former sub-counter is connected with the clock end of the latter sub-counter, and the clock control device is connected with the clock end of the first sub-counter, the output end of the first sub-counter and the clock end of the second sub-counter respectively;

[0057] The clock control device is used for delivering the first counting clock signal to the clock end of the first sub-counter when the comparator outputs the first digital signal, and delivering the second counting clock signal to the clock end of the second sub-counter when the comparator outputs the second digital signal, wherein the frequency of the first counting clock signal is the first frequency, the frequency of the second counting clock signal is the second frequency, and the first frequency is twice the second frequency.

[0058] Any sub-counter is used for counting under the drive of the counting clock signal, wherein the counting clock signal comprises the first counting clock signal and the second counting clock signal.

[0059] Specifically, in the embodiment of the present application, considering that "delivering the first counting clock signal to the clock end of the first sub-counter" is equivalent to realizing the first counting parameter, and "delivering the second counting clock signal to the clock end of the second sub-counter" is equivalent to realizing the second counting parameter, therefore the counting module in the embodiment of the present application comprises the clock control device and the N cascaded sub-counters, and the switching of the counting parameters can be realized by the clock control device according to the different output levels of the comparator, so that the counting module in the embodiment of the present application has simple structure and low cost.

[0060] Of course, in addition to the specific structure, the counting module can also be other types, which is not limited in the embodiment of the present application.

[0061] As an optional embodiment, the clock control device comprises a clock control module and a switch module;

[0062] The switch module is arranged between the output end of the first sub-counter and the clock end of the second sub-counter;

[0063] The clock control module is used for realizing the electrical connection between the output end of the first sub-counter and the clock end of the second sub-counter through the switch module and delivering the first counting clock signal to the clock end of the first sub-counter when the comparator outputs the first digital signal, and disconnecting the electrical connection between the output end of the first sub-counter and the clock end of the second sub-counter through the switch module and delivering the second counting clock signal to the clock end of the second sub-counter through the switch module when the comparator outputs the second digital signal.

[0064] Specifically, considering that when the second counting parameter (the counting frequency is the second frequency, the first frequency is twice the second frequency, and the counting weight is 2) is implemented, the clock signal of the first stage sub-counter is not allowed to be transmitted to the second stage sub-counter, and the output end of the first stage sub-counter and the clock end of the second stage sub-counter can be reliably cut off through the switch module, therefore, the clock control device in the embodiment of the present application comprises a clock control module and a switch module, so that the reliable switching of the counting parameter is realized through the cooperation of the clock control module and the switch module, and the reliability of the single-ramp analog-to-digital converter is improved.

[0065] Of course, in addition to this specific structure, the clock control device can also be of other types, which are not limited in the embodiment of the present application.

[0066] As an optional embodiment, the switch module comprises a first switch and a second switch.

[0067] The first switch is arranged between the output end of the first stage sub-counter and the clock end of the second stage sub-counter, the clock control module is connected with the first end of the first switch, the control end of the first switch and the control end of the second switch respectively, and the second end of the second switch is connected with the clock end of the second stage sub-counter.

[0068] The clock control module is specifically used for, when the comparator outputs the first digital signal, controlling the first switch to be turned on and the second switch to be turned off, and transmitting the first counting clock signal to the clock end of the first stage sub-counter; when the comparator outputs the second digital signal, controlling the first switch to be turned off and the second switch to be turned on, and transmitting the second counting clock signal to the input end of the second switch.

[0069] Specifically, considering that when the first counting parameter is implemented, the second counting clock signal is also not allowed to be input to the clock end of the second stage sub-counter, and the signal path can be cut off through the switch, therefore, the switch module in the embodiment of the present application comprises a first switch and a second switch, and through the cooperation of the two switches, the interference of another possible technical parameter can be prevented when any counting parameter is implemented.

[0070] Of course, in addition to this specific form, the switch module can also be of other types, which are not limited in the embodiment of the present application.

[0071] As an optional embodiment, the clock control module comprises a signal generation module and a clock selection module.

[0072] The clock selection module is connected with the clock end of the first stage sub-counter and the first end of the second switch respectively, and the output end of the signal generation module is connected with the control end of the first switch and the control end of the second switch respectively.

[0073] The signal generation module is configured to output a first switch control signal or a second switch control signal under control, wherein the first switch control signal is configured to control the first switch to be turned on, and the second switch control signal is configured to control the second switch to be turned on.

[0074] The clock selection module is configured to output a first count clock signal under a first constraint condition and output a second count clock signal under a second constraint condition, wherein the first constraint condition comprises that the comparator outputs the first digital signal and the signal generation module outputs the first switch control signal, and the second constraint condition comprises that the comparator outputs the second digital signal and the signal generation module outputs the second switch control signal.

[0075] Specifically, in order to better illustrate the embodiments of the present application, please refer to Figures 2 to 4 , Figure 2 FIG. 1 is a structural schematic diagram of a signal generation module provided by the present application, Figure 3 FIG. 2 is a structural schematic diagram of a clock selection module provided by the present application, Figure 4 FIG. 3 is a structural schematic diagram of an N-stage cascaded sub-counter provided by the present application, wherein the N-bit counter is composed of N cascaded sub-counters. AND4: four-input AND gate structure. DRST: sub-counter reset signal, high level enables, and resets the output of the N-bit counter. EN_RAMP: count enable signal, low level makes the counting module not count. Ψ0: output signal of the D flip-flop, controls the K0 switch to be turned on or turned off, thereby controlling whether the CLK[0] count signal normally works. 0: inverted output signal of the D flip-flop, controls the K1 switch to be turned on or turned off, thereby controlling whether the CLK[1] count signal normally works. LOCK_EN: latching signal, in the pre-comparison stage, the result output by the comparator is sampled by the falling edge, thereby selecting the frequency used by the count module in the signal quantization stage, and the SWITCH_EN signal is used to negate the output result of each bit of the count module. The SWITCH_EN cooperates with the LOCK_EN signal to negate the output result of each bit of the count module. Q <n-1>: the output result of the 0th, 1st, 2nd, 3rd, N-1th sub-counters.

[0076] Specifically, in the embodiment of the present application, on the basis of the N-stage cascaded sub-counters, through the signal generation module, the clock selection module and the two switches, the dual-frequency (i.e. the first frequency and the second frequency) selectable N-bit counter can be realized, without excessively increasing the volume and cost of the single-slope analog-to-digital converter.

[0077] Of course, in addition to this specific form, the counting module can also be in other various forms, which are not limited in the embodiment of the present application.

[0078] As an optional embodiment, the first constraint condition further includes that the counting enable signal is valid, and the second constraint condition further includes that the counting enable signal is valid.

[0079] Specifically, considering that the user can have the control demand for the counting of the single-slope analog-to-digital converter, in order to meet the user demand, the clock selection module in the embodiment of the present application further includes that the first constraint condition and the second constraint condition both include that the counting enable signal is valid, i.e. the clock selection module can output the counting clock signal only when the counting enable signal is valid, so that the user can control the counting of the single-slope analog-to-digital converter through the control of the counting enable signal, thereby improving the user experience.

[0080] As an optional embodiment, the clock selection module includes a first AND gate and a second AND gate.

[0081] The input ends of the first AND gate are respectively connected with the first counting clock signal, the counting enable signal, the output end of the comparator and the first switch control signal output end of the signal generation module, the output end of the first AND gate is connected with the clock end of the first-stage sub-counter, the input ends of the second AND gate are respectively connected with the second counting clock signal, the counting enable signal, the output end of the comparator and the second switch control signal output end of the signal generation module, and the output end of the second AND gate is connected with the first end of the second switch.

[0082] Specifically, please refer to Figure 3 The two AND gates can selectively output the first counting clock signal and the second counting clock signal respectively, and the cost and volume of the AND gates are relatively small, which can further reduce the cost and volume of the counting module.

[0083] Of course, in addition to this specific form, the clock selection module can also be in other various types, which are not limited in the embodiment of the present application.

[0084] As an optional embodiment, the sub-counter comprises an OR gate, a first NAND gate, a second NAND gate, a first inverter, a second inverter, a CMOS switch, a first signal inversion device, a second signal inversion device, and a third signal inversion device.

[0085] The input ends of the OR gate are connected with the latch signal and the clock signal respectively, the output end of the OR gate is connected with the first input end of the first NAND gate, the second input end of the first NAND gate is connected with the switching signal, the output end of the first NAND gate is connected with the enable end of the CMOS switch, the input end of the first inverter, and the enable end of the second signal inversion device respectively, the output end of the first inverter is connected with the enable end of the first signal inversion device and the enable end of the third signal inversion device respectively, the input end of the first signal inversion device, the output end of the second inverter, and the input end of the third signal inversion device are collectively used as the output end of the sub-counter, the output end of the first signal inversion device is connected with the second input end of the second NAND gate and the output end of the second signal inversion device respectively, the first input end of the second NAND gate is used as the reset port of the sub-counter, the output end of the second NAND gate is connected with the input end of the second signal inversion device and the first end of the CMOS switch respectively, and the second end of the CMOS switch is connected with the input end of the second inverter and the output end of the third signal inversion device respectively.

[0086] The switching signal is used for inverting the sub-counter in cooperation with the latch signal.

[0087] Specifically, in order to better illustrate the embodiments of the present application, please refer to Figure 5 , Figure 5 The structure diagram of the sub-counter provided by the present application, OR: OR gate, NAND: NAND gate, INV: inverter, TG: CMOS switch, high level enable, in the enabled state, turn on, in the unenabled state, turn off (EN is the enable end of TG), ENINV: high level enable, invert the input signal and output. When LOCK_EN is low level and SWITCH is high level, the rising edge of CLK reverses the data of the output end Q of the sub-counter and transmits the data to the D end of the sub-counter, and the falling edge of CLK transmits the data of the D end of the sub-counter to the output end Q of the sub-counter. Therefore, the signal output by Q is inverted once every time the falling edge of CLK passes, and N sub-counters are cascaded, so as to realize the binary counter.

[0088] Of course, in addition to this specific form, the sub-counter can also be of other types, which are not limited in the embodiments of the present application.

[0089] As an optional embodiment, the sub-counter is also used for:

[0090] Inverting the count value of the controlled to itself after completing the first quantization;

[0091] The count value after the second quantization of the count module is taken as the pixel digital signal corresponding to the pixel signal to be processed.

[0092] Specifically, in order to obtain the difference between the second quantization result and the first quantization result, considering that the count module itself can perform inversion, the negative of the first quantization result is obtained, and then the count module is normally used for the second quantization, and the output result of the count module after the second quantization is equivalent to the difference between the second quantization result and the first quantization result, so in the embodiment of the application, the count values of the sub-counters in the count module can be inverted after the first quantization, and finally the count value after the second quantization of the count module can be taken as the pixel digital signal corresponding to the pixel signal to be processed, which can avoid increasing additional devices or calculation processes for difference calculation, reduces the cost and further reduces the power consumption.

[0093] Specifically, as introduced in the foregoing embodiment, the sub-counter in the embodiment of the application itself can be controlled to invert the count value thereof, that is, the count value of the sub-counter can be inverted under the control of the SWITCH_EN and LOCK_EN signals, so the sub-counter can be used to realize the work of inverting the count values of the sub-counters in the count module after the first quantization in the embodiment of the application, avoiding increasing the cost and volume caused by increasing the devices.

[0094] Specifically, in order to better introduce the analog-digital conversion process in the embodiment of the application, please refer to Figure 6 and Figure 7 , Figure 6 the analog-digital conversion timing diagram of the weak light pixel signal provided by the application; Figure 6 the analog-digital conversion timing diagram of the strong light pixel signal provided by the application, first introduces the process in Figure 6 .

[0095] (1) The reset quantization stage starts, the RST and DRST signals are high, and the comparators and the counters are reset. In the reset quantization stage, Ψ0 is always high, and the switch K0 is turned on. When V RAMP (starting to change, the voltage will be coupled to the same input end V P of the comparator by the second coupling capacitor C IN+ (solid line) and compared with the inverted input voltage V IN- (dot line), when V IN+ > V IN- When the comparison result Comp_out is high level and the EN_RAMP signal is high level, the counter starts counting from the 0th bit. When the comparison result Comp_out is low level, the counting stops and the counting result is recorded as: IN+ < V IN- When the comparison result Comp_out is low level, the counting stops and the counting result is recorded as:

[0096] ;

[0097] F CLK[0] is the clock frequency when the 0th bit counter starts counting, S is the slope of the ramp voltage signal, V PEAK is the maximum voltage of the ramp voltage signal, V IN+ is the coupling voltage value, V RST is the V IN+ coupling voltage value corresponding to the pixel voltage, V IN- is the coupling voltage value, D out1 is the Q <n-1:0>The corresponding decimal result.

[0098] (2) Pre-comparison stage, V IN+ The voltage is always V REF When the pixel voltage is completed transmission, the comparator inverting input V IN- The value is V SIG , the actual pixel difference voltage is (V RST -V SIG ). At this time, the comparator non-inverting input signal V REF Will be compared with the inverting input signal V SIG In the example of Figure 7 , V SIG Is greater than V REF (Preset voltage threshold), the comparator output is low, the (V RST -V SIG ) signal is judged as a weak light pixel signal, and Ψ0 is always high. At the same time, in order to realize the subtraction operation of DCDS, the output result of (2 N -D out1 -1) is obtained by controlling each bit of the sub-counter through LOCK_EN and SWITCH_EN signals.

[0099] (3) Signal quantization stage, when V RAMP Start to change, the changing voltage will be coupled to the same input of the comparator V IN+ (Solid line) and compared with the inverting input voltage V IN- (Dotted line), when V IN+ > V IN- , the comparison result Comp_out is high, the EN_RAMP signal is high, and the counter starts counting, when V IN+ < V IN- , the comparison result Comp_out is low, the counting stops, and the counting result is recorded as:

[0100] ;

[0101] Ignore the overflow 2 N Counting value, the corresponding quantization result of the pixel difference voltage (V RST -V SIG ) is:

[0102] ;

[0103] Specifically, Figure 7 The flow is:

[0104] The reset quantization stage starts, the RST and DRST signals are high, the comparators and the counters are reset. In the reset quantization stage, Ψ0 is always high, switch K0 is on. When V RAMP The changing voltage is coupled to the non-inverted input terminal V IN+ of the comparator (solid line) and compared with the inverted input terminal pixel signal voltage V IN- (dot line) to be processed. When V IN+ > V IN- , the comparison result Comp_out is high, the EN_RAMP signal is high, the counter starts counting from the 0th bit. When V IN+ < V IN- , the comparison result Comp_out is low, the counting stops, and the counting result is recorded as:

[0105] ;

[0106] F CLK[0] is the clock frequency when the 0th bit counter starts counting, S is the slope of the ramp voltage signal, V PEAK is the maximum voltage of the coupled voltage value of the ramp voltage signal, V IN+ is the coupled voltage value when the 0th bit counter starts counting, V RST is the coupled voltage value when the reset quantization stage starts, V IN+ is the coupled voltage value when the pixel voltage is coupled, D IN- is the coupled voltage value when the reset quantization stage starts, D out1 is the Q <n-1:0>The corresponding decimal result.

[0107] Pre-comparison stage, V IN+ The voltage is always V REF When the pixel voltage is completed transmission, the comparator inverting input V IN- The value is V SIG , the actual pixel difference voltage is (V RST -V SIG ). At this time, the comparator non-inverting input signal V REF Will be compared with the inverting input signal V SIG In the example of Figure 7 , V SIG is less than V REF , so the comparator output becomes high in the pre-comparison stage, and the (V RST -V SIG ) signal is judged as a strong light pixel signal. Ψ0 becomes low in the pre-comparison stage, and the counter will start counting from the first bit in the signal quantization stage, the counting weight is recorded as 2, and the counting frequency becomes half of the reset quantization stage. At the same time, in order to realize the subtraction operation of DCDS, the output result of (2 N -D out1 -1) is obtained by controlling each bit of the sub-counter through the LOCK_EN and SWITCH_EN signals.

[0108] Signal quantization stage when V RAMP Start changing, the changing voltage will be coupled to the same direction input of the comparator V IN+ (Solid line) and compared with the inverting input voltage V IN- (Dotted line), when V IN+ > V IN- , the comparison result Comp_out is high, the EN_RAMP signal is high, and the counter starts counting from the first bit, when V IN+ < V IN- , the comparison result Comp_out is low, the counting stops, and the counting result is recorded as:

[0109] ;

[0110] Because the frequency value of F CLK[1] is half of F CLK[0] , and the counting weight is 2, the value is always even, which is different from the result counted by F CLK[0] 1, 0 or -1, ignoring the overflow 2 N Counting value, the corresponding quantization result of the pixel difference voltage (V RST -V SIG ) is:

[0111] ​ ;

[0112] According to the dynamic power consumption formula of each stage of the counter circuit:

[0113] P=c i V DD 2 E i ;

[0114] c i is the total load capacitance of each logic module inside the i-th stage of the counter, V DD is the power supply voltage of the counter, E i is the switching characteristic of the i-th stage of the counter, representing the number of transitions of the i-th stage of the counter output per unit time, E i and the counting clock frequency. In the quantization of strong light pixel signals, the dynamic power consumption of the signal quantization stage counter can be reduced by half by increasing the weight and reducing the frequency of the counting clock. However, under strong light pixel signals, the counting accuracy of the SS ADC also changes from N bit to (N-1) bit.

[0115] According to the quantization noise formula:

[0116] ;

[0117] V RANGE is the quantization range of the SS ADC, and N is the quantization accuracy of the SS ADC. Therefore, under weak light pixel signals and strong light pixel signals, the quantization noise values considering DCDS are respectively:

[0118] ;

[0119] ;

[0120] (V RST – V REF ) is generally set to 1 / 2V RANGE , then for strong light pixel signals, the minimum photon shot noise value is:

[0121] ;

[0122] CG is the conversion gain of the pixels in the image sensor, and for the image sensor, the value of v shot1 is much larger than v readnoise2 , so reducing the accuracy of quantizing strong light pixel signals will not affect the linearity of the SS ADC, proving the feasibility of the scheme to reduce the dynamic power consumption of the counter to reduce the power consumption of the SS ADC.

[0123] The various embodiments described in this specification are intended to be illustrative only and in no way limit the scope of the application. Those skilled in the art will be able to implement or use the application without departing from the spirit or scope of the application. In addition, although the application is described above in one preferred embodiment or a series of preferred embodiments, other embodiments of the application will be obvious to those of ordinary skill in the art and can be made without departing from the spirit or scope of the application. Accordingly, the scope of the application is intended to be defined only by the appended claims and their equivalents. The specification and drawings are, accordingly, to be regarded simply as an illustration of the embodiment of the application as described by the appended claims, the benefits and privileges sought for the patent, and the limitations thereby imposed.

[0124] The above description of disclosed embodiments is intended to be illustrative only and not limiting of the scope of the application. Numerous modifications of the embodiments described herein, as defined in the following claims, can be undertaken by those skilled in the art without departing from the true scope and spirit of the application. Accordingly, the scope of the application is intended to be defined only by the appended claims and their equivalents. The specification and drawings are, accordingly, to be regarded simply as an illustration of the embodiment of the application as described by the appended claims, the benefits and privileges sought for the patent, and the limitations thereby imposed.

Claims

1. A single-slope analog-to-digital converter, comprising: The application relates to a pixel signal processing circuit. The pixel signal processing circuit comprises a comparator, a counting module, a first digital signal output terminal and a second digital signal output terminal. The comparator is used for resetting the first input terminal and the second input terminal to a reset voltage when being reset, wherein the first input terminal is used for inputting a pixel signal to be processed, and the second input terminal is used for inputting a ramp signal.

2. The single-slope analog-to-digital converter of claim 1, wherein, The counting module is used for quantizing the reset voltage of the first input terminal of the comparator for the first time when the comparator is reset, and is further used for, after the first quantization is completed, quantizing the pixel signal to be processed for the second time based on a first counting parameter if the voltage value of the pixel signal to be processed is not greater than a preset voltage threshold value, wherein the voltage value of the pixel signal to be processed is a voltage difference value of the pixel signal to be processed relative to the reset voltage, and the first counting parameter is that the counting frequency is a first frequency and the counting weight is 1; and the counting module is further used for quantizing the pixel signal to be processed for the second time based on a second counting parameter if the voltage value of the pixel signal to be processed is greater than the preset voltage threshold value, so that the difference between the result of the second quantization and the result of the first quantization is taken as a pixel digital signal corresponding to the pixel signal to be processed, wherein the second counting parameter is that the counting frequency is a second frequency, the first frequency is twice the second frequency, and the counting weight is 2. The counting module comprises a clock control device and N cascaded sub-counters. In the N cascaded sub-counters, the output terminal of a former sub-counter is connected with the clock terminal of a latter sub-counter, and the clock control device is connected with the clock terminal of the first sub-counter, the output terminal of the first sub-counter and the clock terminal of the second sub-counter respectively. The clock control device is used for transmitting the first counting clock signal to the clock terminal of the first sub-counter when the comparator outputs the first digital signal, and transmitting the second counting clock signal to the clock terminal of the second sub-counter when the comparator outputs the second digital signal, wherein the frequency of the first counting clock signal is the first frequency, the frequency of the second counting clock signal is the second frequency, and the first frequency is twice the second frequency.

3. The single-slope analog-to-digital converter of claim 2, wherein, Any sub-counter is used for counting under the drive of a counting clock signal, wherein the counting clock signal comprises the first counting clock signal and the second counting clock signal. The clock control device comprises a clock control module and a switch module. The switch module is arranged between the output terminal of the first sub-counter and the clock terminal of the second sub-counter.

4. The single-slope analog-to-digital converter of claim 3, wherein, The clock control module is used for realizing the electrical connection between the output terminal of the first sub-counter and the clock terminal of the second sub-counter through the switch module when the comparator outputs the first digital signal, transmitting the first counting clock signal to the clock terminal of the first sub-counter, realizing the disconnection between the output terminal of the first sub-counter and the clock terminal of the second sub-counter through the switch module when the comparator outputs the second digital signal, and transmitting the second counting clock signal to the clock terminal of the second sub-counter through the switch module. The switch module comprises a first switch and a second switch. The first switch is arranged between the output end of the first stage sub-counter and the clock end of the second stage sub-counter, the clock control module is connected with the first end of the first switch, the control end of the first switch and the control end of the second switch respectively, and the second end of the second switch is connected with the clock end of the second stage sub-counter; The clock control module is specifically used for controlling the first switch to be turned on and the second switch to be turned off, and delivering the first counting clock signal to the clock end of the first stage sub-counter when the comparator outputs the first digital signal; and controlling the first switch to be turned off and the second switch to be turned on, and delivering the second counting clock signal to the input end of the second switch when the comparator outputs the second digital signal.

5. The single-slope analog-to-digital converter of claim 4, wherein, The clock control module comprises a signal generation module and a clock selection module; The clock selection module is connected with the clock end of the first stage sub-counter and the first end of the second switch respectively, and the output end of the signal generation module is connected with the control end of the first switch and the control end of the second switch respectively. The signal generation module is used for controlled output of the first switch control signal or the second switch control signal, wherein the first switch control signal is used for controlling the first switch to be turned on, and the second switch control signal is used for controlling the second switch to be turned on. The clock selection module is used for outputting the first counting clock signal under the first constraint condition and outputting the second counting clock signal under the second constraint condition, wherein the first constraint condition comprises that the comparator outputs the first digital signal and the signal generation module outputs the first switch control signal, and the second constraint condition comprises that the comparator outputs the second digital signal and the signal generation module outputs the second switch control signal.

6. The single-slope analog-to-digital converter of claim 5, wherein, The first constraint condition further comprises that the counting enable signal is effective, and the second constraint condition further comprises that the counting enable signal is effective.

7. The single-slope analog-to-digital converter of claim 5, wherein, The clock selection module comprises a first AND gate and a second AND gate. The input end of the first AND gate is connected with the first counting clock signal, the counting enable signal, the output end of the comparator and the first switch control signal output end of the signal generation module respectively, the output end of the first AND gate is connected with the clock end of the first stage sub-counter, the input end of the second AND gate is connected with the second counting clock signal, the counting enable signal, the output end of the comparator and the second switch control signal output end of the signal generation module respectively, and the output end of the second AND gate is connected with the first end of the second switch.

8. The single-slope analog-to-digital converter of claim 2, wherein, The sub-counter comprises an OR gate, a first NAND gate, a second NAND gate, a first inverter, a second inverter, a CMOS switch, a first signal reversing device, a second signal reversing device and a third signal reversing device. The input end of the OR gate is connected with the latch signal and the clock signal respectively, the output end of the OR gate is connected with the first input end of the first NAND gate, the second input end of the first NAND gate is connected with the switch signal, the output end of the first NAND gate is connected with the enable end of the CMOS switch, the input end of the first inverter and the enable end of the second signal reverse device respectively, the output end of the first inverter is connected with the enable end of the first signal reverse device and the enable end of the third signal reverse device respectively, the input end of the first signal reverse device, the output end of the second inverter and the input end of the third signal reverse device are collectively used as the output end of the sub-counter, the output end of the first signal reverse device is connected with the second input end of the second NAND gate and the output end of the second signal reverse device respectively, the first input end of the second NAND gate is used as the reset port of the sub-counter, the output end of the second NAND gate is connected with the input end of the second signal reverse device and the first end of the CMOS switch respectively, the second end of the CMOS switch is connected with the input end of the second inverter and the output end of the third signal reverse device respectively. The switch signal is used for cooperating with the latch signal to reverse the sub-counter.

9. The single-slope analog-to-digital converter of any of claims 2 to 8, wherein, The sub-counter is further used for: reversing the count value of itself after completing the first quantization; The count value after the second quantization of the count module is used as the pixel digital signal corresponding to the pixel signal to be processed.

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