Semiconductor package with stacked memory and logic

Abstract

A semiconductor package may include: a first redistribution line structure; a die on the first redistribution line structure; a first memory device on the first surface of the die; a second redistribution line structure on a second surface of the die opposite the first surface; a second memory device on the second redistribution line structure; and at least one semiconductor chip on the second redistribution line structure and electrically connected to the first memory device and the second memory device. The first memory device may be a static RAM (SRAM), and the second memory device may be a dynamic RAM (DRAM).

Description

Technical Field

[0001] The inventive concepts disclosed herein relate to semiconductor packages, and more particularly, to semiconductor packages having a package architecture of stacked memory chips and logic chips. Background Art

[0002] In a computing architecture, a processing component (such as a central processing unit (CPU), a graphics processing unit (GPU), etc.) can obtain data from one or more memory devices, such as a static random access memory (SRAM) device (which is relatively fast but relatively low capacity) that acts as a cache and / or a relatively high capacity but relatively slow dynamic RAM (DRAM).

[0003] Continued developments within the electronics industry and increasing demands from customers have led to further miniaturization and multifunctionality of electronic devices. Accordingly, semiconductor packages including multiple semiconductor chips or dies are being considered and developed. Summary of the invention

[0004] According to some aspects of the present inventive concept, a semiconductor package is provided. The semiconductor package may include: a first redistribution line structure, including a first insulating layer and a first redistribution line pattern; a tube core on the first redistribution line structure; a first memory device on a first surface of the tube core; a second redistribution line structure on a second surface of the tube core opposite to the first surface, the second redistribution line structure including a second insulating layer and a second redistribution line pattern; a second memory device on the second redistribution line structure; and at least one semiconductor chip on the second redistribution line structure and electrically connected to the first memory device and the second memory device. In some embodiments, the first memory device may be a static RAM (SRAM) device, and the second memory device may be a dynamic RAM (DRAM) device.

[0005] According to some aspects of the inventive concept, a semiconductor package may include: a first redistribution line structure having a first portion and a second portion, the first redistribution line structure including a first insulating layer and a first redistribution line pattern; a tube core on the first redistribution line structure; a first memory device on a first surface of the tube core; a second redistribution line structure on a second surface of the tube core opposite to the first surface, the second redistribution line structure including a second insulating layer and a second redistribution line pattern; and a second memory device on an upper surface of the second redistribution line structure. The first memory device may overlap the first portion and the second portion of the first redistribution line structure in a first direction.

[0006] According to some aspects of the present invention, a method for forming a semiconductor package may include: forming a first redistribution line structure including a first insulating layer and a first redistribution line pattern; attaching a first memory device to a first surface of a die; attaching the first surface of the die to the first redistribution line structure; forming a second redistribution line structure on a second surface of the die opposite to the first surface, the second redistribution line structure including a second insulating layer and a second redistribution line pattern; and attaching a second memory device to a surface of the second redistribution line structure opposite to a surface of the second redistribution line structure facing the die.

[0007] The present disclosure is not limited to the above-described embodiments and inventive concepts, and other embodiments and inventive concepts are provided in the accompanying drawings and detailed description thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of a semiconductor package 1 according to some embodiments.

[0009] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F is a cross-sectional view for explaining a method of manufacturing a portion of a semiconductor package according to some embodiments.

[0010] Figure 3A and Figure 3B is a cross-sectional view for explaining a method of manufacturing a portion of a semiconductor package according to some embodiments.

[0011] Figure 4A and Figure 4B is a cross-sectional view for explaining a method of manufacturing a portion of a semiconductor package according to some embodiments.

[0012] Figure 5A , Figure 5B and Figure 5C is a cross-sectional view for explaining a method of manufacturing a portion of a semiconductor package according to some embodiments.

[0013] Like reference numerals may refer to corresponding parts throughout the drawings. DETAILED DESCRIPTION

[0014] High bandwidth memory (HBM) has been introduced and has been integrated directly with the computing engine using advanced packaging, including 2.5D and 3D IC packaging. Placing HBM closer to the processor components can help reduce latency and increase memory bandwidth. However, there may still be latency in transferring large amounts of data between the processor components and HBM through silicon interposers or active silicon. In addition, the increased power consumption in such packaging raises concerns about thermal management and energy efficiency management.

[0015] Accordingly, some embodiments of the inventive concepts of the present disclosure provide semiconductor packaging architectures that provide improved computing performance and storage performance and achieve acceptable thermal properties and / or energy management. For example, some embodiments of the inventive concepts may provide a memory device of a first type (e.g., an SRAM memory device) and a memory device of a second type (e.g., a DRAM memory device) and a processing unit in a stacked architecture (e.g., a silicon stack). This can combine the advantages of both the first memory type (e.g., faster and lower latency, lower power as low as 1 watt (W)) and the second memory type (e.g., higher capacity, up to 32 gigabytes (GB) or more), and can provide improved thermal properties and / or energy management. However, the present disclosure is not limited to these embodiments or advantages.

[0016] Figure 1 is a cross-sectional view of a semiconductor package 1 according to some embodiments. Figure 1 , the semiconductor package 1 may include a lower redistribution line structure 210, an intermediate redistribution line structure 260, a first memory device 300, a die 250, an upper redistribution line structure 290, a second memory device 400 and / or at least one semiconductor chip 500 ( Figure 1 2 and 3. In the embodiment of the present invention, two semiconductor chips 500 are shown in FIG. 2 ). The intermediate redistribution line structure 260, the first memory device 300, and the tube core 250 may be located between the lower redistribution line structure 210 and the upper redistribution line structure 290 in the vertical direction D2, and the second memory device 400 and the at least one semiconductor chip 500 may be located on the upper redistribution line structure 290 in the vertical direction D2. The first memory device 300 may be on a first side of the tube core 250, and the second memory device may be on a second side of the tube core 250 opposite to the first side in the vertical direction D2.

[0017] The lower redistribution line structure 210 may include a plurality of lower insulating layers 216 , a plurality of lower redistribution line patterns 212 on at least one of the top and bottom surfaces of the plurality of lower insulating layers 216 , and a plurality of lower via patterns 214 penetrating at least one of the plurality of lower insulating layers 216 and contacting at least some of the plurality of lower redistribution line patterns 212 .

[0018] Each lower insulating layer 216 may be formed of, for example, an organic material layer, and in some embodiments, each lower insulating layer 216 may include an organic compound. According to some embodiments, each of the plurality of lower insulating layers 216 may be formed of an organic polymer material, such as photosensitive polyimide (PSPI).

[0019] Each lower redistribution line pattern 212 and lower via pattern 214 may include a metal, such as copper (Cu), tungsten (W), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga) or ruthenium (Ru), alloys thereof, or metal nitrides, but the present disclosure is not limited thereto.

[0020] In some embodiments, a portion of the lower redistribution line pattern 212 may be integrally formed with a portion of the lower via pattern 214. For example, at least some of the lower redistribution line patterns 212 may be integrally formed with at least some of the lower via patterns 214. Figure 1 , the lower redistribution line patterns 212 are considered to be within a lower insulation layer 216 among the plurality of lower insulation layers 216, but are not limited thereto. According to some embodiments, some of the lower redistribution line patterns 212 may be located on a top surface of an uppermost layer of the plurality of lower insulation layers 216 and / or on a bottom surface of a lowermost layer.

[0021] A plurality of connection pillars 220 may be on the lower redistribution line structure 210. Each of the plurality of connection pillars 220 may be located on the lower redistribution line structure 210 and spaced apart from the first memory device 300 in the horizontal direction D1. The plurality of connection pillars 220 may be located on portions of the plurality of lower redistribution line patterns 212, respectively. The connection pillars 220 may be connected to, for example, an uppermost redistribution line pattern among the plurality of lower redistribution line patterns 212 of the lower redistribution line structure 210. In some embodiments, the connection pillars 220 may be formed of, for example, the same material as the lower redistribution line pattern 212 or the lower via pattern 214.

[0022] The intermediate redistribution line structure 260 may be positioned on the connection pillar 220. The intermediate redistribution line structure 260 may include at least one intermediate insulating layer 266, a plurality of intermediate redistribution line patterns 262 on a top surface or a bottom surface of the intermediate insulating layer 266, and / or a plurality of intermediate via patterns 264 that penetrate the intermediate insulating layer 266 and contact portions of the plurality of intermediate redistribution line patterns 262, respectively.

[0023] The middle redistribution line pattern 262, the middle via pattern 264, and the middle insulating layer 266 may be the same as the lower redistribution line pattern 212, the lower via pattern 214, and the lower insulating layer 216, respectively, and thus details thereof are not provided. In some embodiments, the number of layers of the middle redistribution line structure 260 may be less than the number of layers of the lower redistribution line structure 210, but the present disclosure is not limited thereto. The middle redistribution line structure 260 may be split or divided in the horizontal direction D1 into a first middle redistribution line structure portion 260A and a second middle redistribution line structure portion 260B.

[0024] The connection pillar 220 may interconnect the lower redistribution line patterns 212 of the lower redistribution line structure 210 and the middle redistribution line patterns 262 of the middle redistribution line structure 260. For example, the connection pillar 220 may contact and electrically interconnect the uppermost one of the plurality of lower redistribution line patterns 212 of the lower redistribution line structure 210 and the lowermost one of the middle redistribution line patterns 262 of the middle redistribution line structure 260.

[0025] The die 250 may be located on the intermediate redistribution line structure 260. The die 250 may include a first semiconductor substrate 252. The first semiconductor substrate 252 may include a first surface 252A, which may be an active surface or an interface on which a transistor layer is formed (e.g., a semiconductor substrate having a plurality of semiconductor layers). Figure 1 The first semiconductor substrate 252 may include a second surface 252B, which may be opposite to the first surface 252A in the vertical direction D2 and may be a passive surface. The first semiconductor substrate 252 may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0026] The die 250 may further include a first chip pad 254 on the first surface 252A of its first semiconductor substrate 252. The first chip pad 254 of the die 250 may be connected to the intermediate redistribution line pattern 262 of the intermediate redistribution line structure 260 via a chip connection member 370. The chip connection member 370 may be, for example, a bump, a solder ball, or a conductive pillar.

[0027] In some embodiments, the die 250 may include a wiring pattern (not shown) on its surface (e.g., the second surface 252B). The wiring pattern may include one or more connection line wirings within a layer, but is not limited thereto. According to some embodiments, the wiring pattern may include connection line wirings within multiple layers and via plugs interconnecting connection line wirings of different layers.

[0028] At least one transistor may be formed in the first semiconductor substrate 252 on the first surface 252A. The die 250 may include logic components and may be a logic die. In some embodiments, the die 250 may be configured to provide functions including (but not limited to) for example, data or signal routing, memory control, input / output interface, etc.

[0029] A via (e.g., a through substrate via or through silicon via (TSV) 256) may be formed in the first semiconductor substrate 252 and may penetrate or extend through the first semiconductor substrate 252 from the first surface 252A to the second surface 252B of the first semiconductor substrate 252. The via 256 may have a plug structure and may be disposed in a via hole (not shown) of the first semiconductor substrate 252. In some embodiments, the via 256 may contact the first chip pad 254 on the first surface 252A of the first semiconductor substrate 252.

[0030] The die 250 may include a bonding pad 258 on the first surface 252A of its first semiconductor substrate 252. In some embodiments, the via 256 in the first semiconductor substrate 252 may contact the bonding pad 258 on the first surface 252A of its first semiconductor substrate 252, for example, via an electrical trace or via. For ease of understanding, Figure 1 Not all electrical connections are shown.

[0031] The first memory device 300 may be disposed on the first surface 252A of the die 250 and coupled to the first surface 252A of the die 250. The first memory device 300 may be a static RAM (SRAM) memory device (e.g., an SRAM memory chip). The first memory device 300 may include a bonding pad 308. The first memory device 300 may be arranged on the die 250 such that the bonding pad 308 of the first memory device 300 faces the bonding pad 258 of the die 250. The bonding pad 308 of the first memory device 300 and the bonding pad 258 of the die 250 may be bonded to each other, for example, by Cu-Cu hybrid bonding.

[0032] The first memory device 300 may be arranged between the first and second intermediate redistribution line structures 260A and 260B in the horizontal direction D1. The first memory device 300 may be arranged to overlap the first and second intermediate redistribution line structures 260A and 260B in the horizontal direction D1.

[0033] The filling insulating layer 222 may be in the region between the lower redistribution line structure 210 and the tube core 250 (and may fill the region). The filling insulating layer 222 may be on and around the sidewalls of the connecting pillars 220 and the first memory device 300. The filling insulating layer 222 may be on the first surface 252A of the first semiconductor substrate 252 of the tube core 250. The filling insulating layer 222 may be on the exposed surface of the intermediate redistribution line structure 260 (and its first and second intermediate redistribution line structure portions 260A and 260B) and on the exposed surface of the chip connection member 370 between the tube core 250 and the intermediate redistribution line structure 260. The filling insulating layer 222 may include, for example, an epoxy mold compound (EMC) or a polymer material. As described in more detail below, the filling insulating layer 222 may include a first filling insulating material layer 223 and a second filling insulating material layer 224. The first filling insulating material layer 223 and the second filling insulating material layer 224 may include different materials, or may include the same material. In some embodiments, the first filling insulating material layer 223 and the second filling insulating material layer 224 may be or may include an embedded molding material, an epoxy molding compound (EMC), or a polymer material.

[0034] The upper redistribution line structure 290 may be located on the second surface 252B of the first semiconductor substrate 252 of the die 250. The upper redistribution line structure 290 may include at least one upper insulating layer 296, a plurality of upper redistribution line patterns 292 on a top surface or a bottom surface of the at least one upper insulating layer 296, and / or a plurality of upper via patterns 294 that penetrate the upper insulating layer 296 and contact portions of the plurality of upper redistribution line patterns 292, respectively.

[0035] The upper redistribution line pattern 292, the upper via pattern 294, and the upper insulating layer 296 may be the same as the lower redistribution line pattern 212, the lower via pattern 214, and the lower insulating layer 216, respectively, and therefore details thereof are not provided. In some embodiments, the number of layers of the upper redistribution line structure 290 may be less than or greater than the number of layers of the lower redistribution line structure 210, but the present disclosure is not limited thereto.

[0036] The second memory device 400 may be on the upper redistribution line structure 290. The second memory device 400 may be connected to the upper redistribution line structure 290 via a device connection member 490. In some embodiments, the second memory device 400 may include a stacked memory device. The second memory device 400 may be a stacked dynamic RAM (DRAM) device.

[0037] For example, the second memory device 400 may include a plurality of memory dies 410. Figure 1The second memory device 400 includes eight memory dies 410, but the number of memory dies is not limited thereto and may be changed differently. For example, the second memory device 400 may include four, twelve, sixteen or more memory dies 410. Each of the memory dies 410 may include a memory cell array. The first memory device 300 may also include a memory cell array.

[0038] Multiple memory dies 410 may be stacked on a logic die 420. The logic die 420 may be referred to as an interface die or a base logic die.

[0039] Each of the memory die 410 and the logic die 420 may include an internal chip pad that is located at Figure 1 Only the logic die 420 is shown as the internal chip pad 424. The internal connection members 470 may be between adjacent memory dies in the memory dies 410 and between the lowermost memory die 410 and the logic die 420. The internal connection members 470 may be, for example, bumps, solder balls, or conductive pillars.

[0040] Each of the memory dies 410 may include a through silicon via (TSV) 415. The TSV is Figure 1 4, for example, the connection members between the memory dies 410 are not shown. The logic die 420 and the memory die 410 may be stacked on each other and electrically connected to each other through the TSV 415. Therefore, the second memory device 400 may have a three-dimensional (3D) memory structure in which a plurality of dies are stacked. For example, the second memory device 400 may be implemented based on the high bandwidth memory (HBM) or hybrid memory cube (HMC) standards.

[0041] The logic die 420 may include an active surface having at least one transistor therein. The active surface of the logic die 420 may face the upper redistribution line structure 290. The logic die 420 may include an interface circuit for communicating with other components of the semiconductor package 1 (e.g., the die 250, the first memory device 300, the at least one semiconductor chip 500), and may be electrically connected to various components of the semiconductor package 1 through the upper redistribution line structure 290. Signals and / or data received by the logic die 420 may be transmitted to the memory die 410 through the TSV 415. In some embodiments, the logic die 420 may include circuits that provide other functions in addition to routing signals and / or data to and from the memory die 410 of the second memory device 400. In some embodiments, the second memory device 400 may be or may be referred to as a custom HBM or "bufferless" HBM, which may be used to distinguish the second memory device 400 from HBM according to a standard (e.g., a JEDEC standard) that utilizes a process (e.g., a memory process) to manufacture a buffer die to connect a DRAM memory die. In some embodiments, the logic die 420 may be manufactured using an advanced manufacturing process and / or an advanced silicon node and may not follow the JEDEC standard size, and the size of the logic die 420 may vary as needed.

[0042] An insulating adhesive layer (not shown) may be between the logic die 420 and the lowermost memory die 410 or between two adjacent memory dies among the plurality of memory dies 410. For example, the insulating adhesive layer may include a non-conductive film (NCF), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin. The second memory device 400 may further include a molding layer 430 that covers the side surfaces of the logic die 420 and the memory die 410. For example, the molding layer 430 may include an epoxy molding compound (EMC).

[0043] The second memory device 400 may include a second chip attach pad 454 , which may be connected to the upper redistribution line structure 290 via a device connection member 490 , which may be, for example, a bump, a solder ball, or a conductive pillar.

[0044] As a non-limiting example, at least one semiconductor chip 500 provided in the semiconductor package 1 may be or may include a processing component, and may be or may include, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip, a neural processing unit (NPU), a tensor processing unit (TPU), a visual processing unit (VPU), an image signal processor (ISP), and / or a digital signal processor (DSP). For example, the first of the at least one semiconductor chip 500 may be one of a CPU chip, a GPU chip, or an AP chip, and the second of the at least one semiconductor chip 500 may be one of a CPU chip, a GPU chip, or an AP chip different from the first of the at least one semiconductor chip 500.

[0045] The at least one semiconductor chip 500 may include a second semiconductor substrate and a third chip pad 554. The third chip pad 554 of the at least one semiconductor chip 500 may be connected to the upper redistribution line pattern 292 of the upper redistribution line structure 290 via a chip connection member 570. The chip connection member 570 may be, for example, a bump, a solder ball, or a conductive pillar.

[0046] The semiconductor package 1 may further include a molding layer 600, which may cover the outer surfaces of the second memory device 400 and the at least one semiconductor chip 500. In some embodiments, the molding layer 600 may surround the outer sidewalls or surfaces of the lower redistribution line structure 210, the filling insulation layer 222, the intermediate redistribution line structure 260, the die 250, and the upper redistribution line structure 290. The molding layer 600 may include, for example, an epoxy molding compound (EMC). In some embodiments, the molding layer 600 may provide or include a heat dissipation or heat dissipation member. The external connection terminal 150 may be adhered to the lowermost layer of the lower redistribution line structure 210, and may provide a connection to and from one or more external devices (not shown).

[0047] The semiconductor package 1 may include a first memory device 300 and a second memory device 400. The first memory device 300 may be an SRAM memory device and the second memory device 400 may be a DRAM memory device (e.g., a stacked DRAM memory device). The processing components of the semiconductor package 1 (e.g., the die 250, the logic die 420, and the at least one semiconductor chip 500) may be provided directly in a stacked architecture (e.g., a silicon stack) with the first memory device 300 and the second memory device 400, thereby allowing the processing components of the semiconductor package 1 to access both the SRAM of the first memory device 300 and the DRAM of the second memory device 400.

[0048] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F is a cross-sectional view for illustrating a method of manufacturing a portion of a semiconductor package according to some embodiments. For example, Figures 2A to 2F It is used to illustrate the manufacturing Figure 1 1 is a cross-sectional view of a method of manufacturing a first portion of a semiconductor package 1 , wherein the first portion includes a lower redistribution line structure 210 and an intermediate redistribution line structure 260 .

[0049] refer to Figure 2A , the lower redistribution line structure 210 may be formed on a carrier substrate 10 (e.g., a glass carrier). In some embodiments, a release film 20 may be adhered to an upper surface of the carrier substrate 10, and the lower redistribution line structure 210 may be formed on the release film 20. The lower redistribution line structure 210 may include a plurality of lower insulating layers 216, a lower redistribution line pattern 212 on a top surface or a bottom surface of each of the plurality of lower insulating layers 216, and / or a lower via pattern 214 penetrating each of the plurality of lower insulating layers 216.

[0050] The lower redistribution line structure 210 may be formed by sequentially stacking each of a plurality of lower insulating layers 216 , and the lower redistribution line pattern 212 , or both the lower via pattern 214 and the lower redistribution line pattern 212 .

[0051] For example, a detailed method of manufacturing the lower redistribution line structure 210 is as follows. First, a lower insulating layer 216 of the lowermost layer is formed, and a lower redistribution line pattern 212 may be formed on the lower insulating layer 216 of the lowermost layer. Next, a lower insulating layer 216 of a higher layer may be formed on the lowermost layer. A lower redistribution line pattern 212 may be formed in a higher layer, which may be performed simultaneously with forming a lower via pattern 214 in the lowermost layer, and the lower via pattern 214 may be connected to the lower redistribution line pattern 212 in the lowermost layer. By repeating such a process, the lower redistribution line structure 210 may be formed. Here, the lower via pattern 214 of the first layer may be formed integrally with the lower redistribution line pattern 212 of the second layer above the first layer, but the present disclosure is not limited thereto.

[0052] refer to Figure 2B , a connection pillar 220 may be formed on the lower redistribution line structure 210 . The connection pillar 220 may be connected to an uppermost portion of the lower redistribution line structure 210 , for example, an uppermost lower redistribution line pattern 212 of the lower redistribution line structure 210 .

[0053] To form the connection pillar 220, a mask pattern including openings at positions where the connection pillar 220 is to be formed is formed on the lower redistribution line structure 210, and an exposed portion of the uppermost lower insulation layer 216 of the lower redistribution line structure 210 may be removed by using the mask pattern as an etching mask so as to expose a portion of the lower redistribution line pattern 212. Next, the connection pillar 220 may be formed.

[0054] refer to Figure 2C , a first filling insulating material layer 223 may be formed on the lower redistribution line structure 210. The first filling insulating material layer 223 may be formed of, for example, an epoxy molding compound (EMC) or a polymer material. The filling insulating material layer may be formed on and around the sidewalls of the connection pillars 220.

[0055] refer to Figure 2D , an intermediate redistribution line structure 260 may be formed on the connection pillars 220 and the first filling insulating material layer 223. The intermediate redistribution line structure 260 may include a plurality of intermediate insulating layers 266, an intermediate redistribution line pattern 262 on a top surface or a bottom surface of each of the plurality of intermediate insulating layers 266, and / or an intermediate via pattern 264 penetrating each of the plurality of intermediate insulating layers 266. The intermediate redistribution line structure 260 may be formed via a process similar to that used to form the lower redistribution line structure 210, and for the sake of brevity, a repeated description thereof is omitted here.

[0056] refer to Figure 2E , trenches T may be formed in the intermediate redistribution line structure 260 and in the first filling insulating material layer 223. The trenches T may divide or separate the intermediate redistribution line structure 260 into a first intermediate redistribution line structure portion 260A and a second intermediate redistribution line structure portion 260B, which may be separated or spaced apart from each other in the horizontal direction D1.

[0057] refer to Figure 2F The chip connection member 370 may be formed on the upper surface of the intermediate redistribution line structure 260. The chip connection member 370 may be, for example, a bump, a solder ball, or a conductive pillar. In some embodiments, the chip connection member 370 may be formed before the trench T is formed.

[0058] Figure 3A and Figure 3B is a cross-sectional view for explaining a method of manufacturing a portion of a semiconductor package according to some embodiments.

[0059] refer to Figure 3A, the first memory device 300 can be disposed on the first surface 252A of the first semiconductor substrate 252 of the tube core 250 and connected to the first surface 252A of the first semiconductor substrate 252 of the tube core 250. The first memory device 300 can be a static RAM (SRAM) memory device (e.g., an SRAM memory chip). The first memory device 300 may include a bonding pad 308 that can be bonded to the bonding pad 258 of the tube core 250. The bonding pad 308 of the first memory device 300 and the bonding pad 258 of the tube core 250 can be bonded to each other (for example) by Cu-Cu hybrid bonding. The first semiconductor substrate 252 can have a via 256 and a first chip pad 254 formed therein.

[0060] refer to Figure 3B , the first semiconductor substrate 252 of the die 250 may be thinned from the second surface 252B thereof to expose the via 256 therein.

[0061] Figure 4A and Figure 4B is a cross-sectional view for explaining a method of manufacturing a portion of a semiconductor package according to some embodiments. Figures 4A to 4B It is used to illustrate the manufacturing Figure 1 A cross-sectional view of a method of manufacturing a third portion of a semiconductor package 1, wherein the third portion is included in Figures 2A to 2F The first part formed in Figure 3A and 3B The second part is formed in.

[0062] Reference Figure 4A , Figure 3A and Figure 3B The second part (designated P2) formed in the FIG. 2A to FIG. 2F More specifically, the first chip pad 254 of the die 250 may be adhered to the chip connection member 370 formed on the upper surface of the middle redistribution line structure 260. The first memory device 300 may be inserted into the trench T formed in the first portion of the semiconductor package 1.

[0063] refer to Figure 4B, a second filling insulating material layer 224 may be formed on the lower redistribution line structure 210. The second filling insulating material layer 224 may be on the sidewalls of the first memory device 300 and surround the sidewalls of the first memory device 300. The second filling insulating material layer 224 may be on the first surface 252A of the first semiconductor substrate 252 of the tube core 250. The second filling insulating material layer 224 may be on the exposed surface of the first intermediate redistribution line structure portion 260A and the second intermediate redistribution line structure portion 260B and on the exposed surface of the chip connection member 370 between the tube core 250 and the intermediate redistribution line structure 260. The second filling insulating material layer 224 may be formed of, for example, an epoxy molding compound (EMC) or a polymer material. The first filling insulating material layer 223 and the second filling insulating material layer 224 may form a filling insulating layer 222 together.

[0064] Figure 5A , Figure 5B and Figure 5C It is used to illustrate Figure 1 A cross-sectional view of a method for manufacturing a semiconductor package 1, comprising: FIG. 2A to FIG. 2F , Figure 3A and Figure 3B as well as Figure 4A and Figure 4B The manufactured part.

[0065] refer to Figure 5A , an upper redistribution line structure 290 may be formed on the die 250. The upper redistribution line structure 290 may include at least one upper insulating layer 296, an upper redistribution line pattern 292 on a top surface or a bottom surface of the at least one upper insulating layer 296, and an upper via pattern 294 penetrating the at least one upper insulating layer 296. The upper redistribution line structure 290 may be formed via a process similar to that used to form the lower redistribution line structure 210, and a repeated description thereof is omitted here for the sake of brevity.

[0066] refer to Figure 5B , at least one semiconductor chip 500 and the second memory device 400 may be attached (in any order) to the upper redistribution line structure 290. For example, the second chip pad 454 of the second memory device 400 may be attached to the device connection member 490 formed on the upper surface of the upper redistribution line structure 290, and the third chip pad 554 of the at least one semiconductor chip 500 may be attached to the chip connection member 570 formed on the upper surface of the upper redistribution line structure 290.

[0067] The at least one semiconductor chip 500 and the second memory device 400 may be manufactured through separate processes before forming the semiconductor package 1 .

[0068] refer to Figure 5C , a molding layer 600 may be formed, and the molding layer 600 may cover the outer surfaces of the second memory device 400 and the at least one semiconductor chip 500. In some embodiments, the molding layer 600 may surround the outer sidewalls or surfaces of the lower redistribution line structure 210, the filling insulation layer 222, the middle redistribution line structure 260, the die 250, and the upper redistribution line structure 290. The molding layer 600 may include, for example, an epoxy molding compound (EMC). After the molding layer 600 is formed, a grinding operation may be performed on its upper surface to expose the upper surfaces of the second memory device 400 and the at least one semiconductor chip 500 (for example, for attaching a cooling device thereto).

[0069] refer to Figure 1 , the carrier substrate 10 and the release film 20 may be separated from the lower redistribution line structure 210. The external connection terminals 150 may be adhered to the lower redistribution line structure 210. Figure 1 , FIG. 2A to FIG. 2F , Figure 3A and Figure 3B , Figure 4A and Figure 4B as well as FIG. 5A to FIG. 5C The process shown in Figure 1 A semiconductor package 1.

[0070] Some examples of embodiments of the inventive concept are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the scope of the inventive concept. Therefore, the inventive concept should not be interpreted as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided to make this disclosure thorough and complete and to convey the scope of the invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0071] Example embodiments of the present inventive concept are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments and intermediate structures of the example embodiments. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, example embodiments of the present inventive concept should not be construed as limited to the specific shapes shown herein, but rather include deviations in shapes caused, for example, by manufacturing, unless the context clearly indicates otherwise.

[0072] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0073] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0074] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the scope of the present invention, the first element can be referred to as the second element.

[0075] The subject matter disclosed above should be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the inventive concept. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0076] CROSS-REFERENCE TO RELATED APPLICATIONS

[0077] This application claims priority to U.S. Provisional Application No. 63 / 589,597, filed on October 11, 2023, and the entire contents of the above application are incorporated herein by reference.

Claims

1. A semiconductor package, comprising: a first redistribution line structure including a first insulating layer and a first redistribution line pattern; a die on the first redistribution line structure; a first memory device on a first surface of the die; a second redistribution line structure on a second surface of the die opposite to the first surface, the second redistribution line structure comprising a second insulating layer and a second redistribution line pattern; a second memory device on the second redistribution line structure; as well as At least one semiconductor chip is on the second redistribution line structure and is electrically connected to the first memory device and the second memory device.

2. The semiconductor package according to claim 1, wherein The first memory device comprises a static RAM (SRAM), and wherein the second memory device comprises a dynamic RAM (DRAM).

3. The semiconductor package according to claim 2, wherein: The DRAM includes a stacked DRAM including at least one memory die.

4. The semiconductor package according to claim 1, wherein: The second memory device includes at least one memory die and a logic die configured to perform at least one function in addition to routing data to and from the at least one memory chip. 5 . The semiconductor package according to claim 1 , further comprising a third redistribution line structure including a third insulating layer and a third redistribution line pattern, the third redistribution line structure being between the first redistribution line structure and the second redistribution line structure.

6. The semiconductor package according to claim 5, further comprising: a connecting post between the first redistribution line structure and the third redistribution line structure; as well as An insulating layer is filled between the first redistribution line structure and the third redistribution line structure and around the connection pillar.

7. The semiconductor package according to claim 5, wherein: The third redistribution line structure includes a first redistribution line structure portion and a second redistribution line structure portion spaced apart from each other in the first direction.

8. The semiconductor package according to claim 5, wherein: The first memory device overlaps the third redistribution line structure in a first direction. 9 . The semiconductor package according to claim 1 , further comprising a molding layer surrounding the at least one semiconductor chip on the second redistribution line structure.

10. The semiconductor package according to claim 1, wherein The first memory device includes bonding pads corresponding to bonding pads on the first surface of the die.

11. A semiconductor package, comprising: a first redistribution line structure having a first portion and a second portion, the first redistribution line structure comprising a first insulating layer and a first redistribution line pattern; a die on the first redistribution line structure; a first memory device on a first surface of the die; a second redistribution line structure on a second surface of the die opposite to the first surface, the second redistribution line structure comprising a second insulating layer and a second redistribution line pattern; as well as a second memory device on an upper surface of the second redistribution line structure, The first memory device overlaps the first portion and the second portion of the first redistribution line structure in a first direction.

12. The semiconductor package according to claim 11, wherein The second memory device comprises a stacked dynamic RAM (DRAM) device including at least one memory die.

13. The semiconductor package according to claim 11, wherein The second memory device includes at least one memory die and a logic die configured to perform at least one function in addition to routing data to and from the at least one memory die.

14. The semiconductor package according to claim 11, wherein The first memory device includes a static RAM (SRAM) device including bonding pads corresponding to bonding pads on the first surface of the die.

15. A method of forming a semiconductor package, the method comprising: forming a first redistribution line structure including a first insulating layer and a first redistribution line pattern; attaching a first memory device to the first surface of the die; attaching the first surface of the die to the first redistribution line structure; forming a second redistribution line structure on a second surface of the die opposite to the first surface, the second redistribution line structure comprising a second insulating layer and a second redistribution line pattern; as well as A second memory device is attached to a second surface of the second redistribution line structure, the second surface of the second redistribution line structure being opposite to a first surface of the second redistribution line structure facing the die.

16. The method according to claim 15, further comprising: before attaching the first surface of the die to the first redistribution line structure, forming a trench in the first redistribution line structure, Wherein attaching the first surface of the die to the first redistribution line structure includes inserting the first memory device into the trench. 17 . The method of claim 15 , further comprising forming a connection stud, wherein the first redistribution line structure is on the connection stud.

18. The method of claim 15, further comprising attaching at least one semiconductor chip to the second surface of the second redistribution line structure, wherein the at least one semiconductor chip is electrically connected to the first memory device and the second memory device.

19. The method of claim 15, further comprising forming a molding layer on the second redistribution line structure.

20. The method according to claim 15, wherein: The first memory device comprises a static RAM (SRAM), and wherein the second memory device comprises a dynamic RAM (DRAM).

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