IGBT device and manufacturing method thereof
By using a positive PI photoresist layer and wet etching process in IGBT devices, the problem of high alignment difficulty of contact hole mask plate and trench gate mask plate is solved, and a high consistency Vcesat is achieved, providing an effective solution for IGBT devices below 0.2μm.
Patent Information
- Application Number
- CN202510006538.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-11
AI Technical Summary
In existing IGBT devices, it is difficult to align the contact hole mask plate and the trench gate mask plate, resulting in discrete and increase of saturation voltage drop (Vcesat).
A positive PI photoresist layer combined with a wet etching process is used to form a second groove with a wide upper and a narrow upper groove on the trench gate, and an oxide layer and a dielectric layer are formed in the second groove. Self-alignment etching is performed as a self-alignment mask layer to form contact holes to prepare a contact structure.
The contact hole mask plate is not required, which avoids the problem of alignment between the contact hole mask plate and the trench gate, and provides guarantee for obtaining a high consistency Vcesat. It is especially suitable for IGBT devices with a distance between the contact hole and the trench gate of less than 0.2 μm.
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Figure CN119815849A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor integrated circuit design and manufacture, and relates to an IGBT device and a manufacturing method thereof. Background Art
[0002] As a hybrid power device, IGBT has the characteristics of MOS structure input and bipolar structure output. Therefore, it has the advantages of high input impedance of MOSFET, low drive circuit power, simple drive, fast switching speed and low switching loss, and has the advantages of high current density, strong current handling capability and low on-saturation voltage drop of bipolar power transistor. Since the early 1980s, IGBT has been widely studied at home and abroad. At present, IGBT has broad application prospects and is widely used in many fields such as new energy vehicles, industrial frequency conversion, photovoltaics, smart grids and locomotives.
[0003] After nearly 40 years of development, IGBT has evolved from a planar type to a trench type, and the pitch (minimum repeating unit) of the cell has become smaller and smaller, and the distance from the active area contact hole to the trench gate has also become smaller and smaller, and the alignment accuracy requirements for the contact hole mask and the trench gate mask have become higher and higher. If the alignment accuracy of the contact hole mask and the trench gate mask is poor, and the distance from the contact hole to the trench gate is insufficient, the saturation voltage drop (Vcesat) in the IGBT will be discrete and increase. At present, the consistency of the distance from the contact hole to the trench gate of the mainstream IGBT is completely dependent on the alignment consistency of the contact hole mask and the trench gate mask.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an IGBT device and a manufacturing method thereof, so as to solve the problem of high difficulty in aligning the contact hole mask and the trench gate mask in the prior art.
[0006] To achieve the above object and other related objects, the present invention provides a method for manufacturing an IGBT device, comprising the following steps:
[0007] providing a substrate, the substrate comprising a first side and a second side opposite to each other;
[0008] forming a carrier storage layer in the substrate from a first surface of the substrate;
[0009] forming a body region in the substrate and located on the carrier storage layer;
[0010] Providing a trench gate mask and performing etching to form a gate trench penetrating the body region and the carrier storage layer;
[0011] forming a gate oxide layer in the gate trench and a polysilicon layer filling the gate trench to form a trench gate;
[0012] Etching the polysilicon layer to form a first groove;
[0013] forming an emitter region in the substrate and located on the body region;
[0014] Forming a positive PI photoresist layer on the first surface of the substrate, and using the trench gate mask, performing etching to pattern the positive PI photoresist layer to form an etching window, and the etching window is arranged corresponding to the first groove;
[0015] Performing wet etching based on the etching window to transform the first groove into a second groove with a top width greater than a bottom width;
[0016] removing the positive PI photoresist layer;
[0017] forming an oxide layer covering the second groove and the emitter region by a thermal oxidation process;
[0018] forming a dielectric layer covering the oxide layer, wherein the dielectric layer fills the second groove;
[0019] Etching the dielectric layer and the oxide layer to expose the emitter region;
[0020] Using the dielectric layer and the oxide layer as self-aligned mask layers, self-aligned etching is performed to form a contact hole in the emitter region;
[0021] A contact structure is formed, wherein the contact structure fills the contact hole.
[0022] Optionally, the dielectric layer includes a BPSG layer, a silicon oxide layer or a silicon nitride layer.
[0023] Optionally, a height difference between the bottom of the first groove and the top surface of the emission region is 0.3-0.6 μm.
[0024] Optionally, the contact hole passes through the emission region; and the contact structure formed in the contact hole includes one or a combination of a metal layer and a doped semiconductor layer.
[0025] Optionally, the method further comprises the following steps:
[0026] Performing a thinning process from the second surface of the substrate;
[0027] forming a collector region on the second surface of the substrate;
[0028] Performing multiple hydrogen ion implantation and annealing on the second surface of the substrate to form a buffer zone, wherein the buffer zone has a plurality of hydrogen ion doping layers with different hydrogen ion doping concentrations, and the hydrogen ion doping concentrations of the plurality of hydrogen ion doping layers gradually decrease from the second surface of the substrate toward the first surface of the substrate;
[0029] A collector electrode is formed on the surface of the collector region.
[0030] Optionally, a distance between the contact hole and the trench gate is less than 0.2 μm.
[0031] The present invention further provides an IGBT device, comprising:
[0032] substrate;
[0033] A carrier storage layer, wherein the carrier storage layer is located in the substrate;
[0034] a body region, the body region being located in the substrate and on the carrier storage layer;
[0035] an emitter region, the emitter region being located in the substrate and on the body region;
[0036] A trench gate, wherein the trench gate penetrates the body region and the carrier storage layer and comprises a gate oxide layer and a polysilicon layer;
[0037] A second groove, wherein the second groove is located above the trench gate, and a top width of the second groove is greater than a bottom width;
[0038] an oxide layer, wherein the oxide layer covers an inner wall of the second groove;
[0039] a dielectric layer, wherein the dielectric layer fills the second groove;
[0040] a contact hole, wherein the contact hole is located in the emitter region;
[0041] A contact structure fills the contact hole.
[0042] Optionally, the dielectric layer includes a BPSG layer, a silicon oxide layer or a silicon nitride layer.
[0043] Optionally, a distance between the contact structure and the trench gate is less than 0.2 μm.
[0044] Optionally, the contact structure includes one or a combination of a metal layer and a doped semiconductor layer.
[0045] As described above, the IGBT device and the manufacturing method thereof of the present invention use a positive PI photoresist layer combined with a wet etching process to form a second groove that is wide at the top and narrow at the bottom on the trench gate, and form an oxide layer and a dielectric layer in the second groove, and perform self-aligned etching based on the oxide layer and the dielectric layer as a self-aligned mask layer to form a contact hole in the emitter region to prepare a contact structure. The self-aligned etching process of the present invention does not require a contact hole mask, thereby avoiding the problem of aligning the contact hole mask with the trench gate, providing a guarantee for obtaining a highly consistent Vcesat, and is particularly suitable for IGBT devices with a distance between the contact hole and the trench gate of less than 0.2 μm. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 Shown is a schematic diagram of the process flow of preparing an IGBT device in an embodiment of the present invention.
[0047] Figure 2 to Figure 11 It shows a schematic diagram of the structure presented in each step of the process of preparing an IGBT device in an embodiment of the present invention.
[0048] Description of Reference Numerals
[0049] 100 Substrate
[0050] 200 Carrier storage layer
[0051] 300 Body Area
[0052] 400 Trench Gate
[0053] 401 Gate Trench
[0054] 402 Gate Oxide Layer
[0055] 403 Polysilicon layer
[0056] 501 First Groove
[0057] 502 Second groove
[0058] 600 Launch Area
[0059] 700 Positive PI photoresist layer
[0060] 701 Etching Window
[0061] 800 Oxide layer
[0062] 900 Dielectric layer
[0063] 110 Contact hole
[0064] 120 Contact structure
[0065] 121 Doped semiconductor layer
[0066] 122 W Metal contact area
[0067] 123 AlCu metal contact area
[0068] 130 collector area
[0069] 140 Buffer
[0070] 141 First N-type doping peak
[0071] 142 Second N-type doping peak
[0072] 143 The third N-type doping peak
[0073] 144 Fourth N-type doping peak
[0074] 150 Collector DETAILED DESCRIPTION
[0075] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0076] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.
[0077] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.
[0078] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0079] like Figure 1 This embodiment provides a method for manufacturing an IGBT device. In this embodiment, a positive PI (polyimide) photoresist layer is combined with a wet etching process to form a second groove that is wide at the top and narrow at the bottom on the trench gate, and an oxide layer and a dielectric layer are formed in the second groove. Self-aligned etching is performed based on the oxide layer and the dielectric layer as self-aligned mask layers to form a contact hole in the emitter region to prepare a contact structure.
[0080] This embodiment does not require a contact hole mask, thereby avoiding the problem of alignment between the contact hole mask and the trench gate, providing a guarantee for obtaining a highly consistent Vcesat, and is particularly suitable for IGBT devices with a distance between the contact hole and the trench gate of less than 0.2 μm.
[0081] The following is in conjunction with the instruction manual Figure 2 to Figure 11 , the IGBT device and its preparation are described.
[0082] First, see Figure 1 and Figure 2 , perform step S1, provide a substrate 100, and the substrate 100 includes a first surface and a second surface opposite to each other.
[0083] Specifically, the substrate 100 may be a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a IIIV compound substrate, etc. The substrate 100 may be a pre-doped substrate. In this embodiment, the substrate 100 is an N-type doped silicon substrate, and the doping concentration and substrate thickness may be selected according to the withstand voltage requirement of the IGBT device.
[0084] Next, see Figure 1 and Figure 2 , executing step S2, forming a carrier storage layer 200 located in the substrate 100 from the first surface of the substrate 100.
[0085] Specifically, the N-type carrier storage layer 200 located in the substrate 100 may be formed from the first surface of the substrate 100 by implanting phosphorus ions.
[0086] Next, see Figure 1 and Figure 2 , executing step S3 , forming a body region 300 located on the carrier storage layer 200 in the substrate 100 .
[0087] Specifically, the P-type body region 300 located in the carrier storage layer 200 may be formed from the first surface of the substrate 100 by, for example, implantation of boron ions.
[0088] Next, see Figure 1 and Figure 2 , perform step S4, provide a trench gate mask (not shown), and perform etching to form a gate trench 401 that penetrates the body region 300 and the carrier storage layer 200.
[0089] Specifically, photolithography and etching are performed based on the trench gate mask to form the gate trench 401 penetrating the body region 300 and the carrier storage layer 200. The size of the gate trench 401 can be selected from a suitable trench gate mask as required, and the specific size is not limited here.
[0090] Next, see Figure 1 and Figure 3 , executing step S5 , forming a gate oxide layer 402 in the gate trench 401 and a polysilicon layer 403 filling the gate trench 401 to form a trench gate 400 .
[0091] Specifically, a thermal oxidation reaction may be performed through a furnace process to form the gate oxide layer 402 in the gate trench 401 , and then the polysilicon layer 403 filling the gate trench 401 may be formed through a deposition process.
[0092] Next, see Figure 1 and Figure 4 , perform step S6 to etch the polysilicon layer 403 to form a first groove 501.
[0093] Specifically, Figure 4 By etching back the polysilicon layer 403, part of the polysilicon layer 403 can be removed to expose the gate oxide layer 402, and due to the different etching selectivity between the gate oxide layer 402 and the polysilicon layer 403, part of the polysilicon layer 403 located in the gate trench 401 can be etched back to form the first groove 501, so that the top surface of the remaining polysilicon layer 403 is lower than the top surface of the body region 300. The gate oxide layer 402 located on the surface of the body region 300 can be removed by etching. The etching back depth of the first groove 501 can be 0.3-0.6 μm, such as 0.3 μm, 0.5 μm, 0.6 μm, etc.
[0094] Next, see Figure 1 and Figure 5 , executing step S7 to form an emitter region 600 located on the body region 300 in the substrate 100 .
[0095] Specifically, the emitter region 600 with N-type doping can be formed in the body region 300 by ion implantation and diffusion processes. There is no limitation on doping ions and doping concentrations herein.
[0096] Next, see Figure 1 and Figure 6 , perform step S8, form a positive PI photoresist layer 700 on the first surface of the substrate 100, and use the trench gate mask to perform etching to pattern the positive PI photoresist layer 700 to form an etching window 701, and the etching window 701 is set corresponding to the first groove 501.
[0097] Specifically, in this embodiment, a positive PI photoresist layer 700 is formed on the first surface of the substrate 100, that is, on the upper surface of the emitter region 600, and the positive PI photoresist layer 700 is exposed in combination with the trench gate mask when preparing the gate trench 401, and then developed to form the etching window 701. Since the mask used in this step is the trench gate mask and is a positive photoresist, the prepared etching window 701 can be arranged corresponding to the first groove 501, that is, they have the same central axis in the vertical direction. The selection of PI photoresist is to prepare for the subsequent wet etching to form the second groove 502.
[0098] Next, see Figure 1 and Figure 7 , execute step S9, perform wet etching based on the etching window 701, and transform the first groove 501 into a second groove 502 with a top width greater than a bottom width.
[0099] Specifically, the second groove 502 having a top width greater than a bottom width can effectively control the distance between the contact hole 110 and the polysilicon layer 403 by exceeding the width of the trench gate 400 .
[0100] Next, see Figure 1 and Figure 8 , perform step S10 to remove the positive PI photoresist layer 700. The removal method may be an ashing method.
[0101] Next, see Figure 1 and Figure 8 , perform step S11, use a thermal oxidation process to form an oxide layer 800 covering the second groove 502 and the emitter region 600, and perform step S12 to form a dielectric layer 900 covering the oxide layer 800, and the dielectric layer 900 fills the second groove 502.
[0102] Specifically, due to the difference in material between the body region 300 and the polysilicon layer 403, and the top surface of the polysilicon layer 403 is lower than the body region 300, during the thermal oxidation process, the thickness of the oxide layer 800 located on the surface of the body region 300 is greater than the thickness of the oxide layer 800 located on the surface of the polysilicon layer 403. The thickness of the oxide layer 800 located on the surface of the body region 300 may be like The thickness of the oxide layer 800 located on the surface of the polysilicon layer 403 may be The following, such as wait.
[0103] After the thermal oxidation process, the second groove 502 may be filled with the dielectric layer 900, and the dielectric layer 900 may include a BPSG (boron phospho-silicate glass) layer, a silicon oxide layer, or a silicon nitride layer. In this embodiment, the thickness of the BPSG layer may be The densification temperature of BPSG may be 900° C. to 950° C., and the time may be 20 seconds to 1 minute. Of course, the dielectric layer 900 may also include a silicon oxide layer or a silicon nitride layer.
[0104] The oxide layer 800 and the dielectric layer 900 that fill the second groove 502 can be used as a mask for subsequent self-aligned etching to protect the polysilicon layer 403 from being etched.
[0105] Next, see Figure 1 and Fig. 9 , execute step S13, etch the dielectric layer 900 and the oxide layer 800 to expose the emitter region 600; and execute step S14, use the dielectric layer 900 and the oxide layer 800 as self-aligned mask layers to perform self-aligned etching to form a contact hole 110 in the emitter region 600; and execute step S15 to form a contact structure 120, and the contact structure 120 fills the contact hole 110.
[0106] The contact structure 120 formed in the contact hole 110 includes one or a combination of a metal layer and a doped semiconductor layer 121 .
[0107] In this embodiment, refer to Fig. 9 and Fig.10 The contact hole 110 penetrates the emitter region 600, and the contact structure 120 preferably has a P-type doped semiconductor layer 121 at the bottom and a metal layer composed of a W metal contact region 122 and an AlCu metal contact region 123 at the top to reduce contact resistance. The type of the contact structure 120 is not limited thereto, and may also be a metal contact structure 120, etc.
[0108] The distance between the contact structure 120 and the trench gate 400 may be less than 0.2 μm, that is, the minimum distance between the edge of the contact structure 120 and the edge of the trench gate 400 in the lateral direction may be less than 0.2 μm, such as 0.2 μm, 0.15 μm, etc.
[0109] Next, see Fig.11 , further comprising the following steps:
[0110] Performing a thinning process on the second surface of the substrate 100;
[0111] forming a collector region 130 on the second surface of the substrate 100;
[0112] Performing multiple hydrogen ion implantation and annealing on the second surface of the substrate 100 to form a buffer zone 140, wherein the buffer zone 140 has a plurality of hydrogen ion doping layers with different hydrogen ion doping concentrations, and the hydrogen ion doping concentrations of the plurality of hydrogen ion doping layers gradually decrease from the second surface of the substrate 100 to the first surface of the substrate 100;
[0113] A collector electrode 150 is formed on the surface of the collector region 130 .
[0114] Specifically, the thickness of the substrate 100 depends on the withstand voltage requirement of the IGBT device. The collector region 130 can be prepared by, for example, boron ion implantation, with an implantation energy of 20 to 60 KeV and an implantation dose of 1e12 to 1e14 cm -2 , and then the implanted boron ions are activated by laser annealing equipment to form the P-type doped collector region 130. Next, hydrogen can be implanted and annealed from the second surface of the substrate 100 to form the hydrogen ion doping layers with multiple different hydrogen ion doping concentrations, that is, to form the buffer region 140, and the hydrogen ion doping concentrations of the multiple hydrogen ion doping layers gradually decrease from the second surface of the substrate 100 to the first surface of the substrate 100. Fig.11 , 141 represents a first N-type doping peak formed by hydrogen injection, 142 represents a second N-type doping peak formed by hydrogen injection, 143 represents a third N-type doping peak formed by hydrogen injection, and 144 represents a fourth N-type doping peak formed by hydrogen injection. The doping concentrations of the first N-type doping peak 141, the second N-type doping peak 142, the third N-type doping peak 143, and the fourth N-type doping peak 144 gradually increase. Finally, a metal such as Al / Ti / Ni / Ag is deposited to form the collector 150.
[0115] See also Figure 2 to Figure 11 This embodiment further provides an IGBT device, the IGBT device comprising:
[0116] Substrate 100;
[0117] A carrier storage layer 200, wherein the carrier storage layer 200 is located in the substrate 100;
[0118] a body region 300 , wherein the body region 300 is located in the substrate 100 and on the carrier storage layer 200 ;
[0119] an emitter region 600 , wherein the emitter region 600 is located in the substrate 100 and on the body region 300 ;
[0120] A trench gate 400 , wherein the trench gate 400 penetrates the body region 300 and the carrier storage layer 200 , and includes a gate oxide layer 402 and a polysilicon layer 403 ;
[0121] A second groove 502, wherein the second groove 502 is located above the trench gate 400, and a top width of the second groove 502 is greater than a bottom width;
[0122] an oxide layer 800, wherein the oxide layer 800 covers an inner wall of the second groove 502;
[0123] A dielectric layer 900 , wherein the dielectric layer 900 fills the second groove 502 ;
[0124] A contact hole 110, wherein the contact hole 110 is located in the emitter region 600;
[0125] A contact structure 120 fills the contact hole 110 .
[0126] As an example, the dielectric layer 900 includes a BPSG layer, a silicon oxide layer, or a silicon nitride layer.
[0127] As an example, the distance between the contact structure 120 and the trench gate 400 is less than 0.2 μm.
[0128] As an example, the contact structure 120 includes one or a combination of a metal layer and a doped semiconductor layer 121 .
[0129] The specific preparation and structure of the IGBT device can refer to the above-mentioned preparation method of the IGBT device, which will not be described in detail here. Of course, the preparation of the IGBT device is not limited to the above-mentioned preparation method.
[0130] In summary, the IGBT device and its manufacturing method of the present invention use a positive PI photoresist layer combined with a wet etching process to form a second groove that is wide at the top and narrow at the bottom on the trench gate, and form an oxide layer and a dielectric layer in the second groove, and perform self-aligned etching based on the oxide layer and the dielectric layer as a self-aligned mask layer to form a contact hole in the emitter region to prepare a contact structure. The self-aligned etching process of the present invention does not require a contact hole mask, thereby avoiding the problem of aligning the contact hole mask with the trench gate, providing a guarantee for obtaining a highly consistent Vcesat, and is particularly suitable for IGBT devices with a distance between the contact hole and the trench gate of less than 0.2μm.
[0131] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing an IGBT device, characterized in that: The following steps are involved: providing a substrate, the substrate comprising a first side and a second side opposite to each other; forming a carrier storage layer in the substrate from a first surface of the substrate; forming a body region in the substrate and located on the carrier storage layer; Providing a trench gate mask and performing etching to form a gate trench penetrating the body region and the carrier storage layer; forming a gate oxide layer in the gate trench and a polysilicon layer filling the gate trench to form a trench gate; Etching the polysilicon layer to form a first groove; forming an emitter region in the substrate and located on the body region; Forming a positive PI photoresist layer on the first surface of the substrate, and using the trench gate mask, performing etching to pattern the positive PI photoresist layer to form an etching window, and the etching window is arranged corresponding to the first groove; Performing wet etching based on the etching window to transform the first groove into a second groove with a top width greater than a bottom width; removing the positive PI photoresist layer; forming an oxide layer covering the second groove and the emitter region by a thermal oxidation process; forming a dielectric layer covering the oxide layer, wherein the dielectric layer fills the second groove; Etching the dielectric layer and the oxide layer to expose the emitter region; Using the dielectric layer and the oxide layer as self-aligned mask layers, self-aligned etching is performed to form a contact hole in the emitter region; A contact structure is formed, wherein the contact structure fills the contact hole.
2. The method for manufacturing an IGBT device according to claim 1, characterized in that: The dielectric layer includes a BPSG layer, a silicon oxide layer or a silicon nitride layer.
3. The method for manufacturing an IGBT device according to claim 1, characterized in that: A height difference between the bottom of the first groove and the top surface of the emission region is 0.3 μm to 0.6 μm.
4. The method for manufacturing an IGBT device according to claim 1, characterized in that: The contact hole penetrates the emitter region; The contact structure formed in the contact hole includes one or a combination of a metal layer and a doped semiconductor layer.
5. The method for manufacturing an IGBT device according to claim 1, characterized in that: The following steps are also included: Performing a thinning process from the second surface of the substrate; forming a collector region on the second surface of the substrate; Performing multiple hydrogen ion implantation and annealing on the second surface of the substrate to form a buffer zone, wherein the buffer zone has a plurality of hydrogen ion doping layers with different hydrogen ion doping concentrations, and the hydrogen ion doping concentrations of the plurality of hydrogen ion doping layers gradually decrease from the second surface of the substrate toward the first surface of the substrate; A collector electrode is formed on the surface of the collector region.
6. The method for manufacturing an IGBT device according to claim 1, characterized in that: The distance between the contact hole and the trench gate is less than 0.2 μm.
7. An IGBT device, characterized in that: The IGBT device comprises: substrate; A carrier storage layer, wherein the carrier storage layer is located in the substrate; a body region, the body region being located in the substrate and on the carrier storage layer; an emitter region, the emitter region being located in the substrate and on the body region; A trench gate, wherein the trench gate penetrates the body region and the carrier storage layer and comprises a gate oxide layer and a polysilicon layer; A second groove, wherein the second groove is located above the trench gate, and a top width of the second groove is greater than a bottom width; an oxide layer, wherein the oxide layer covers an inner wall of the second groove; a dielectric layer, wherein the dielectric layer fills the second groove; a contact hole, wherein the contact hole is located in the emitter region; A contact structure fills the contact hole.
8. The IGBT device according to claim 7, characterized in that: The dielectric layer includes a BPSG layer, a silicon oxide layer or a silicon nitride layer.
9. The IGBT device according to claim 7, characterized in that: The distance between the contact structure and the trench gate is less than 0.2 μm.
10. The IGBT device according to claim 7, characterized in that: The contact structure includes one or a combination of a metal layer and a doped semiconductor layer.