Power semiconductor device structure and manufacturing method thereof

Abstract

The invention provides a power semiconductor device structure and a manufacturing method thereof, and the method comprises the steps: forming a side wall structure on the side wall of the top of a polycrystalline silicon layer, limiting a self-alignment window through the side wall structure, and limiting the transverse distance between a source electrode contact hole and a groove through controlling the transverse width of the side wall structure for a small-cell power semiconductor device. Especially for an IGBT with the distance between a source electrode contact hole and trench gate polycrystalline silicon smaller than 0.2 micrometer, the precision of the distance between the source electrode contact hole and a polycrystalline layer can be greatly improved, the requirement for alignment precision of a subsequent source electrode contact hole mask and a trench gate mask is lowered, and then the consistency of in-wafer and inter-wafer saturation voltage drop of IGBT wafers is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a power semiconductor device structure and a manufacturing method thereof. Background Art

[0002] As a hybrid power device, the insulated gate bipolar transistor (IGBT) has the characteristics of MOS structure input and bipolar structure output. Therefore, it has the advantages of high input impedance, low drive circuit power, simple drive, fast switching speed and low switching loss of MOSFET, and has the advantages of high current density, strong current handling capability and low on-saturation voltage drop of bipolar power transistor. Since the early 1980s, IGBT has been widely studied at home and abroad. At present, IGBT has broad application prospects and is widely used in new energy vehicles, industrial frequency conversion, photovoltaics, smart grids and locomotives. In addition, the Chinese IGBT market accounts for about one-third of the global IGBT market.

[0003] After nearly four decades of development, IGBT has evolved from a planar type to a trench type, and the pitch (minimum repeating unit) of the cell is getting smaller and smaller, and the distance from the active area contact hole to the trench gate is also getting smaller and smaller, and the alignment accuracy requirements of the contact hole mask and the trench gate mask are getting higher and higher. If the alignment accuracy of the contact hole mask and the trench gate mask is poor, and the distance from the contact hole to the trench gate is insufficient, the saturation voltage drop (Vcesat) in the IGBT wafer will be discrete and increase. The consistency of the distance from the contact hole to the trench gate depends entirely on the alignment consistency of the mask and the trench gate mask, and the mask and the trench gate mask need to be strictly aligned, which has high requirements for processes and equipment, which will lead to an increase in production costs and it is difficult to guarantee product yield.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power semiconductor device structure and a manufacturing method thereof, so as to solve the problem of poor consistency of the distance from the source contact hole to the trench gate in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for manufacturing a power semiconductor device structure, the manufacturing method comprising: providing a semiconductor substrate, forming a hard mask layer on the front side of the semiconductor substrate, the hard mask layer having an etching window, forming a plurality of spaced-apart gate trenches in the semiconductor substrate based on the etching window, and a source region is formed between adjacent gate trenches; forming a gate oxide layer at the bottom and sidewalls of each gate trench, forming a polysilicon layer in the gate trench and in the etching window; removing the hard mask layer to expose the top sidewall of the polysilicon layer; forming a sidewall structure on the top sidewall of the polysilicon layer, the sidewall structure shielding a portion of the source region, and defining a self-aligned window exposing the surface of the source region between the sidewall structures; forming a first etching resist in the self-aligned window The invention relates to a method for producing a semiconductor substrate having a gate electrode and a semiconductor material, wherein the gate electrode is provided with a first etch barrier layer and a second etch barrier layer. The method comprises the following steps: removing a sidewall structure and a polysilicon layer located on the surface of the first etch barrier layer, exposing a source region between the first etch barrier layer and the polysilicon layer; removing a portion of the polysilicon in the gate trench by etching the barrier layer to form a first groove, and removing a portion of the exposed source region to form a second groove; removing the first etch barrier layer to expose the surface of the source region; depositing a second etch barrier layer on the source region, the second etch barrier layer at least filling the first groove and the second groove, removing the second etch barrier layer on the surface of the source region until the surface of the source region is exposed; using the remaining second etch barrier layer as a self-aligned mask, etching the source region to form a source contact hole in the source region; forming a contact metal layer in the source contact hole and forming a metal layer on the front side of the semiconductor substrate.

[0007] Optionally, the lateral distance between the source contact hole and the gate trench is limited by controlling the lateral width of the spacer structure.

[0008] Optionally, a lateral distance between the source contact hole and the gate trench is less than 0.2 microns.

[0009] Optionally, the material of the sidewall structure includes one or a composite layer composed of two or more of nitride, oxide and oxynitride.

[0010] Optionally, a portion of the source region is removed by a wet etching process or a dry etching process to form a second groove, the top size of the second groove is larger than its bottom size, and the top size of the second etch stop layer subsequently filled into the second groove is larger than its bottom size.

[0011] Optionally, a top dimension of the source contact hole is larger than a bottom dimension thereof, and an inclination angle of a sidewall of the source contact hole is 80° to 85°.

[0012] Optionally, forming the first etch stop layer in the self-aligned window includes: etching the source region to form a receiving groove on the surface of the source region, and forming the first etch stop layer in the receiving groove.

[0013] Optionally, the first etch stop layer has a thickness of 0.2 micrometers to 0.5 micrometers; and / or the first etch stop layer includes organic matter.

[0014] Optionally, the preparation method further comprises the step of: performing ion implantation on the semiconductor substrate in sequence to form a carrier storage region, a body region and a source region in the semiconductor substrate.

[0015] Optionally, the depth of the first groove and the second groove is less than the depth of the source region, and the depth of the first groove and the second groove is 0.5 micrometer to 1 micrometer.

[0016] Optionally, after forming the front metal, the method further includes the steps of: performing ion implantation on the back side of the semiconductor substrate to form a collector region; performing ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is arranged adjacent to the collector region; and forming a back metal layer on the back side of the semiconductor substrate.

[0017] The present invention further provides a power semiconductor device structure, which is manufactured by the method for manufacturing a power semiconductor device structure according to any one of claims 1 to 11.

[0018] The present invention further provides a power semiconductor device structure, which is manufactured using the method for manufacturing a power semiconductor device structure according to any one of the above schemes.

[0019] As described above, the power semiconductor device structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0020] The present invention forms a sidewall structure on the top sidewall of the polysilicon layer, and defines a self-alignment window through the sidewall structure. For small-cell power semiconductor devices, the lateral spacing between the source contact hole and the polysilicon layer in the trench is limited by controlling the lateral width of the sidewall structure, especially for an IGBT in which the distance between the source contact hole and the trench gate polysilicon is less than 0.2 microns. The accuracy of the distance between the source contact hole and the polysilicon layer can be greatly improved, and the subsequent alignment accuracy requirement of the source contact hole mask and the trench gate mask can be reduced, thereby greatly improving the consistency of the saturation voltage drop (Vcesat) within and between IGBT wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0022] Figure 1 to Figure 14 The structure diagram shown is presented in each step of the method for manufacturing the power semiconductor device structure according to an embodiment of the present invention, wherein: Fig.14 Shown is a schematic structural diagram of a power semiconductor device structure according to an embodiment of the present invention.

[0023] Component number description

[0024] 1 Semiconductor substrate

[0025] 2 Carrier storage area

[0026] 3 Body Regions

[0027] 4 Source area

[0028] 5 Hard mask layer

[0029] 6 Gate trench

[0030] 7 Gate Oxide

[0031] 8 Polysilicon layer

[0032] 9 Side wall structure

[0033] 9a Self-aligning window

[0034] 10. First Etch Stop Layer

[0035] 11 First groove

[0036] 12 Second groove

[0037] 111 Blank Area

[0038] 13. Second etching stop layer

[0039] 14 Source contact hole

[0040] 15 Contact metal layer

[0041] 16 Front metal layer

[0042] 17 Hydrogen ion doped region

[0043] 18 Collector region

[0044] 19 Back metal layer DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0047] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0048] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0049] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0050] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0051] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] like Figure 1 to Figure 14 As shown, this embodiment provides a method for manufacturing a power semiconductor device structure. The power semiconductor device may be, for example, an IGBT device. The manufacturing method includes the following steps:

[0053] like Figure 1 As shown, firstly, step 1) is performed to provide a semiconductor substrate 1, and a hard mask layer 5 is formed on the semiconductor substrate. The hard mask layer 5 has an etching window. Based on the etching window, a plurality of spaced-apart gate trenches 6 are formed in the semiconductor substrate 1, and source regions 4 are formed between adjacent gate trenches 6.

[0054] In one embodiment, the semiconductor substrate 1 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc. The semiconductor substrate 1 may be doped, and its doping concentration and thickness may be set according to the withstand voltage requirements of the IGBT device. In this embodiment, the semiconductor substrate 1 is a silicon substrate, and its doping type is N-type doping.

[0055] In one embodiment, the method further includes sequentially performing ion implantation on the semiconductor substrate 1 to form a carrier storage region 2 , a body region 3 and a source region 4 in the semiconductor substrate 1 .

[0056] Specifically, the carrier storage area 2 is injected through a mask or the carrier storage area 2 is generally injected without a mask. The injected ions may be phosphorus and the injection dose may be 1e12 cm -2 ~5e13cm -2 The implantation energy can be 80KeV~2MeV, the push temperature is 1050℃~1250℃, the time is 30min~300min, and then the body region 3 is implanted. The implanted ions can be boron, and the implantation dose is 4e13cm -2 ~1e14cm -2 The injection energy is 60keV~200keV, the push temperature can be 1050℃~1250℃, the time is 10min~120min, and then the source region is injected through the mask. The injected ions can be arsenic and the injection dose can be 5e15cm -2 ~2e16cm -2 The injection energy can be 60keV~600keV, the advancement temperature can be 900℃~1000℃, and the time can be 30min~120min.

[0057] Afterwards, a hard mask layer 5 is deposited, and the thickness of the mask layer is preferably 3000 angstroms to 8000 angstroms. An etching window is formed in the hard mask layer 5 by a photolithography and etching process, and then a plurality of gate trenches 6 arranged at intervals are etched in the semiconductor substrate 1 through the etching window. The depth of the gate trench 6 can be 2 microns to 6 microns. The hard mask layer 5 can be, for example, silicon dioxide, silicon nitride, silicon oxynitride, a carbon-containing dielectric material, or a stack of the above materials.

[0058] like Figure 2 As shown, step 2) is then performed to form a gate oxide layer 7 at the bottom and sidewall of each gate trench 6, and a polysilicon layer 8 is formed in the gate trench 6 and in the etching window.

[0059] like Figure 2 As shown, firstly, a gate oxide layer 7 can be formed at the bottom and sidewalls of the gate trench 6 by thermal growth. The thickness of the gate oxide layer 7 can be 1000 angstroms to 1500 angstroms. Then, a polysilicon layer 8 is deposited, and the polysilicon layer 8 above the surface of the hard mask layer 5 is removed by etching back.

[0060] like Figure 3 As shown, step 3) is then performed to remove the hard mask layer 5 to expose the top sidewall of the polysilicon layer 8.

[0061] In one embodiment, the hard mask layer 5 may be removed by a wet etching process.

[0062] It should be noted that the carrier storage region 2 , the body region 3 and the source region 4 are prepared after the hard mask layer 5 is removed, and are not limited to the examples listed above.

[0063] like Figure 4 As shown, step 4 is then performed to form a sidewall structure 9 on the top sidewall of the polysilicon layer 8. The sidewall structure 9 shields part of the source region 4. The sidewall structures 9 define a self-aligned window 9a that exposes the surface of the source region 4.

[0064] In one embodiment, the sidewall structure 9 is preferably a material having a higher etching selectivity ratio with the source region 4, and its material may include a composite layer composed of one or more of nitride, oxide and oxynitride, wherein the nitride may be, for example, silicon nitride, the oxide may be, for example, silicon oxide, and the oxynitride may be, for example, silicon oxynitride. In this embodiment, the sidewall structure 9 is made of silicon nitride, and the thickness of the silicon nitride is 3000 angstroms to 10000 angstroms. Then, the silicon nitride is etched through the sidewall manufacturing process, and finally the silicon nitride on the top sidewall of the polysilicon layer 8 is retained to form the silicon nitride sidewall structure 9.

[0065] In one embodiment, the lateral spacing between the source contact hole 14 and the gate trench 6 is limited by controlling the lateral width of the sidewall structure 9. For example, the lateral width of the sidewall structure 9 can be set to vary between 0.05 microns and 5 microns according to the requirement of the lateral spacing between the source contact hole 14 and the gate trench 6, thereby ultimately limiting the lateral spacing between the source contact hole 14 and the gate trench 6.

[0066] In a preferred example, the lateral distance between the source contact hole 14 and the gate trench 6 can be controlled to be less than 0.2 micrometers by the lateral width of the spacer structure 9 to meet the requirements of small cell power devices.

[0067] like Figure 5 As shown, step 5) is then performed to form a first etching stopper layer 10 in the self-aligned window 9a.

[0068] In one embodiment, forming the first etch stop layer 10 in the self-aligned window 9 a includes: etching the source region 4 to form a receiving groove on the surface of the source region 4 , and forming the first etch stop layer 10 in the receiving groove.

[0069] In one embodiment, the thickness of the first etch stop layer 10 is 0.2 microns to 0.5 microns. The first etch stop layer 10 is formed in the receiving groove by a spin coating process. The first etch stop layer 10 includes organic matter, such as photoresist, epoxy resin, etc.

[0070] By first forming a receiving groove on the surface of the source region 4 and then spin coating the first etch stop layer 10 in the receiving groove, the stability of the first etch stop layer 10 can be greatly improved. For example, the damage to the first etch stop layer 10 caused by the subsequent removal of the polysilicon layer 8 and the side wall structure 9 can be greatly reduced, thereby improving its accuracy as a mask.

[0071] like Figure 6 As shown, step 6 is then performed to remove the sidewall structure 9 and the polysilicon layer 8 located on the surface of the first etch stop layer 10 to expose the source region 4 between the first etch stop layer 10 and the polysilicon layer 8 .

[0072] In one embodiment, the spacer structure 9 may be removed by a wet process first, and then the polysilicon layer 8 on the first etch stop layer 10 may be removed by a chemical mechanical polishing (CMP) process.

[0073] In another embodiment, the polysilicon layer 8 may be first etched through an etching process to make the height of the polysilicon layer 8 flush with the surface of the first etch barrier layer 10 or slightly higher than the surface of the first etch barrier layer 10 or slightly lower than the surface of the first etch barrier layer 10, and then the sidewall structure 9 may be removed through a wet etching process.

[0074] like Figure 7 As shown, step 7 is then performed to remove a portion of the polysilicon in the gate trench 6 based on the barrier layer etching to form a first groove 11 , and to remove a portion of the exposed source region 4 to form a second groove 12 .

[0075] In one embodiment, Figure 7 As shown, a portion of the source region 4 is removed by a dry etching process to form a second groove 12, the top size of the second groove 12 is larger than its bottom size, and the top size of the second etch stop layer 13 subsequently filled into the second groove 12 is larger than its bottom size. For example, the second groove 12 can be an inverted triangle formed by the area sandwiched by the gate oxide layer 7 and the source region 4.

[0076] In one embodiment, the depth of the first groove 11 and the second groove 12 is less than the depth of the source region 4 , and the depth of the first groove 11 and the second groove 12 is 0.5 micrometer to 1 micrometer.

[0077] In another embodiment, Figure 8As shown, the first groove 11 and the second groove 12 are formed simultaneously by a wet etching process, and at the same time, the gate oxide layer 7 between the first groove 11 and the second groove 12 is also removed, so that the first groove 11 and the second groove 12 are connected to form a blank area 111.

[0078] like Fig. 9 As shown, step 8 is then performed to remove the first etching stop layer 10 to expose the surface of the source region 4.

[0079] In one embodiment, the first etch stopper layer 10 may be removed by a dry process or a wet process.

[0080] like Figure 10-11 As shown, step 9 is then performed to deposit a second etch stop layer 13 on the source region 4, the second etch stop layer 13 at least filling the first groove 11 and the second groove 12, and remove the second etch stop layer 13 on the surface of the source region 4 until the surface of the source region 4 is exposed.

[0081] In one embodiment, Fig.10 As shown, a BPSG layer (boron phospho-silicate glass) is deposited on the source region 4 by a deposition process as the second etching stop layer 13, and the thickness of the BPSG layer can be 0.8 microns to 1.5 microns.

[0082] In one embodiment, Fig.10 As shown, the top size of the second etch stopper layer 13 filled into the second groove 12 is larger than the bottom size thereof. For example, the second etch stopper layer 13 in the second groove 12 may be in an inverted triangle shape.

[0083] In one embodiment, Fig.11 As shown, the BPSG layer and the gate oxide layer 7 are etched by dry etching until the surface of the source region 4 is exposed.

[0084] like Fig.12 As shown, step 10 is then performed to etch the source region 4 using the remaining second etch stop layer 13 as a self-aligned mask to form a source contact hole 14 in the source region 4 , wherein the source contact hole 14 extends into the body region 3 .

[0085] In one embodiment, the top dimension of the source contact hole 14 is larger than the bottom dimension thereof, and the sidewall of the source contact hole 14 has an inclination angle of 80° to 85°. Preferably, the source contact hole 14 may be in an inverted trapezoidal shape. The inverted triangular self-aligned mask and the inverted trapezoidal source contact hole 14 may allow the sidewall of the source contact hole 14 to retain a source region 4 of a certain lateral width, and the source contact hole 14 may contact the four peripheral sides of the source region 4 at the same time, thereby effectively improving the contact between the source contact hole 14 and the source region 4 and reducing the contact resistance, such as Fig.12 shown.

[0086] like Fig.13 As shown, step 11 is then performed to form a contact metal layer 15 in the source contact hole 14 and a front metal layer 16 on the semiconductor substrate.

[0087] In one embodiment, Ti / TiN / W is formed in the source contact hole 14 as the contact metal layer 15 , and then an AlCu alloy layer is formed on the semiconductor substrate as the front metal layer 16 .

[0088] like Fig.14 As shown, step 12) is finally performed, including: ion implantation on the back side of the semiconductor substrate to form a collector region 18; ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region 17, wherein the hydrogen ion doped region 17 is arranged adjacent to the collector region 18; and a back metal layer 19 is formed on the back side of the semiconductor substrate.

[0089] In one embodiment, the semiconductor substrate is first turned over and thinned to a certain thickness, the thickness of which depends on the withstand voltage requirement of the power device, and then a boron ion implantation is performed with an implantation energy of 60KeV to 20KeV and an implantation dose of 3e12cm -2 ~1e14cm -2 , forming a P-type collector region 18, and then using laser annealing equipment to activate the injected boron ions; then secondary hydrogen injection and annealing are performed from the back side of the semiconductor substrate to form a hydrogen ion doped region 17, and finally a back metal layer 19 is formed on the back side of the semiconductor substrate, and the back metal layer 19 can be Al / Ti / Ni / Ag.

[0090] like Fig.14 As shown, this embodiment further provides a power semiconductor device structure, and the power semiconductor device structure is manufactured using the manufacturing method of the power semiconductor device structure of the above embodiment.

[0091] It should be noted that, in some embodiments, there are multiple gate trenches 6 and source contact holes 14. Through the manufacturing method of the above embodiment, it can be ensured that the multiple source contact holes 14 and the polysilicon layer 8 in the corresponding gate trenches 6 have basically the same spacing, thereby greatly improving the consistency of the saturation voltage drop (Vcesat) within and between IGBT wafers.

[0092] As described above, the power semiconductor device structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0093] The present invention forms a sidewall structure 9 on the top sidewall of the polysilicon layer 8, and defines a self-aligned window 9a through the sidewall structure 9. For small-cell power semiconductor devices, the lateral spacing between the source contact hole 14 and the polysilicon layer 8 in the gate trench 6 is limited by controlling the lateral width of the sidewall structure 9, especially for IGBTs in which the distance between the source contact hole 14 and the gate polysilicon of the trench 6 is less than 0.2 microns. The accuracy of the distance between the source contact hole 14 and the polysilicon layer can be greatly improved, and the alignment accuracy requirement of the subsequent contact hole mask and the gate mask of the trench 6 can be reduced, thereby greatly improving the consistency of the saturation voltage drop (Vcesat) within and between IGBT wafers.

[0094] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a power semiconductor device structure, characterized in that: The manufacturing method comprises: A semiconductor substrate is provided, a hard mask layer is formed on the front surface of the semiconductor substrate, the hard mask layer has an etching window, a plurality of gate trenches arranged at intervals are formed in the semiconductor substrate based on the etching window, and a source region is formed between adjacent gate trenches; forming a gate oxide layer at the bottom and sidewall of each gate trench, and forming a polysilicon layer in the gate trench and in the etching window; removing the hard mask layer to expose the top sidewall of the polysilicon layer; forming a sidewall structure on the top sidewall of the polysilicon layer, wherein the sidewall structure shields a portion of the source region, and a self-aligned window exposing the surface of the source region is defined between the sidewall structures; forming a first etching stop layer in the self-alignment window; Removing the sidewall structure and the polysilicon layer located on the surface of the first etch stop layer to expose the source region between the first etch stop layer and the polysilicon layer; Based on the barrier layer, a portion of polysilicon in the gate trench is removed by etching to form a first groove, and a portion of the exposed source region is removed to form a second groove; removing the first etching stop layer to expose the surface of the source region; Depositing a second etch stop layer on the source region, wherein the second etch stop layer at least fills the first groove and the second groove, and removing the second etch stop layer on the surface of the source region until the surface of the source region is exposed; Using the remaining second etching stop layer as a self-aligned mask, etching the source region to form a source contact hole in the source region; A contact metal layer is formed in the source contact hole and a metal layer is formed on the front surface of the semiconductor substrate.

2. The method for manufacturing a power semiconductor device structure according to claim 1, characterized in that: The lateral distance between the source contact hole and the gate trench is limited by controlling the lateral width of the spacer structure.

3. The method for manufacturing a power semiconductor device structure according to claim 2, characterized in that: The lateral spacing between the source contact hole and the gate trench is less than 0.2 microns.

4. The method for manufacturing a power semiconductor device structure according to claim 1, characterized in that: The material of the sidewall structure includes one or a composite layer composed of two or more of nitride, oxide and oxynitride.

5. The method for manufacturing a power semiconductor device structure according to claim 1, characterized in that: A second groove is formed by removing part of the source region through a wet etching process or a dry etching process, wherein the top dimension of the second groove is larger than the bottom dimension thereof, and the top dimension of the second etch stop layer subsequently filled into the second groove is larger than the bottom dimension thereof.

6. The method for manufacturing a power semiconductor device structure according to claim 1, characterized in that: The top size of the source contact hole is larger than the bottom size thereof, and the sidewall inclination angle of the source contact hole is 80° to 85°.

7. The method for manufacturing a power semiconductor device structure according to claim 1, characterized in that: Forming the first etch stop layer in the self-aligned window includes: etching the source region to form a receiving groove on the surface of the source region, and forming the first etch stop layer in the receiving groove.

8. The method for manufacturing a power semiconductor device structure according to claim 7, characterized in that: The thickness of the first etch stop layer is 0.2 micrometer to 0.5 micrometer; and / or The first etch stop layer includes organic matter.

9. The method for manufacturing a power semiconductor device structure according to claim 1, characterized in that: The preparation method further comprises the steps of: performing ion implantation on the semiconductor substrate in sequence to form a carrier storage region, a body region and a source region in the semiconductor substrate.

10. The method for manufacturing a power semiconductor device structure according to claim 9, characterized in that: The depths of the first groove and the second groove are smaller than the depth of the source region, and the depths of the first groove and the second groove are in the range of 0.5 micrometer to 1 micrometer.

11. The method for manufacturing a power semiconductor device structure according to claim 1, characterized in that: After forming the front metal, the following steps are also included: Performing ion implantation on the back side of the semiconductor substrate to form a collector region; Performing ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is disposed adjacent to the collector region; A back metal layer is formed on the back side of the semiconductor substrate.

12. A power semiconductor device structure, characterized in that: The power semiconductor device structure is manufactured by the method for manufacturing a power semiconductor device structure according to any one of claims 1 to 11.

Images