Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. According to the invention, on the basis of not adding a new manufacturing process, a plurality of lightly doped drain regions with different doping concentration gradients in the transverse direction are formed by utilizing a multi-layer structure side wall, taking self-alignment as a barrier layer of ion implantation and performing multi-section ion implantation, and the doping concentration of the lightly doped drain structure jointly formed by the plurality of lightly doped drain regions is gradually distributed; buffer of hot carriers can be effectively increased, a peak electric field is further reduced, and therefore the purpose of further improving the hot carrier injection effect is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process technology, and in particular to a semiconductor device capable of improving HCI effect and a preparation method thereof. Background Art

[0002] As the process size continues to shrink, the power supply voltage has not been able to decrease proportionally with the reduction of device channel length, junction depth, gate oxide thickness and the increase of substrate doping concentration, resulting in a significant increase in the channel lateral and longitudinal electric fields. The high electric field will accelerate the movement of carriers, thereby converting the carriers into hot carriers with high energy, thereby generating the hot carrier injection (HCI) effect. The HCI effect is a common problem in the design of integrated circuit devices and is the main factor affecting device characteristics and reliability. High-voltage complementary metal oxide semiconductor (CMOS) uses a lightly doped drain (LDD) structure to reduce the peak electric field near the gate end to the drain end of the device. The LDD structure, as a connecting area, causes the electric field to undergo a slow change process, weakening the peak electric field strength to improve the HCI effect.

[0003] At present, the traditional device process is: after the gate etching is completed, the ion implantation (IMP) of the LDD structure is performed, and then the corresponding area of ​​the LDD structure is shielded by the spacer process, and then the ion implantation of the source and drain (S / D) area is performed. In this implantation sequence, due to the thermal annealing (Anneal) after the ion implantation, the thermal annealing temperature of S / D is greater than the thermal annealing temperature of LDD, resulting in that while the S / D area is thermally annealed, the LDD area will also be affected by the thermal budget of the S / D thermal annealing, causing the ions in the LDD area to further diffuse, thereby reducing the HCI effect; however, the electric field changes greatly in the connection area of ​​an LDD ion implantation, and the HCI phenomenon is still large. Another method is to realize two LDD ion implantations by adding an additional sidewall growth and removal process. Although the LDD ion concentration gradient can be reduced, the process needs to be modified to add the sidewall growth and removal process, resulting in an increase in process time and cost.

[0004] Therefore, how to effectively increase the buffering of hot carriers and reduce the peak electric field based on the existing sidewall structure without adding a new process, so as to achieve the purpose of improving the HCI effect, has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor device and a preparation method thereof, which can effectively increase the buffering of hot carriers and reduce the peak electric field based on the existing sidewall structure without adding a new process, thereby achieving the purpose of improving the HCI effect and saving process time and cost.

[0006] To solve the above problems, an embodiment of the present invention provides a method for preparing a semiconductor device, the method comprising the following steps: forming a substrate, the substrate comprising a substrate having an active area, a gate oxide layer covering the top surface of the substrate, a gate formed on the gate oxide layer, a pocket injection region formed in the active area on both sides of the gate, and a first initial lightly doped drain region; forming a first sidewall material layer covering the gate, and performing lightly doped drain ion implantation in the first initial lightly doped drain region to form a second initial lightly doped drain region, the first initial lightly doped drain region between the second initial lightly doped drain region and the pocket injection region serving as the first lightly doped drain region; forming a sidewall material layer covering the first sidewall material layer, A second sidewall material layer of the layer is formed, and lightly doped drain ions are implanted to form a third initial lightly doped drain region, and the second initial lightly doped drain region between the third initial lightly doped drain region and the first lightly doped drain region serves as the second lightly doped drain region; an etching process is performed, and the second sidewall material layer remaining on the gate sidewall and the first sidewall material layer jointly form a sidewall; a source and drain region is formed in the third initial lightly doped drain region under the self-alignment of the sidewall, and the third initial lightly doped drain region between the source and drain region and the second lightly doped drain region serves as the third lightly doped drain region, and the first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region with successively increasing doping concentrations jointly constitute a lightly doped drain structure.

[0007] In order to solve the above problem, an embodiment of the present invention further provides a semiconductor device, wherein the semiconductor device is manufactured by the method for manufacturing a semiconductor device described in the present invention.

[0008] The above technical solution, without the need for adding new processes, utilizes a multi-layer structure side wall, and uses self-alignment as a barrier layer for ion implantation. Through multi-stage ion implantation, multiple lightly doped drain regions with different lateral doping concentration gradients are formed. The doping concentration of the lightly doped drain structure formed by multiple lightly doped drain regions is gradually distributed, which can effectively increase the buffering of hot carriers and further reduce the peak electric field, thereby achieving the purpose of further improving the hot carrier injection effect. Among them, the existence of the pocket injection region can reduce the depletion degree of the depletion region to generate a smaller penetration current; by first performing pocket ion implantation before forming the second protective layer to form the pocket injection region, and then performing lightly doped drain ion implantation after forming the second protective layer to form the first initial lightly doped drain region, the concentration gradient between the pocket injection region and the first initial lightly doped drain region can be reduced, so that the electric field has a slow change process. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 A schematic diagram of the steps of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0011] Figure 2 A schematic diagram of a device structure of a substrate provided in one embodiment of the present invention;

[0012] Figure 3 A schematic diagram of a device structure after a pocket-shaped implantation region is formed according to an embodiment of the present invention;

[0013] Figure 4 A schematic diagram of a device structure after a silicon nitride material layer is formed according to an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of a device structure after forming a second protective layer according to an embodiment of the present invention;

[0015] Figure 6 A schematic diagram of a device structure after forming a first initial lightly doped drain region according to an embodiment of the present invention;

[0016] Figure 7 A schematic diagram of a device structure after forming a first spacer material layer provided by an embodiment of the present invention;

[0017] Figure 8 A schematic diagram of a device structure after forming a second initial lightly doped drain region according to an embodiment of the present invention;

[0018] Fig. 9 A schematic diagram of a device structure after forming a second spacer material layer provided by an embodiment of the present invention;

[0019] Fig.10 A schematic diagram of a device structure after forming a third initial lightly doped drain region according to an embodiment of the present invention;

[0020] Fig.11 A schematic diagram of a device structure after forming a third spacer material layer according to an embodiment of the present invention;

[0021] Fig.12 A schematic diagram of a device structure after forming a sidewall spacer according to an embodiment of the present invention;

[0022] Fig.13A schematic diagram of a device structure after forming source and drain regions according to an embodiment of the present invention;

[0023] Fig.14 A comparison diagram of electric field distribution of one-stage ion implantation and three-stage ion implantation provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0025] An embodiment of the present invention provides a method for manufacturing a semiconductor device.

[0026] Please also read Figures 1 to 13 ,in, Figure 1 A schematic diagram of the steps of a method for preparing a semiconductor device provided by an embodiment of the present invention; Figure 2 A schematic diagram of a device structure of a substrate provided in one embodiment of the present invention; Figure 3 A schematic diagram of a device structure after a pocket-shaped implantation region is formed according to an embodiment of the present invention; Figure 4 A schematic diagram of a device structure after a silicon nitride material layer is formed according to an embodiment of the present invention; Figure 5 A schematic diagram of a device structure after forming a second protective layer according to an embodiment of the present invention; Figure 6 A schematic diagram of a device structure after forming a first initial lightly doped drain region according to an embodiment of the present invention; Figure 7 A schematic diagram of a device structure after forming a first spacer material layer provided by an embodiment of the present invention; Figure 8 A schematic diagram of a device structure after forming a second initial lightly doped drain region according to an embodiment of the present invention; Fig. 9 A schematic diagram of a device structure after forming a second spacer material layer provided by an embodiment of the present invention; Fig.10 A schematic diagram of a device structure after forming a third initial lightly doped drain region according to an embodiment of the present invention; Fig.11 A schematic diagram of a device structure after forming a third spacer material layer according to an embodiment of the present invention; Fig.12 A schematic diagram of a device structure after forming a sidewall spacer according to an embodiment of the present invention; Fig.13 A schematic diagram of a device structure after forming source and drain regions according to an embodiment of the present invention.

[0027] like Figure 1As shown, the preparation method of the semiconductor device described in this embodiment includes the following steps: S1, forming a substrate, the substrate including a substrate with an active area, a gate oxide layer covering the top surface of the substrate, a gate formed on the gate oxide layer, a pocket injection region in the active area formed on both sides of the gate, and a first initial lightly doped drain region; S2, forming a first sidewall material layer covering the gate, and performing lightly doped drain ion implantation in the first initial lightly doped drain region to form a second initial lightly doped drain region, and the first initial lightly doped drain region between the second initial lightly doped drain region and the pocket injection region serves as a first lightly doped drain region; S3, forming a second sidewall material layer covering the first sidewall material layer layer, and perform lightly doped drain ion implantation to form a third initial lightly doped drain region, and the second initial lightly doped drain region between the third initial lightly doped drain region and the first lightly doped drain region serves as the second lightly doped drain region; S4, perform an etching process, and the second sidewall material layer remaining on the gate sidewall and the first sidewall material layer jointly form a sidewall; and S5, form a source and drain region in the third initial lightly doped drain region under the self-alignment of the sidewall, and the third initial lightly doped drain region between the source and drain region and the second lightly doped drain region serves as the third lightly doped drain region, and the first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region with successively increasing doping concentrations jointly constitute a lightly doped drain structure.

[0028] Please refer to step S1 and Figure 6 , forming a substrate, the substrate comprising a substrate 20 having an active area AA, a gate oxide layer 21 covering the top surface of the substrate 20, a gate 22 formed on the gate oxide layer 21, a pocket injection region 23 formed in the active area AA on both sides of the gate 22, and a first initial lightly doped drain region 240. Specifically, a first direction D1 is defined to be parallel to the top surface of the substrate 20, and a second direction D2 is defined to be perpendicular to the top surface of the substrate 20.

[0029] In this embodiment, in a first direction D1 parallel to the top surface of the substrate 20 , the pocket implantation region 23 and the first initial lightly doped drain region 240 are sequentially away from the gate 22 .

[0030] In this embodiment, the step of forming the base specifically includes: (1) providing a substrate 20, wherein the active area AA is isolated in the substrate 20 by an isolation structure (not shown), the top surface of the substrate 20 is covered with the gate oxide layer 21, and the gate 22 is formed on the gate oxide layer 21, such as Figure 2 (2) forming a first protective layer 31 covering the gate 22, and performing pocket ion implantation to form a pocket implantation region 23 partially located below the gate 22 in the active area AA, such as Figure 3(3) forming a second protective layer 51 covering the side wall of the gate 22 of the first protective layer 31, and performing lightly doped drain ion implantation in the active area AA to form a first initial lightly doped drain region 240 located on the side of the pocket-shaped implantation region 23 away from the gate 22, as shown in FIG. Figure 6 shown.

[0031] The existence of the pocket injection region 23 can reduce the depletion degree of the depletion region to generate a smaller penetration current. In this embodiment, the pocket injection region 23 is formed by first performing pocket ion implantation (Pocket IMP) before forming the second protective layer 51, and then performing lightly doped drain ion implantation (LDDIMP) after forming the second protective layer 51 to form the first initial lightly doped drain region 240, which can reduce the concentration gradient between the pocket injection region 23 and the first initial lightly doped drain region 240, so that the electric field has a slow change process.

[0032] In some embodiments, the substrate 20 is used to support the device structure above it, and the device structure can also be formed in the substrate. In this embodiment, the substrate 20 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 20 may also be a stacked structure, such as a silicon / germanium silicon stack. The material of the gate oxide layer 21 may be silicon dioxide (SiO 2 ), a silicon dioxide film layer covering the top surface of the substrate 20 can prevent subsequent processes from causing damage to the top surface of the substrate 20.

[0033] In this embodiment, the material of the gate 22 is polysilicon (Poly), and the step of forming the first protective layer 31 covering the gate 22 specifically includes: performing an oxidation process, oxidizing the polysilicon on the surface of the gate 22 to form a silicon dioxide layer covering the gate 22 as the first protective layer 31.

[0034] In this embodiment, the step of forming the second protective layer 51 of the first protective layer 31 covering the side wall of the gate 22 specifically includes: (31) depositing a silicon nitride (SiN) material to form a silicon nitride material layer 510 covering the gate oxide layer 21 and the first protective layer 31, such as Figure 4 (32) anisotropic etching process is used to etch away the silicon nitride material layer 510 other than the side wall of the gate 22, and the remaining silicon nitride material layer 510 forms the second protective layer 51, as shown Figure 5Specifically, the film thickness of the silicon nitride material layer 510 is 90 to 110 angstroms; for example, it can be 90 angstroms, 95 angstroms, 100 angstroms, 105 angstroms, 110 angstroms, etc.

[0035] Anisotropic etching can be understood as only etching downwards without side etching. Because there is a silicon dioxide layer as the first protective layer 31 under the silicon nitride material layer 510, the etching stops on the silicon dioxide layer and will not affect the substrate 20. Specifically, after etching using the anisotropic etching process, the first protective layer 31 on the top of the gate 22 is retained, the silicon nitride material layer 510 outside the side wall of the gate 22 is etched away, and the silicon nitride material layer 510 on the side wall of the gate 22 is retained to form the second protective layer 51. The total width of the first protective layer 31 and the second protective layer 51 on the side wall of the gate 22 is the length of the first lightly doped drain region 24 formed subsequently.

[0036] Please refer to step S2 and Figure 7 , Figure 8 , forming a first spacer material layer 710 covering the gate 22, such as Figure 7 and performing lightly doped drain ion implantation in the first initial lightly doped drain region 240 to form a second initial lightly doped drain region 250, the second initial lightly doped drain region 250 and the first initial lightly doped drain region 240 between the pocket-shaped injection region 23 as the first lightly doped drain region 24, such as Figure 8 The first spacer material layer 710 has a film thickness that satisfies the ion implantation and can pass through the film.

[0037] After the first spacer material layer 710 is formed, lightly doped drain ion implantation is performed directly. The ion implantation can pass through the first spacer material layer 710 with a relatively thin film layer. Normal ion implantation can be achieved on the basis of reducing the number of etching times.

[0038] In this embodiment, in a first direction D1 parallel to the top surface of the substrate 20 , the pocket injection region 23 and the first lightly doped drain region 24 are successively away from the gate 22 ; the second initial lightly doped drain region 250 is located on a side of the first lightly doped drain region 24 away from the pocket injection region 23 .

[0039] In this embodiment, the material of the first sidewall material layer 710 is TEOS. TEOS generally refers to tetraethoxysilane, also known as tetraethyl silicate, which is an organic compound mainly used as an electrical insulation material. At the same time, the decomposition reaction of TEOS can reduce the thickness of the second protective layer 51 using SIN, thereby reducing the film stress of SIN.

[0040] Please refer to step S3 and Fig. 9 , Fig.10 , forming a second spacer material layer 910 covering the first spacer material layer 710, such as Fig. 9 and performing lightly doped drain ion implantation to form a third initial lightly doped drain region 260, the third initial lightly doped drain region 260 and the first lightly doped drain region 24 between the second initial lightly doped drain region 250 as a second lightly doped drain region 25, such as Fig.10 The total thickness of the second spacer material layer 910 and the first spacer material layer 710 is sufficient for ion implantation to pass through the total film layer.

[0041] After forming the second spacer material layer 910, lightly doped drain ion implantation is performed directly. The ion implantation can pass through the second spacer material layer 910 and the first spacer material layer 710 with thinner film layers; normal ion implantation can be achieved on the basis of reducing the number of etching times.

[0042] In this embodiment, in the first direction D1 parallel to the top surface of the substrate 20, the pocket injection region 23 and the first lightly doped drain region 24 are respectively away from the gate 22; the second lightly doped drain region 25 is located on the side of the first lightly doped drain region 24 away from the pocket injection region 23; the third initial lightly doped drain region 260 is located on the side of the second lightly doped drain region 25 away from the first lightly doped drain region 24.

[0043] In this embodiment, the material of the second spacer material layer 910 is silicon nitride (SiN).

[0044] like Fig.11 As shown, in order to reduce the film stress of silicon nitride (SiN), an embodiment of the present invention further includes, after the step of forming the third initial lightly doped drain region 260: performing TEOS deposition again to form a third spacer material layer 110 covering the second spacer material layer 910, and the decomposition reaction of TEOS in the third spacer material layer 110 can reduce the film thickness of the silicon nitride film layer of the second spacer material layer 910. Accordingly, in the subsequent step S4 of performing the etching process, the third spacer material layer 110 is also partially etched, and the remaining third spacer material layer 110, the second spacer material layer 910 and the first spacer material layer 710 on the side wall of the gate 22 jointly form the spacer 29, as shown in FIG. Fig.12 shown.

[0045] Please refer to step S4 and Fig.12 , an etching process is performed, and the second spacer material layer 910 remaining on the side wall of the gate 22 and the first spacer material layer 710 together form a spacer 29 .

[0046] When the step of forming the third initial lightly doped drain region 260 further includes forming the third spacer material layer 110, in the step of performing the etching process described in step S4, the third spacer material layer 110 is also partially etched, and the remaining third spacer material layer 110, the second spacer material layer 910 and the first spacer material layer 710 on the sidewall of the gate 22 together form the spacer 29. At the same time, the first protective layer 31 and the second protective layer 51 on the sidewall of the gate 22 can also serve as part of the spacer 29.

[0047] Please refer to step S5 and Fig.13 , a source-drain region 28 is formed in the third initial lightly doped drain region 260 under the self-alignment of the sidewall 29, and the third initial lightly doped drain region 260 between the source-drain region 28 and the second lightly doped drain region 25 serves as the third lightly doped drain region 26; the first lightly doped drain region 24, the second lightly doped drain region 25, and the third lightly doped drain region 26, which have increasing doping concentrations, together constitute a lightly doped drain structure. That is, by using the existing sidewall of the sandwich structure as a barrier and by multi-stage ion implantation, three LDD ion implantations are directly implemented without adding new processes.

[0048] In this embodiment, in the first direction D1 parallel to the top surface of the substrate 20, the pocket injection region 23 and the first lightly doped drain region 24 are respectively away from the gate 22; the second lightly doped drain region 25 is located on the side of the first lightly doped drain region 24 away from the pocket injection region 23; the third lightly doped drain region 26 is located on the side of the second lightly doped drain region 25 away from the first lightly doped drain region 24; the source and drain region 28 is located on the side of the third lightly doped drain region 26 away from the second lightly doped drain region 25.

[0049] In this embodiment, a straight line passing through the center of the gate 22 and perpendicular to the top surface of the substrate 20 is used as a symmetry axis 131 , and the pocket injection region 23 , the lightly doped drain structure and the source and drain regions 28 are symmetrically distributed on both sides of the gate 22 .

[0050] In this embodiment, the lightly doped drain ions implanted in the first lightly doped drain region 24, the second lightly doped drain region 25, and the third lightly doped drain region 26 are all N-type lightly doped drain ions (NLDD for short); accordingly, the transistor formed is an NMOS transistor. NLDD ion implantation is a low-energy, shallow junction depth, low-doped arsenic (As) ion implantation, which can effectively weaken the hot carrier injection (HCI) effect of NMOS. In some embodiments, the lightly doped drain ion implantation has an injection energy (Energy) of 2.8-7K and a dose (Dose) of 5-8E14 As, the second lightly doped drain region has an injection energy of 2-5K and a dose of 5-8E14 As, and the third lightly doped drain region has an injection energy of 2.8-7K and a dose of 5-8E14 As. The energy band diagram can effectively increase the buffering of hot carriers, further reduce the peak electric field, and reduce the HCI effect by 30%.

[0051] See also Fig.14 , which is a comparison diagram of the electric field distribution of one-stage ion implantation and three-stage ion implantation provided by an embodiment of the present invention. In the figure, reference numeral 141 is a schematic diagram of the electric field distribution of one-stage ion implantation in the prior art, and reference numeral 143 is a schematic diagram of the electric field distribution of the three-stage ion implantation of the present invention. Fig.14 It can be seen that the method for preparing a semiconductor device provided by the present invention can effectively increase the buffering of hot carriers and further reduce the peak electric field, thereby achieving the purpose of further improving the hot carrier injection effect.

[0052] The above-mentioned embodiment of the present invention, without the need for adding new processes, utilizes a multi-layer structure side wall, which is used as a barrier layer for ion injection through self-alignment, and forms a plurality of lightly doped drain regions with different lateral doping concentration gradients through multi-stage ion injection. The doping concentration of the lightly doped drain structure formed by the plurality of lightly doped drain regions is gradually distributed, which can effectively increase the buffering of hot carriers and further reduce the peak electric field, thereby achieving the purpose of further improving the hot carrier injection effect.

[0053] Based on the same inventive concept, an embodiment of the present invention provides a semiconductor device, which forms a lightly doped drain structure semiconductor device composed of the first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region with increasing doping concentrations by adopting the semiconductor device preparation method of the present invention.

[0054] Please also read Figure 2 to Figure 13 A semiconductor device provided in one embodiment of the present invention is formed by the semiconductor device preparation method of the present invention, and the lightly doped drain structure of the semiconductor device is composed of the first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region with increasing doping concentrations.

[0055] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0056] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises the following steps: Forming a substrate, the substrate comprising a substrate having an active area, a gate oxide layer covering a top surface of the substrate, a gate formed on the gate oxide layer, a pocket implantation region formed in the active area on both sides of the gate, and a first initial lightly doped drain region; Forming a first spacer material layer covering the gate, and performing lightly doped drain ion implantation in the first initial lightly doped drain region to form a second initial lightly doped drain region, and the first initial lightly doped drain region between the second initial lightly doped drain region and the pocket-shaped implantation region serves as a first lightly doped drain region; Forming a second spacer material layer covering the first spacer material layer, and performing lightly doped drain ion implantation to form a third initial lightly doped drain region, wherein the second initial lightly doped drain region between the third initial lightly doped drain region and the first lightly doped drain region serves as a second lightly doped drain region; Performing an etching process, so that the second spacer material layer remaining on the gate sidewall and the first spacer material layer together form a spacer; A source-drain region is formed in the third initial lightly doped drain region under the self-alignment of the side wall, and the third initial lightly doped drain region between the source-drain region and the second lightly doped drain region serves as the third lightly doped drain region. The first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region with successively increasing doping concentrations together constitute a lightly doped drain structure.

2. The method according to claim 1, characterized in that: In a first direction parallel to the top surface of the substrate, the pocket injection region and the first initial lightly doped drain region are successively away from the gate, the second initial lightly doped drain region is located on a side of the first initial lightly doped drain region away from the pocket injection region, the third initial lightly doped drain region is located on a side of the second initial lightly doped drain region away from the first lightly doped drain region, and the source drain region is located on a side of the third initial lightly doped drain region away from the second lightly doped drain region.

3. The method according to claim 1, characterized in that Taking a straight line passing through the center of the gate and perpendicular to the top surface of the substrate as a symmetry axis, the pocket-shaped injection region, the lightly doped drain structure and the source and drain regions are symmetrically distributed on both sides of the gate.

4. The method according to claim 1, characterized in that: The step of forming the base specifically includes: providing a substrate, wherein the active area is isolated by an isolation structure in the substrate, the top surface of the substrate is covered with the gate oxide layer, and the gate is formed on the gate oxide layer; Forming a first protection layer covering the gate, and performing pocket ion implantation to form a pocket implantation region partially located below the gate in the active region; A second protection layer of the first protection layer covering the side wall of the gate is formed, and lightly doped drain ions are implanted in the active area to form a first initial lightly doped drain area located on a side of the pocket implantation area away from the gate.

5. The method according to claim 4, characterized in that The gate is made of polysilicon, and the step of forming a first protective layer covering the gate specifically includes: An oxidation process is performed to oxidize the polysilicon on the surface of the gate to form a silicon dioxide layer covering the gate as the first protection layer.

6. The method according to claim 4, characterized in that The step of forming a second protective layer covering the first protective layer on the side wall of the gate specifically includes: Depositing silicon nitride material to form a silicon nitride material layer covering the gate oxide layer and the first protective layer; The silicon nitride material layer except for the gate sidewall is etched away by an anisotropic etching process, and the remaining silicon nitride material layer forms the second protective layer.

7. The method according to claim 6, characterized in that The film thickness of the silicon nitride material layer is 90 to 110 angstroms.

8. The method according to claim 1, characterized in that: The material of the first spacer material layer is TEOS, and the material of the second spacer material layer is silicon nitride.

9. The method according to claim 8, characterized in that After the step of forming the third initial lightly doped drain region, the method further comprises: Depositing TEOS again to form a third spacer material layer covering the second spacer material layer, wherein the TEOS in the third spacer material layer undergoes a decomposition reaction to reduce the film thickness of the silicon nitride film layer in the second spacer material layer; In the step of performing the etching process, the third spacer material layer is also partially etched, and the remaining third spacer material layer, the second spacer material layer and the first spacer material layer on the gate sidewall jointly form the spacer.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, and the lightly doped drain structure of the semiconductor device is composed of the first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region with increasing doping concentrations.

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