Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a silicon nanostructure in an n-type region and a silicon germanium nanostructure in a p-type region, in which at least one silicon germanium nanostructure includes a silicon core region having a first germanium concentration of about 20% or less, a silicon germanium region having a first interface between the silicon core region and the silicon germanium region, and a second silicon germanium region having a second interface between the silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second germanium concentration of up to about 40%. A concentration gradient of germanium increases from a first germanium concentration to a second germanium concentration. A high-k dielectric layer surrounds at least one of the silicon nanostructures and at least one of the silicon germanium nanostructures.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically produced by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using lithography processes to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise that should be addressed. Summary of the invention

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a plurality of silicon nanostructures, a plurality of silicon germanium nanostructures, a high-k dielectric layer, and a gate electrode. The plurality of silicon nanostructures are located on a semiconductor substrate in an n-type region of the semiconductor substrate. The plurality of silicon germanium nanostructures are located on a semiconductor substrate in a p-type region of the semiconductor substrate. At least one of the silicon germanium nanostructures includes a silicon core region, a first silicon germanium region, and a second silicon germanium region. The silicon core region has a first germanium concentration, wherein the first germanium concentration is about 20% or less. The first silicon germanium region has a first interface located between the silicon core region and the first silicon germanium region. The second silicon germanium region has a second interface located between the first silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second germanium concentration, wherein the second germanium concentration is up to about 40%, wherein the first concentration gradient of germanium increases from the first germanium concentration at the first interface to the second germanium concentration at the second interface. The high-k dielectric layer surrounds at least one of the silicon nanostructures and at least one of the silicon germanium nanostructures. The gate electrode fills a gap between at least one of the adjacent silicon germanium nanostructures.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes the following steps. A plurality of silicon nanostructures are formed on a semiconductor substrate in an n-type region of the semiconductor substrate. A plurality of silicon germanium nanostructures are formed on a semiconductor substrate in a p-type region of the semiconductor substrate, wherein at least one of the silicon germanium nanostructures includes a silicon core region, a first silicon germanium region, and a second silicon germanium region. The silicon core region has a first germanium concentration, wherein the first germanium concentration is about 20% or less. The first silicon germanium region has a first interface located between the silicon core region and the first silicon germanium region. The second silicon germanium region has a second interface located between the first silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second germanium concentration, wherein the second germanium concentration is up to about 40%, wherein a first concentration gradient of germanium increases from a first germanium concentration at the first interface to a second germanium concentration at the second interface. A high-k dielectric layer is deposited around at least one of the silicon nanostructures and at least one of the silicon germanium nanostructures. A gate electrode is formed to fill a gap between at least one of the adjacent silicon germanium nanostructures.

[0006] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes the following steps: forming a plurality of nanowires over a plurality of semiconductor fins in an n-type region and a p-type region; forming a hard mask layer over a first plurality of nanowires in the n-type region; performing a trimming process on a second plurality of nanowires in the p-type region; depositing silicon germanium over each of the second plurality of nanowires; and performing an annealing process on the second plurality of nanowires, wherein the annealing process diffuses germanium into at least one of the second plurality of nanowires, thereby forming a plurality of silicon germanium nanostructures in the p-type region, wherein the silicon germanium nanostructures have a plurality of different regions with a plurality of different germanium concentrations. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of this disclosure are in accordance with the attached Figure 1 It is best understood from the following detailed description when read together.

[0008] Figure 1 An example of a nanostructure field-effect transistor (nano-FET) is shown in a three-dimensional view according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig. 16C , Fig.16D , Fig.16E , Fig.16F , Figure 16G , Fig.16H , Fig.16I , Fig.16J , Figure 16K , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig. 18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B and Fig. 20C , is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010]

Explanation of symbols

[0011] 102: Gate electrode

[0012] 104: Gate mask

[0013] 106: Second ILD

[0014] 108: The third groove

[0015] 112: Contact

[0016] 114: Contact

[0017] 1601: Hard mask layer

[0018] 1603:Hard mask patterning process

[0019] 1607:SiGe Deposition Process

[0020] 1609: Germanium source layer

[0021] 1613: Silicon Covering Layer

[0022] 1615: Dielectric Structure

[0023] 1617: Interface layer

[0024] 1619: High-k dielectric layer

[0025] 1654:Nanostructured Core

[0026] 1654A: Nanostructured Core

[0027] 1654B: Nanostructured Core

[0028] 1654C: Nanostructured Core

[0029] 1670A:SiGe Nanostructures

[0030] 1670B:SiGe Nanostructures

[0031] 1670C:SiGe Nanostructures

[0032] 20: Divider

[0033] 50:Semiconductor device

[0034] 50N: n-type region

[0035] 50P: p-type region

[0036] 51A: first semiconductor layer

[0037] 51B: first semiconductor layer

[0038] 51C: first semiconductor layer

[0039] 52A: First Nanostructure

[0040] 52B: First Nanostructure

[0041] 52C: The first nanostructure

[0042] 53A: Second semiconductor layer

[0043] 53B: Second semiconductor layer

[0044] 53C: Second semiconductor layer

[0045] 54A: Second Nanostructure

[0046] 54B: Second Nanostructure

[0047] 54C: Second Nanostructure

[0048] 55: Nanostructure

[0049] 64: Multi-layer stacking

[0050] 66: Fin

[0051] 68:STI area

[0052] 70: Virtual dielectric layer

[0053] 71: Virtual gate dielectric layer

[0054] 72: Virtual gate layer

[0055] 74: Mask layer

[0056] 76: Virtual Gate

[0057] 78:Mask

[0058] 80: First spacer layer

[0059] 81: first spacer

[0060] 82: Second spacer layer

[0061] 83: Second spacer

[0062] 86: First groove

[0063] 88: Depression

[0064] 90: first inner spacer

[0065] 92: Source / drain region

[0066] 92A: first semiconductor material layer

[0067] 92B: Second semiconductor material layer

[0068] 92C: third semiconductor material layer

[0069] 94:CESL

[0070] 96: First ILD

[0071] 98: Second groove

[0072] A-A': Section

[0073] a-b': contour

[0074] B-B': Section

[0075] C-C': Section

[0076] R1: First Area

[0077] R2: Second Area

[0078] R3: The third area

[0079] R4: The fourth area

[0080] Th1: Thickness

[0081] Th2: Thickness

[0082] Th3: Thickness

[0083] Th4: Thickness

[0084] Th5: Thickness

[0085] Th6: Thickness

[0086] Th7: Thickness

[0087] Th8:Thickness

[0088] W1: Width

[0089] W2: Width

[0090] W3: Width DETAILED DESCRIPTION

[0091] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, the formation of a first feature on a second feature means that the first feature is formed in direct contact with the second feature. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0092] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0093] Some embodiments are discussed in which a channel structure of a PMOS device is formed by depositing germanium over a silicon nanostructure and performing an annealing process on the resulting structure to form a silicon germanium channel. By depositing germanium over the silicon nanostructure and annealing the structure, the resulting silicon germanium channel has a varying germanium concentration over the channel structure in the PMOS device. By controlling the germanium concentration over the silicon germanium channel structure, better device performance can be achieved.

[0094] Figure 1 An example of a nano FET (e.g., a nanowire FET, a nanosheet FET, etc.) is shown in a three-dimensional view according to some embodiments. The nano FET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nano FET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation (STI) region 68 is disposed between adjacent fins 66, which may be above adjacent STI regions 68 and protrude from between adjacent STI regions 68. Although the STI region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. In addition, although the bottom of the fin 66 is shown as being a single, continuous material with the substrate 50, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 66 refers to the portion extending between adjacent STI regions 68.

[0095] High-k dielectric layer 1619 is located on the top surface of fin 66 and along the top surface, sidewalls and bottom surface of nanostructure 55. Gate electrode 102 is located above high-k dielectric layer 1619. Epitaxial source / drain regions 92 are disposed on fin 66 on opposite sides of high-k dielectric layer 1619 and gate electrode 102.

[0096] Figure 1 Reference cross sections used in subsequent figures are further described. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nanoFET and in a direction, for example, along the direction of current flow between epitaxial source / drain regions 92 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0097] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0098] Figures 2 to 20C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , FIG. 16C to FIG. 16G , FIG. 16I to FIG. 16J , Fig.17A , Fig.18A , Fig.19A and Fig. 20A It shows Figure 1 Reference section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B and Fig. 20B It shows Figure 1 Reference section BB' is shown. Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig. 18C , Fig.19C and Fig. 20C Shows Figure 1 Reference section CC' shown in .

[0099] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination thereof.

[0100] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type element, such as an NMOS transistor, such as an n-type nano FET, and the p-type region 50P can be used to form a p-type element, such as a PMOS transistor, such as a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separation line 20), and any number of device parts (e.g., other active components, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be set.

[0101] Further in Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material, such as silicon, silicon carbon, etc.

[0102] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. Thus, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form a channel region.

[0103] Reference now Figure 3 According to some embodiments, the fin 66 is formed in the substrate 50 and the nanostructure 55 is formed in the multilayer stack 64. In some embodiments, the nanostructure 55 and the fin 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching grooves in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. Forming the nanostructure 55 by etching the multilayer stack 64 can also define the first nanostructure 52A-52C (collectively referred to as the first nanostructure 52) from the first semiconductor layer 51 and define the second nanostructure 54A-54C (collectively referred to as the second nanostructure 54) from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can also be collectively referred to as the nanostructure 55.

[0104] The fin 66 and the nanostructure 55 can be patterned by any suitable method. For example, the fin 66 and the nanostructure 55 can be patterned using one or more lithography processes (including double patterning or multi-patterning processes). In general, the double patterning or multi-patterning process combines lithography and self-alignment processes, allowing the creation of patterns with, for example, a pitch smaller than that obtained using a single direct lithography etching process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography etching process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0105] For illustration purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or thinner than the fins 66 in the p-type region 50P. In addition, although each of the fins 66 and nanostructures 55 is shown as having a consistent width throughout, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each fin 66 and / or nanostructure 55 increases continuously in a direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0106] exist Figure 4 In the embodiment shown, an STI region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (flowable CVD, FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed via an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments can be multilayer. For example, in some embodiments, a liner (not shown separately) can be formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as those discussed above can be formed on the liner.

[0107] The insulating material is then subjected to a removal process to remove excess insulating material on the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used. The planarization process exposes the nanostructure 55 so that the top surface of the nanostructure 55 and the insulating material are level after the planarization process is completed.

[0108] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (e.g., a concave surface) as shown, or a combination thereof. The top surface of the STI region 68 may be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55). For example, oxide removal such as dilute hydrofluoric (dHF) may be used.

[0109] Reference above Figures 2 to 4 The process described is just one example of how the fins 66 and nanostructures 55 may be formed. In some embodiments, the fins 66 and / or nanostructures 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing the epitaxial structure, the epitaxially grown material may be doped in situ during growth, which may avoid prior and / or subsequent implantation, although in situ doping and implantation doping may be used together.

[0110] In addition, for the purpose of illustration only, here, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed as including the same material in the p-type region 50P and the n-type region 50N. As such, in some embodiments, in the p-type region 50P and the n-type region 50N, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in a different order.

[0111] In addition, Figure 4 In the embodiment with different well types, different implantation steps of the n-type region 50N and the p-type region 50P may be implemented using a photoresist or other mask (not shown separately). For example, a photoresist may be formed over the fins 66 and STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable lithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted in the region, with a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0112] After or before implanting the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region, and its concentration is about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0113] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0114] exist Figure 5In the embodiment of the present invention, a virtual dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The virtual dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A virtual gate layer 72 is formed above the virtual dielectric layer 70, and a mask layer 74 is formed above the virtual gate layer 72. The virtual gate layer 72 can be deposited above the virtual dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited above the virtual gate layer 72. The virtual gate layer 72 can be a conductive or non-conductive material, and can be selected from amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide and metal. The virtual gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition or other techniques for depositing selected materials. The virtual gate layer 72 can be made of other materials with high etching selectivity for etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55 for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0115] exist Fig. 6A and Figure 6B In the embodiment, the mask layer 74 (see Figure 5 ) is patterned to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric layer 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from an adjacent dummy gate 76. The dummy gate 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 66.

[0116] exist Fig. 7A and Figure 7B In the embodiment, the first spacer layer 80 and the second spacer layer 82 are respectively formed on Fig. 6A and Figure 6B The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7BIn the embodiment of the present invention, a first spacer 80 is formed on the top surface of the STI region 68, the top surface and sidewalls of the fin 66, the nanostructure 55 and the mask 78, and the sidewalls of the dummy gate 76 and the dummy gate dielectric layer 71. A second spacer 82 is deposited over the first spacer 80. The first spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation or deposited by CVD, ALD, etc. The second spacer 82 may be formed of a material having a different etching rate from the material of the first spacer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, ALD, etc.

[0117] After forming the first spacer layer 80 and before forming the second spacer layer 82, implantation of lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above Figure 4 As discussed in the implantation, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a thickness of about 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implantation damage and activate implanted impurities.

[0118] exist Fig. 8A and Figure 8B, the first spacer 80 and the second spacer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source / drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer 80 and the second spacer 82 can be etched using a suitable etching process, such as an isotropic etching process (such as a wet etching process), an anisotropic etching process (dry etching process), etc. In some embodiments, the material of the second spacer 82 has a different etching rate from the material of the first spacer 80, so that the first spacer 80 can act as an etching stop layer when the second spacer 82 is patterned, and so that the second spacer 82 can act as a mask when the first spacer 80 is patterned. For example, the second spacer 82 can be etched using an anisotropic etching process, wherein the first spacer 80 acts as an etching stop layer, and wherein the remaining portion of the second spacer 82 forms the second spacer 83, such as Fig. 8A Thereafter, the second spacer 83 is used as a mask, and the exposed portion of the first spacer layer 80 is etched at the same time, thereby forming Fig. 8A The first spacer 81 is shown.

[0119] like Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric layer 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric layer 71. In other embodiments, a portion of the second spacer layer 82 can remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric layer 71.

[0120] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), and additional spacers may be formed and removed. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0121] exist Fig.9A and Fig. 9B In some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Fig.9A As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; or similar. The first recess 86 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). The first spacer 81, the second spacer 83, and the mask 78 shield the fin 66, the nanostructure 55, and a portion of the substrate 50 during the etching process for forming the first recess 86. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching of the first recess 86 after the first recess 86 reaches a desired depth.

[0122] exist Fig. 10A and Fig. 10B In the embodiment of the present invention, portions of the sidewalls of the layers of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first recess 86 are etched to form a sidewall recess 88. Although the sidewalls of the first nanostructure 52 in the sidewall recess 88 are Fig. 10B , but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process such as a wet etch. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, the sidewalls of the first nanostructure 52 may be etched using a dry etching process such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0123] exist FIG. 11A to FIG. 11B In the embodiment, the first inner spacer 90 is formed in the sidewall recess 88. The first inner spacer 90 can be formed by Fig. 10A and Fig. 10B The inner spacer layer (not shown separately) is deposited on the structure shown to form. The first inner spacer 90 acts as an isolation member between the subsequently formed source / drain region and the gate structure. As will be discussed in more detail below, the source / drain region will be formed in the first recess 86, and the first nanostructure 52 will be replaced by a corresponding gate structure.

[0124] The inner spacer can be deposited by a conformal deposition process, such as CVD, ALD, etc. The inner spacer can include a material such as silicon nitride or silicon oxynitride, but any suitable material can be utilized, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer can then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 can extend beyond the sidewalls of the second nanostructure 54 or be recessed from the sidewalls of the second nanostructure 54.

[0125] In addition, although the outer side wall of the first inner spacer 90 is Fig. 11B Although shown as straight in the figure, the outer sidewall of the first inner spacer 90 may be concave or convex. The first inner spacer 90 may be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 may be used to prevent the subsequently formed source / drain regions (e.g., epitaxial source / drain regions 92, hereinafter referred to as FIG. 12A to FIG. 12C Discussion) is damaged by a subsequent etching process (eg, an etching process used to form a gate structure).

[0126] exist FIG. 12A to FIG. 12C In the embodiment, the epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the source / drain region 92 can apply stress to the second nanostructure 54, thereby improving performance. Fig. 12B As shown, epitaxial source / drain regions 92 are formed in the first recesses 86, so that each dummy gate 76 is disposed between each pair of adjacent epitaxial source / drain regions 92. In some embodiments, the first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gate layer 72, and the first inner spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, so that the epitaxial source / drain regions 92 will not be short-circuited with the gate of the resulting nanoFET formed subsequently.

[0127] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by shielding the p-type region 50P (e.g., PMOS region). Then, the source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nano FETs. For example, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55 and may have a facet.

[0128] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for a p-type nano FET. For example, the epitaxial source / drain region 92 may include a material that applies compressive strain to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 may also have a surface protruding from a corresponding surface of the multilayer stack 56 and may have a facet.

[0129] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process for forming lightly doped source / drain regions discussed previously, followed by annealing. The source / drain regions may have a density of about 1×10 19 Atom / cm 3 and approximately 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0130] Due to the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets result in the merging of adjacent epitaxial source / drain regions 92 of the same NSFET, such as Fig. 12A In other embodiments, as shown in Fig. 12C As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Fig. 12A and Fig. 12C In the illustrated embodiment, the first spacer 81 can be formed to the top surface of the STI region 68, preventing epitaxial growth. In some other embodiments, the first spacer 81 can cover a portion of the sidewalls of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0131] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

[0132] Fig.12D An embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Fig.12D As shown, the epitaxial source / drain region 92 may be formed to contact the first inner spacer 90 and may extend beyond the sidewalls of the second nanostructure 54 in the n-type region 50N and the sidewalls of the first nanostructure 52 in the p-type region 50P.

[0133] exist FIG. 13A to FIG. 13C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Fig. 6A , Fig. 12B and Fig. 12A The structure shown ( 7A to 12D The process does not change Fig. 6A96 is formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is set between the first ILD 96 and the epitaxial source / drain regions 92, the mask layer 74, and the first spacer 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etching rate than the material of the overlying first ILD 96.

[0134] exist FIG. 14A to FIG. 14B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are level within process variations. Therefore, the top surface of the dummy gate layer 72 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0135] exist Fig.15A and Fig. 15BIn the embodiment of the present invention, the dummy gate layer 72 and the mask layer 74 (if present) are removed in one or more etching steps to form a second groove 98. A portion of the dummy gate dielectric layer 71 in the second groove 98 is also removed. In some embodiments, the dummy gate layer 72 and the dummy gate dielectric layer 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 72 at a faster rate than the first ILD 96 or the first spacer 81. Each second groove 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in a subsequently completed nanoFET. The portion of the nanostructure 55 that serves as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During the removal process, when the dummy gate layer 72 is etched, the dummy gate dielectric layer 71 may be used as an etch stop layer. Then, after removing the dummy gate layer 72, the dummy gate dielectric layer 71 may be removed.

[0136] exist Fig.16A and Fig. 16B In the embodiment, the first nanostructure 52 in the n-type region 50N and the p-type region 50P is removed, and the second recess 98 is extended between the second nanostructure 54. The first nanostructure 52 can be removed by an isotropic etching process such as wet etching using an etchant selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A-54C include, for example, Si or SiC, the first nanostructure 52 can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0137] exist Fig. 16C In the embodiment, after removing the first nanostructure 52 in the n-type region 50N and the p-type region 50P, a hard mask layer 1601 may be formed over the second nanostructure 54. In one embodiment, the hard mask layer 1601 may include a nitride such as silicon nitride, and may be formed by deposition such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. However, the hard mask layer 1601 may be formed using any suitable material and process.

[0138] exist Fig.16DIn the embodiment, a first hard mask patterning process 1603 is performed to remove a portion of the hard mask layer 1601 above the p-type region 50P, exposing the second nanostructure 54 in the p-type region 50P, while exposing the second nanostructure 54 in the n-type region 50N still covered by the hard mask layer 1601. In one embodiment, the first hard mask patterning process 1603 may be a lithography patterning process. However, any suitable mask removal process may be used to remove the hard mask layer 1601 above the p-type region 50P.

[0139] exist Fig.16E In one embodiment, the nanostructure trimming process 1605 is performed on the second nanostructure 54 exposed in the p-type region 50P to form a nanostructure core 1654 (e.g., nanostructure cores 1654A-1654C). In one embodiment, the nanostructure trimming process 1605 reduces the size of the second nanostructure 54 (e.g., the first width W1) to the size of the resulting nanostructure core 1654 (e.g., the second width W2). In one embodiment, the nanostructure trimming process 1605 may also reduce the size of the fin 66 protruding above the STI region 68 exposed in the p-type region 50P (e.g., from the first width W1 to the second width W2). In some embodiments, after the nanostructure trimming process 1605, the second nanostructure 54 exposed in the p-type region 50P is reduced from the first width W1 of the nanostructure core 1654 to the second width W2. In one embodiment, the first width W1 is in the range of 3 nm to 10 nm. In an embodiment, the second width W2 is about 8 nm or less (wherein one of ordinary skill in the art will understand that “about” refers to standard process variations associated with dimensions width and thickness).

[0140] In an embodiment, the nanostructure trimming process 1605 may be any acceptable etching process, such as an etching process that is selective to the second nanostructure 54 (eg, selectively etches the material of the second nanostructure 54). The etching may be isotropic.

[0141] In some embodiments, the nanostructure trimming process 1605 includes performing a plurality of oxidation and etching cycles. For example, during each oxidation cycle, the portion of the second nanostructure 54 exposed in the p-type region 50P may be oxidized, and during each etching cycle, the oxidized portion of the second nanostructure 54 is removed. The oxidation and etching cycles are repeated until a desired amount of material is trimmed from the second nanostructure 54 in the p-type region 50P, thereby forming a nanostructure core 1654. For example, the oxidation and etching cycles may be cyclically repeated for a predetermined number of times. Oxidation may be performed by any acceptable oxidation process, such as a native oxidation process, a thermal oxidation process, a rapid thermal oxidation (RTO) process, a chemical oxidation process, an in-situ stream generation (ISSG) process, or a similar process. Other oxidation processes or combinations thereof may be performed. Etching may be performed by any acceptable etching process, such as wet etching, dry etching, or a combination thereof. For example, chemical oxide removal of any acceptable etching process, such as dilute hydrofluoric (dHF) acid, may be used.

[0142] exist Fig.16F, a silicon germanium (SiGe) deposition process 1607 is performed over the nanostructure core 1654, the exposed portion of the fin 66, and the exposed portion of the STI region 68. In one embodiment, the SiGe deposition process 1607 forms a germanium source layer 1609 on the nanostructure core 1654 and the exposed portion of the fin 66. In one embodiment, the SiGe deposition process 1607 is performed by a CVD process. The SiGe deposition process 1607 can be performed in a CVD chamber. In an embodiment, the SiGe deposition process 1607 uses GeH4 as a first reaction gas as a germanium source. However, any suitable first reaction gas can be used as a germanium source. In one embodiment, the SiGe deposition process 1607 uses SiH4 as a second reaction gas as a silicon source. However, any suitable second reaction gas can be used as a silicon source. The carrier gas used during the SiGe deposition process 1607 can be H2 gas or N2 gas, or other suitable carrier gas. The SiGe deposition process 1607 may be performed at a first process temperature in a range of about 300° C. to about 600° C. and a first process pressure in a range of about 3 Torr to about 100 Torr. In one embodiment, the SiGe deposition process 1607 may be performed for a time in a range of about 1,000 seconds to about 4,000 seconds (wherein one of ordinary skill in the art will understand that “about” refers to standard process variations associated with process parameters of temperature, pressure, and time). After the SiGe deposition process 1607, the germanium source layer 1609 may be formed to a first thickness Th1, wherein the first thickness Th1 is in a range of about 0.5 nm to about 3 nm.

[0143] Furthermore, in one embodiment, during the SiGe deposition process 1607, the flow rate of the first reaction gas and the flow rate of the second reaction gas may be controlled to produce a germanium source layer 1609, which will produce a desired germanium concentration profile (to be discussed later) after an annealing process 1611. Figure 16G 1607). In such an embodiment, the flow rate of the first reactant gas is reduced toward the end of the SiGe deposition process 1607 compared to the flow rate of the second reactant gas to reduce the germanium concentration toward the outer surface of the germanium source layer 1609. In such an embodiment, the germanium source layer 1609 can have a germanium concentration reduced to about zero percent germanium at the outer surface of the germanium source layer 1609. By reducing the germanium concentration at the outer surface of the germanium source layer 1609, scattering between subsequently formed layers (e.g., silicon capping layer 1613) formed on the outer surface of the germanium source layer 1609 due to differences in crystal orientations from different lattice structures can reduce the amount of material at the interface between the germanium source layer 1609 and the subsequently formed layer (e.g., silicon capping layer 1613).

[0144] exist Figure 16GIn the embodiment, an annealing process 1611 is performed on the germanium source layer 1609 and the nanostructure core 1654, wherein the annealing process 1611 forms a silicon germanium (SiGe) nanostructure 1670 (e.g., SiGe nanostructures 1670A-1670C, which may be referred to as a SiGe channel structure). In one embodiment, during the annealing process 1611, germanium from the germanium source layer 1609 diffuses into silicon from the nanostructure core 1654 to form the SiGe nanostructure 1670. The annealing process 1611 is performed such that the concentration of germanium varies across the SiGe nanostructure 1670. The distribution of the germanium concentration across the SiGe nanostructure 1670 may be Figure 16G The distribution of SiGe nanostructures 1670 shown in “ab” is seen in FIG. 1 and referenced below. Fig.16H Discuss in more detail.

[0145] In one embodiment, the annealing process 1611 may be an in-situ annealing process performed in a CVD chamber of the SiGe deposition process 1607. The annealing process 1611 may be performed at a second process temperature in a range of about 500° C. to about 900° C. and a second process pressure in a range of about 3 Torr to about 100 Torr. The carrier gas used during the annealing process 1611 may be H2 gas, however, any suitable carrier gas may be used. In one embodiment, the annealing process 1611 may be performed for a time in a range of about 60 seconds or less. In one embodiment, the second process temperature increased from the first process temperature may drive germanium to diffuse from the germanium source layer 1609 to the nanostructure core 1654. In an embodiment where the nanostructure core 1654 includes silicon, the diffusion of germanium from the germanium source layer 1609 may mitigate the difference in lattice structure at the interface between the germanium source layer 1609 and the nanostructure core 1654. The gradient change in the lattice structure caused by the diffusion of germanium from the germanium source layer 1609 into the nanostructure core 1654 can reduce scattering within the resulting SiGe nanostructure 1670. After the annealing process 1611, the concentration distribution of germanium can be divided into four regions: a first region R1, a second region R2, a third region R3, and a fourth region R4. Each of the four regions is characterized by a different germanium percentage (e.g., about Fig.16H discussed in more detail).

[0146] exist Fig.16H In, from Figure 16G The profile "ab" of the moved SiGe nanostructure 1670 depicts two germanium concentration profiles. Both profile 1 and profile 2 depict four regions and the associated thickness of each region.

[0147] In one embodiment, the first region R1 has a second thickness Th2 in the range of about 0 nm to about 1 nm. In one embodiment, profiles 1 and 2 are characterized in that the first region R1 has a germanium percentage of about 0% at the outer surface of the SiGe nanostructure 1670, wherein the germanium percentage increases through the first region R1 into the SiGe nanostructure 1670 until the interface with the second region R2, wherein the germanium percentage has a maximum value there, and the germanium percentage is in the range of about 5% to about 40% (where one of ordinary skill in the art will understand that "approximately" refers to standard process variations and nominal diffusion effects associated with chemical concentrations).

[0148] In one embodiment, the second region R2 has a third thickness Th3 in the range of about 1 nm to about 4 nm. In one embodiment, profiles 1 and 2 are characterized in that the second region R2 has a constant germanium percentage (within process variations and nominal diffusion ranges) across the second region R2 in the SiGe nanostructure 1670, wherein the constant germanium percentage is in the range of about 5% to about 40%. The germanium percentage remains constant over the second region R2 from the interface with the first region R1 to the interface with the third region R3.

[0149] In one embodiment, the third region R3 has a fourth thickness Th4 in the range of about 0 nm to about 2 nm. In one embodiment, the germanium percentage in the third region R3 decreases from the interface with the second region R2 having about 5% to about 40% to the interface with the fourth region R4 having a maximum germanium percentage of about 20% to about 0%.

[0150] In one embodiment, the fourth region R4 has a fifth thickness Th5 in the range of about 0 nm to about 8 nm. In one embodiment, the fourth region R4 shown in profile 1 represents that the fourth region R4 has a constant maximum germanium percentage of about 0% from the interface with the third region R3 to the mirror interface with the third region R3 positioned oppositely. In this embodiment, the fourth region may include pure silicon (within process variations). In another embodiment, the fourth region R4 shown in profile 2 represents that the fourth region R4 has a constant maximum germanium percentage of about 20% from the interface with the third region to the mirror interface with the third region R3 positioned oppositely. It should be noted that the fourth region R4 may have a constant germanium percentage between the relative third regions R3, which is between about 0% germanium and about 20% germanium.

[0151] exist Fig.16IIn one embodiment, the silicon capping layer 1613 may be deposited over the SiGe nanostructure 1670. In one embodiment, the silicon capping layer 1613 may be deposited by CVD, however any suitable deposition method may be used. In one embodiment, the deposition of the silicon capping layer 1613 may be performed in a CVD chamber. In one embodiment, the deposition of the silicon capping layer 1613 utilizes SiH4 or Si2H6 as a reactive gas for the silicon source. The carrier gas used during the deposition of the silicon capping layer 1613 may be H2 gas or N2 gas, or other suitable carrier gas. The deposition process of the silicon capping layer 1613 may be performed at a third process temperature in the range of about 300° C. to about 600° C. and a third process pressure in the range of about 3 Torr to about 100 Torr. In one embodiment, the deposition of the silicon capping layer 1613 may be performed for a time in the range of about 100 seconds to about 300 seconds. The silicon capping layer 1613 may be formed to have a sixth thickness Th6, wherein the sixth thickness Th6 is in the range of about 0.5 nm to about 2 nm. If the thickness of the silicon capping layer 1613 is less than the sixth thickness Th6, sufficient protection of the defect formation of the SiGe nanostructure 1670 may not occur. If the thickness of the silicon capping layer 1613 is greater than the sixth thickness Th6, sufficient space between the channel structures may not be achieved. In one embodiment, the formation of the silicon capping layer 1613 helps prevent defects that protect the silicon germanium nanostructure 1670 from oxidation. Protecting the silicon germanium nanostructure 1670 from oxidation also helps improve the interface with the subsequently formed interface layer 1617 (see below). Figure 16K discussed in more detail).

[0152] exist Fig.16J In the embodiment, the hard mask layer 1601 is removed, and the dielectric structure 1615 can be performed between the second nanostructure 54 in the n-type region 50N and the SiGe nanostructure 1670 in the p-type region. In one embodiment, the hard mask layer 1601 can be removed using an ashing process followed by a wet cleaning process or other suitable photoresist removal process. In addition, the dielectric structure 1615 can include a silicon compound, a nitrogen compound, a carbon compound, an oxygen compound, etc. or a combination thereof. The dielectric structure 1615 can be used to isolate the NMOS element in the n-type region 50N and the PMOS element in the p-type region 50P.

[0153] exist Figure 16K In the embodiment, the interface layer 1617 is formed on the second structure 54, the SiGe nanostructure 1670 (and the silicon capping layer 1613, if present), and on the fin 66. In one embodiment, the interface layer is formed to improve the subsequently formed high-k dielectric layer 1619 ( Fig.17A16 and 16. In one embodiment, the interface layer 1617 comprises silicon oxide, however any suitable material may be used. In addition, the interface layer 1617 may be formed to have a seventh thickness Th7, which is in the range of about 0.5 nm to about 2 nm. If the thickness of the interface layer 1617 is insufficient, sufficient interface quality may not occur between the channel structure and the high-k dielectric layer 1619. If the thickness of the interface layer 1617 is too large, sufficient space between the channel structures may not be achieved.

[0154] exist Fig.17A and Fig. 17B , a high-k dielectric layer 1619 and a gate electrode 102 are formed to replace the gate. The high-k dielectric layer 1619 is conformally deposited in the second groove 98. In the n-type region 50N, the high-k dielectric layer 1619 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54. And in the p-type region 50P, the high-k dielectric layer 1619 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the SiGe nanostructure 1670. The high-k dielectric layer 1619 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68.

[0155] According to some embodiments, the high-k dielectric layer 1619 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the high-k dielectric layer 1619 includes a high-k dielectric material, and in these embodiments, the high-k dielectric layer 1619 may have a k value greater than about 7.0 and may include hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the high-k dielectric layer 1619 in the n-type region 50N and the p-type region 50P may be the same or different. The formation method of the high-k dielectric layer 1619 may include molecular beam deposition (MBD), ALD, PECVD, etc. In addition, the high-k dielectric layer 1619 may be formed to have an eighth thickness Th8, and the eighth thickness Th8 is in the range of about 0.5 nm to about 2 nm. After forming the high-k dielectric layer 1619, the channel gap between the SiGe nanostructures 1670 may have a third width W3 in the range of about 3 nm to about 10 nm. In one embodiment, the SiGe nanostructures 1670 may achieve a threshold voltage in the range of about 100 mV to about 300 mV.

[0156] The gate electrode 102 is deposited over the high-k dielectric layer 1619 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, copper, tungsten, combinations thereof, or multiple layers thereof. For example, although Fig.17A and Fig. 17B A single-layer gate electrode 102 is shown in FIG. 1 , but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent SiGe nanostructures 1670.

[0157] The formation of the high-k dielectric layer 1619 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the high-k dielectric layer 1619 in each region is formed of the same material, and the formation of the gate electrode 102 can be performed simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the high-k dielectric layer 1619 in each region can be formed by different processes, such that the high-k dielectric layer 1619 in each region can be a different material and / or have a different number of layers and / or the gate electrode 102 can be formed by different processes, such that the gate electrode 102 can be a different material and / or have a different number of layers. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0158] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the material of the high-k dielectric layer 1619 and the gate electrode 102 that are above the top surface of the first ILD 96. The remaining portions of the material of the gate electrode 102 and the high-k dielectric layer 1619 thus form a replacement gate structure for the resulting nanoFET. The gate electrode 102 and the high-k dielectric layer 1619 may be collectively referred to as a "gate structure."

[0159] exist 18A to 18C In the embodiment, the gate structure is recessed so that the recess is formed directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. A gate contact formed subsequently penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0160] like 18A to 18CAs further shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed via FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0161] exist FIG. 19A to FIG. 19C In the embodiment of the present invention, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (such as RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; can be etched through the gate mask 104 using a second etching process; and can then be etched through the CESL 94 using a third etching process. A mask such as a photoresist can be formed over the second ILD 106 and patterned to shield portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, since the etching process may cause over-etching, the third recess 108 may extend into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (for example, on the same horizontal plane, or at the same distance as the substrate) or lower than (for example, closer to the substrate) the epitaxial source / drain region 92 and / or the gate structure. Fig.19BThe third recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross section, however, in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed at different cross sections, thereby reducing the risk of shorting of subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) that can react with the semiconductor material of the underlying epitaxial source / drain region 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region or a silicon germanium region (eg, a region containing silicide and germanide). In one embodiment, the silicide region 110 includes TiSi and has a thickness ranging between about 2 nm and about 10 nm.

[0162] Next, in FIG. 20A to FIG. 20C In the embodiment, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer (not shown separately) and a conductive material (not shown separately), and are electrically coupled to the underlying conductive component (e.g., the gate structure 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate structure 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0163] Although the illustrated embodiment shows the same number of channel regions with uniform thickness, width, and spacing in the n-type region (50N) and the p-type region (50P), this is merely illustrative, and the various structures on the n-type region (50N) and the p-type region (50P) and the various structures within the n-type region (50N) and the p-type region (50P) may have different sizes. It should also be noted that although the above embodiments are discussed as performing each process on each structure, this is merely illustrative, and not every structure (e.g., every nanostructure within the n-type region) needs to perform each process on the structure.

[0164] Embodiments can achieve multiple advantages. For example, by varying the germanium concentration on four regions (e.g., first region R1, second region R2, third region R3, and fourth region R4) within SiGe nanostructure 1670, better device performance functions can be achieved through greater control over the device, such as improving the ability to reliably achieve a threshold voltage in the range of 100 microvolts to 300 microvolts. The use of silicon capping layer 1613 helps prevent surface oxidation and defect generation of SiGe nanostructure 1670. In addition, the implementation of interface layer 1617 improves the interface quality between SiGe nanostructure 1670 and high-k dielectric layer 1619.

[0165] According to one embodiment, a device includes a plurality of silicon nanostructures on a semiconductor substrate in an n-type region of the semiconductor substrate, a plurality of silicon germanium nanostructures on a semiconductor substrate in a p-type region of the semiconductor substrate, a high-k dielectric layer, and a gate electrode. At least one of the silicon germanium nanostructures includes a silicon core region having a first germanium concentration, wherein the first germanium concentration is about 20% or less; a first silicon germanium region having a first interface between the silicon core region and the first silicon germanium region; and a second silicon germanium region having a second interface between the first silicon germanium region and the second silicon germanium region, and the second silicon germanium region having a second germanium concentration, wherein the second germanium concentration is up to about 40%, wherein the first concentration gradient of germanium increases from the first germanium concentration at the first interface to the second germanium concentration at the second interface. The high-k dielectric layer surrounds at least one of the plurality of silicon nanostructures and at least one of the plurality of silicon germanium nanostructures. The gate electrode fills a gap between at least one of the adjacent plurality of silicon germanium nanostructures. In one embodiment, at least one of the silicon germanium nanostructures further comprises a third silicon germanium region, the third silicon germanium region having a third interface located between the second silicon germanium region and the third silicon germanium region and an outer surface opposite the third interface, wherein the second concentration gradient of germanium decreases from the second germanium concentration at the third interface to about 0% at the outer surface. In one embodiment, the gap between at least one of the silicon germanium nanostructures is in the range of about 3 nm to about 10 nm. In one embodiment, each of the silicon nanostructures has the same width as each of the silicon germanium nanostructures in the silicon germanium nanostructures. In one embodiment, the device further comprises a silicon capping layer surrounding at least one of the silicon germanium nanostructures. In one embodiment, the silicon capping layer has a thickness in the range of about 0.5 nm to about 2 nm. In one embodiment, the device further comprises an interface layer disposed between at least one of the silicon germanium nanostructures and the high-k dielectric layer, wherein the interface layer comprises silicon oxide. In one embodiment, the device further comprises a dielectric structure disposed between the n-type region and the p-type region, wherein the dielectric structure electrically isolates the silicon nanostructure from the silicon germanium nanostructure.

[0166] According to one embodiment, a method includes: forming a plurality of silicon nanostructures on a semiconductor substrate in an n-type region of the semiconductor substrate; forming a plurality of silicon germanium nanostructures on a semiconductor substrate in a p-type region of the semiconductor substrate, wherein at least one of the silicon germanium nanostructures includes: a silicon core region having a first germanium concentration, wherein the first germanium concentration is about 20% or less; a first silicon germanium region having a first interface between the silicon core region and the first silicon germanium region; and a second silicon germanium region having a second interface between the first silicon germanium region and a second silicon germanium region, the second silicon germanium region having a second germanium concentration, wherein the second germanium concentration is up to about 40%, wherein a first concentration gradient of germanium increases from the first germanium concentration at the first interface to the second germanium concentration at the second interface; depositing a high-k dielectric layer surrounding at least one of the silicon nanostructures and at least one of the silicon germanium nanostructures; and forming a gate electrode filling a gap between at least one of the adjacent silicon germanium nanostructures. In one embodiment, at least one of the silicon germanium nanostructures further comprises a third silicon germanium region, the third silicon germanium region having a third interface located between the second silicon germanium region and the third silicon germanium region and an outer surface opposite the third interface, wherein the second concentration gradient of germanium decreases from the second germanium concentration at the third interface to about 0% at the outer surface. In one embodiment, forming the silicon germanium nanostructure comprises: trimming the silicon nanostructure on the semiconductor substrate in an n-type region of the semiconductor substrate to form a plurality of trimmed silicon nanostructures; depositing silicon germanium over the trimmed silicon nanojunctions; and performing an annealing process to diffuse germanium into the trimmed silicon nanostructures, wherein the annealing process forms a silicon core region, a first silicon germanium region, a second silicon germanium region, and a third silicon germanium region of at least one of the silicon germanium nanostructures. In one embodiment, depositing silicon germanium is chemical vapor deposition performed in a chemical vapor deposition chamber at a first temperature. In one embodiment, the annealing process is performed in the chemical vapor deposition chamber at a second temperature higher than the first temperature. In one embodiment, the method further comprises forming a silicon capping layer surrounding at least one of the silicon germanium nanostructures. In one embodiment, the method further comprises forming an interfacial layer between at least one of the silicon germanium nanostructures and the high-k dielectric layer, wherein the interfacial layer comprises silicon oxide.

[0167] According to one embodiment, a method includes: forming a plurality of nanowires over a plurality of semiconductor fins in an n-type region and a p-type region; forming a hard mask layer over a first plurality of nanowires in the n-type region; performing a trimming process on a second plurality of nanowires in the p-type region; depositing silicon germanium over each of the second plurality of nanowires; and performing an annealing process on the second plurality of nanowires, wherein the annealing process diffuses germanium into at least one of the second plurality of nanowires, thereby forming a plurality of silicon germanium nanostructures in the p-type region, wherein the silicon germanium nanostructures have a plurality of different regions with a plurality of different germanium concentrations. In one embodiment, depositing silicon germanium and the annealing process are performed in the same chemical vapor deposition chamber. In one embodiment, the nanowires include silicon, and the annealing process diffuses germanium at a concentration of up to about 20% into the center of at least one of the nanowires. In one embodiment, depositing silicon germanium is performed at a first temperature, and the annealing process is performed at a second temperature higher than the first temperature. In one embodiment, the method further includes forming a silicon capping layer over at least one of the silicon germanium nanostructures.

[0168] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A plurality of silicon nanostructures are located on a semiconductor substrate in an n-type region of the semiconductor substrate; A plurality of silicon germanium nanostructures are located on the semiconductor substrate in a p-type region of the semiconductor substrate, wherein at least one of the plurality of silicon germanium nanostructures comprises: a silicon core region having a first germanium concentration, wherein the first germanium concentration is 20% or less; a first silicon germanium region having a first interface between the silicon core region and the first silicon germanium region; and a second silicon germanium region having a second interface between the first silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second germanium concentration, wherein the second germanium concentration is up to 40%, wherein a first concentration gradient of germanium increases from the first germanium concentration at the first interface to the second germanium concentration at the second interface; a high-k dielectric layer surrounding at least one of the plurality of silicon nanostructures and at least one of the plurality of silicon germanium nanostructures; and A gate electrode fills a gap between at least one of the adjacent silicon germanium nanostructures.

2. The semiconductor device according to claim 1, wherein At least one of the plurality of silicon germanium nanostructures further includes a third silicon germanium region having a third interface between the second silicon germanium region and the third silicon germanium region and an outer surface opposite to the third interface, wherein a second concentration gradient of germanium decreases from the second germanium concentration at the third interface to 0% at the outer surface.

3. The semiconductor device according to claim 1, wherein A silicon capping layer is also included surrounding at least one of the plurality of silicon germanium nanostructures.

4. The semiconductor device according to claim 1, wherein: The invention also includes an interface layer disposed between at least one of the plurality of silicon germanium nanostructures and the high-k dielectric layer, wherein the interface layer includes silicon oxide.

5. A method for manufacturing a semiconductor device, characterized in that: include: forming a plurality of silicon nanostructures on a semiconductor substrate in an n-type region of the semiconductor substrate; forming a plurality of silicon germanium nanostructures on the semiconductor substrate in a p-type region of the semiconductor substrate, wherein at least one of the plurality of silicon germanium nanostructures comprises: a silicon core region having a first germanium concentration, wherein the first germanium concentration is 20% or less; a first silicon germanium region having a first interface between the silicon core region and the first silicon germanium region; and a second silicon germanium region having a second interface between the first silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second germanium concentration, wherein the second germanium concentration is up to 40%, wherein a first concentration gradient of germanium increases from the first germanium concentration at the first interface to the second germanium concentration at the second interface; depositing a high-k dielectric layer surrounding at least one of the plurality of silicon nanostructures and at least one of the plurality of silicon germanium nanostructures; and A gate electrode is formed to fill a gap between at least one of the adjacent silicon germanium nanostructures.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: At least one of the plurality of silicon germanium nanostructures further includes a third silicon germanium region having a third interface between the second silicon germanium region and the third silicon germanium region and an outer surface opposite to the third interface, wherein a second concentration gradient of germanium decreases from the second germanium concentration at the third interface to 0% at the outer surface.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of the plurality of silicon germanium nanostructures comprises: trimming the plurality of silicon nanostructures on the semiconductor substrate in the n-type region of the semiconductor substrate to form a plurality of trimmed silicon nanostructures; depositing silicon germanium over the plurality of trimmed silicon nanojunctions; and An annealing process is performed to diffuse germanium into the plurality of trimmed silicon nanostructures, wherein the annealing process forms the silicon core region, the first silicon germanium region, the second silicon germanium region, and the third silicon germanium region of at least one of the plurality of silicon germanium nanostructures.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The method also includes forming a silicon capping layer surrounding at least one of the plurality of silicon germanium nanostructures.

9. A method for manufacturing a semiconductor device, characterized in that: include: forming a plurality of nanowires over a plurality of semiconductor fins in an n-type region and a p-type region; forming a hard mask layer over a first plurality of nanowires in the n-type region; Performing a trimming process on a second plurality of nanowires in the p-type region; depositing silicon germanium over each nanowire in the second plurality of nanowires; as well as An annealing process is performed on the second plurality of nanowires, wherein the annealing process diffuses germanium into at least one of the second plurality of nanowires to form a plurality of silicon germanium nanostructures in the p-type region, wherein the plurality of silicon germanium nanostructures have a plurality of different regions with a plurality of different germanium concentrations.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The method also includes forming a silicon capping layer over at least one of the plurality of silicon germanium nanostructures.

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