Semiconductor device

Abstract

The semiconductor device includes: an active region extending in a first direction on a substrate; channel layers on the active region and vertically spaced apart; a gate structure crossing the active region and the channel layer, the gate structure extending in a second direction and surrounding the channel layer; and a source / drain region on the active region on one side of the gate structure, the source / drain region contacting the channel layer, the source / drain region including a first epitaxial layer and a second epitaxial layer, the first epitaxial layer having a first component and including a first layer on a side surface of the channel layer and a second layer on the active region at a lower end of the source / drain region, the second epitaxial layer has a second composition different from the first composition, is located between the first epitaxial layers in the first direction, and is vertically located between the first epitaxial layers in the third direction.

Description

[0001] This application is a divisional application based on the Chinese patent application filed on January 7, 2020, with application number 202010014972.1 and invention name “Semiconductor Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] Korean Patent Application No. 2019 filed on January 8, 2019, entitled “Semiconductor Devices”, filed in the Korean Intellectual Property Office.

[0004] 10-2019-0002425, Korean Patent Application No. filed on January 25, 2019

[0005] 10-2019-0009967 and Korean Patent Application No.

[0006] 10-2019-0068893 is incorporated herein by reference in its entirety. Technical Field

[0007] Example embodiments relate to a semiconductor device. Background Art

[0008] As the demand for high performance, high speed, multi-function, etc. of semiconductor devices increases, the integration density of semiconductor devices has been improved. In order to meet the demand for high integration density of semiconductor devices, semiconductor devices with fine patterns have been developed, and it has become important to implement patterns with fine widths or fine spacing therebetween. In addition, in order to overcome the limitation of the operating performance of planar metal oxide semiconductor FETs (MOSFETs) with reduced size, the development of semiconductor devices including fin FETs (FinFETs) with three-dimensional channels has been carried out. Summary of the invention

[0009] An embodiment relates to a semiconductor device, comprising: an active area extending in a first direction on a substrate; a plurality of channel layers located on the active area and vertically spaced apart from each other; a gate structure intersecting the active area and the plurality of channel layers, the gate structure extending in a second direction on the substrate and surrounding the plurality of channel layers; and a source / drain area located on the active area on at least one side of the gate structure, the source / drain area contacting the plurality of channel layers, the source / drain area comprising: respective first epitaxial layers having a first composition and including a first layer and a second layer, the first layer being located on a side surface of the plurality of channel layers taken in the first direction, the second layer being located on the active area at a lower end of the source / drain area; and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being interposed between the first epitaxial layers in the first direction and vertically interposed between the first epitaxial layers in a third direction, wherein the third direction is perpendicular to the first direction and the second direction.

[0010] An embodiment also relates to a semiconductor device comprising: an active area; a plurality of channel layers located on the active area and vertically spaced apart from each other; a gate structure surrounding an upper surface, a lower surface and a side surface taken in a first direction of the plurality of channel layers; and a source / drain region located on the active area on at least one side of the gate structure, the source / drain region contacting the plurality of channel layers, the source / drain region comprising: at least one first epitaxial layer having a first composition and covering the side surfaces taken in a second direction of the plurality of channel layers and covering at least a portion of the upper surface of the active area at the lower end of the source / drain region; and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being stacked on the first epitaxial layer and extending upward further than the uppermost surfaces of the plurality of channel layers.

[0011] An embodiment also relates to a semiconductor device, comprising: an active area extending in a first direction on a substrate; a plurality of channel layers located on the active area and vertically spaced apart from each other; a gate structure intersecting the active area and the plurality of channel layers, the gate structure extending in a second direction on the substrate and surrounding the plurality of channel layers; an internal spacer layer located on an opposite side of the gate structure taken in the first direction, the internal spacer layer being disposed in a lower portion of each of the plurality of channel layers; and a source / drain area located on the active area on at least one side of the gate structure, the source / drain area contacting the plurality of channel layers and including a plurality of epitaxial layers, and having a concentration gradient corresponding to a vertical arrangement of the internal spacer layer and the plurality of channel layers in a third direction, wherein the third direction is perpendicular to the first direction and the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Features will become apparent to those skilled in the art by describing example embodiments in detail with reference to the accompanying drawings, in which:

[0013] Figure 1shows a plan view of a semiconductor device according to an example embodiment;

[0014] Figure 2 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Figure 3 shows an enlarged view of a portion of a semiconductor device according to an example embodiment;

[0016] FIG. 4A to FIG. 5B A diagram illustrating a distribution of concentration of impurities included in source / drain regions in a semiconductor device according to example embodiments;

[0017] Figure 6 shows an enlarged view of a portion of a semiconductor device according to an example embodiment;

[0018] Figure 7 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0019] Figure 8 shows an enlarged view of a portion of a semiconductor device according to an example embodiment;

[0020] Fig. 9 shows an enlarged view of a portion of a semiconductor device according to an example embodiment;

[0021] FIG. 10A to FIG. 10C shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0022] FIG. 11A to FIG. 11K A diagram showing processes of a method of manufacturing a semiconductor device according to an example embodiment in order;

[0023] Fig.12 A block diagram showing an electronic apparatus including a semiconductor device according to example embodiments; and

[0024] Fig.13 A diagram of a system including a semiconductor device according to example embodiments is shown. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments will be described with reference to the accompanying drawings as follows.

[0026] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments. Figure 2 The diagram taken along line II' and line II-II' is shown. Figure 1 For ease of description, only the cross section of the semiconductor device is shown in FIG. Figure 1 and Figure 2 The main components of a semiconductor device are shown in FIG.

[0027] Reference Figure 1 and Figure 2 , the semiconductor device 100 may include: a substrate 101; an active region 105 located on the substrate 101; a channel structure 140 including a plurality of channel layers 141, 142, and 143 located on the active region 105 and vertically spaced apart from each other; a source / drain region 150 in contact with the plurality of channel layers 141, 142, and 143; a gate structure 160 intersecting the active region 105 and extending in the Y direction; and a contact plug 180 connected to the source / drain region 150. The semiconductor device 100 may further include a device isolation layer 110, an internal spacer layer 130, and an interlayer insulating layer 190. The gate structure 160 may include a gate dielectric layer 162, a gate electrode 165, a gate spacer layer 164, and a gate capping layer 166.

[0028] In the semiconductor device 100, the active region 105 may have a fin-shaped structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the plurality of channel layers 141, 142, and 143 of the channel structure 140, and in an upper portion of the channel structure 140. Therefore, the semiconductor device 100 may include a surround gate field effect transistor (FET) formed by the channel structure 140, the source / drain regions 150, and the gate structure 160. The transistor may be, for example, an NMOS transistor.

[0029] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as, for example, a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0030] The device isolation layer 110 may define the active area 105 on the substrate 101. For example, the device isolation layer 110 may be formed by a shallow trench isolation (STI) process. In an example embodiment, the device isolation layer 110 may also include a region having a step portion and extending toward the lower portion of the substrate 101. The device isolation layer 110 may partially expose the upper portion of the active area 105. In an example embodiment, the device isolation layer 110 may have a curved upper surface, and its horizontal height may increase toward the active area 105. The device isolation layer 110 may be formed of an insulating material. For example, the device isolation layer 110 may be an oxide, a nitride, or a combination thereof.

[0031] The active region 105 may be defined by the device isolation layer 110 and may extend in a first direction (e.g., X direction) in the substrate 101. The active region 105 may be configured to protrude from the substrate 101. The upper end of the active region 105 may be configured to protrude from the upper surface of the device isolation layer 110 to a specific height. The active region 105 may be a portion of the substrate 101, or may include an epitaxial layer grown from the substrate 101. In both side regions of the gate structure 160, a portion of the active region 105 on the substrate 101 may be recessed, and the source / drain region 150 may be disposed in the recessed active region 105. The active region 105 may include impurities (e.g., dopants), or may include a doped region containing impurities.

[0032] The channel structure 140 may include two or more channel layers (e.g., first to third channel layers 141, 142, and 143) vertically spaced apart from each other on the active region 105 in a direction perpendicular to the upper surface of the active region 105 (e.g., the Z direction). The first to third channel layers 141, 142, and 143 may be connected to the source / drain region 150 and may be spaced apart from the upper surface of the active region 105. The width of the first to third channel layers 141, 142, and 143 may be the same or similar to the width of the active region 105 in the Y direction, and may be the same or similar to the width of the gate structure 160 in the X direction. In example embodiments, the first to third channel layers 141, 142, and 143 may also have a reduced width so that the side surfaces of the first to third channel layers 141, 142, and 143 may be disposed in the lower portion of the gate structure 160 in the X direction.

[0033] The first to third channel layers 141, 142, and 143 may be formed of a semiconductor material. For example, the first to third channel layers 141, 142, and 143 may include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first to third channel layers 141, 142, and 143 may be formed of the same material as the material of the substrate 101. In example embodiments, the first to third channel layers 141, 142, and 143 may include an impurity region, which is disposed in an area adjacent to the source / drain region 150. The number and shape of the channel layers 141, 142, and 143 included in a single channel structure 140 may be changed in example embodiments. For example, in example embodiments, the channel structure 140 may also include a channel layer located on the upper surface of the active region 105.

[0034] The source / drain region 150 may be located on the active region 105 on both side regions of the channel structure 140. The source / drain region 150 may include a first epitaxial layer 152 located on each side surface of the first to third channel layers 141, 142, and 143 of the channel structure 140 and on the active region 105 in the lower end of the source / drain region 150. The source / drain region 150 may further include a second epitaxial layer 154 filling a space between the first epitaxial layers 152. The first epitaxial layer 152 and the second epitaxial layer 154 may be semiconductor layers including silicon (Si), and may include impurities of different types and / or different concentrations from each other.

[0035] The first epitaxial layer 152 may include a first layer 152A located on the side surfaces of the first to third channel layers 141, 142, and 143 and a second layer 152B located on the upper surface of the active region 105. The first layer 152A may be located on both side surfaces of the channel structure 140 in the X direction. When the first layer 152A is located on both side surfaces of the channel structure 140, the short channel effect caused by the diffusion of impurities included in the second epitaxial layer 154 may be reduced or prevented. The first layer 152A may be separated from each other among the first channel layer 141, the second channel layer 142, and the third channel layer 143 vertically arranged in the Z direction. The first layer 152A may also be separated from the second layer 152B. In addition, the first layer 152A may protrude toward the second epitaxial layer 154 from the coplanar side surface formed by the internal spacer layer 130 and the first to third channel layers 141, 142, and 143. Therefore, the second epitaxial layer 154 may be interposed between the first layers 152A spaced apart from each other in the Z direction. The second epitaxial layer 154 may also be interposed between the first layers 152A spaced apart from each other in the X direction in a single source / drain region 150. On a plane, at least a portion of the first epitaxial layer 152 may overlap with the second epitaxial layer 154, and may be configured not to overlap with the inner spacer layer 130.

[0036] The second layer 152B may be located on at least a portion of the upper surface of the active region 105 in the lower portion. For example, the second layer 152B may be disposed in a central region, for example, taken in the X direction. The maximum thickness of the second layer 152B may be greater than the thickness of the first layer 152A. The width of the upper portion of the second layer 152B may be less than the width of the lower portion of the second layer 152B, and the second layer 152B may have an upwardly curved shape. The shape of the lower surface of the source / drain region 150 may be changed in example embodiments. For example, the lower surface of the source / drain region 150 may be curved at different depths, or may have a planar shape. Therefore, the shape of the second layer 152B may also be changed in example embodiments.

[0037] The first epitaxial layer 152 may be a region including an impurity having a higher concentration than that of the impurity included in the active region 105. The first epitaxial layer 152 may be epitaxially grown from the first channel layer to the third channel layers 141, 142, and 143 and the active region 105. For example, the first epitaxial layer 152 may include an n-type impurity such as arsenic (As) and / or phosphorus (P). For example, the first epitaxial layer 152 may be a SiAs layer, a SiP layer, a SiPC layer, a SiC layer, a SiPAs layer, or a SiGeP layer. The concentration of the impurity included in the first epitaxial layer 152 may be about 2×10 20 / cm 3 Up to 8×10 20 / cm 3 For example, the thickness of each first layer 152A may be in the range of about 4 nm to 8 nm, and the thickness of the second layer 152B may be greater than the thickness of the first layer 152A.

[0038] The second epitaxial layer 154 may be configured to fill the region between adjacent channel structures 140. The second epitaxial layer 154 may surround the surface of the first epitaxial layer 152 on which the first epitaxial layer 152 is not in contact with the channel structure 140 or the active area 105. The second epitaxial layer 154 may cover the side surface of the inner spacer layer 130. The second epitaxial layer 154 may be configured to fill the space between the first layers 152A of the first epitaxial layer 152 spaced apart from each other upward and downward. Therefore, at least a portion of the second epitaxial layer 154 may overlap each of the first layer 152A and the second layer 152B of the first epitaxial layer 152 in a plane. The second epitaxial layer 154 may extend upward further than the uppermost surface of the channel structure 140.

[0039] The second epitaxial layer 154 may have a composition different from that of the first epitaxial layer 152. For example, the second epitaxial layer 154 may be a region including an impurity having a higher concentration than that of the impurity included in the first epitaxial layer 152. The second epitaxial layer 154 may be epitaxially grown from the first epitaxial layer 152. The impurity may be the same as or different from the impurity included in the first epitaxial layer 152. For example, the first epitaxial layer 152 may include a first impurity of a first conductivity type at a first concentration, and the second epitaxial layer 154 may include the same first impurity or second impurity of the first conductivity type at a second concentration higher than the first concentration. The second concentration may be in a range of 10 to 20 times the first concentration. The concentration of the impurity included in the second epitaxial layer 154 may be about 3.1×10 21 / cm 3 to 3.9×10 21 / cm 3For example, the second epitaxial layer 154 may be a SiP layer including phosphorus (P). In example embodiments, the first epitaxial layer 152 may be a SiP or SiAs epitaxial layer, and the second epitaxial layer 154 may be a SiP epitaxial layer.

[0040] The impurity of the second epitaxial layer 154 may be partially diffused into the adjacent first epitaxial layer 152, and the impurity may be partially included in the first epitaxial layer 152 at a concentration lower than that in the second epitaxial layer 154. In addition, the impurity of the first epitaxial layer 152 may be partially diffused into the adjacent second epitaxial layer 154, and the impurity may be partially included in the second epitaxial layer 154 at a concentration lower than that in the first epitaxial layer 152. The first epitaxial layer 152 and the second epitaxial layer 154 may be formed as epitaxial layers. Therefore, damage to the film caused by the ion implantation process when the first epitaxial layer 152 and the second epitaxial layer 154 are formed as doped regions may be avoided, which may help improve the electrical properties of the semiconductor device 100.

[0041] The gate structure 160 may intersect the active region 105 and the channel structure 140, and may extend in one direction (e.g., the Y direction) in the upper portion of the active region 105 and the channel structure 140. The channel region of the transistor may be formed in the active region 105 and the channel structure 140 intersecting the gate structure 160. The gate structure 160 may include: a gate electrode 165; a gate dielectric layer 162 disposed between the gate electrode 165 and the first to third channel layers 141, 142, and 143; a gate spacer layer 164 located on the side surface of the gate electrode 165; and a gate cap layer 166 located on the upper surface of the gate electrode 165.

[0042] The gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165. The gate dielectric layer 162 may be configured to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may surround all surfaces of the gate electrode 165 except for the uppermost surface. For example, the gate dielectric layer 162 may extend to the space between the gate electrode 165 and the gate spacer layer 164. For example, the gate dielectric layer 162 may include an oxide, a nitride, or a high-k material. The high-k material may refer to a material having a dielectric constant that is higher than that of silicon oxide (SiO 2 ) film has a high dielectric constant. For example, the high-k material can be aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 )

[0043] The gate electrode 165 may fill the space between the first to third channel layers 141, 142, and 143 in the upper portion of the active region 105, and may extend to the upper portion of the channel structure 140. The gate electrode 165 may be spaced apart from the plurality of channel layers 141, 142, and 143 by the gate dielectric layer 162. The gate electrode 165 may include a conductive material. For example, the gate electrode 165 may include a metal nitride material (such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film) and / or a metal material (such as aluminum (Al), tungsten (W), molybdenum (Mo), etc.) or a semiconductor material (such as doped polysilicon). The gate electrode 165 may include multiple layers, for example, two or more layers. The gate electrode 165 may be separated from each other by a separation portion between at least a portion of adjacent transistors, depending on the configuration of the semiconductor device 100.

[0044] The gate spacer layer 164 may be located on both side surfaces of the gate electrode 165. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. In example embodiments, the gate spacer layer 164 may have a multilayer structure. For example, the gate spacer layer 164 may be formed of oxide, nitride, or oxynitride, and may be formed of a low-k material film.

[0045] The gate capping layer 166 may be disposed on an upper portion of the gate electrode 165 , and each of a lower surface and a side surface of the gate capping layer 166 may be surrounded by the gate electrode 165 and the gate spacer layer 164 .

[0046] The inner spacer layer 130 may be disposed between the channel structures 140 in parallel with the gate electrode 165. The gate electrode 165 may be spaced apart from and electrically isolated from the source / drain region 150 by the inner spacer layer 130 in the lower portion of the third channel layer 143. For example, a side surface of the inner spacer layer 130 facing the gate electrode 165 may be recessed and curved toward the gate electrode 165. For example, the inner spacer layer 130 may be formed of oxide, nitride, or oxynitride, and may be formed of a low-k material film.

[0047] The contact plug 180 may penetrate the interlayer insulating layer 190 and may be connected to the source / drain region 150. The contact plug 180 may apply an electrical signal to the source / drain region 150. The contact plug 180 may be located at a position such as Figure 1 142, and may have a length in the Y direction that is longer than that of the source / drain region 150. For example, the contact plug 180 may have an inclined side surface in which the width of the lower portion is smaller than the width of the upper portion according to the aspect ratio. For example, the contact plug 180 may extend further downward from the upper portion than the third channel layer 143. In example embodiments, for example, the contact plug 180 may be recessed at a height corresponding to the upper surface of the second channel layer 142. In example embodiments, the contact plug 180 may not be recessed into the source / drain region 150, and may be configured to contact the upper surface of the source / drain region 150 and be disposed along the upper surface of the source / drain region 150. For example, the contact plug 180 may include a metal nitride material (such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film) and / or a metal material (such as aluminum (Al), tungsten (W), molybdenum (Mo), etc.).

[0048] The interlayer insulating layer 190 may cover the source / drain regions 150 and the gate structure 160, and may be configured to cover the device isolation layer 110 in a region not shown in the drawings. For example, the interlayer insulating layer 190 may include oxide, nitride, or oxynitride, and may include a low-k material.

[0049] Figure 3 It is shown Figure 2 FIG. 4 is a diagram of an enlarged region A of a semiconductor device according to example embodiments.

[0050] Reference Figure 3 , the first layer 152A of the first epitaxial layer 152 may be respectively located on the side surfaces of the first to third channel layers 141, 142, and 143, and may be vertically spaced apart from each other by a first spacing distance D1 in the Z direction. The first layer 152A may be spaced apart from the second layer 152B by a second spacing distance D2 (shortest distance) on the active region 105. The first spacing distance D1 may be different from the second spacing distance D2.

[0051] A portion of the first layer 152A may extend onto the side surface of the inner spacer layer 130. In another embodiment, the first layer 152A may be configured to be located only on the side surfaces of the first to third channel layers 141, 142, and 143. Each of the first layers 152A may have a first maximum thickness T1 from the side surfaces of the first to third channel layers 141, 142, and 143, and the second layer 152B may have a second maximum thickness T2 from the upper surface of the active region 105. For example, the second maximum thickness T2 may be greater than the first maximum thickness T1.

[0052] Figure 4A and Figure 4B Shown along Figure 3 The distribution profile of the concentration of the impurities included in the source / drain region 150 is cut by the line BB′ shown in FIG. Figure 4A shows a profile when the first epitaxial layer 152 and the second epitaxial layer 154 include the same impurities, Figure 4B A profile is shown when the first epitaxial layer 152 includes a first impurity and the second epitaxial layer 154 includes a second impurity different from the first impurity.

[0053] exist Figure 4A and Figure 4B , the first portion L1 may be a region corresponding to the first epitaxial layer 152 of the source / drain region 150, and the second portion L2 may be a region corresponding to the second epitaxial layer 154. In addition, the first portion L1 may be a region corresponding to at least a portion of the outer region of the first to third channel layers 141, 142, and 143, and the second portion L2 may include a region corresponding to the outer region of the inner spacer layer 130.

[0054] like Figure 4A As shown in FIG. 1 , the first epitaxial layer 152 may include impurities at a first concentration C1, and the second epitaxial layer 154 may include impurities at a second concentration C2 higher than the first concentration C1. The first concentration C1 and the second concentration C2 may be the maximum concentrations of the first portion L1 and the second portion L2. For example, the second concentration C2 may be in a range of about 10 to 20 times the first concentration C1. As described above, the source / drain region 150 may have a concentration gradient corresponding to the inner spacer layer 130 and the first to third channel layers 141, 142, and 143 in the outer region of the inner spacer layer 130 and the first to third channel layers 141, 142, and 143 in the Z direction. In addition, since the contours with different concentrations appear alternately, it appears that the first portion L1 and the second portion L2 can be distinguished from each other.

[0055] In example embodiments, the concentration variation of impurities on the boundary between the first portion L1 and the second portion L2 may be steeper or gentler than the concentration variation in the example shown in the drawings. In addition, a portion in which the concentration of impurities is constant or uniform may appear in each of the portions L1 and L2. However, in example embodiments, a peak value of the concentration of impurities may appear in each of the portions L1 and L2. In another embodiment, the maximum concentration of impurities in the second layer 152B may be the first concentration C1.

[0056] like Figure 4B In the example shown in FIG. 1 , even when the first epitaxial layer 152 and the second epitaxial layer 154 include different impurities, profiles having different concentrations may alternately appear in the first portion L1 and the second portion L2. The first epitaxial layer 152 may further include the second impurity at least in a region adjacent to the second epitaxial layer 154, and the second epitaxial layer 154 may further include the first impurity in a region adjacent to the first epitaxial layer 152.

[0057] Figure 5A and Figure 5B Shown along Figure 3 The line CC′ shown in FIG. 1 cuts off a profile of impurities included in the source / drain region 150 . Figure 5A shows a profile when the first epitaxial layer 152 and the second epitaxial layer 154 include the same impurities, Figure 5B A profile is shown when the first epitaxial layer 152 includes a first impurity and the second epitaxial layer 154 includes a second impurity different from the first impurity.

[0058] exist Figure 5A and Figure 5B In the embodiment, the first portion L1 may be a region corresponding to the first epitaxial layer 152 of the source / drain region 150 , and the second portion L2 may be a region corresponding to the second epitaxial layer 154 .

[0059] like Figure 5A , in the second epitaxial layer 154 including the center taken in the X direction, the source / drain region 150 may include impurities at a second concentration C2, and the first epitaxial layer 152 on both ends may include impurities at a first concentration C1 lower than the second concentration C2. The source / drain region 150 may have a portion where the concentration of the impurities is substantially constant or uniform in a central region (region of the second epitaxial layer 154) including the center. In example embodiments, the concentration variation of the impurities on the boundary between the first portion L1 and the second portion L2 may be steeper or gentler than the concentration variation in the example shown in the drawings.

[0060] like Figure 5BAs shown in FIG. 1 , even when the first epitaxial layer 152 and the second epitaxial layer 154 include different impurities, profiles having different concentrations (e.g., different maximum concentrations) may appear in the first portion L1 and the second portion L2 in a corresponding manner. The first epitaxial layer 152 may further include the second impurity at least in a region adjacent to the second epitaxial layer 154, and the second epitaxial layer 154 may further include the first impurity in a region adjacent to the first epitaxial layer 152.

[0061] Figure 6 is a diagram illustrating an enlarged portion of a semiconductor device according to example embodiments. Figure 6 Shown with Figure 2 The area A shown in FIG.

[0062] Reference Figure 6 In the semiconductor device 100 a , the source / drain region 150 a may include a first epitaxial layer 152 and a second epitaxial layer 154 filling a space between the first epitaxial layers 152 , and may further include a third epitaxial layer 151 configured to contact the first epitaxial layer 152 .

[0063] The third epitaxial layer 151 may be located on the side surfaces of the first to third channel layers 141, 142, and 143, respectively, and may be located on at least a portion of the upper surface of the active region 105 at the lower end of the source / drain region 150a. The third epitaxial layer 151 may be a layer configured to facilitate the growth of the first epitaxial layer 152 or reduce the lattice mismatch of the first epitaxial layer 152. For example, the third epitaxial layer 151 may be a SiAs layer, a SiP layer, a SiPC layer, a SiC layer, a SiPAs layer, or a SiGeP layer. The third epitaxial layer 151 may include impurities at a concentration lower than that of the impurities included in the first epitaxial layer 152, or may not include impurities. In example embodiments, the third epitaxial layer 151 may be located only on portions of the side surfaces of the first to third channel layers 141, 142, and 143. In example embodiments, the size of the region in which the third epitaxial layer 151 contacts the upper surface of the active region 105 may vary.

[0064] Figure 7 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 7 shows that along with Figure 1 The area corresponding to the cross-sections taken by lines II' and II-II'. Figure 8 is a diagram illustrating an enlarged portion of a semiconductor device according to example embodiments. Figure 8 Shown in magnified form Figure 7 Area A' is shown in FIG.

[0065] Reference Figure 7 and Figure 8, in the source / drain region 150b in the semiconductor device 100b, the first epitaxial layer 152b may be provided as a single layer that extends along the side surfaces of the first to third channel layers 141, 142, and 143 of the channel structure 140 and the side surface of the internal spacer layer 130, and forms the lower surface of the source / drain region 150b at the lower end. Therefore, the first epitaxial layer 152b may be configured to completely surround the lower surface and the side surface of the second epitaxial layer 154b in the X direction. Therefore, the second epitaxial layer 154b may not be in direct contact with the active region 105.

[0066] The first epitaxial layer 152b may contact the gate spacer layer 164 at an upper end of the first epitaxial layer 152b. A length D3 of the first epitaxial layer 152b in contact with the gate spacer layer 164 may vary in example embodiments, or the first epitaxial layer 152b may not contact the gate spacer layer 164 in another implementation.

[0067] In example embodiments, the thickness of the first epitaxial layer 152b may be non-uniform. The first epitaxial layer 152b may have a third maximum thickness T3 on the sidewalls of the first to third channel layers 141, 142, and 143, and may have a fourth maximum thickness T4 greater than the third maximum thickness T3 at the lower portion. In example embodiments, the fourth maximum thickness T4 may be twice or more times the third maximum thickness T3. The first epitaxial layer 152b may have a fifth thickness T5 smaller than the third maximum thickness T3 on the sidewalls of the inner spacer layer 130, and may have a flexure formed with the thickness. The structure of the first epitaxial layer 152b may be controlled according to the growth direction, the growth thickness, and the like. The depth of the downward flexure of the lower surface of the source / drain region 150b may be changed in example embodiments, whereby the shape of the first epitaxial layer 152b may also be changed on the lower surface of the source / drain region 150.

[0068] Fig. 9 is an enlarged view illustrating a portion of a semiconductor device according to example embodiments. Fig. 9 Shown with Figure 7 The area A' shown in FIG.

[0069] Reference Fig. 9 In the semiconductor device 100c, the source / drain region 150c may include a first epitaxial layer 152c. The source / drain region 150c may also include a second epitaxial layer 154c filling a space between the first epitaxial layers 152c, and may also include a third epitaxial layer 151 contacting the first epitaxial layer 152c at, for example, the bottom of the first epitaxial layer 152c.

[0070] As reference Figure 6As described, the third epitaxial layer 151 may be located on the side surfaces of the first to third channel layers 141, 142, and 143, respectively, and may be located on at least a portion of the upper surface of the active region 105 at the lower end of the source / drain region 150c. The first epitaxial layer 152c may be provided as a single layer that covers the surface on which the third epitaxial layer 151 does not contact the first to third channel layers 141, 142, and 143. The second epitaxial layer 154c may be provided as a single layer that fills the space between the first epitaxial layers 152c.

[0071] FIG. 10A to FIG. 10C is a cross-sectional view illustrating a semiconductor device according to example embodiments. Fig. 10A and Fig. 10B shows that along with Figure 1 The area corresponding to the cross-section taken by lines II-I' and II-II' in Fig. 10C shows that along with Figure 1 The area corresponding to the cross section taken by line II-II'.

[0072] Reference Fig. 10A , the semiconductor device 100d may not include the inner spacer layer 130 (with reference to Figure 2 The gate electrode 165 may extend in the X direction among the first to third channel layers 141, 142, and 143 of the channel structure 140. Therefore, both side surfaces of the gate electrode 165 taken in the X direction may be arranged side by side upward and downward with both side surfaces of the channel structure 140, and may be coplanar with both side surfaces of the channel structure 140.

[0073] Reference Fig. 10B In the semiconductor device 100e, both side surfaces of the channel structure 140 and the inner spacer layer 130 taken in the X direction may be disposed in the lower portion of the gate structure 160 (with reference to Figure 2 The example embodiments described are different). Therefore, the channel structure 140 may have a smaller width relative to the width of the gate structure 160. Therefore, at least a portion of the first layer 152A of the first epitaxial layer 152 may overlap the gate structure 160 in a plane. Fig. 10B For example, both side surfaces taken in the X direction of the channel structure 140 and the inner spacer layer 130 may be disposed in a lower portion of the gate spacer layer 164. For example, in example embodiments, the side surfaces may be disposed in a lower portion of the gate electrode 165.

[0074] Reference Fig. 10C In the semiconductor device 100f, the widths of the active region 105a and the channel structure 140a may be Figure 2The active region 105a and the channel structure 140a may have a relatively narrow width, and therefore, each of the plurality of channel layers 141a, 142a, and 143a of the channel structure 140a may have a circular shape, an elliptical shape (in which the difference between the length of the major axis and the minor axis is relatively small in a cross section taken along the Y direction), etc. For example, in Figure 2 In the example embodiment shown in , each of the plurality of channel layers 141, 142, and 143 may have a width of about 20 nm to 50 nm in the Y direction, and in the example embodiment, each of the plurality of channel layers 141a, 142a, and 143a may have a width of about 3 nm to 12 nm in the Y direction. In example embodiments, the width of the active region 105a and the channel structure 140a and the shapes of the active region 105a and the channel structure 140a formed along the width may vary.

[0075] FIG. 11A to FIG. 11K are diagrams illustrating sequential processes of a method of fabricating a semiconductor device according to example embodiments. FIG. 11A to FIG. 11K Shows the manufacturing Figure 6 An exemplary embodiment of a method for a semiconductor device is shown in Figure 2 The cross section shown in corresponds to the cross section.

[0076] Reference Fig.11A The sacrificial layer 120 may be alternately stacked between the channel layers 141, 142, and 143 on the substrate 101 (the sacrificial layer 120 may be processed by subsequent steps such as Figure 2 142 and 143). The sacrificial layer 120 may be formed of a material having an etching selectivity relative to the plurality of channel layers 141, 142, and 143. The plurality of channel layers 141, 142, and 143 may include a material different from that of the sacrificial layer 120. For example, the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may include a semiconductor material including at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and may include different materials, and the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may include impurities or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the plurality of channel layers 141, 142, and 143 may include silicon (Si).

[0077] The sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may be formed by performing an epitaxial growth process using the substrate 101 as a seed. Each of the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may have a thickness of approximately The number of layers of the plurality of channel layers 141 , 142 , and 143 alternately stacked with the sacrificial layer 120 may vary in example embodiments.

[0078] Reference Fig. 11B , an active structure may be formed by removing a portion of the substrate 101 and a stacked structure of the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143. The active structure may include the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 alternately stacked, and may further include an active region 105 configured to protrude from the upper surface of the substrate 101 by removing a portion of the substrate 101. The active structure may be configured to have a line form extending in one direction (e.g., the X direction), and may be spaced apart from each other in the Y direction.

[0079] In the region from which a portion of the substrate 101 is removed, a device isolation layer 110 may be formed by filling the region with an insulating material and configuring the insulating material to be recessed to allow the active region 105 to protrude. The upper surface of the device isolation layer 110 may be formed to be disposed lower than the upper surface of the active region 105.

[0080] Reference Fig. 11C , a sacrificial gate structure 170 and a gate spacer layer 164 may be formed on the active structure.

[0081] The sacrificial gate structure 170 may be a sacrificial structure formed in a region in which the gate dielectric layer 162 and the gate electrode 165 are disposed in the upper portion of the channel structure 140. The sacrificial gate structure 170 may include a first sacrificial gate layer 172 and a second sacrificial gate layer 175 stacked sequentially, and a mask pattern layer 176. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be patterned using the mask pattern layer 176. For example, the first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be an insulating layer and a conductive layer, respectively. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be configured to be integrated into a single layer. For example, the first sacrificial gate layer 172 may include silicon oxide, and the second sacrificial gate layer 175 may include polysilicon. The mask pattern layer 176 may include silicon oxide and / or silicon nitride. The sacrificial gate structure 170 may have a line form that intersects with the active structure and extends in one direction. For example, the sacrificial gate structure 170 may extend in the Y direction and may be spaced apart from each other in the X direction.

[0082] The gate spacer layer 164 may be located on both sidewalls of the sacrificial gate structure 170. The gate spacer layer 164 may be formed by forming a film having a uniform thickness along the upper and side surfaces of the sacrificial gate structure 170 and the active structure and performing an anisotropic etching process. The gate spacer layer 164 may be formed of a low-k material and may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0083] Reference Fig.11D , a recess region RC may be formed by removing the exposed sacrificial layer 120 and the plurality of channel layers 141 , 142 , and 143 between the sacrificial gate structures 170 , thereby forming the channel structure 140 .

[0084] The exposed sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may be removed using the sacrificial gate structure 170 and the gate spacer layer 164 as a mask. Thus, each of the plurality of channel layers 141, 142, and 143 may have a defined length in the X direction, and the channel structure 140 may be formed. Fig. 10B As shown in FIG. 1 , the sacrificial layer 120 and the channel structure 140 may be partially removed from the side surface of the sacrificial gate structure 170 in the lower portion of the sacrificial gate structure 170 , and both side surfaces taken in the X direction may be disposed in the lower portion of the sacrificial gate structure 170 or the gate spacer layer 164 .

[0085] Reference Fig.11E , the exposed sacrificial layer 120 may be partially removed from the side surface.

[0086] The sacrificial layer 120 may be selectively etched with respect to the channel structure 140 by a wet etching process, and may be removed to a certain depth from a side surface taken in the X direction. For example, the sacrificial layer 120 may have an inwardly recessed side surface by the above-mentioned side surface etching process.

[0087] Reference Fig.11F , the inner spacer layer 130 may be formed in the region from which the sacrificial layer 120 is removed.

[0088] The inner spacer layer 130 may be formed by filling the region from which the sacrificial layer 120 is removed with an insulating material and removing the insulating material deposited in the outer region of the channel structure 140. For example, the inner spacer layer 130 may be formed of the same material as that of the gate spacer layer 164. For example, the inner spacer layer 130 may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0089] Reference Fig.11G, a third epitaxial layer 151 for forming the source / drain region 150 a may be disposed in the recess region RC on both side regions of the sacrificial gate structure 170 .

[0090] The third epitaxial layer 151 may be formed on the side surfaces of the first to third channel layers 141, 142, and 143 by the SEG process, and may also be formed in the active region 105 on the bottom surface of the recessed region RC. The third epitaxial layer 151 may include impurities at a lower concentration than the concentration of impurities included in the first epitaxial layer 152 and the second epitaxial layer 154 formed in a subsequent process. However, in the case of Figure 2 In the example embodiment shown in FIG. 1 , the process of forming the third epitaxial layer 151 may not be performed in the example embodiment.

[0091] Reference Fig.11H , a first epitaxial layer 152 of the source / drain region 150 a may be formed in the recessed region RC.

[0092] The first epitaxial layer 152 may be formed by epitaxial growth from the third epitaxial layer 151, and may include impurities by an in-situ doping process. The first epitaxial layer 152 may be a SiAs layer, a SiP layer, a SiPC layer, a SiC layer, a SiPAs layer, or a SiGeP layer. The first layer 152A of the first epitaxial layer 152 may be formed on the side surfaces of the first to third channel layers 141, 142, and 143, and the second layer 152B may be formed on the third epitaxial layer 151 on the bottom surface of the recessed region RC. The first layer 152A may be formed to have a surface having an outer curvature (e.g., a curvature from the side surfaces of the first to third channel layers 141, 142, and 143). For example, the second layer 152B may be constructed to have an upwardly curved surface on the surface of the active region 105 located on the bottom surface of the recessed region RC. In Figure 7 and Fig. 9 In the example embodiment shown in FIG. 1 , the manufacturing process may be performed while controlling the growth speed and growth thickness of the first epitaxial layer 152 in the above-described process.

[0093] Reference Fig.11I , a second epitaxial layer 154 of the source / drain region 150 a may be formed to fill the recessed region RC.

[0094] The second epitaxial layer 154 may be grown from the first epitaxial layer 152 and the active region 105 using, for example, a SEG process, and may be configured as, for example, an in-situ doped semiconductor layer (e.g., a SiP layer). The concentration of phosphorus (P) included in the second epitaxial layer 154 may be higher than the concentration of arsenic (As) or phosphorus (P) included in the first epitaxial layer 152.

[0095] The second epitaxial layer 154 may have a form similar to an ellipse together with the first epitaxial layer 152, and an upper surface of the second epitaxial layer 154 may be formed to be flat. The second epitaxial layer 154 may be formed to fill a space between the first epitaxial layers 152 disposed upward and downward in the Z direction, and may be formed to fill a space between the first epitaxial layers 152 located on both side surfaces of the recessed region RC in the X direction.

[0096] In the source / drain region 150a, a first epitaxial layer 152, a second epitaxial layer 154, and a third epitaxial layer 151 may be epitaxially grown. Therefore, in the source / drain region 150a formed by the above process, the boundary among the first epitaxial layer 152, the second epitaxial layer 154, and the third epitaxial layer 151 may not be obvious in a microscope image. However, since the first epitaxial layer 152, the second epitaxial layer 154, and the third epitaxial layer 151 have different compositions from each other, the first epitaxial layer 152, the second epitaxial layer 154, and the third epitaxial layer 151 may be substantially distinguished from each other by analysis such as transmission electron microscope energy dispersive X-ray spectroscopy (TEM-EDX) analysis.

[0097] Reference Fig.11J , the interlayer insulating layer 190 may be formed, and the sacrificial layer 120 and the sacrificial gate structure 170 may be removed.

[0098] The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 170 and the source / drain regions 150 a and performing a planarization process.

[0099] The sacrificial layer 120 and the sacrificial gate structure 170 may be selectively removed relative to the gate spacer layer 164, the interlayer insulating layer 190, and the channel structure 140. The upper gap region UR may be formed by removing the sacrificial gate structure 170, and the lower gap region LR may be formed by removing the sacrificial layer 120 exposed by the upper gap region UR. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 120 may be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source / drain region 150a may be protected by the interlayer insulating layer 190 and the inner spacer layer 130.

[0100] Reference Figure 11K , a gate structure 160 may be disposed in the upper gap region UR and the lower gap region LR.

[0101] The gate dielectric layer 162 may be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 may be formed to completely fill the upper gap region UR and the lower gap region LR, and the gate electrode 165 may be removed from the upper portion of the upper gap region UR to a certain depth. A gate capping layer 166 may be formed in the region of the upper gap region UR from which the gate electrode 165 is removed. Thus, a gate structure 160 including a gate dielectric layer 162, a gate electrode 165, a gate spacer layer 164, and a gate capping layer 166 may be formed.

[0102] Return to reference Figure 2 , a contact plug 180 may be formed.

[0103] The contact hole may be formed by patterning the interlayer insulating layer 190, and the contact plug 180 may be formed by filling the contact hole with a conductive material. The lower surface of the contact hole may be recessed into the source / drain region 150a, or may have a flexure formed along the upper surface of the source / drain region 150a. In example embodiments, the shape and position of the contact plug 180 may vary.

[0104] Fig.12 is a block diagram illustrating an electronic apparatus including a semiconductor device according to example embodiments.

[0105] Reference Fig.12 , the electronic device 1000 in the example embodiment may include a communicator 1010 , an input portion 1020 , an output portion 1030 , a memory 1040 , and a processor 1050 .

[0106] The communicator 1010 may include a wired / wireless communication module, and may include a wireless Internet module, a near field communication module, a GPS module, a mobile communication module, etc. The wired / wireless communication module included in the communicator 1010 may be connected to an external communication network based on various communication standards, and may transmit and receive data.

[0107] The input portion 1020 may be a module provided to the user to control the operation of the electronic device 1000, and may include a mechanical switch, a touch screen, a voice recognition module, etc. The input portion 1020 may also include a mouse or a finger mouse device operated using a trackball or laser pointer method, and may also include various sensor modules through which the user can input data.

[0108] The output part 1030 can output information processed in the electronic device 1000 in the form of voice or image, and the memory 1040 can store programs, data, etc. for processing operations and control operations of the processor 1050. The processor 1050 can transmit command words to the memory 1040 according to the required operation, and can store or read out data.

[0109] The memory 1040 may be embedded in the electronic device 1000, or may communicate with the processor 1050 using a separate interface. When the memory 1040 communicates with the processor 1050 using a separate interface, the processor 1050 may store data in the memory 1040, or may read data from the memory 1040 through various interface standards (such as SD, SDHC, SDXC, MICRO SD, USB, etc.).

[0110] The processor 1050 may control the operation of each component included in the electronic device 1000. The processor 1050 may perform a control operation or a processing operation related to a voice call, a video call, a data communication, etc., or may perform a control operation or a processing operation related to the reproduction and management of multimedia. The processor 1050 may also process an input transmitted from a user through the input part 1020, and may output a result through the output part 1030. In addition, the processor 1050 may store data required for controlling the operation of the electronic device 1000 in the memory 1040, or may read out data from the memory 1040. At least one of the processor 1050 and the memory 1040 may include a reference Figures 1 to 10C The semiconductor devices described in the foregoing example embodiments are described.

[0111] Fig.13 is a diagram illustrating a system including a semiconductor device according to example embodiments.

[0112] Reference Fig.13 , the system 2000 may include a controller 2100, an input / output device 2200, a memory 2300, and an interface 2400. The system 2000 may be a mobile system, or may be a system for sending or receiving information. The mobile system may be implemented as a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

[0113] The controller 2100 may execute a program, and may control the system 2000. The controller 2100 may be implemented as a microprocessor, a digital signal processor, a microcontroller, or other similar devices.

[0114] The input / output device 2200 may be used to input and output data of the system 2000. The system 2000 may be connected to an external device (such as a personal computer or a network) using the input / output device 2200, and may exchange data with the external device. The input / output device 2200 may be implemented as a keypad, a keyboard, or a display.

[0115] The memory 2300 may store codes and / or data for operating the controller 2100 and / or may store data processed in the controller 2100 .

[0116] The interface 2400 may be a data transmission path between the system 2000 and an external device. The controller 2100 , the input / output device 2200 , the memory 2300 , and the interface 2400 may communicate with each other through the bus 2500 .

[0117] At least one of the controller 2100 and the memory 2300 may include a reference Figures 1 to 10C The semiconductor devices described in the aforementioned example embodiments are described.

[0118] According to the foregoing example embodiments, a semiconductor device having improved electrical properties may be provided by controlling the structure of source / drain regions.

[0119] As described above, example embodiments may provide a semiconductor device having improved electrical properties.

[0120] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted only in a general and descriptive sense and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art by the time this application is filed, unless otherwise specifically noted, the features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: an active region extending in a first direction on the substrate; a plurality of channel layers located on the active region and vertically spaced apart from each other; a gate structure extending in a second direction on the substrate and surrounding the plurality of channel layers; an inner spacer layer covering a side surface of the gate structure in the first direction on a lower surface of each of the plurality of channel layers, the inner spacer layer having an inner side surface facing the gate structure and curved toward the gate structure in the first direction; as well as A source / drain region, which is located on the active region at one side of the gate structure, the source / drain region is in contact with the plurality of channel layers and extends upwards further than the uppermost surface of the plurality of channel layers, the source / drain region comprising: a first epitaxial layer including arsenic (As) and including a first layer on side surfaces of the plurality of channel layers in the first direction and a second layer on the active region at a lower end of the source / drain region; and a second epitaxial layer located on the first epitaxial layer, the second epitaxial layer filling a space between the first epitaxial layers and including phosphorus (P), wherein the second layer has a first thickness in an edge region adjacent to the plurality of channel layers and has a second thickness greater than the first thickness in a central region in the first direction, and The gate structure includes a gate electrode having a first width in the first direction on an uppermost surface of the plurality of channel layers and a second width in the first direction below the plurality of channel layers that is greater than the first width.

2. The semiconductor device according to claim 1, wherein The second epitaxial layer is interposed between the first epitaxial layers in the first direction, and is interposed between the first epitaxial layers in a third direction, which is a vertical direction perpendicular to the first direction and the second direction.

3. The semiconductor device according to claim 2, wherein: The first layer is separated from each other between the plurality of channel layers disposed along the third direction, and is separated from the second layer.

4. The semiconductor device according to claim 1, wherein: Each of the first epitaxial layers includes arsenic (As) at a first concentration, and the second epitaxial layers include phosphorus (P) at a second concentration, the second concentration being higher than the first concentration.

5. The semiconductor device according to claim 1, wherein The concentration of arsenic (As) included in the first epitaxial layer is about 2×10 20 / cm 3 Up to 8×10 20 / cm 3 within the range.

6. The semiconductor device according to claim 1, wherein The concentration of phosphorus (P) included in the second epitaxial layer may be about 3.1×10 21 / cm 3 to 3.9×10 21 / cm 3 within the range.

7. The semiconductor device according to claim 1, wherein In a plane, at least a portion of the first epitaxial layer overlaps with the second epitaxial layer.

8. The semiconductor device according to claim 1, wherein The inner spacer layer has an outer side surface that is substantially coplanar with the side surfaces of the plurality of channel layers.

9. The semiconductor device according to claim 1, wherein: The first layer protrudes toward the second epitaxial layer from a side surface formed by the inner spacer layer and the plurality of channel layers.

10. The semiconductor device according to claim 1, wherein Each of the first layers has a side surface facing the second epitaxial layer and curved toward the second epitaxial layer in the first direction.

11. The semiconductor device according to claim 1, wherein A side surface of the first layer taken in the first direction is surrounded by the second epitaxial layer, the plurality of channel layers, and the inner spacer layer.

12. The semiconductor device according to claim 1, wherein The second layer has an upper surface curved toward the second epitaxial layer.

13. The semiconductor device according to claim 1, wherein The first layer has a first maximum thickness at side surfaces of the plurality of channel layers, and The second layer has a second maximum thickness at the upper surface of the active region that is greater than the first maximum thickness.

14. The semiconductor device according to claim 1, wherein In a plane, at least a portion of the first epitaxial layer overlaps with the gate structure.

15. A semiconductor device comprising: Active area; a plurality of channel layers located on the active region and vertically spaced apart from each other; a gate structure extending in the second direction and surrounding the plurality of channel layers; A source / drain region, which is located on the active region at one side of the gate structure, the source / drain region is in contact with the plurality of channel layers, and the source / drain region includes: a first epitaxial layer having a first composition and extending along side surfaces of the plurality of channel layers in a first direction and covering an upper surface of the active region at a lower end of the source / drain region; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition different from the first composition and extending upwardly further than an uppermost surface of the plurality of channel layers, The first epitaxial layer has a flexure formed by a non-uniform thickness, and the first epitaxial layer has a first thickness on side surfaces of the plurality of channel layers and a second thickness greater than the first thickness on an upper surface of the active region.

16. The semiconductor device according to claim 15, wherein: The first epitaxial layer has a third thickness on a side surface of the gate structure in a lower portion of each of the plurality of channel layers in the first direction, and the third thickness is different from the first thickness.

17. The semiconductor device according to claim 16, wherein: The second thickness is greater than the third thickness.

18. The semiconductor device according to claim 15, wherein: The first epitaxial layer surrounds a lower surface and side surfaces of the second epitaxial layer in the first direction.

19. The semiconductor device according to claim 18, wherein: The second epitaxial layer is spaced apart from the active region by the first epitaxial layer.

20. The semiconductor device according to claim 15, further comprising: contact plugs connected to the source / drain regions, The first epitaxial layer is spaced apart from the contact plug.

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