Preparation method of stacked transistor, stacked transistor and semiconductor device

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps that a fin-shaped structure is formed on a semiconductor substrate, the fin-shaped structure comprises a first part and a second part which are stacked in the first direction, at least one first transistor is formed based on the first part, and the first transistor comprises a first drain electrode structure, a first gate electrode structure and a first source electrode structure which are sequentially arranged in the second direction; reversing and removing the semiconductor substrate; on the basis of the second part, at least one second transistor is formed, and the second transistor comprises a second drain electrode structure, a second gate electrode structure and a second source electrode structure which are sequentially arranged in the second direction; the second gate structure and the first drain structure are stacked along the first direction, and the second drain structure and the first gate structure are stacked along the first direction; and forming a first metal interconnection through hole for communicating the second drain electrode structure and the first gate structure, and forming a second metal interconnection through hole for communicating the second gate structure and the first drain electrode structure.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a method for preparing a stacked transistor, a stacked transistor, and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for preparing stacked transistors, active regions of upper and lower layers of transistors of the same source are formed by etching, and stacked transistors are made on the front and back sides of the wafer by flipping the wafer. This can also be called a "self-aligned flip transistor" scheme. However, the front and back structures of the "self-aligned flip transistor" have a mirror-symmetric relationship, which results in complex internal wiring of the transistor in the process of forming a decoupling capacitor (decap cell) based on the "self-aligned flip transistor", which is extremely difficult to prepare and is not conducive to the miniaturization of the integrated circuit. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device to realize a staggered design using upper and lower layers of transistors of the same source, so that the interconnection line inside the decoupling capacitor can be realized by using a first metal interconnection through hole and a second metal interconnection through hole, thereby effectively reducing the difficulty of preparation without increasing the size of the transistor unit, which helps to further improve the integration of the circuit.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, comprising: forming a fin structure on a semiconductor substrate, wherein the fin structure comprises a first portion and a second portion stacked along a first direction, the first portion being closer to the semiconductor substrate than the second portion; based on the first portion, forming at least one first transistor, wherein the first transistor comprises: a first drain structure, a first gate structure and a first source structure arranged in sequence along a second direction; the second direction is perpendicular to the first direction; flipping and removing the semiconductor substrate; based on the second portion, forming at least one second transistor, wherein the second transistor comprises: a second source structure, a second gate structure and a second drain structure arranged in sequence along the second direction; the second gate structure and the first drain structure are stacked along the first direction, and the second drain structure and the first gate structure are stacked along the first direction; forming a first metal interconnection through-hole connecting the second drain structure and the first gate structure, and forming a second metal interconnection through-hole connecting the second gate structure and the first drain structure.

[0006] In some possible embodiments, at least one second transistor is formed based on the second part, including: based on the second part, forming a second source structure and a second drain structure that are alternately arranged in sequence along the second direction; based on the second part, forming a second gate structure and a second single diffusion isolation structure between the second source structure and the second drain structure, so that the second source structure, the second gate structure, the second drain structure and the second single diffusion isolation structure are arranged in sequence; wherein the second single diffusion isolation structure and the first source structure are stacked along the first direction; the second source structure and the first single diffusion isolation structure in the first transistor are stacked along the first direction; a second gate structure and adjacent second source structures and second drain structures form a second transistor; the second single diffusion isolation structure is used to electrically isolate two adjacent second transistors.

[0007] In some possible embodiments, based on the second part, a second gate structure and a second single diffusion isolation structure are formed between the second source structure and the second drain structure, including: based on the second part, forming a second gate structure above the first source structure and the first drain structure; removing the second gate structure located above the first source structure, and depositing insulating material at the position where the second gate structure is removed to form a second single diffusion isolation structure.

[0008] In some possible embodiments, based on the second portion, a second source structure and a second drain structure are formed and arranged alternately in sequence along the second direction, including: based on the second portion, a second drain structure is formed on the first gate structure; based on the second portion, a second source structure is formed on both sides of the second drain structure, so that the second source structure and the second drain structure are arranged alternately in sequence along the second direction.

[0009] In some possible embodiments, at least one first transistor is formed based on the first part, including: based on the first part, forming a first drain structure and a first source structure that are alternately arranged in sequence along the second direction; based on the first part, forming a first gate structure and a first single diffusion isolation structure between the first drain structure and the first source structure, so that the first single diffusion isolation structure, the first drain structure, the first gate structure and the first source structure are arranged in sequence; the first single diffusion isolation structure is used to electrically isolate two adjacent first transistors.

[0010] In some possible embodiments, the second transistor includes a second drain metal; forming a first metal interconnection through-hole connecting the second drain structure and the first gate structure, and forming a second metal interconnection through-hole connecting the second gate structure and the first drain structure, including any of the following: before forming the second drain metal, forming a first metal interconnection through-hole connecting the second drain structure and the first gate structure, and before the second gate structure, forming a second metal interconnection through-hole connecting the second gate structure and the first drain structure; before forming the second drain metal, forming a first metal interconnection through-hole connecting the second drain structure and the first gate structure, and after the second gate structure, forming a second metal interconnection through-hole connecting the second gate structure and the first drain structure; after forming the second drain metal, forming a first metal interconnection through-hole connecting the second drain structure and the first gate structure, and before the second gate structure, forming a second metal interconnection through-hole connecting the second gate structure and the first drain structure.

[0011] In a second aspect, an embodiment of the present application provides a stacked transistor, which includes: at least one first transistor and at least one second transistor, the first transistor and the second transistor are stacked along a first direction; wherein the first transistor includes: a first drain structure, a first gate structure and a first source structure arranged in sequence along a second direction; the second direction is perpendicular to the first direction; the second transistor includes: a second source structure, a second gate structure and a second drain structure arranged in sequence along the second direction; the second drain structure and the first gate structure are stacked along the first direction, and a first metal interconnection through-hole is arranged between the second drain structure and the first gate structure; the second gate structure and the first drain structure are stacked along the first direction, and a second metal interconnection through-hole is arranged between the second gate structure and the first drain structure; the first metal interconnection through-hole is used to connect the second drain structure and the first gate structure, and the second metal interconnection through-hole structure is used to connect the second gate structure and the first drain structure.

[0012] In some possible embodiments, the stacked transistor further includes: a first single diffusion isolation structure stacked with the second source structure along the first direction, and a second single diffusion isolation structure stacked with the first source structure along the first direction; wherein the first single diffusion isolation structure is used to electrically isolate two adjacent first transistors; and the second single diffusion isolation structure is used to electrically isolate two adjacent second transistors.

[0013] In some possible implementations, when at least one first transistor is a plurality of first transistors, two adjacent first transistors share a first source structure, and / or when at least one second transistor is a plurality of second transistors, two adjacent second transistors share a second source structure.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0015] In the embodiment of the present application, the upper and lower layers of transistors are prepared by using the front and back sides of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors. In addition, the upper and lower layers of transistors are staggered, so that the electrical connection between the different structures in the upper and lower layers of transistors can be achieved only through the preparation process of forming metal interconnection through holes. Compared with the solution of setting complex connecting lines in the related art, the embodiment of the present application is not only easier to meet the needs of different logic circuits and effectively reduce the difficulty of preparation, but also does not increase the size of the transistor unit, which helps to further improve the integration of the circuit.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 is a schematic diagram of a first structure of a stacked transistor in an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of a second structure of a stacked transistor in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a circuit composition of a decoupling capacitor in an embodiment of the present application;

[0021] Figure 4 In the embodiment of this application Figure 3 A schematic diagram of a layout of a decoupling capacitor shown;

[0022] Figure 5 A schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application;

[0023] Figures 6 to 21 It is a schematic diagram of a preparation process of a stacked transistor in an embodiment of the present application.

[0024] Figures 10, stacked transistor; 11, first transistor; 112, first source-drain structure; 1121, first source structure; 1122, first drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 1151, first source metal; 1152, first drain metal; 116, first metal interconnect layer; 12, second transistor; 122, second source-drain structure; 1221, second source structure; 1222, second drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 1251, second source metal; 1252, second drain metal; 126, second metal interconnect layer; 13, metal connection line; 131, first metal interconnect via; 132, second metal interconnect via;

[0025] 20. Semiconductor substrate; 21. Fin structure; 211. First part; 212. Second part; 22. Shallow trench isolation structure; 23. First isolation structure; 24. First single diffusion isolation structure; 25. Front dielectric layer; 26. Second pseudo gate structure; 27. Second single diffusion isolation structure; 28. Back dielectric layer; 29. ​​First pseudo gate structure; 32. Insulating layer; 33. Carrier wafer. DETAILED DESCRIPTION

[0026] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0027] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0028] In one embodiment, there are two schemes for manufacturing the stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0029] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0030] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the already manufactured lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection lines. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0031] In order to solve the technical problems of the above two solutions, a "self-aligned flip transistor" solution is proposed. The "self-aligned flip transistor" solution forms the active areas of the upper and lower layers of the same source transistors by etching, and realizes the production of stacked transistors on the front and back sides of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions.

[0032] For example, Figure 1 is a schematic diagram of a first structure of a stacked transistor in an embodiment of the present application, wherein: Figure 1 (a), (b) and (c) are cross-sectional views of the stacked transistor at different positions. Figure 1 As shown, in the "self-aligned flip-chip transistor", a first transistor 11 is formed on the front side of the wafer, and a second transistor 12 is formed on the back side of the wafer. The first transistor 11 and the second transistor 12 are arranged back to back, and the first source-drain structure 112 in the first transistor 11 and the second source-drain structure 122 in the second transistor 12 are stacked along a first direction, and the first gate structure 114 in the first transistor 11 and the second gate structure 124 in the second transistor 12 are stacked along the first direction.

[0033] Figure 2 is a schematic diagram of a second structure of a stacked transistor in an embodiment of the present application, wherein: Figure 2 (a), (b) and (c) are cross-sectional views of the stacked transistor at different positions. Figure 2 As shown in (a), in a "self-aligned flip-chip transistor", in order to realize a decoupling capacitor, it is necessary to set up complex connection lines in the metal interconnect layer connecting the gate structure.

[0034] First, let’s introduce decoupling capacitors.

[0035] In some embodiments, a decoupling capacitor is a capacitor installed at the power supply terminal of a component in a circuit. This capacitor can provide a more stable power supply and can also reduce the noise coupled from the component to the power supply terminal, thereby indirectly reducing the impact of the noise of this component on other components.

[0036] In some embodiments, the decoupling capacitor can be composed of an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor in parallel. In one embodiment, the source and drain of the PMOS transistor are short-circuited and connected to the power supply VDD, and the gate is connected to the power supply VSS. Similarly, the source and drain of the NMOS transistor are connected to the power supply VSS, and the gate is connected to the power supply VDD.

[0037] In one embodiment, the decoupling capacitor may be composed of a cross-coupled PMOS transistor and an NMOS transistor, wherein the source of the PMOS transistor may be connected to a power source VDD, and the source of the NMOS transistor may be connected to a power source VSS.

[0038] Secondly, a method of realizing decoupling capacitor based on “self-aligned flip-chip transistor” is introduced.

[0039] See also Figure 2 As shown in (b) and (c), in the "self-aligned flip-chip transistor", in order to realize the decoupling capacitor, in addition to setting up complex connection lines in the metal interconnect layer connecting the source and drain metals, it is also necessary to form a metal connection line 13 inside the stacked transistor. Here, compared with Figure 1 The stacked transistor shown, Figure 2 The stacked transistor shown is difficult to manufacture in order to realize the metal connection line 13, and the source and drain metals need to be arranged alternately, which occupies more space inside the stacked transistor and is not conducive to the miniaturization of the integrated circuit.

[0040] It can be seen that there is room for improvement in the solution of forming a decoupling capacitor (decap cell) based on a "self-aligned flip-chip transistor". To this end, the embodiments of the present application provide a method for preparing a stacked transistor, a stacked transistor, and a semiconductor device to achieve a staggered design using upper and lower layers of homologous transistors, so that the interconnection line inside the decoupling capacitor can be realized by using the first metal interconnection via and the second metal interconnection via, thereby effectively reducing the difficulty of preparation and not increasing the size of the transistor unit, which helps to further improve the integration of the circuit.

[0041] Figure 3 A schematic diagram of a circuit composition of a decoupling capacitor in an embodiment of the present application, see Figure 3 As shown, between the power supply VDD and the power supply VSS, two decoupling capacitors with a cross-coupling structure can be arranged in parallel, which are respectively denoted as the first decoupling capacitor Decap1 and the second decoupling capacitor Decap2. Among them, the first decoupling capacitor Decap1 can be composed of a PMOS transistor and an NMOS transistor. The PMOS transistor and the NMOS transistor can be stacked. Among them, the source of the PMOS transistor can be connected to the power supply VDD, the gate of the PMOS transistor can be connected to the drain of the NMOS transistor, the drain of the PMOS transistor can be connected to the gate of the NMOS transistor, and the source of the NMOS transistor can be connected to the power supply VSS. Similarly, the second decoupling capacitor Decap2 has the same structure as the first decoupling capacitor Decap1.

[0042] Figure 4 In the embodiment of this application Figure 3 A schematic diagram of a layout of decoupling capacitors is shown in FIG. Figure 4 As shown, Figure 4 The first decoupling capacitor Decap1 and the second decoupling capacitor Decap2 are shown in FIG. The first decoupling capacitor Decap1 and the second decoupling capacitor Decap2 each include two transistors, which may be composed of a fin structure, a gate structure, a source-drain metal, a single diffusion isolation structure, a connection line in a metal interconnection layer, a first metal interconnection through hole, and a second metal interconnection through hole.

[0043] Here, according to Figure 4 As can be seen from the layout shown, the first decoupling capacitor Decap1 and the second decoupling capacitor Decap2 can be formed by stacked transistors.

[0044] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor. Figure 5 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application, see Figure 5 As shown, the method for preparing a stacked transistor may include:

[0045] Step S501: forming a fin structure on a semiconductor substrate, wherein the fin structure includes a first portion and a second portion stacked along a first direction, and the first portion is closer to the semiconductor substrate than the second portion;

[0046] Step S502: forming at least one first transistor based on the first part, wherein the first transistor comprises: a first drain structure, a first gate structure and a first source structure sequentially arranged along a second direction; the second direction is perpendicular to the first direction;

[0047] Step S503: flipping the wafer and removing the semiconductor substrate;

[0048] Step S504: forming at least one second transistor based on the second part, wherein the second transistor comprises: a second drain structure, a second gate structure, and a second source structure sequentially arranged along the second direction; the second drain structure and the first gate structure are stacked along the first direction, and the second gate structure and the first drain structure are stacked along the first direction;

[0049] Step S505: forming a first metal interconnection through hole connecting the second drain structure and the first gate structure, and forming a second metal interconnection through hole connecting the second gate structure and the first drain structure; wherein the first metal interconnection through hole is used to connect the second drain structure and the first gate structure, and the second metal interconnection through hole structure is used to connect the second gate structure and the first drain structure.

[0050] It should be noted that Figure 5 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 5 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0051] Figures 6 to 21 Schematic diagram of a preparation process of a stacked transistor in an embodiment of the present application, for ease of understanding, Figures 6 to 21 (a) shows the Figure 4 The cross-sectional view along the dashed line AA'. Figures 6 to 21 (b) shows the Figure 2 A cross-sectional view in the direction of the middle dotted line BB'; Figures 6 to 20 (a) shows the Figure 4 The cross-sectional view along the dotted line CC', Figures 6 to 21 (b) shows the Figure 2 The cross-sectional view along the dashed line DD' direction will be combined with Figures 3 to 21 The method for preparing the stacked transistor provided in the embodiment of the present application and the prepared stacked transistor are exemplarily described.

[0052] In step S501 , a fin structure 21 is formed on a semiconductor substrate 20 .

[0053] Reference Figure 6 As shown, a semiconductor substrate 20 is provided. The semiconductor substrate 20 can be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, etc. Next, a plurality of fin structures 21 vertically standing on the semiconductor substrate can be formed on the semiconductor substrate 20 .

[0054] In some embodiments, when the stacked transistor 10 is a fin field effect transistor, the above S501 may include: forming a semiconductor epitaxial layer on the surface of the semiconductor substrate 20 through an epitaxial growth process; etching the semiconductor epitaxial layer to a certain depth in the semiconductor epitaxial layer or to the surface of the semiconductor substrate or to a certain depth in the substrate, thereby forming a plurality of fin structures 21.

[0055] In some embodiments, when the stacked transistor 10 is a full-surround gate transistor, the above S301 may include: material layer deposition, epitaxial growth and other processes may be performed on the semiconductor substrate 20 to form a stacked structure on the semiconductor substrate 20. Subsequently, a single etching process may be used to etch the stacked structure to form a fin structure 21 on the semiconductor substrate 20.

[0056] In the embodiment of the present application, since the stacked transistor 10 includes two layers of transistors (composed of a first transistor 11 and a second transistor 12), and the active structures of the two layers of transistors are formed by the same etching process. That is, the first active structure of the first transistor 11 and the second active structure of the second transistor 12 are formed by the same etching process. Therefore, when etching the semiconductor substrate 20, a larger etching depth can be used. For example, the height of the fin-shaped structure 21 obtained by etching can be greater than 100nm. It should be noted that the height of the fin-shaped structure 21 can be set according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0057] It can be understood that the fin structure 21 includes a first portion 211 and a second portion 212 . The first portion 211 and the second portion 212 are stacked along a first direction (a direction perpendicular to the semiconductor substrate 20 ), and the second portion 212 is closer to the semiconductor substrate 20 than the first portion 211 .

[0058] It can be understood that the first portion 211 of the fin structure 21 is used to form an active region of the first transistor 11 in a subsequent step; and the second portion 212 of the fin structure 21 is used to form an active region of the second transistor 12 .

[0059] It should be noted that the first transistor 11 is formed based on the front surface of the semiconductor substrate 20 , and after the stacked transistor 10 is prepared, the first transistor 11 is located at the lower layer of the stacked transistor 10 . The second transistor 12 is opposite to the first transistor 11 .

[0060] In step S502 , at least one first transistor 11 is formed based on the first portion 211 .

[0061] In some embodiments, the first transistor 11 includes: a first drain structure 1122 , a first gate structure 114 , and a first source structure 1121 arranged in sequence along a second direction; the second direction is perpendicular to the first direction.

[0062] It is understandable that the first transistor 11 can be formed based on the first portion 211 of the fin structure 21. In one embodiment, when the first transistor 11 is a P-type (P-channel) field effect transistor, the second transistor 12 can be an N-type (N-channel) field effect transistor; when the first transistor 11 is an N-type field effect transistor, the second transistor 12 can be a P-type field effect transistor. The following description is made by taking the first transistor 11 as an N-type field effect transistor as an example.

[0063] In some embodiments, see Figure 7 As shown, before forming the first transistor 11, an insulating material may be deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 22 (STI), wherein the shallow trench isolation structure 22 wraps the second portion 212 of the fin structure 21 and exposes the first portion 211 of the active structure. The insulating material forming the shallow trench isolation structure 22 may be silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0064] In some embodiments, step S502 may include: based on the first part 211, forming a first drain structure 1122 and a first source structure 1121 that are alternately arranged in sequence along the second direction; based on the first part, forming a first gate structure 114 and a first single diffusion isolation structure 24 between the first drain structure 1122 and the first source structure 1121, so that the first single diffusion isolation structure 24, the first drain structure 1122, the first gate structure 114, and the first source structure 1121 are arranged in sequence.

[0065] See also Figure 8 As shown, based on Figure 7When the semiconductor structure shown forms at least one first transistor 11, a dummy gate material such as polysilicon or amorphous silicon may be deposited in the gate region of the front transistor to form a first dummy gate structure 29. After the first dummy gate structure 29 is formed, an insulating material may be deposited on the sidewalls of the first dummy gate structure 29 to form a first dummy gate spacer covering the sidewalls of the first dummy gate structure 29.

[0066] In some embodiments, the material forming the dummy gate spacer is silicon dioxide (SiO 2 ).

[0067] See also Fig. 9 As shown, after forming the first dummy gate structure 29, a first source-drain structure 112 may be formed in the source-drain region between two adjacent first dummy gate structures 29 based on the first portion 211 of the fin structure 21. Here, the first source-drain structure 112 may include a first drain structure 1122 and a first source structure 1121. The first drain structure 1122 and the first source structure 1121 may be alternately arranged in sequence along the second direction in the front transistor.

[0068] It can be understood that after forming the first dummy gate structure 29, the first dummy gate structure 29 can be used as a hard mask to etch the first portion 211 located in the source and drain region of the front transistor to form a source and drain groove in the source and drain region of the front transistor. Subsequently, a strained material such as silicon germanium or silicon carbide can be selectively epitaxially grown in the source and drain groove to fill the source and drain groove, and then a first source and drain structure 112 of the first transistor 11 is formed on the strained material through a heavy doping process.

[0069] In some embodiments, after the first source-drain structure 112 is formed based on the source-drain grooves, a dielectric layer material may be deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113 .

[0070] In one embodiment, the dielectric layer material forming the first interlayer dielectric layer 113 has a very high insulation performance. In one embodiment, the method of forming the first interlayer dielectric layer 113 is chemical vapor deposition or high aspect ratio trench filling process (High Aspect Ratio Process, HARP). The use of the high aspect ratio trench filling process can increase the isolation effect of the first interlayer dielectric layer 113.

[0071] See also Fig.10 As shown, after forming the first source-drain structure 112, the first dummy gate structure 29 can be removed, so that a dielectric material and a metal material are sequentially deposited at the position where the first dummy gate structure 29 is removed to form a first gate dielectric layer and a first gate metal layer, respectively. Here, the first gate dielectric layer and the first gate metal layer can constitute a first gate structure 114.

[0072] In some embodiments, the materials of the first gate dielectric layer and the first gate electrode layer can be set according to actual needs, and the embodiments of the present application do not specifically limit this. Exemplarily, the first gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. Exemplarily, the first gate electrode layer can be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide). In one example, the first gate dielectric layer may include: a 0.6nm silicon oxide layer and a 1.7nm hafnium oxide layer.

[0073] See also Fig.11 As shown, after forming the first gate structure 114, a first source-drain metal 115 may be formed. Here, the first source-drain metal 115 may include a first source metal 1151 and a first drain metal 1152. That is, after forming the first gate structure 114, a metal material may be deposited on the first source structure 1121 to form the first source metal 1151; and a metal material may be deposited on the first drain structure 1122 to form the first drain metal 1152.

[0074] See also Fig.12 As shown, after forming the first source-drain metal 115, the first gate structure 114 located at the edge or between the two first transistors 11 can be removed, and an insulating material is deposited at the position where the first gate structure 114 is removed to form a first single diffusion isolation structure 24. Here, the first single diffusion isolation structure 24 is used to electrically isolate two adjacent first transistors 11. Alternatively, the first single diffusion isolation structure 24 is used to electrically isolate the transistor unit from other electronic components.

[0075] In some embodiments, the insulating material forming the first single diffusion isolation structure 24 can be selected according to actual needs, and the embodiments of the present application are not limited to this.

[0076] It can be understood that after obtaining the first single diffusion isolation structure 24, the first source structure 1121 and the first drain structure 1122 are respectively located on both sides of a first gate structure 114. The first single diffusion isolation structure 24, the first drain structure 1122, the first gate structure 114 and the first source structure 1121 can be arranged in sequence.

[0077] It should be noted that, when there are multiple first transistors 11 in the stacked transistor, the first single diffusion isolation structure 24, the first drain structure 1122, the first gate structure 114 and the first source structure 1121 in two adjacent first transistors 11 may be arranged in different directions. For example, the first single diffusion isolation structure 24, the first drain structure 1122, the first gate structure 114 and the first source structure 1121 in the first first transistor 11 are arranged in sequence along the second direction, and the first single diffusion isolation structure 24, the first drain structure 1122, the first gate structure 114 and the first source structure 1121 in the second first transistor 11 are arranged in sequence along the third direction. The third direction may be opposite to the second direction.

[0078] In some embodiments, see Fig.13 As shown, after forming the first gate structure 114 and the first source-drain metal 115, the method further includes: depositing a dielectric material on the first gate structure 114 and the first source-drain metal 115 to form a front dielectric layer 25; on the front dielectric layer 25, using a standard back-end process for semiconductor preparation (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) to form a first metal interconnect layer 116 of the stacked transistor 10.

[0079] In step S503 , the semiconductor substrate 20 is flipped over and removed.

[0080] It is understandable that after obtaining at least one first transistor 11 , the first transistor 11 can be flipped so that the prepared first transistor 11 is located at the bottom and the second part 212 of the fin structure 21 can be located at the top, which is convenient for the subsequent preparation of the second transistor 12 .

[0081] In one embodiment, see Fig.14 As shown, after the back-end process of the first transistor 11 is completed, the first transistor 11 can be bonded to the carrier wafer 33. For example, an insulating material (such as silicon oxide) can be deposited on the first transistor 11 to form an insulating layer 32, and the insulating layer 32 can be bonded to the carrier wafer 33. Then, the wafer is flipped, and after the flip, the first transistor 11 is located at the bottom. After the flip, the semiconductor substrate 20 can be removed by polishing or chemical mechanical planarization to expose the second portion 212 of the fin structure 21.

[0082] In the embodiment of the present application, the bonded carrier wafer 33 can provide physical support for the flipped first transistor 11 after flipping, thereby effectively preventing the first transistor 11 from being broken by external force during the preparation of the second transistor 12 .

[0083] See also Fig.15As shown, after removing the semiconductor substrate 20 , the shallow trench isolation structure 22 may be thinned to form a first isolation structure 23 , and the first isolation structure 23 may isolate the first transistor 11 from the second transistor 12 to be formed later.

[0084] In step S504 , at least one second transistor 12 is formed based on the second portion 212 .

[0085] In some embodiments, the second transistor includes: a second source structure 1221, a second gate structure 124, and a second drain structure 1222 arranged in sequence along the second direction. The second transistor and the first transistor 11 have a staggered arrangement feature, that is, the gate region of the second transistor corresponds to the source and drain region of the first transistor 11, and the source and drain region of the second transistor corresponds to the gate region of the first transistor 11.

[0086] In some embodiments, the second source structure 1221 and the first single diffusion isolation structure 24 are stacked along the first direction; the second gate structure 124 and the first drain structure 1122 are stacked along the first direction; and the second drain structure 1222 and the first gate structure 114 are stacked along the first direction.

[0087] It is understandable that the first transistor 11 may be formed based on the second portion 212 of the fin structure 21. Taking the first transistor 11 as an N-type field effect transistor as an example, the second transistor 12 may be a P-type field effect transistor.

[0088] In some embodiments, step S504 may include: based on the second portion 212, forming a second source structure 1221 and a second drain structure 1222 arranged alternately in sequence along the second direction; based on the second portion, forming a second gate structure 124 and a second single diffusion isolation structure between the second source structure 1221 and the second drain structure 1222, so that the second drain structure 1222, the second gate structure 124, the second source structure 1221 and the second single diffusion isolation structure are arranged in sequence.

[0089] See also Fig.16 As shown, based on Fig.15 When the semiconductor structure shown forms at least one second transistor 12, a dummy gate material such as polysilicon or amorphous silicon can be deposited in the gate region of the reverse transistor to form a second dummy gate structure 26. Here, the gate region of the reverse transistor corresponds to the source and drain region of the front transistor. After forming the second dummy gate structure 26, an insulating material can be deposited on the sidewalls of the second dummy gate structure 26 to form a second dummy gate sidewall covering the sidewalls of the second dummy gate structure 26.

[0090] In some embodiments, a second dummy gate structure 26 may be formed over the first drain structure 1122 .

[0091] See also Fig.17 As shown, after forming the second dummy gate structure 26, a second source-drain structure 122 may be formed in the source-drain region between two adjacent second dummy gate structures 26 based on the second portion of the fin structure 21. Here, the second source-drain structure 122 may include a second source structure 1221 and a second drain structure 1222. The second source structure 1221 and the second drain structure 1222 may be alternately arranged in sequence along the second direction in the reverse transistor.

[0092] In some embodiments, when forming the second source structure 1221 and the second drain structure 1222, the second drain structure 1222 may be formed on the first gate structure 114. The second source structure 1221 is formed on both sides of the second drain structure 1222, so that the second source structure 1221 and the second drain structure 1222 are alternately arranged in sequence along the second direction.

[0093] See also Fig.18 As shown, after forming the second source-drain structure 122, the second dummy gate structure 26 can be removed, and a dielectric material and a metal material are sequentially deposited at the position where the second dummy gate structure 26 is removed to form a second gate dielectric layer and a second gate metal layer, respectively. Here, the second gate dielectric layer and the second gate metal layer can constitute a second gate structure 124.

[0094] See also Fig.19 As shown, after forming the second gate structure 124, a second source-drain metal 125 may be formed. Here, the second source-drain metal 125 may include a second source metal 1251 and a second drain metal 1252. That is, after forming the second gate structure 124, a metal material may be deposited on the second source structure 1221 to form the second source metal 1251; and a metal material may be deposited on the second drain structure 1222 to form the second drain metal 1252.

[0095] See also Fig. 20 As shown, after forming the second source-drain metal 125, the second gate structure 124 located on the first source structure 1121 is removed, that is, the second gate structure 124 located at the edge or between the two second transistors 12 can be removed, and an insulating material is deposited at the position where the second gate structure 124 is removed to form a second single diffusion isolation structure 27. Here, the second single diffusion isolation structure 27 is used to electrically isolate two adjacent second transistors 12. Alternatively, the second single diffusion isolation structure 27 is used to electrically isolate the transistor unit from other electronic components.

[0096] It can be understood that after obtaining the second single diffusion isolation structure 27, the second source structure 1221 and the second drain structure 1222 are respectively located on both sides of a second gate structure 124. The second source structure 1221, the second gate structure 124, the second drain structure 1222 and the second single diffusion isolation structure 27 can be arranged in sequence along the second direction.

[0097] It should be noted that when there are multiple second transistors 12 in the stacked transistor, the second source structure 1221, the second gate structure 124, the second drain structure 1222 and the second single diffusion isolation structure 27 in two adjacent second transistors 12 may be arranged in different directions. For example, the second source structure 1221, the second gate structure 124, the second drain structure 1222 and the second single diffusion isolation structure 27 in the first second transistor 12 are arranged in sequence along the second direction, and the second source structure 1221, the second gate structure 124, the second drain structure 1222 and the second single diffusion isolation structure 27 in the second second transistor 12 are arranged in sequence along the third direction. The third direction may be opposite to the second direction.

[0098] In some embodiments, see Fig.21 As shown, after forming the first gate structure 114 and the first source-drain metal 115, the method further includes: depositing a dielectric material on the first gate structure 114 and the first source-drain metal 115 to form a reverse dielectric layer 28; on the reverse dielectric layer 28, using a standard back-end process for semiconductor preparation (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) to form a second metal interconnect layer 126 of the stacked transistor 10.

[0099] It should be noted that the process of forming the structure in the second transistor 12 may also refer to the process of forming the relevant structure in the first transistor 11 .

[0100] In step S505, see Figure 18 to Figure 19 As shown, a first metal interconnection through hole 131 connecting the second drain structure 1222 and the first gate structure 114 is formed, and a second metal interconnection through hole connecting the second gate structure 124 and the first drain structure 1122 is formed.

[0101] It is understandable that in the process of forming the second transistor, a first metal interconnection through hole 131 connecting the second drain structure 1222 and the first gate structure 114 and a second metal interconnection through hole connecting the second gate structure 124 and the first drain structure 1122 may also be formed.

[0102] In some embodiments, step S505 may include: before forming the second drain metal 1252, forming a first metal interconnection through hole 131 connecting the second drain structure 1222 and the first gate structure 114, and before forming the second gate structure 124, forming a second metal interconnection through hole 132 connecting the second gate structure 124 and the first drain structure 1122.

[0103] It can be understood that the first metal interconnection through hole 131 can be formed before the second drain metal 1252 is formed. The process of forming the first metal interconnection through hole 131 includes: etching the second interlayer dielectric layer 123 and the first isolation structure 23 that wrap the second drain structure 1222 until the first gate structure 114 is exposed, so as to form a first through hole; etching the second interlayer dielectric 123 layer that wraps the second drain structure 1222 until the second drain structure 1222 is exposed, so as to form a second drain metal through hole; the first through hole is connected to the second drain metal through hole; depositing a metal material in the first through hole to form the first metal interconnection through hole 131; depositing a metal material in the second drain metal through hole to form the second drain metal 1252.

[0104] It can be understood that the second metal interconnection through hole 132 can be formed before the second gate structure 124 is formed. The process of forming the second metal interconnection through hole 132 includes: after removing the second dummy gate structure 26, etching the first isolation structure 23 between the first transistor 11 and the second transistor 12, and the first interlayer dielectric layer 113 wrapping the first drain structure 1122 until the first source metal 1151 is exposed to form a second through hole; depositing a metal material in the second through hole to form the second metal interconnection through hole 132.

[0105] In some embodiments, step S505 may include: before forming the second drain metal 1252, forming a first metal interconnection through hole 131 connecting the second drain structure 1222 and the first gate structure 114, and after the second gate structure 124, forming a second metal interconnection through hole 132 connecting the second gate structure 124 and the first drain structure 1122.

[0106] It can be understood that the first metal interconnection via 131 can be formed before the second drain metal 1252 is formed. The formation process of the first metal interconnection via 131 can refer to the description in the above embodiment, which will not be repeated here.

[0107] It can be understood that the second metal interconnection through hole 132 can be formed after the second gate structure 124 is formed. The process of forming the second metal interconnection through hole 132 includes: etching the second gate structure 124, the first isolation structure 23 between the first transistor 11 and the second transistor, and the first interlayer dielectric layer 113 wrapping the first drain structure 1122 until the first source metal 1151 is exposed to form a third through hole; depositing a metal material in the third through hole to form the second metal interconnection through hole 132.

[0108] In some embodiments, step S505 may include: after forming the second drain metal 1252, forming a first metal interconnection through hole 131 connecting the second drain structure 1222 and the first gate structure 114, and before forming the second gate structure 124, forming a second metal interconnection through hole 132 connecting the second gate structure 124 and the first drain structure 1122.

[0109] It can be understood that the first metal interconnection through hole 131 can be formed after the second drain metal 1252 is formed. The process of forming the first metal interconnection through hole 131 includes: a fourth through hole can be formed by etching the second drain metal 1252, the second interlayer dielectric layer 123 wrapping the second drain structure 1222, and the first isolation structure 23 until the first gate structure 114 is exposed; the fourth through hole passes through the second drain metal 1252, and a metal material is deposited in the fourth through hole to form the first metal interconnection through hole 131.

[0110] It is understandable that the second metal interconnection via 132 can be formed before the second gate structure 124 is formed. The formation process of the second metal interconnection via 132 can refer to the description in the above embodiment, which will not be repeated here.

[0111] In the embodiment of the present application, the upper and lower layers of transistors are prepared by using the front and back sides of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors. In addition, the upper and lower layers of transistors are staggered, so that the electrical connection between the different structures in the upper and lower layers of transistors can be achieved only through the preparation process of forming metal interconnection through holes. Compared with the solution of setting complex connecting lines in the related art, the embodiment of the present application is not only easier to meet the needs of different logic circuits and effectively reduce the difficulty of preparation, but also does not increase the size of the transistor unit, which helps to further improve the integration of the circuit.

[0112] In a second aspect, the present application provides a stacked transistor. Fig.21As shown, the stacked transistor 10 may include: at least one first transistor 11 and at least one second transistor 12, the first transistor 11 and the second transistor 12 are stacked along a first direction; wherein the first transistor 11 includes: a first drain structure 1122, a first gate structure 114 and a first source structure 1121 arranged in sequence along a second direction; the second direction is perpendicular to the first direction; the second transistor 12 includes: a second drain structure 1222, a second gate structure 124 and a second source structure 1221 arranged in sequence along the second direction. The second drain structure 1222 is stacked with the first gate structure 114 along the first direction, and a first metal interconnection through-hole 131 is arranged between the second drain structure 1222 and the first gate structure 114; the second gate structure 124 is stacked with the first drain structure 1122 along the first direction, and a second metal interconnection through-hole 132 is arranged between the second gate structure 124 and the first drain structure 1122; the first metal interconnection through-hole 131 is used to connect the second drain structure 1222 and the first gate structure 114, and the second metal interconnection through-hole 132 structure is used to connect the second gate structure 124 and the first drain structure 1122.

[0113] In some embodiments, the stacked transistor 10 further includes: a first single diffusion isolation structure 24 stacked along the first direction with the second source structure 1221, and a second single diffusion isolation structure 27 stacked along the first direction with the first source structure 1121; wherein the first single diffusion isolation structure 24 is used to electrically isolate two adjacent first transistors 11; and the second single diffusion isolation structure 27 is used to electrically isolate two adjacent second transistors 12.

[0114] In some embodiments, when at least one first transistor 11 is a plurality of first transistors 11 , two adjacent first transistors 11 share a first source structure 1121 , and / or, when at least one second transistor 12 is a plurality of second transistors 12 , two adjacent second transistors 12 share a second source structure 1221 .

[0115] Understandably, see Figure 4 As can be seen from the diagram shown in Figure 4The first coupling capacitor Decap1 and the second coupling capacitor Decap2 are included. The first coupling capacitor Decap1 includes a pair of stacked transistors (consisting of a first transistor 11 and a second transistor 12), and the second coupling capacitor Decap1 includes a pair of stacked transistors (consisting of a first transistor 11 and a second transistor 12), that is, there are two first transistors 11 and two second transistors 12. Among them, two adjacent second transistors 12 can be isolated by a second single diffusion isolation structure 27, and two adjacent first transistors 11 can share the structure in the cross-sectional view in the DD' direction, that is, the first source structure 1121. Similarly, in some embodiments, the two adjacent first transistors 11 in the first coupling capacitor Decap1 and the second coupling capacitor Decap2 can be isolated by a first single diffusion isolation structure 24, and the two adjacent second transistors 12 can share a second source structure 1221.

[0116] Furthermore, assuming that Figure 4 If a pair of stacked transistors (consisting of a first transistor 11 and a second transistor 12) is added to the structure shown, the first transistor 11 in the second coupling capacitor Decap2 can be isolated from the newly added first transistor 11 by the first single diffusion isolation structure 24, and the second transistor 12 in the second coupling capacitor Decap2 and the newly added second transistor can share a second source structure 1221. Based on this, the embodiment of the present application can achieve that when the number of pairs of transistors is N, the area occupied by the stacked transistors is 3N+1 contact pitches (CPP).

[0117] In the embodiment of the present application, the interconnection lines inside the coupling capacitor do not need to rely on metal interconnection layers, nor do they require a large aspect ratio (via), and are compatible with the original process flow, which can reduce dependence on the process. At the same time, when multiple coupling capacitors are connected in parallel, each coupling capacitor unit does not need to occupy more space, and the layout area of ​​multiple coupling capacitors only increases one contact spacing compared to the related technology, thereby improving the integration performance of the transistor.

[0118] In one or more of the above-mentioned embodiments of preparing stacked transistors, the stacked transistors are also self-aligned, which solves the long-standing problems of complex processes and alignment difficulties in the existing mainstream technical solutions for stacked transistors, and promotes the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through stacked transistors, which greatly releases metal wiring resources without changing the extremely miniaturized 4T track unit design.

[0119] Finally, the solution of realizing upper and lower transistors by flipping the wafer is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, FinFET, GAA Nanosheet and even vertical transistors (VTFET), without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for development.

[0120] In a third aspect, an embodiment of the present application provides a semiconductor device, including: a stacked transistor as in the above embodiment. The specific definition of the stacked transistor can be at least referred to in the above Fig.21 The stacked transistors shown are not described in detail here.

[0121] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as in the above embodiment, wherein the semiconductor device is disposed on the circuit board. The semiconductor device comprises the above stacked transistor. The specific definition of the stacked transistor can be at least referred to in the above Fig.21 The structure shown in FIG. 1 is not described in detail here.

[0122] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0123] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: include: forming a fin structure on a semiconductor substrate, wherein the fin structure comprises a first portion and a second portion stacked along a first direction, the first portion being closer to the semiconductor substrate than the second portion; Based on the first part, at least one first transistor is formed, wherein the first transistor comprises: a first drain structure, a first gate structure and a first source structure arranged in sequence along a second direction; the second direction is perpendicular to the first direction; Flipping and removing the semiconductor substrate; Based on the second part, at least one second transistor is formed, wherein the second transistor comprises: a second source structure, a second gate structure, and a second drain structure arranged in sequence along a second direction; the second gate structure and the first drain structure are stacked along a first direction, and the second drain structure and the first gate structure are stacked along the first direction; A first metal interconnection through hole is formed to connect the second drain structure and the first gate structure, and a second metal interconnection through hole is formed to connect the second gate structure and the first drain structure.

2. The preparation method according to claim 1, characterized in that: The forming of at least one second transistor based on the second portion comprises: Based on the second part, the second source structure and the second drain structure are alternately arranged in sequence along the second direction; Based on the second part, the second gate structure and the second single diffusion isolation structure are formed between the second source structure and the second drain structure, so that the second source structure, the second gate structure, the second drain structure and the second single diffusion isolation structure are arranged in sequence; wherein the second single diffusion isolation structure and the first source structure are stacked along the first direction; the second source structure and the first single diffusion isolation structure in the first transistor are stacked along the first direction; one second gate structure and the adjacent second source structure and the second drain structure form a second transistor; the second single diffusion isolation structure is used to electrically isolate two adjacent second transistors.

3. The preparation method according to claim 2, characterized in that: The second gate structure and the second single diffusion isolation structure are formed between the second source structure and the second drain structure based on the second portion, including: Based on the second portion, forming the second gate structure on the first source structure and the first drain structure; The second gate structure located above the first source structure is removed, and an insulating material is deposited at the location where the second gate structure is removed to form the second single diffusion isolation structure.

4. The preparation method according to claim 2, characterized in that: The method of forming the second source structure and the second drain structure alternately arranged in sequence along the second direction based on the second portion includes: Based on the second portion, forming the second drain structure on the first gate structure; Based on the second portion, the second source structure is formed on both sides of the second drain structure, so that the second source structure and the second drain structure are alternately arranged in sequence along the second direction.

5. The preparation method according to claim 1, characterized in that: The forming of at least one first transistor based on the first portion comprises: Based on the first part, forming the first drain structure and the first source structure alternately arranged in sequence along the second direction; Based on the first part, the first gate structure and the first single diffusion isolation structure are formed between the first drain structure and the first source structure, so that the first single diffusion isolation structure, the first drain structure, the first gate structure and the first source structure are arranged in sequence; the first single diffusion isolation structure is used to electrically isolate two adjacent first transistors.

6. The preparation method according to claim 1, characterized in that: The second transistor includes a second drain metal; The forming of a first metal interconnection through hole connecting the second drain structure and the first gate structure, and the forming of a second metal interconnection through hole connecting the second gate structure and the first drain structure, include any one of the following: Before forming the second drain metal, forming a first metal interconnection through hole connecting the second drain structure and the first gate structure, and before forming the second gate structure, forming a second metal interconnection through hole connecting the second gate structure and the first drain structure; Before forming the second drain metal, forming a first metal interconnection through hole connecting the second drain structure and the first gate structure, and after forming the second gate structure, forming a second metal interconnection through hole connecting the second gate structure and the first drain structure; After forming the second drain metal, a first metal interconnection through hole connecting the second drain structure and the first gate structure is formed, and before the second gate structure, a second metal interconnection through hole connecting the second gate structure and the first drain structure is formed.

7. A stacked transistor, characterized in that: include: At least one first transistor and at least one second transistor, wherein the first transistor and the second transistor are stacked along a first direction; Wherein, the first transistor comprises: a first drain structure, a first gate structure and a first source structure arranged in sequence along a second direction; the second direction is perpendicular to the first direction; the second transistor comprises: a second source structure, a second gate structure and a second drain structure arranged in sequence along the second direction; The second drain structure is stacked with the first gate structure along a first direction, and a first metal interconnection through hole is provided between the second drain structure and the first gate structure; the second gate structure is stacked with the first drain structure along the first direction, and a second metal interconnection through hole is provided between the second gate structure and the first drain structure; The first metal interconnection through hole is used to connect the second drain structure and the first gate structure, and the second metal interconnection through hole structure is used to connect the second gate structure and the first drain structure.

8. The stacked transistor according to claim 7, characterized in that: The stacked transistor further includes: a first single diffusion isolation structure stacked with the second source structure along the first direction, and a second single diffusion isolation structure stacked with the first source structure along the first direction; The first single diffusion isolation structure is used to electrically isolate two adjacent first transistors; and the second single diffusion isolation structure is used to electrically isolate two adjacent second transistors.

9. The stacked transistor according to claim 7, characterized in that: The at least one first transistor is a plurality of first transistors, two adjacent first transistors share a first source structure, and / or, When the at least one second transistor is a plurality of second transistors, two adjacent second transistors share one second source structure.

10. A semiconductor device, characterized in that: include: A stacked transistor as claimed in any one of claims 7 to 9.

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