Preparation method of stacked transistor, stacked transistor, device and equipment

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment, and the method comprises the steps: forming a semiconductor structure on a substrate, the semiconductor structure at least comprises a sacrificial layer, a first semiconductor structure and a second semiconductor structure which are stacked in sequence; etching the semiconductor structure of the source-drain region, and filling an insulating material in a region corresponding to the sacrificial layer of the source-drain region to form a placeholder structure; a first part of the first transistor is formed on the placeholder structure through a previous process based on the first semiconductor structure, and the first part at least comprises a first source-drain structure; forming a second transistor based on the second semiconductor structure; performing wafer reversing on the second transistor, and exposing the occupying structure; removing the placeholder structure to form first source-drain contact metal of the first transistor; and forming a first metal interconnection layer of the first transistor on the first source-drain contact metal through a back-end process. According to the invention, self-aligned contact between the top transistor and the bottom transistor can be realized.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a stacked transistor, a transistor, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In the related art, the source-drain contact metal and metal interconnect layer of the top transistor and the bottom transistor of the stacked transistor are prepared separately by wafer flipping. However, wafer flipping also brings about the problem that the source-drain contact metal of the top transistor and the bottom transistor cannot be aligned. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus, which can achieve self-aligned contact between a top transistor and a bottom transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, the method comprising: forming a semiconductor structure on a substrate, the semiconductor structure comprising at least a sacrificial layer, a first semiconductor structure, and a second semiconductor structure stacked in sequence; etching the semiconductor structure in the source and drain regions, and filling an insulating material in the region corresponding to the sacrificial layer in the source and drain regions to form a placeholder structure; on the placeholder structure, through a front-end process, based on the first semiconductor structure, forming a first part of a first transistor, the first part comprising at least a first source and drain structure; based on the second semiconductor structure, forming a second transistor; flipping the second transistor and exposing a placeholder (PH) structure; removing the placeholder structure to form a first source and drain contact metal of the first transistor; and through a back-end process, forming a first metal interconnection layer of the first transistor on the first source and drain contact metal.

[0006] In a possible implementation, removing the placeholder structure to form a first source-drain contact metal of the first transistor includes: removing the placeholder structure to expose the first source-drain structure; and depositing a metal material on the first source-drain structure to form a first source-drain contact metal.

[0007] In one possible embodiment, exposing the placeholder structure includes: removing the substrate to expose the sacrificial layer in the gate region and the placeholder structure in the source and drain region; forming a first metal interconnection layer of the first transistor on the first source and drain contact metal through a back-end process, including: removing the sacrificial layer in the gate region to form a first groove; filling the first groove with a metal material to form a gate contact metal of the first transistor; forming a first metal interconnection layer on the gate contact metal and the first source and drain contact metal, wherein one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnection layer.

[0008] In one possible embodiment, after forming the first source-drain contact metal, the method also includes: depositing a dielectric material on the first source-drain contact metal to form a first isolation structure, one side of the first isolation structure contacts the first source-drain contact metal in a first direction, and the first direction is a direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure; filling an insulating material on the gate region to form a second isolation structure, the second isolation structure contacts the other side of the first isolation structure in the first direction; removing the sacrificial layer in the gate region to form a first groove, including: anisotropically etching a portion of the second isolation structure and the sacrificial layer to form the first groove.

[0009] In one possible embodiment, before etching the first semiconductor structure in the source-drain region, the method also includes: depositing semiconductor material in the gate region to form a pseudo-gate structure surrounding the first semiconductor structure and the second semiconductor structure; based on the first semiconductor structure, forming a first part of the first transistor, including: epitaxially growing a first source-drain structure on the first semiconductor structure; forming a first interlayer dielectric layer on the first source-drain structure; based on the second semiconductor structure, forming a second transistor, including: epitaxially growing a second source-drain structure on the second semiconductor structure; forming a second interlayer dielectric layer on the second source-drain structure; removing the pseudo-gate structure to expose the semiconductor structure in the gate region; forming a gate structure based on the semiconductor structure in the gate region, the gate structure including a first gate structure corresponding to the first semiconductor structure and a second gate structure corresponding to the second semiconductor structure; etching the second interlayer dielectric layer to expose the second source-drain structure; depositing metal material on the second source-drain structure to form a second source-drain contact metal of the second transistor; and forming a second metal interconnect layer of the second transistor on the second source-drain contact metal through a back-end process.

[0010] In a possible implementation, after forming a gate structure based on the semiconductor structure in the gate region, the method further includes: forming a gate cutoff structure on both sides of the gate structure, the gate cutoff structure being used to isolate the gate region of the stacked transistor from the gate region of an adjacent stacked transistor.

[0011] In a second aspect, an embodiment of the present application provides a stacked transistor, which is manufactured using the preparation method described in the first aspect and any one of its embodiments, and includes: a first transistor; a second transistor, the first transistor and the second transistor are stacked; wherein the first source-drain contact metal of the first transistor is self-aligned with the second source-drain contact metal of the second transistor.

[0012] In one possible embodiment, one side of the first source-drain contact metal is connected to the first source-drain structure of the first transistor, the other side of the first source-drain contact metal is connected to the first metal interconnection layer of the first transistor, one side of the second source-drain contact metal is connected to the second source-drain structure of the second transistor, and the other side of the second source-drain contact metal is connected to the second metal interconnection layer of the second transistor.

[0013] In a possible implementation, the first transistor includes a gate contact metal, one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnection layer of the first transistor.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a stacked transistor as described in the second aspect above.

[0015] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0016] In the embodiment of the present application, a sacrificial layer, a first semiconductor structure and a second semiconductor structure are stacked sequentially on a substrate, and then the semiconductor structure in the source and drain region is etched, and an insulating material is filled in the region corresponding to the sacrificial layer in the source and drain region to form a placeholder structure, which is used to locate the source and drain contact metal of the bottom transistor; on the placeholder structure, a first part of the first transistor is formed based on the first semiconductor structure through a front-end process; a second transistor is formed based on the second semiconductor structure; the wafer is flipped and the placeholder structure is exposed; the placeholder structure is removed to form a first source and drain contact metal of the first transistor; and a first metal interconnection layer of the first transistor is formed on the first source and drain contact metal through a back-end process. After flipping the transistor, there is no need to select the region where the source and drain contact metal is located by photolithography, and the placeholder structure can be directly removed by material selectivity, and a metal material can be filled in the groove after the placeholder structure is removed to form a source and drain contact metal that is self-aligned with the source and drain contact metal of the top transistor. Therefore, the embodiment of the present application can realize self-aligned contact between the top transistor and the bottom transistor, while avoiding the short circuit failure problem caused by misalignment between the top transistor and the bottom transistor.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application;

[0020] Figure 2 is a schematic top view of a stacked transistor in an embodiment of the present application;

[0021] FIG. 3A to FIG. 3M This is a schematic diagram of the structure of a stacked transistor during the preparation process in an embodiment of the present application;

[0022] Figure 4 Schematic diagram of the structure of stacked transistors in an embodiment of the present application.

[0023] The above pictures:

[0024] 10. stacked transistor; 11. first transistor (bottom transistor); 111. first nanosheet structure; 112. first source-drain structure; 113. first interlayer dielectric layer; 114. first gate structure; 1141. first gate dielectric layer; 1142. first gate electrode layer; 115. first source-drain contact metal; 116. first metal interconnect layer; 12. second transistor (top transistor); 121. second nanosheet structure; 122. second source-drain structure; 123. second interlayer dielectric layer; 124. second gate structure; 1241. second gate dielectric layer; 1242. second gate electrode layer; 125. second source-drain contact metal; 126. second metal interconnect layer; 13. insulating layer; 14. carrier wafer; 20. substrate Bottom; 21, first sacrificial layer; 22, stacked layer; 23, semiconductor structure; 231, first semiconductor structure; 232, second semiconductor structure; 24, second sacrificial layer; 25, third isolation structure; 26, oxide layer; 27, pseudo gate structure; 28, side wall; 29, inner side wall; 30, protective layer; 31, second groove; 32, placeholder structure; 33, source-drain isolation dielectric layer; 34, third groove; 35, first BDI layer; 36, gate cut-off structure; 361, SDB structure; 37, fourth groove; 38, fourth isolation structure; 39, insulating structure; 40, bottom dielectric layer; 41, fifth groove; 42, first isolation structure; 43, second isolation structure; 44, first groove; 45, gate contact metal. DETAILED DESCRIPTION

[0025] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0026] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0027] In one embodiment, there are two schemes for the preparation process of stacked transistors, the first is a monolithic stacking scheme, and the second is a sequential scheme, but both schemes have certain technical problems. In order to solve the technical problems, a stacked transistor is proposed, which forms the active area of ​​the upper and lower layers of the same source transistors by etching, and realizes the production of stacked transistors on the front and back of the wafer by wafer flipping, so as to overcome the shortcomings of the above two schemes. However, wafer flipping also brings about the problem of misalignment of the source and drain contact metals of the top transistor and the bottom transistor, which leads to the short circuit failure problem between the device electrodes.

[0028] To solve the above technical problems, an embodiment of the present application provides a method for preparing a stacked transistor, which can achieve self-aligned contact between the top transistor and the bottom transistor, while avoiding the short circuit failure problem caused by misalignment of the top transistor and the bottom transistor.

[0029] In the embodiments of the present application, the stacked transistor can be applied to semiconductor devices such as memory and processor.

[0030] In some embodiments, the stacked transistor may include at least two transistors. Taking a first transistor and a second transistor as an example, the first transistor and the second transistor are stacked, and a first source-drain contact metal of the first transistor is self-aligned with a second source-drain contact metal of the second transistor in a vertical direction.

[0031] In some embodiments, the first transistor includes a gate contact metal, one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnect layer of the first transistor.

[0032] In an embodiment of the present application, the first transistor and the second transistor in the stacked transistor are transistors of the same type, and the type of the transistor may include but is not limited to: fin field effect transistor (FinFET), gate-all-around field effect transistor (GAAFET), planar transistor, vertical field effect transistor (VFET), etc.

[0033] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application. Figure 1 As shown, the method for preparing the stacked transistor in the embodiment of the present application includes the following steps.

[0034] Step S110: forming a semiconductor structure on a substrate.

[0035] In some embodiments, the semiconductor structure includes a sacrificial layer (a second sacrificial layer), a first semiconductor structure, and a second semiconductor structure stacked in sequence.

[0036] In some embodiments, the implementation process of step S110 can be divided into the following three steps: providing a substrate; sequentially forming a sacrificial layer and a first material layer on the substrate; etching the sacrificial layer and the first material layer to form a semiconductor structure, wherein the etched first sacrificial layer serves as the second sacrificial layer, the etched first material layer close to the substrate serves as the first semiconductor structure, and the etched first material layer far from the substrate serves as the second semiconductor structure.

[0037] By way of example, the substrate may be any semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate.

[0038] After providing a substrate, semiconductor materials can be stacked on the substrate to form a first sacrificial layer and a first material layer, and certain areas of the first sacrificial layer and the first material layer can be etched to form a plurality of semiconductor structures standing on the substrate. The material forming the first sacrificial layer is different from the material forming the first material layer, so that the first sacrificial layer (second sacrificial layer) after etching can be removed by material selectivity in the subsequent process, and the role of the second sacrificial layer will be described later. The etching process can be, for example, at least one of dry etching, wet etching, reactive ion etching, etc.

[0039] Here, each semiconductor structure includes a first part (first semiconductor structure) and a second part (second semiconductor structure), and the first part is closer to the substrate than the second part, that is, the first material layer after etching is divided into two parts, the lower half close to the substrate is used as the first semiconductor structure, and the upper half away from the substrate is used as the second semiconductor structure.

[0040] In some embodiments, the first material layer may include a first semiconductor material, or the first material layer may include at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along an arrangement direction of the semiconductor structure. For example, the first semiconductor material may be silicon, and the second semiconductor material may be silicon germanium.

[0041] It can be understood that the first material layer can be a single layer formed by depositing one material, or can be a stacked layer formed by alternately depositing two different materials.

[0042] In one example, when the stacked transistor is a FinFET, the material forming the substrate may be silicon, the material forming the second sacrificial layer may be silicon germanium, and the material forming the first material layer in the first semiconductor structure and the second semiconductor structure may be silicon. The first semiconductor structure and the second semiconductor structure here may also be referred to as the first active structure and the second active structure. When the stacked transistor is a GAAFET, the material forming the substrate may be silicon, the material forming the second sacrificial layer may be silicon germanium, and the material forming the first material layer in the first semiconductor structure and the second semiconductor structure may be silicon germanium and silicon deposited alternately. The silicon germanium material in the first semiconductor structure and the second semiconductor structure may be removed subsequently to form the first active structure and the second active structure. Among them, the germanium content in the silicon germanium material forming the second sacrificial layer is different from the germanium content in the silicon germanium material forming the first semiconductor structure and the second semiconductor structure. For example, SiGe 1 may be used to prepare the second sacrificial layer, and SiGe 2 may be used to prepare the first semiconductor structure and the second semiconductor structure).

[0043] In some embodiments, after forming the semiconductor structure, an insulating material may be deposited on the substrate to form an isolation structure. For ease of distinction, the isolation structure here is referred to as a third isolation structure.

[0044] It is understandable that after forming the semiconductor structure, an insulating material may be deposited on the substrate and the oxide material may be thinned so that the upper surface of the formed third isolation structure is flush with the upper surface of the second sacrificial layer to expose the first semiconductor structure.

[0045] In one example, the third isolation structure may be formed by shallow trench isolation (STI). For example, the oxide material forming the third isolation structure may be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO). The thinning process may be a process such as chemical-mechanical planarization (CMP).

[0046] In some embodiments, after forming the semiconductor structure, a semiconductor material may be deposited in the gate region to form a dummy gate structure surrounding the first semiconductor structure and the second semiconductor structure.

[0047] To distinguish the semiconductor material from the first semiconductor material and the second semiconductor material, the semiconductor material here is referred to as a third semiconductor material, where the third semiconductor material may be, for example, polysilicon (poly Si), amorphous silicon, or the like.

[0048] It is understandable that after forming the semiconductor structure and the third isolation structure, the gate region can be opened by photolithography, and a third semiconductor material such as polysilicon can be deposited in the gate region as a pseudo-gate structure shared by the top transistor and the bottom transistor. That is, the embodiment of the present application defines the gate region of the top transistor and the bottom transistor in the stacked transistor by the pseudo-gate structure, so that the self-alignment of the upper and lower transistors in the stacked transistor can be achieved in the gate region. Among them, the height of the pseudo-gate structure is greater than the height of the semiconductor structure.

[0049] In some embodiments, after forming the dummy gate structure, spacers may be formed on both sides of the dummy gate structure. For example, the spacers may have a single layer structure and be made entirely of the same material, such as porous silicon oxycarbon hydride (SICOH).

[0050] In some embodiments, after forming the semiconductor structure, an oxide material may be deposited on the substrate to form an oxide layer, the oxide layer covering the semiconductor structure. After forming the oxide layer, a dummy gate may be formed on the oxide layer.

[0051] It is understandable that when depositing oxide to form an oxide layer, an atomic layer deposition (ALD) method may be used to deposit a very thin film on the surface of the substrate.

[0052] Step S120: etching the semiconductor structure in the source and drain regions, and filling the region corresponding to the sacrificial layer in the source and drain regions with insulating material to form a placeholder structure.

[0053] It can be understood that the pseudo-gate structure, the oxide layer, the first semiconductor structure and the second semiconductor structure in the source and drain region can be etched to expose the second sacrificial layer in the source and drain region and the third isolation structure on both sides of the second sacrificial layer, and then the second sacrificial layer is further etched, and the insulating material is filled in the groove formed after the second sacrificial layer is etched to form a placeholder structure. Since the location of the second sacrificial layer is the location of the source and drain contact metal of the top transistor, the embodiment of the present application pre-positions the location of the source and drain contact metal of the bottom transistor through the placeholder structure to avoid the position of the transistor being offset due to wafer bending after subsequent flipping, and the lithography being misaligned, thereby causing the source and drain contact metal of the formed bottom transistor to be misaligned with the source and drain contact of the top transistor. By way of example, the insulating material can be silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc.

[0054] In some embodiments, when etching the dummy gate structure, the oxide layer, the first semiconductor structure, and the second semiconductor structure, a portion of the bottom dummy gate structure and the oxide layer may be retained to serve as a guide oxide layer. In this way, when forming a placeholder structure, the upper surface of the placeholder structure is flush with the upper surface of the guide oxide layer.

[0055] In some embodiments, when the semiconductor structure of the stacked transistor includes Si and SiGe2 stacked in sequence, before etching the second sacrificial layer to form a placeholder structure, a portion of the SiGe2 in the first semiconductor structure and the second semiconductor structure may be laterally etched, and the etched area may be filled with insulating material to form a first inner spacer located on both sides of the SiGe2 in the first semiconductor structure, and a second inner spacer located on both sides of the SiGe2 in the second semiconductor structure.

[0056] In some embodiments, after forming the first inner sidewall spacer and the second inner sidewall spacer, a protective layer may be formed on both sides of the stacked layer of the top transistor to avoid affecting the top transistor when preparing the bottom transistor.

[0057] Step S130: forming a first part of a first transistor on the placeholder structure through a front-end process based on the first semiconductor structure.

[0058] It can be understood that after forming the placeholder structure, a portion of the bottom transistor (first transistor) can be formed on the placeholder structure.

[0059] In some embodiments, the implementation process of step S130 may be: epitaxially growing a first source-drain structure on the first semiconductor structure; forming a first interlayer dielectric layer on the first source-drain structure;

[0060] It can be understood that after etching the first semiconductor structure in the source-drain region in the aforementioned step, a source-drain groove will be formed, so source-drain epitaxial growth can be performed in the source-drain groove to form a first source-drain structure.

[0061] Exemplarily, strained materials such as silicon germanium or silicon carbide can be formed in the source and drain grooves by selective epitaxial growth to fill the source and drain grooves of the bottom transistor (first transistor), and then a first source and drain structure is formed on the strained material by a heavy doping process.

[0062] After forming the first source-drain structure, an interlayer dielectric may be deposited on the first source-drain structure, and the interlayer dielectric may be thinned to the upper surface of the first source-drain structure to form a first interlayer dielectric layer. The interlayer dielectric may be SiO2, for example.

[0063] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the first source-drain contact metal, the second source-drain structure, the second source-drain contact metal, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0064] In some embodiments, after forming the first interlayer dielectric layer, an insulating material may be deposited on the first interlayer dielectric layer and CMP may be performed to form a source-drain isolation dielectric layer, the source-drain isolation dielectric layer being used to isolate the first source-drain structure of the first transistor from the second source-drain structure of the second transistor. In this case, a top transistor (second transistor) may be formed on the first interlayer dielectric layer.

[0065] Step S140: forming a second transistor based on the second semiconductor structure.

[0066] In some embodiments, the implementation process of step S140 may be: epitaxially growing a second source-drain structure on a second semiconductor structure; forming a second interlayer dielectric layer on the second source-drain structure; removing the dummy gate structure to expose the semiconductor structure in the gate region; forming a gate structure based on the semiconductor structure in the gate region, the gate structure including a first gate structure corresponding to the first semiconductor structure and a second gate structure corresponding to the second semiconductor structure; etching the second interlayer dielectric layer to expose the second source-drain structure; depositing metal material on the second source-drain structure to form a second source-drain contact metal of the second transistor; and forming a second metal interconnect layer of the second transistor on the second source-drain contact metal through a back-end process.

[0067] It can be understood that after the second semiconductor structure in the etching area is formed, a source-drain groove will be formed, so source-drain epitaxial growth can be performed at the source-drain groove to form a second source-drain structure, and then an interlayer dielectric is deposited on the second source-drain structure, and the interlayer dielectric is thinned to the upper surface of the second source-drain structure to form a second interlayer dielectric layer. The pseudo-gate structure formed above can then be removed to form a first gate structure of the first transistor and a second gate structure of the second transistor. A gate groove is obtained after the pseudo-gate structure, and a gate structure shared by the bottom transistor and the top transistor is formed at the gate groove. Among them, the gate structure includes a gate dielectric layer formed by depositing an insulating material at the gate groove, and a gate electrode layer formed by depositing a metal material on the gate dielectric layer. Accordingly, the first gate structure includes a first gate dielectric layer and a first gate electrode layer, and the second gate structure includes a second gate dielectric layer and a second gate electrode layer.

[0068] For example, the gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0069] By way of example, the gate electrode layer may be composed of multiple layers of electrode materials, each layer of which includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0070] In the case where the stacked transistor is a GAAFET, the first material layer forming the first semiconductor structure and the second semiconductor structure is alternately deposited silicon germanium and silicon, so when removing the dummy gate structure, the silicon germanium material in the first semiconductor structure and the second semiconductor structure can be removed to form a nanosheet structure. The nanosheet structure includes a first nanosheet structure of the bottom transistor and a second nanosheet structure of the top transistor.

[0071] It is understandable that after forming the gate structure, a portion of the second interlayer dielectric layer may be etched to expose the second source-drain structure, and then a metal material may be deposited on the second source-drain structure to form a second source-drain contact metal. After forming the second source-drain contact metal, a back-end process may be performed to form a second metal interconnect layer.

[0072] It can be understood that the back-end process may be, for example, dielectric deposition between interconnect lines, metal line formation, lead pad formation and the like. For example, the second metal interconnect layer may include power lines and signal lines.

[0073] In some embodiments, when etching the second interlayer dielectric layer to expose the second source-drain structure, a portion of the second source-drain structure may be etched at an angle, and then a second source-drain contact metal is formed, thereby increasing the contact area.

[0074] The gate structure of the bottom transistor and the gate structure of the top transistor are formed at one time. The gate structure of the bottom transistor and the gate structure of the top transistor can also be formed separately. In this case, after removing the dummy gate structure and forming a gate structure shared by the bottom transistor and the top transistor, the gate structure can be back-etched to the bottom of the top transistor, and the retained gate structure is used as the first gate structure of the bottom transistor, and metal material is filled in the exposed gate area to form a second gate structure of the top transistor. At this time, the metal material in the second gate structure can be different from the metal material in the first gate structure.

[0075] In some embodiments, after forming the gate structure and before forming the second source-drain contact metal, a gate cut structure may be formed on both sides of the gate structure, the gate cut structure being used to isolate the gate region of the stacked transistor from the gate region of the adjacent stacked transistor. Accordingly, the gate cut structure includes a first gate cut structure corresponding to the first gate structure and a second gate cut structure corresponding to the second gate structure.

[0076] It can be understood that the gate cut-off structure can be formed by cutting off the gate at the edge of the gate structure, that is, at both ends of the gate structure along the extension direction to form two grooves, and then filling the two grooves with insulating material.

[0077] In some embodiments, after forming the gate cutoff structure and before forming the second source-drain contact metal, a single diffusion break (SDB) structure may be formed at the edge of the stacked transistor, and the single diffusion break (SDB) structure may electrically isolate the stacked transistor from adjacent stacked transistors.

[0078] It can be understood that by removing the structures located at the edges of both sides of the stacked transistor through an etching process and depositing insulating materials at the removed positions, a single diffusion isolation structure can be formed.

[0079] In some embodiments, while removing the dummy gate structure, a portion of the third isolation structure in the gate region may also be removed, and then the second sacrificial layer located between the third isolation structures may be removed, and an insulating dielectric may be deposited in the groove after the second sacrificial layer is removed to form a bottom dielectric isolation (BDI) layer.

[0080] It is understandable that when depositing the insulating medium, it is deposited from bottom to top on the surface of the substrate, so there will also be a portion of the insulating medium on the retained third isolation structure, which can be removed later to ensure that the BDI layer is located in the middle of the retained third isolation structure.

[0081] Step S150: flipping the second transistor and exposing the placeholder structure.

[0082] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the second metal interconnect layer to form an insulating layer, and the insulating layer may be bonded to a carrier wafer, and then flipped over to place a substrate thereon.

[0083] In some embodiments, after flipping the wafer, the upper substrate may be removed to expose the sacrificial layer in the gate region and the placeholder structure in the source and drain region. It should be noted that in the case of forming the BDI layer, what is exposed in the gate region is the BDI layer, and in the case of not forming the BDI layer, what is exposed in the gate region is the second sacrificial layer.

[0084] In some embodiments, when the BDI layer is exposed in the gate region, the BDI layer can be selectively removed, and a fourth isolation structure is formed on both sides of the placeholder structure in the removed position to isolate the sidewalls contacting the gate region. Then, an insulating material can be deposited in the remaining removed positions to form an insulating structure.

[0085] In some embodiments, when the second sacrificial layer is exposed in the gate region, the second sacrificial layer can be selectively removed, and a fourth isolation structure can be formed on both sides of the placeholder structure in the removed position, and then an insulating material can be deposited in the remaining removed position to form an insulating structure.

[0086] Step S160: removing the placeholder structure to form a first source-drain contact metal of the first transistor.

[0087] In some embodiments, the implementation process of step S160 may be: removing the placeholder structure to expose the first source-drain structure, and depositing a metal material on the first source-drain structure to form a first source-drain contact metal.

[0088] It can be understood that since the placeholder structure is used to locate the source and drain contact metal of the bottom transistor, after the transistor is flipped over, there is no need to select the location of the source and drain contact metal by photolithography. The placeholder structure can be directly removed by selective removal of the material, and the metal material can be filled in the groove after removing the placeholder structure to form a source and drain contact metal that is self-aligned with the source and drain contact metal of the top transistor.

[0089] In some embodiments, when the placeholder structure is removed to expose the first source-drain structure, a portion of the first source-drain structure may be etched at an angle, and then a first source-drain contact metal is formed to increase the contact area.

[0090] In some embodiments, before removing the placeholder structure, an insulating material may be deposited on the first transistor to form a bottom dielectric layer, and then the bottom dielectric layer is photolithographically processed to form a pattern of the source-drain contact metal of the bottom transistor to expose the placeholder structure below, and then the placeholder structure is selectively etched to expose the first source-drain structure, and then a metal material is deposited on the first source-drain structure and CMP is performed to form a first source-drain contact metal, and the upper surface of the first source-drain contact metal is flush with the bottom dielectric layer. In this case, the height of the formed first source-drain contact metal is relatively high.

[0091] In the case where a bottom dielectric layer exists, after the first source-drain contact metal is formed, the bottom dielectric layer is removed.

[0092] In some embodiments, after forming the first source-drain contact metal, a dielectric material may be deposited on the first source-drain contact metal and backetched to form a first isolation structure, one side of the first isolation structure is in contact with the first source-drain contact metal in a first direction, and the first direction is a direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure; an insulating material is filled on the gate region to form a second isolation structure, and the second isolation structure is in contact with the other side of the first isolation structure in the first direction.

[0093] It can be understood that after forming the first source-drain contact metal, a dielectric material can be isotropically deposited, and the dielectric material structure deposited in this way is located above and on both sides of the first source-drain contact metal. Then, anisotropic etching can be performed to remove the dielectric material located above the first source-drain contact metal to form a first isolation structure, and the first isolation structure is used as a sidewall isolation of the gate metal in the gate region and the source-drain contact metal in the source-drain region. After forming the first isolation structure, an insulating material can be deposited and CMPed in the exposed area to form a second isolation structure, and the second isolation structure is in contact with the first isolation structure, and the height of the second isolation structure is the same as the height of the first isolation structure.

[0094] Step S170: forming a first metal interconnection layer of the first transistor on the first source-drain contact metal through a back-end process.

[0095] In some embodiments, the implementation process of step S170 may be: removing the sacrificial layer in the gate area to form a first groove; filling the first groove with metal material to form a gate contact metal of the first transistor; forming a first metal interconnection layer on the gate contact metal and the first source and drain contact metal, wherein one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnection layer.

[0096] It can be understood that in the case of removing the second sacrificial layer in the gate region to form an insulating structure, the insulating structure and the third isolation structure are above the gate structure in the gate region, so the insulating structure can be etched, and metal material can be deposited at the etched position to form a gate contact metal, and then the first metal interconnection layer is formed through a back-end process. For example, there can be power lines and signal lines in the first metal interconnection layer. The embodiment of the present application can be compatible with other signal line arrangements, such as the metal interconnection layer of the top transistor has signal lines and power lines, and the metal interconnection layer of the bottom transistor has only power lines and signal lines for internal winding only, etc. The embodiment of the present application does not limit the arrangement of signal lines in the metal interconnection layers of the top transistor and the bottom transistor.

[0097] When the second isolation structure is formed in the aforementioned step S160 , a portion of the second isolation structure and the insulating structure may be anisotropically etched to form a first groove, and then a metal material is deposited to form a gate contact metal.

[0098] In the embodiment of the present application, a sacrificial layer, a first semiconductor structure and a second semiconductor structure are stacked sequentially on a substrate, and then the semiconductor structure in the source and drain region is etched, and an insulating material is filled in the region corresponding to the sacrificial layer in the source and drain region to form a placeholder structure, which is used to locate the source and drain contact metal of the bottom transistor; on the placeholder structure, a first part of the first transistor is formed based on the first semiconductor structure through a front-end process; a second transistor is formed based on the second semiconductor structure; the wafer is flipped and the placeholder structure is exposed; the placeholder structure is removed to form a first source and drain contact metal of the first transistor; and a first metal interconnection layer of the first transistor is formed on the first source and drain contact metal through a back-end process. After flipping the transistor, there is no need to select the region where the source and drain contact metal is located by photolithography, and the placeholder structure can be directly removed by material selectivity, and a metal material can be filled in the groove after the placeholder structure is removed to form a source and drain contact metal that is self-aligned with the source and drain contact metal of the top transistor. Therefore, the embodiment of the present application can realize self-aligned contact between the top transistor and the bottom transistor, while avoiding the short circuit failure problem caused by misalignment between the top transistor and the bottom transistor. The solution of the present application is beneficial to improving the process success rate and the electrical performance of transistors, and is beneficial to further miniaturization of the size of standard cells.

[0099] The following describes a method for preparing a stacked transistor provided in an embodiment of the present application by taking a stacked transistor in which the active structure is a nanosheet structure as an example. Figure 2 is a schematic top view of a stacked transistor in an embodiment of the present application, Figure 2(a) is the front layout in the top view, and (b) is the back layout. It should be noted that for ease of understanding, only the nanosheet structure, gate structure, and source-drain structure are shown in the top view. The AA' direction is the cross-sectional direction of the stacked transistor along the gate structure; the BB' direction is the cross-sectional direction of the stacked transistor along the source-drain structure; and the CC' direction is the cross-sectional direction of the stacked transistor along the nanosheet structure.

[0100] The following describes the preparation process of the stacked transistor provided in the embodiment of the present application. FIG. 3A to FIG. 3M is a schematic diagram of the structure of the stacked transistor in the manufacturing process of an embodiment of the present application, Figure 4 It is a schematic diagram of the structure of the stacked transistor according to an embodiment of the present application.

[0101] Step 1: forming a first sacrificial layer 21 on the original substrate 20, and forming a stacked layer 22 on the first sacrificial layer 21 (see Figure 3A (a) in the figure.

[0102] For example, a Si layer 20 may be provided, and SiGe 1 material may be deposited on the Si layer 20 to form a first sacrificial layer 21; then SiGe 2 material and Si material may be alternately deposited on the first sacrificial layer 21 to form a stacked layer 22 of a preset thickness. It should be noted that the SiGe 1 material and SiGe 2 material here are only exemplary descriptions, and other materials may actually be used.

[0103] Step 2: sequentially etch the stacked layer 22 and the first sacrificial layer 21 until the substrate 20 to form a semiconductor structure 23 and a second sacrificial layer 24 (see Figure 3A (b) in the figure.

[0104] The second sacrificial layer 24 , the first semiconductor structure 231 close to the substrate, and the second semiconductor structure 232 far from the substrate may be formed by etching.

[0105] Step 3: depositing an oxide material on the substrate 20 to form a third isolation structure 25, and performing CMP and etching to the upper surface of the second sacrificial layer 24 (see Figure 3A (c) in the figure.

[0106] Step 4: Form an oxide layer 26 on the substrate 20 (see Figure 3B (a) in the figure.

[0107] It can be understood that the oxide layer 26 is a thin film deposited on the surface of the semiconductor structure 23 and the second sacrificial layer 24 .

[0108] Step 5: Deposit polysilicon or other materials on the oxide layer 26 to form a pseudo gate structure 27 shared by the front and back sides, and form sidewalls (spacers) 28 on both sides of the pseudo gate structure and the semiconductor structure (see Figure 3B (b) in the figure.

[0109] It can be understood that by defining the gate regions of the top transistor and the bottom transistor in the stacked transistor by the dummy gate structure, self-alignment of the upper and lower transistors in the stacked transistor at the gate regions can be achieved.

[0110] Step 6: Etch the stacked layer (semiconductor structure) of the top transistor and the bottom transistor in the source and drain region, and retain part of the spacer as a guide oxide layer (see Figure 3B (c) in the figure.

[0111] Step 7: Laterally etch a portion of the SiGe2 material of the top transistor and the bottom transistor, fill with insulating material and etch to form an inner spacer 29 (see Figure 3C (a) in the figure.

[0112] It can be understood that the inner sidewalls include a first inner sidewall located on both sides of SiGe2 of the bottom transistor and a second inner sidewall located on both sides of SiGe2 of the top transistor.

[0113] Step 8: Form a protective layer 30 to cover the inner sidewall of the top transistor (see Figure 3C (b) in the figure.

[0114] Step 9: Anisotropically etch and remove the second sacrificial layer 24 in the source and drain regions to form a second groove 31 (see Figure 3C (c) in the figure.

[0115] Step 10: Deposit insulating material between the first groove 31 and the retained spacer and etch back to form a placeholder structure 32 for the bottom transistor to contact the back of the source and drain region (see Figure 3D (a) in the figure.

[0116] It can be understood that the placeholder structure 32 will be selectively etched away later and then deposited to form the source and drain contact metal of the bottom transistor, so as to achieve self-aligned contact between the top transistor and the bottom transistor.

[0117] Step 11: epitaxially grow the first semiconductor structure 231 on the placeholder structure 32 to form the first source-drain structure 112 of the bottom transistor (see Figure 3D (b) in the figure.

[0118] Step 12: Remove the protective layer 30 (see Figure 3D (c) in the figure.

[0119] Step 13: Deposit an interlayer dielectric in the source / drain region and etch back to form a first interlayer dielectric layer 113 (see Figure 3E (a) in the figure.

[0120] Step 14: Form a source-drain isolation dielectric layer 33 on the first interlayer dielectric layer 113 (see Figure 3E (b) in the figure.

[0121] Step 15: Epitaxially grow the second semiconductor structure 232 on the source-drain isolation dielectric layer 33 to form the second source-drain structure 122 of the top transistor (see Figure 3E (c) in the figure.

[0122] Step 16: Deposit interlayer dielectric and etch back to form a second interlayer dielectric layer 123 (see Figure 3F (a) in the figure.

[0123] Step 17: Remove the dummy gate structure 27 and a portion of the third isolation structure 25 in the gate region (see Figure 3F (b) in the figure.

[0124] Step 18: Remove the second sacrificial layer 24 in the gate region to form a third groove 34 (see Figure 3F (c) in the figure.

[0125] Step 19: Deposit an insulating dielectric on the third groove 24 and a portion of the third isolation structure 25 to form a BDI layer 35 (see Figure 3G (a) in the figure.

[0126] It can be understood that the sum of the height of the fourth isolation structure 35 in the gate region and the height of a portion of the third isolation structure that is retained is the same as the height of the third isolation structure in the source and drain regions.

[0127] Step 20: Anisotropically etch the BDI layer on both sides of the semiconductor structure 23 to ensure the subsequent deposition of the gate contact metal (see Figure 3G (b) in the figure.

[0128] Step 21: Remove the SiGe2 material in the first semiconductor structure and the second semiconductor structure to form a first nanosheet structure 111 and a second nanosheet structure 121, and form a first gate structure 114 based on the first nanosheet structure 111 and a second gate structure 124 based on the second nanosheet structure 121 (see Figure 3G (c) in the figure.

[0129] It can be understood that an insulating material can be deposited on the surface of the first nanosheet structure 111 to form a first gate dielectric layer 1141, and a metal material can be deposited on the first gate dielectric layer 1141 in the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute a first gate structure 114. An insulating material is deposited on the surface of the second nanosheet structure 121 to form a second gate dielectric layer 1241, and a metal material is deposited on the second gate dielectric layer 1241 in the gate region to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute a second gate structure 124. Therefore, the gate structure of the bottom transistor and the gate structure of the top transistor in the embodiment of the present application are formed at one time.

[0130] Step 22: Form a gate cut-off structure 36 on both sides of the gate structure (see Figure 3H (a) in the figure.

[0131] It can be understood that the gate cut-off structure includes a first gate cut-off structure corresponding to the first gate structure and a second gate cut-off structure corresponding to the second gate structure.

[0132] Step 23: Forming SDB structure 361 (see Figure 3H (b) in the figure.

[0133] Step 24: Form the second source-drain contact metal 125 of the top transistor (see Figure 3H (c) in the figure.

[0134] Step 25: Forming a second metal interconnection layer 126 (see Fig. 3I (a) in the figure.

[0135] It can be understood that the second metal interconnection layer includes both signal lines and power lines.

[0136] Step 26: Deposit insulating material on the second metal interconnect layer 126 to form an insulating layer 13, bond the carrier wafer 14 to the insulating layer 13, flip the second transistor 12, and remove the substrate 20 (see Fig. 3I (b) in the figure.

[0137] Step 27: Selectively remove the bottom BDI layer 35 to form a fourth groove 37 and expose a portion of the placeholder structure 32 (see Fig. 3I (c) in the figure.

[0138] Step 28: A fourth isolation structure 38 is formed on both sides of the exposed placeholder structure on the gate cut-off structure 36 to isolate the sidewalls contacting the gate region (see Figure 3J (a) in the figure.

[0139] Step 29: Deposit an insulating material in the fourth groove 37 to form an insulating structure 39 (see Figure 3J (b) in the figure.

[0140] Step 30: Forming a bottom dielectric layer 40 (see Figure 3J (c) in the figure.

[0141] Step 31: Photolithography forms the pattern of the source and drain contact metal of the bottom transistor to obtain the fifth groove 41 (see Figure 3K (a) in the figure.

[0142] Step 32: Selectively etch the placeholder structure 32 (see Figure 3K (b) in the figure.

[0143] Step 33: Fill the fifth groove 41 and the groove formed after etching the placeholder structure with metal material to form the first source-drain contact metal 115 (see Figure 3K (c) in the figure.

[0144] Step 34: Remove the bottom dielectric layer 40 (see Figure 3L (a) in the figure.

[0145] Step 35: Isotropically deposit an isolation dielectric on the first source-drain contact metal 115 and on both sides to form a first isolation structure 42 (see Figure 3L (b) in the figure.

[0146] Step 36: Anisotropic etching to remove the first isolation structure on the first source-drain contact metal 115 (see Figure 3L (c) in the figure.

[0147] It can be understood that the first isolation structure located on both sides of the first source-drain contact metal acts as a sidewall isolation between the gate metal and the source-drain metal.

[0148] Step 37: Deposit insulating material and perform CMP to form a second isolation structure 43 (see Figure 3M (a) in the figure.

[0149] Step 38: Photolithography forms a gate bottom interconnection groove (first groove 44) (see Figure 3M (b) in the figure.

[0150] It can be understood that a portion of the second isolation structure and the insulating structure 39 may be anisotropically etched to form the first groove.

[0151] Step 39: Deposit metal material in the first groove 44 and perform CMP to form a gate contact metal 45 (see Figure 3M (c) in the figure.

[0152] Step 40: Forming a first metal interconnection layer 116 (see Figure 4 ).

[0153] It can be understood that the first metal interconnection layer includes both signal lines and power lines.

[0154] In the embodiment of the present application, the first gate structure and the second gate structure in the stacked transistor can be formed at one time or separately, and accordingly, the first gate cut-off structure and the second gate cut-off structure can be formed at one time or separately. In the above embodiment, the BDI process is adopted, and the specific process is as steps 17 to 19. The BDI process may not be adopted, and the second sacrificial layer can be selectively removed directly after flipping. Moreover, in the embodiment of the present application, after removing the placeholder structure in step 32, a part of the first source-drain structure may be etched at an angle to increase the contact area, and the second source-drain structure may also be operated accordingly. In addition, in the above embodiment, the metal interconnection layer of the bottom transistor and the metal interconnection layer of the top transistor both have signal lines and power lines. In some embodiments, they may also be compatible with other signal line arrangements, such as the metal interconnection layer of the bottom transistor having both signal lines and power lines, and the metal interconnection layer of the top transistor having only power lines and signal lines for internal winding only, etc. The embodiment of the present application does not limit the arrangement of the signal lines in the metal interconnection layers of the top transistor and the bottom transistor.

[0155] Furthermore, the stacked transistor provided in the embodiment of the present application can be inspected using an inspection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to inspect the structure of the stacked transistor, and the back of the stacked transistor simultaneously forms contact metals at the gate region and the source and drain region of the bottom transistor by self-alignment, and there is no misalignment problem between the source, drain, and gate of the top transistor and the bottom transistor.

[0156] An embodiment of the present application provides a semiconductor device, including: a stacked transistor as described in the above embodiment.

[0157] An embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board, and the semiconductor device includes the above stacked transistor.

[0158] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0159] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: forming a semiconductor structure on a substrate, the semiconductor structure comprising a sacrificial layer, a first semiconductor structure and a second semiconductor structure stacked in sequence; Etching the semiconductor structure in the source and drain regions, and filling the region corresponding to the sacrificial layer in the source and drain regions with insulating material to form a placeholder structure; On the placeholder structure, forming a first part of a first transistor based on the first semiconductor structure through a front-end process, wherein the first part at least includes a first source-drain structure; Based on the second semiconductor structure, forming a second transistor; Flipping the second transistor and exposing the placeholder structure; removing the placeholder structure to form a first source-drain contact metal of the first transistor; A first metal interconnection layer of the first transistor is formed on the first source-drain contact metal through a back-end process.

2. The method according to claim 1, characterized in that The removing the placeholder structure to form a first source-drain contact metal of the first transistor includes: removing the placeholder structure to expose the first source-drain structure; A metal material is deposited on the first source-drain structure to form the first source-drain contact metal.

3. The method according to claim 1, characterized in that The exposing the placeholder structure comprises: Removing the substrate to expose the sacrificial layer in the gate region and the placeholder structure in the source and drain region; The step of forming a first metal interconnection layer of the first transistor on the first source-drain contact metal by a back-end process includes: Removing the sacrificial layer in the gate region to form a first groove; Filling a metal material in the first groove to form a gate contact metal of the first transistor; The first metal interconnection layer is formed on the gate contact metal and the first source-drain contact metal, wherein one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnection layer.

4. The method according to claim 3, characterized in that After forming the first source-drain contact metal, the method further includes: Depositing a dielectric material on the first source-drain contact metal and etching back to form a first isolation structure, wherein one side of the first isolation structure is in contact with the first source-drain contact metal in a first direction, and the first direction is a direction perpendicular to a stacking direction of the first semiconductor structure and the second semiconductor structure; Filling an insulating material on the gate region to form a second isolation structure, wherein the second isolation structure is in contact with the other side of the first isolation structure in the first direction; The step of removing the sacrificial layer in the gate region to form a first groove comprises: A portion of the second isolation structure and the sacrificial layer are anisotropically etched to form the first groove.

5. The method according to claim 4, characterized in that Before etching the first semiconductor structure in the source / drain region, the method further includes: Depositing a semiconductor material in the gate region to form a dummy gate structure surrounding the first semiconductor structure and the second semiconductor structure; The step of forming a first part of a first transistor based on the first semiconductor structure includes: epitaxially growing a first source-drain structure on the first semiconductor structure; forming a first interlayer dielectric layer on the first source-drain structure; The forming of a second transistor based on the second semiconductor structure comprises: epitaxially growing a second source-drain structure on the second semiconductor structure; forming a second interlayer dielectric layer on the second source-drain structure; Removing the dummy gate structure to expose the semiconductor structure in the gate region; Based on the semiconductor structure in the gate region, forming a gate structure, the gate structure comprising a first gate structure corresponding to the first semiconductor structure and a second gate structure corresponding to the second semiconductor structure; Etching the second interlayer dielectric layer to expose the second source-drain structure; Depositing a metal material on the second source-drain structure to form a second source-drain contact metal of the second transistor; A second metal interconnection layer of the second transistor is formed on the second source-drain contact metal through a back-end process.

6. The method according to claim 5, characterized in that After forming a gate structure based on the semiconductor structure in the gate region, the method further includes: A gate cut-off structure is formed on both sides of the gate structure, and the gate cut-off structure is used to isolate the gate region of the stacked transistor from the gate region of the adjacent stacked transistor.

7. A stacked transistor, prepared using the preparation method according to any one of claims 1 to 6, characterized in that: include: a first transistor; a second transistor, wherein the first transistor and the second transistor are stacked; The first source-drain contact metal of the first transistor is self-aligned with the second source-drain contact metal of the second transistor.

8. The stacked transistor according to claim 7, characterized in that: The first transistor includes a gate contact metal, one side of the gate contact metal is connected to the first gate structure of the first transistor, and the other side of the gate contact metal is connected to the first metal interconnection layer of the first transistor.

9. A semiconductor device, characterized in that: include: A stacked transistor as claimed in claim 7 or 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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