Display panel and method for manufacturing display panel

Abstract

The present application discloses a display panel and a method for manufacturing the display panel, comprising a display area and a non-display area peripheral to the display area. The display panel comprises a substrate and a first thin-film transistor disposed on the substrate, the first thin-film transistor being located in the non-display area and comprising a first gate, a first gate insulating layer, a first active layer, and a second active layer. The first gate is disposed on the substrate; the first gate insulating layer is disposed on the substrate and covers the first gate; the first active layer is disposed on a surface of the first gate insulating layer away from the substrate, the first active layer comprising a crystalline oxide; the second active layer is disposed on a surface of the first active layer away from the substrate, the second active layer comprising an amorphous oxide; wherein the mobility of the first active layer is greater than the mobility of the second active layer. This advantageously improves the driving capability of the thin-film transistors in the non-display area of ​​the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the display panel. Background Art

[0002] The thin film transistors in the non-display area of ​​the display panel are used for driving circuits, signal processing, scanning, and signal transmission. The active layer of the thin film transistors in the non-display area of ​​the display panel has relatively high requirements for mobility, but the active layer of the thin film transistors in the non-display area of ​​the display panel of the conventional solution has low mobility, resulting in insufficient driving capability of the thin film transistors in the non-display area of ​​the display panel. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a method for manufacturing the display panel to enhance the driving capability of thin film transistors in a non-display area of ​​the display panel.

[0004] In a first aspect, embodiments of the present application provide a display panel including a display area and a non-display area peripheral to the display area, the display panel including a substrate and a first thin film transistor disposed on the substrate, the first thin film transistor being located in the non-display area, the first thin film transistor including:

[0005] a first gate disposed on the substrate;

[0006] a first gate insulating layer, wherein the first gate insulating layer is disposed on the substrate and covers the first gate;

[0007] a first active layer, the first active layer being disposed on a surface of the first gate insulating layer away from the substrate, the first active layer comprising a crystalline oxide, wherein the first active layer is obtained by first annealing a first semiconductor thin film formed on the first gate insulating layer;

[0008] a second active layer, the second active layer comprising an amorphous oxide, wherein the second active layer is obtained by performing a second annealing on a second semiconductor thin film formed on the first active layer after the first annealing;

[0009] The mobility of the first active layer is higher than the mobility of the second active layer.

[0010] Furthermore, the first thin film transistor further includes a first source and a first drain. The first source is disposed on a surface of the second active layer away from the substrate, and the first drain is disposed on a surface of the second active layer away from the substrate.

[0011] Furthermore, in a top view of the display panel, the second active layer overlaps with the first active layer.

[0012] Furthermore, the display panel further includes a second thin film transistor, which is located in the display area and includes:

[0013] a second gate, the second gate being disposed on the substrate and being in the same layer as the first gate;

[0014] a second gate insulating layer, the second gate insulating layer being disposed on the substrate, covering the second gate, and being in the same layer as the first gate insulating layer;

[0015] a third active layer, the third active layer being disposed on a surface of the second gate insulating layer away from the substrate, the third active layer comprising amorphous oxide, and being disposed in the same layer as the second active layer;

[0016] The mobility of the third active layer is smaller than the mobility of the first active layer.

[0017] Furthermore, in the length direction of the channel, the length of the first active layer is greater than the length of the third active layer, and / or the length of the second active layer is greater than the length of the third active layer.

[0018] Furthermore, in the thickness direction of the display panel, the thickness of the third active layer is equal to that of the second active layer.

[0019] In a second aspect, an embodiment of the present application provides a method for manufacturing a display panel, wherein the display panel includes a display area and a non-display area peripheral to the display area, the display panel includes a substrate and a first thin film transistor disposed on the substrate, the first thin film transistor being located in the non-display area, the manufacturing method comprising the following steps:

[0020] forming a first gate on the substrate;

[0021] forming a first gate insulating layer on the substrate, wherein the first gate insulating layer covers the first gate;

[0022] forming a first semiconductor thin film on the first gate insulating layer, and performing a first annealing on the first semiconductor thin film to form a first active layer after the annealing, wherein the first active layer includes a crystalline oxide;

[0023] forming a second semiconductor thin film on the first active layer, and annealing the second semiconductor thin film to form a second active layer after the annealing, wherein the second active layer includes amorphous oxide;

[0024] The mobility of the first active layer is greater than the mobility of the second active layer.

[0025] Furthermore, the preparation method further comprises:

[0026] A conductive material film is deposited on the second active layer, and a patterning process is performed on the conductive material film to form a first source electrode and a first drain electrode.

[0027] Furthermore, the display panel further includes a second thin film transistor, and the second thin film transistor is located in the display area. The preparation method further includes the following steps:

[0028] forming a second gate on the substrate, the second gate being in the same layer as the first gate;

[0029] forming a second gate insulating layer on the substrate, so that the second gate insulating layer covers the second gate, and the second gate insulating layer is in the same layer as the first gate insulating layer;

[0030] forming a third semiconductor thin film on the second gate insulating layer, and annealing the third semiconductor thin film to form a third active layer after the annealing, wherein the third active layer includes amorphous oxide and is disposed in the same layer as the second active layer;

[0031] The mobility of the third active layer is smaller than the mobility of the first active layer.

[0032] Furthermore, after depositing the second semiconductor film on the first active layer and the third semiconductor film on the second gate insulating layer, the second semiconductor film and the third semiconductor film are annealed at the same time, so that the second semiconductor film forms a second active layer after annealing, and the third semiconductor film forms a third active layer after annealing.

[0033] Beneficial effects of this application:

[0034] The present application provides a display panel, which includes a first thin-film transistor including a first gate, a first active layer, and a second active layer. The first gate is provided on the substrate, and the first active layer is provided on a surface of the first gate insulating layer away from the substrate. The first active layer is obtained by performing a first annealing on a first semiconductor thin film formed on the first gate insulating layer, and the second active layer is obtained by performing a second annealing on a second semiconductor thin film formed on the first active layer after the first annealing. The mobility of the first active layer is greater than the mobility of the second active layer, which can improve the mobility of the active layer of the thin-film transistor in the non-display area of ​​the display panel, thereby improving the driving capability of the first thin-film transistor in the non-display area of ​​the display panel.

[0035] The present application provides a method for preparing a display panel, by forming a first semiconductor thin film on a first gate insulating layer, annealing the first semiconductor thin film once to form a first active layer after annealing the first semiconductor thin film, wherein the first active layer includes a crystalline oxide, forming a second semiconductor thin film on the first active layer, and annealing the second semiconductor thin film a second time to form a second active layer after annealing the second semiconductor thin film, wherein the second active layer includes an amorphous oxide, and setting the mobility of the first active layer to be greater than the mobility of the second active layer, which can improve the mobility of the active layer of the thin film transistor in the non-display area of ​​the display panel, thereby improving the driving capability of the first thin film transistor in the non-display area of ​​the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a display panel of the present application;

[0037] Figure 2 yes Figure 1 A cross-sectional view of the display panel taken along line CC′ is shown;

[0038] Figures 3a-3c is a flow chart of a method for preparing a display panel of the present application;

[0039] Figure 4 This is a schematic diagram of abnormal contact between the first active layer and the second active layer of the present application.

[0040] 10-display panel; 100-substrate; 200-first thin film transistor, 210-first gate electrode, 220-first gate insulating layer, 230-first active layer, 240-second active layer, 250-first source electrode, first drain electrode; 300-second thin film transistor, 310-second gate electrode, 320-second gate insulating layer, 330-third active layer, 340-second source electrode, second drain electrode. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0042] In addition, the terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0043] The first embodiment of the present application provides a display panel 10, referring to Figure 1 and Figure 2 The display panel 10 includes a display area AA and a non-display area BB outside the display area AA.

[0044] Specifically, the display panel 10 includes a substrate 100 and a first thin film transistor 200 provided on the substrate 100, the first thin film transistor 200 is located in the non-display area BB, and the first thin film transistor 200 includes a first gate 210, a first gate insulating layer 220, a first active layer 230, and a second active layer 240; the first gate 210 is provided on the substrate 100; the first gate insulating layer 220 is provided on the substrate 100, and the first gate insulating layer 220 covers the first gate 210; the first active layer 230 is provided on the first gate insulating layer 220 The first active layer 230 includes a crystalline oxide on a surface away from the substrate 100, wherein the first active layer is obtained by performing a first annealing on a first semiconductor thin film formed on the first gate insulating layer; the second active layer 240 is provided on a surface of the first active layer 230 away from the substrate 100, and the second active layer 240 includes a non-crystalline oxide, wherein the second active layer is obtained by performing a second annealing on a second semiconductor thin film formed on the first active layer after the first annealing; the mobility of the first active layer 230 is greater than the mobility of the second active layer 240.

[0045] The first thin film transistor 200 includes a first gate 210, a first active layer 230 and a second active layer 240. The first gate 210 is provided on the substrate 100. The first active layer 230 is provided on a surface of the first gate insulating layer 220 away from the substrate 100. The first active layer is obtained by performing a first annealing on a first semiconductor thin film formed on the first gate insulating layer. The second active layer is obtained by performing a second annealing on a second semiconductor thin film formed on the first active layer after the first annealing. The mobility of the first active layer 230 is greater than the mobility of the second active layer 240. The mobility of the active layer of the first thin film transistor 200 in the non-display area BB of the display panel 10 can be improved, thereby improving the driving capability of the first thin film transistor 200 in the non-display area BB of the display panel 10. Moreover, since the GOA area is usually located at the periphery of the display , it needs to occupy a certain width, so setting the mobility of the first active layer 230 to be greater than the mobility of the second active layer can reduce the length of the first active layer 230 in the length direction L of the channel, thereby reducing the width of the frame of the display panel 10, which is conducive to achieving a narrow frame; at the same time, since the first thin film transistor 200 is a bottom-gate structure, compared with the solution of setting the first thin film transistor 200 to a top-gate structure, it can avoid the current leakage of the first thin film transistor 200, thereby improving the working stability of the first thin film transistor 200; at the same time, since the first active layer 230 is annealed for the first time to obtain a crystalline oxide, a second semiconductor thin film is formed on the first active layer 230, and the second semiconductor thin film is annealed to form a second active layer 240 after the second semiconductor thin film is annealed, and the first active layer 230 and the second active layer 240 are obtained by annealing twice, reference Figure 4 Compared with the one-time annealing solution, it can avoid the formation of the second active layer 240 of amorphous oxide on the first active layer 230 that has also crystallized, resulting in poor contact between the first active layer 230 and the second active layer 240. On the one hand, it can reduce the stress on the contact surface between the first active layer 230 and the second active layer 240. On the other hand, it can reduce the contact resistance between the first active layer 230 and the second active layer 240, thereby reducing the impact on the carrier transmission efficiency of the first thin film transistor 200, and further reducing the risk of electrical abnormality of the first thin film transistor 200.

[0046] In this embodiment, the non-display area BB includes a GOA region, and the first thin film transistor 200 is located in the GOA region.

[0047] In this embodiment, the mobility of the first active layer 230 is 30 cm 2 / V·s~50cm 2 / V·s. The preferred mobility of the first active layer 230 is 30cm2 / V·s、32cm 2 / V·s、34cm 2 / V·s、36cm 2 / V·s、38cm 2 / V·s、40cm 2 / V·s、42cm 2 / V·s、44cm 2 / V·s、46cm 2 / V·s、48cm 2 / V·s or 50cm 2 / V·s.

[0048] In this embodiment, the mobility of the second active layer 240 is not greater than 10 cm 2 / V·s. Preferably, the mobility of the second active layer 240 is 8cm 2 / V·s、8.2cm 2 / V·s、8.4cm 2 / V·s、8.6cm 2 / V·s、8.8cm 2 / V·s、9.0cm 2 / V·s、9.2cm 2 / V·s、9.4cm 2 / V·s、9.6cm 2 / V·s、9.8cm 2 / V·s or 10cm 2 / V·s.

[0049] In this embodiment, the temperature of the first annealing is higher than the temperature of the second annealing.

[0050] In this embodiment, the temperature of the first annealing is 450°C to 550°C.

[0051] In this embodiment, the temperature of the second annealing is 200°C to 300°C.

[0052] In this embodiment, reference Figure 2The first thin film transistor 200 further includes a first source electrode 250 and a first drain electrode 250, which are disposed on a surface of the second active layer 240 away from the substrate 100. By configuring the first thin film transistor 200 to further include the first source electrode 250 and the first drain electrode 250, and by configuring the first source electrode 250 and the first drain electrode 250 to be disposed on a surface of the second active layer 240 away from the substrate 100, the first source electrode 250 and the first drain electrode 250 are directly electrically connected to the second active layer 240, without requiring the first source electrode 250 and the first drain electrode 250 to be in direct contact with the first active layer 230. This can avoid an increase in contact resistance between the first source electrode 250 and the first drain electrode 250 and the first active layer 230 due to direct contact with the first source electrode 250 and the first drain electrode 250, thereby preventing electrical abnormalities in the first thin film transistor 200.

[0053] In this embodiment, reference Figure 2 In a top view of the display panel 10, the second active layer 240 overlaps with the first active layer 230. By arranging the second active layer 240 to overlap with the first active layer 230 in a top view of the display panel 10, the second active layer 240 can shield the first active layer 230, thereby preventing damage to the surface of the first active layer 230 on the side close to the second active layer 240.

[0054] In this embodiment, reference Figure 2The display panel 10 also includes a second thin film transistor 300, which is located in the display area AA. The second thin film transistor 300 includes a second gate electrode 310, a second gate insulating layer 320 and a third active layer 330; the second gate electrode 310 is provided on the substrate 100, and the second gate electrode 310 is in the same layer as the first gate electrode 210; the second gate insulating layer 320 is provided on the substrate 100, and the second gate insulating layer 320 covers the second gate electrode 310, and the second gate insulating layer 320 is in the same layer as the first gate insulating layer 220; the third active layer 330 is provided on a surface of the second gate insulating layer 320 away from the substrate 100, the third active layer 330 includes amorphous oxide, and the third active layer 330 is provided in the same layer as the second active layer 240; wherein, the mobility of the third active layer 330 is less than the mobility of the first active layer. Since the thin film transistors in the non-display area BB of the display panel 10 are used for driving circuits, signal processing, scanning, and signal transmission, the mobility requirement of the active layer of the thin film transistors in the non-display area BB of the display panel 10 is relatively high, and the thin film transistors in the display area AA of the display panel 10 are used to control the switching of pixels. Therefore, the mobility requirement of the active layer of the thin film transistors in the non-display area BB of the display panel 10 is relatively low. When the mobility of the active layer of the thin film transistors in the non-display area BB of the display panel 10 is low, it is easy to cause insufficient driving capability of the thin film transistors in the non-display area BB of the display panel 10. When the mobility of the active layer of the thin film transistors in the display area AA of the display panel 10 is high, it is easy to cause the stability of the thin film transistors in the display area AA of the display panel 10 to be reduced. Therefore, by arranging the third active layer 330 on a surface of the second gate insulating layer 320 away from the substrate 100, the mobility of the third active layer 330 is less than the mobility of the first active layer, which can avoid the mobility of the active layer of the first thin film transistor 200 in the non-display area BB of the display panel 10 being too high, thereby ensuring the driving capability of the first thin film transistor 200 in the non-display area BB of the display panel 10 and the stability of the second thin film transistor 300 in the display area AA of the display panel 10 at the same time; and because the third active layer 330 and the second active layer 240 are arranged in the same layer, the mobility of the second active layer 240 is less than the mobility of the first active layer, and the mobility of the third active layer 330 is less than the mobility of the first active layer. When preparing the display panel 10, the second active layer 240 and the third active layer 330 can be prepared at the same time, thereby improving the preparation efficiency of the display panel 10.

[0055] In this embodiment, the mobility of the third active layer 330 is not greater than 10 cm 2 / V·s. Preferably, the mobility of the second active layer 240 is 8cm 2 / V·s、8.2cm 2 / V·s、8.4cm 2 / V·s、8.6cm 2 / V·s、8.8cm 2 / V·s、9.0cm 2 / V·s、9.2cm 2 / V·s、9.4cm 2 / V·s、9.6cm 2 / V·s、9.8cm 2 / V·s or 10cm 2 / V·s.

[0056] In this embodiment, reference Figure 2 The second thin film transistor 300 further includes a second source electrode 340 and a second drain electrode 340. The second source electrode 340 and the second drain electrode 340 are disposed on a surface of the second active layer 240 away from the substrate 100. The second source electrode 340 and the second drain electrode 340 are disposed in the same layer as the first source electrode 250 and the first drain electrode 250. By disposing the second source electrode 340 and the second drain electrode 340 in the same layer as the first source electrode 250 and the first drain electrode 250, the second source electrode 340 and the second drain electrode 340 can be manufactured simultaneously with the first source electrode 250 and the first drain electrode 250, thereby improving the manufacturing efficiency of the display panel 10.

[0057] In this embodiment, reference Figure 2 In the longitudinal direction L of the channel, the length d1 of the first active layer 230 is greater than the length d2 of the third active layer 330, and / or the length of the second active layer 240 is greater than the length d2 of the third active layer 330. By arranging in the longitudinal direction L of the channel that the length d1 of the first active layer 230 is greater than the length d2 of the third active layer 330, and / or the length of the second active layer 240 is greater than the length d2 of the third active layer 330, the length of the third active layer 330 in the longitudinal direction L of the channel can be reduced, thereby improving the response speed of the first thin film transistor 200.

[0058] In this embodiment, in the thickness direction M of the display panel 10 , the thickness of the third active layer 330 is equal to that of the second active layer 240 .

[0059] In this embodiment, the material of the third active layer 330 is the same as that of the second active layer 240 .

[0060] In this embodiment, the material of the first active layer 230 includes at least one of indium zinc oxide (Indium Zinc Oxide), indium zinc tin oxide (Indium Tin Zinc Oxide), and indium gallium zinc tin oxide (Indium Gallium Zinc Tin Oxide); the material of the second active layer 240 includes at least one of indium gallium zinc oxide (Indium Gallium Zinc Oxide) and indium gallium oxide (Indium Gallium Oxide); and the material of the third active layer 330 includes at least one of indium gallium zinc oxide and indium gallium oxide.

[0061] The second embodiment of the present application provides a method for manufacturing a display panel 10, referring to Figures 3a-3c The display panel 10 includes a display area AA and a non-display area BB outside the display area AA. The display panel 10 includes a substrate 100 and a first thin film transistor 200 provided on the substrate 100. The first thin film transistor 200 is located in the non-display area BB. The manufacturing method comprises the following steps:

[0062] SA1: forming a first gate 210 on the substrate 100;

[0063] SB1: forming a first gate insulating layer 220 on the substrate 100 , wherein the first gate insulating layer 220 covers the first gate 210 ;

[0064] SC1: forming a first semiconductor thin film on the first gate insulating layer 220, and annealing the first semiconductor thin film to form a first active layer 230 after one annealing of the first semiconductor thin film, wherein the first active layer 230 includes a crystalline oxide;

[0065] SD1: forming a second semiconductor thin film on the first active layer 230, and performing a secondary annealing on the second semiconductor thin film to form a second active layer 240 after the annealing, wherein the second active layer 240 includes an amorphous oxide;

[0066] The mobility of the first active layer 230 is greater than the mobility of the second active layer 240 .

[0067] The method comprises forming a first semiconductor film on the first gate insulating layer 220, annealing the first semiconductor film once, so that the first active layer 230 is formed after the annealing, wherein the first active layer 230 includes a crystalline oxide, forming a second semiconductor film on the first active layer 230, annealing the second semiconductor film, so that the second active layer 240 is formed after the annealing, wherein the second active layer 240 includes an amorphous oxide, and setting the mobility of the first active layer 230 to be greater than the mobility of the second active layer 240. The mobility of the active layer of the first thin film transistor 200 in the non-display area BB of the display panel 10 can be improved, thereby improving the driving capability of the first thin film transistor 200 in the non-display area BB of the display panel 10; and since the first active layer 230 is annealed to obtain a crystalline oxide after the first annealing, a second semiconductor thin film is formed on the first active layer 230, and the second semiconductor thin film is annealed to form a second active layer 240 after the second semiconductor thin film is annealed, the first active layer 230 and the second active layer 240 are obtained by annealing twice, referring to Figure 4 Compared with the one-time annealing solution, it can avoid the formation of the second active layer 240 of amorphous oxide on the first active layer 230 that has also crystallized, resulting in poor contact between the first active layer 230 and the second active layer 240. On the one hand, it can reduce the stress on the contact surface between the first active layer 230 and the second active layer 240. On the other hand, it can reduce the contact resistance between the first active layer 230 and the second active layer 240, thereby reducing the impact on the carrier transmission efficiency of the first thin film transistor 200, and further reducing the risk of electrical abnormality of the first thin film transistor 200.

[0068] In this embodiment, the temperature at which the first semiconductor film is subjected to the primary annealing to form the first active layer 230 is higher than the temperature at which the second semiconductor film is subjected to the secondary annealing to form the second active layer 240 .

[0069] In this embodiment, the temperature of the first semiconductor film annealing to form the first active layer 230 is 450° C. to 550° C.

[0070] In this embodiment, the temperature of the second semiconductor film secondary annealing to form the second active layer 240 is 200° C. to 300° C.

[0071] In this embodiment, the preparation method further includes:

[0072] SE1: depositing a conductive material thin film on the second active layer 240 , and performing a patterning process on the conductive material thin film to form a first source electrode 250 and a first drain electrode 250 .

[0073] In this embodiment, the display panel 10 further includes a second thin film transistor 300, and the second thin film transistor 300 is located in the display area AA. The manufacturing method further includes the following steps:

[0074] SA2: forming a second gate 310 on the substrate 100 , the second gate 310 being in the same layer as the first gate 210 ;

[0075] SB2: forming a second gate insulating layer 320 on the substrate 100 , and making the second gate insulating layer 320 cover the second gate 310 , and the second gate insulating layer 320 is in the same layer as the first gate insulating layer 220 ;

[0076] SC2: forming a third semiconductor thin film on the second gate insulating layer 320, and annealing the third semiconductor thin film to form a third active layer 330 after annealing. The third active layer 330 includes an amorphous oxide and is disposed in the same layer as the second active layer 240.

[0077] The mobility of the third active layer 330 is smaller than the mobility of the first active layer.

[0078] By forming a third semiconductor thin film on the second gate insulating layer 320, annealing the third semiconductor thin film to form a third active layer 330 after annealing, and setting the mobility of the third active layer 330 to be low, it is possible to avoid the mobility of the active layer of the first thin film transistor 200 in the non-display area BB of the display panel 10 being too high, thereby ensuring the driving capability of the first thin film transistor 200 in the non-display area BB of the display panel 10 and the stability of the second thin film transistor 300 in the display area AA of the display panel 10 at the same time; and because the third active layer 330 and the second active layer 240 are arranged in the same layer, the mobility of the second active layer 240 is lower than that of the first active layer, and the mobility of the third active layer 330 is lower than that of the first active layer. When preparing the display panel 10, the second active layer 240 and the third active layer 330 can be prepared simultaneously, thereby improving the preparation efficiency of the display panel 10.

[0079] In this embodiment, the preparation method further includes:

[0080] SD2: A conductive material film is deposited on the third active layer 330 and patterned to form a second source electrode 340 and a second drain electrode 340 ; the second source electrode 340 and the second drain electrode 340 are disposed in the same layer as the first source electrode 250 and the first drain electrode 250 . Disposing the second source electrode 340 and the second drain 340 in the same layer as the first source electrode 250 and the first drain electrode 250 allows the second source electrode 340 and the second drain 340 to be fabricated simultaneously with the first source electrode 250 and the first drain electrode 250 , thereby improving the fabrication efficiency of the display panel 10 .

[0081] In this embodiment, after depositing the second semiconductor film on the first active layer 230 and the third semiconductor film on the second gate insulating layer 320, the second semiconductor film and the third semiconductor film are simultaneously annealed, so that the second semiconductor film forms the second active layer 240 after annealing, and the third semiconductor film forms the third active layer 330 after annealing. By annealing the second semiconductor film and the second semiconductor film after depositing the second semiconductor film on the first active layer 230 and the third semiconductor film on the second gate insulating layer 320, so that the second semiconductor film forms the second active layer 240 after annealing, and the third semiconductor film forms the third active layer 330 after annealing, the second active layer 240 and the third active layer 330 can be prepared simultaneously, eliminating the need for separate annealing when forming the third active layer 330, thereby reducing the complexity of manufacturing the display panel 10.

[0082] In this embodiment, in a top view of the display panel 10, the second active layer 240 overlaps with the first active layer 230. By arranging the second active layer 240 to overlap with the first active layer 230 in a top view of the display panel 10, the second active layer 240 can shield the first active layer 230, thereby preventing damage to the surface of the first active layer 230 on the side closest to the second active layer 240.

[0083] In this embodiment, in the channel length direction L, the length d1 of the first active layer 230 is greater than the length d2 of the third active layer 330, and / or the length of the second active layer 240 is greater than the length d2 of the third active layer 330. By arranging in the channel length direction L that the length d1 of the first active layer 230 is greater than the length d2 of the third active layer 330, and / or the length of the second active layer 240 is greater than the length d2 of the third active layer 330, the length of the third active layer 330 in the channel length direction L can be reduced, thereby improving the response speed of the first thin film transistor 200.

[0084] In this embodiment, in the thickness direction M of the display panel 10 , the thickness of the third active layer 330 is equal to that of the second active layer 240 .

[0085] In this embodiment, the material of the third active layer 330 is the same as that of the second active layer 240 .

[0086] In this embodiment, the material of the first active layer 230 includes at least one of indium zinc oxide (Indium Zinc Oxide), indium zinc tin oxide (Indium Tin Zinc Oxide), and indium gallium zinc tin oxide (Indium Gallium Zinc Tin Oxide); the material of the second active layer 240 includes at least one of indium gallium zinc oxide (Indium Gallium Zinc Oxide) and indium gallium oxide (Indium Gallium Oxide); and the material of the third active layer 330 includes at least one of indium gallium zinc oxide and indium gallium oxide.

[0087] The above describes in detail the specific embodiments of the present application. The above embodiments disclosed in this application are merely preferred embodiments of the present application. Those skilled in the art will appreciate that many variations and improvements can be made without departing from the spirit of the present application. These variations and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area outside the display area. The display panel includes a substrate and a first thin film transistor provided on the substrate. The first thin film transistor is located in the non-display area. The first thin film transistor includes: a first gate disposed on the substrate; a first gate insulating layer, wherein the first gate insulating layer is disposed on the substrate and covers the first gate; a first active layer, the first active layer being disposed on a surface of the first gate insulating layer away from the substrate, the first active layer comprising a crystalline oxide, wherein the first active layer is obtained by first annealing a first semiconductor thin film formed on the first gate insulating layer; a second active layer, the second active layer comprising an amorphous oxide, wherein the second active layer is obtained by performing a second annealing on a second semiconductor thin film formed on the first active layer after the first annealing; The mobility of the first active layer is greater than the mobility of the second active layer.

2. The display panel according to claim 1, wherein: The first thin film transistor further includes a first source and a first drain. The first source is disposed on a surface of the second active layer away from the substrate, and the first drain is disposed on a surface of the second active layer away from the substrate.

3. The display panel according to claim 1, wherein: In a top view of the display panel, the second active layer overlaps with the first active layer.

4. The display panel according to claim 1, wherein: The display panel further includes a second thin film transistor, which is located in the display area and includes: a second gate, the second gate being disposed on the substrate and being in the same layer as the first gate; a second gate insulating layer, the second gate insulating layer being disposed on the substrate, covering the second gate, and being in the same layer as the first gate insulating layer; a third active layer, the third active layer being disposed on a surface of the second gate insulating layer away from the substrate, the third active layer comprising amorphous oxide, and being disposed in the same layer as the second active layer; The mobility of the third active layer is smaller than the mobility of the first active layer.

5. The display panel according to claim 4, wherein: In the length direction of the channel, the length of the first active layer is greater than that of the third active layer, and / or the length of the second active layer is greater than that of the third active layer.

6. The display panel according to claim 4, wherein: In a thickness direction of the display panel, the third active layer and the second active layer have the same thickness.

7. A method for preparing a display panel, characterized in that: The display panel includes a display area and a non-display area outside the display area. The display panel includes a substrate and a first thin film transistor provided on the substrate. The first thin film transistor is located in the non-display area. The preparation method comprises the following steps: forming a first gate on the substrate; forming a first gate insulating layer on the substrate, wherein the first gate insulating layer covers the first gate; forming a first semiconductor thin film on the first gate insulating layer, and performing a first annealing on the first semiconductor thin film to form a first active layer after the annealing, wherein the first active layer includes a crystalline oxide; forming a second semiconductor thin film on the first active layer, and performing a secondary annealing on the second semiconductor thin film to form a second active layer after the annealing, wherein the second active layer includes amorphous oxide; The mobility of the first active layer is greater than the mobility of the second active layer.

8. The method for manufacturing a display panel according to claim 7, wherein: The preparation method further comprises: A conductive material film is deposited on the second active layer, and a patterning process is performed on the conductive material film to form a first source electrode and a first drain electrode.

9. The method for manufacturing a display panel according to claim 7 or 8, wherein: The display panel further includes a second thin film transistor, which is located in the display area. The manufacturing method further includes the following steps: forming a second gate on the substrate, the second gate being in the same layer as the first gate; forming a second gate insulating layer on the substrate, so that the second gate insulating layer covers the second gate, and the second gate insulating layer is in the same layer as the first gate insulating layer; forming a third semiconductor thin film on the second gate insulating layer, and annealing the third semiconductor thin film to form a third active layer after the annealing, wherein the third active layer includes an amorphous oxide, wherein the third active layer is provided in the same layer as the second active layer; The mobility of the third active layer is smaller than the mobility of the first active layer.

10. The method for manufacturing a display panel according to claim 9, wherein: After depositing the second semiconductor film on the first active layer and the third semiconductor film on the second gate insulating layer, the second semiconductor film and the third semiconductor film are annealed at the same time, so that the second semiconductor film forms a second active layer after annealing, and the third semiconductor film forms a third active layer after annealing.

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