Semiconductor device design method and system
By dynamically adjusting the gap distance value between device unit patterns in semiconductor devices and filtering out the target gap distance value that meets the preset conditions based on electrical performance data, the bridging problem caused by device gap reduction is solved, and the accurate determination of device gap and performance guarantee is achieved.
Patent Information
- Application Number
- CN202510033218.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-08
- Publication Date
- 2025-04-11
AI Technical Summary
As the semiconductor device process node size decreases, the device gap decreases, resulting in possible bridging problems between devices, affecting the normal operation of the device.
By setting different gap distance values in the semiconductor device pattern, multiple semiconductor devices are made, and their electrical performance is tested, target electrical performance data that meets preset performance conditions are selected, and the corresponding target gap distance values are determined.
The precise determination of the gap distance between device units in semiconductor devices is achieved, avoiding bridging problems and ensuring the normal operation and performance of the device.
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Figure CN119815927A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device design method and system thereof. Background Art
[0002] As the size of process nodes decreases, the area of semiconductor devices decreases, and accordingly, the gaps between related devices also gradually decrease. This will cause the following problem: the gap originally plays an insulating isolation role, but as the gap gradually decreases, bridge problems will occur between these devices, which may cause device failure.
[0003] Therefore, how to determine the gap distance between devices is a topic that the industry needs to consider.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a semiconductor device design method and system thereof, which overcomes the difficulties of the prior art and can accurately design the gap distance value between related device units in the semiconductor device.
[0006] A first aspect of the present disclosure provides a semiconductor device design method, wherein the semiconductor device comprises at least one pair of device units that are adjacent to each other and separated by a gap; the semiconductor device design method comprises:
[0007] Setting different gap distance values for the gaps in the pattern of the semiconductor device to obtain a plurality of patterns of the semiconductor device;
[0008] Using a plurality of patterns of the semiconductor device, respectively manufacturing a plurality of the semiconductor devices;
[0009] Testing the electrical performance of the plurality of semiconductor devices respectively to obtain a plurality of corresponding sets of electrical performance data, and screening out target electrical performance data that meets preset performance conditions from the plurality of sets of electrical performance data, and using the gap distance value corresponding to the target electrical performance data as the target gap distance value;
[0010] The electrical performance data includes a bridge current between adjacent device units separated by the gap, and / or a leakage current of the device units.
[0011] In some embodiments, the preset performance condition includes that the leakage current corresponding to the target electrical performance data is at the picoampere level.
[0012] In some embodiments, the preset performance condition further includes: starting from the leakage current corresponding to the target electrical performance data, each leakage current thereafter shows a decreasing trend and the fluctuation value does not exceed a fluctuation value threshold.
[0013] In some implementations, the step of testing electrical performance of the plurality of semiconductor devices separately includes:
[0014] When the device unit is controlled to be cut off, a leakage current between an input terminal and an output terminal in the device unit is measured.
[0015] In some embodiments, the preset performance condition includes that the bridge current corresponding to the target electrical performance data is lower than an expected value.
[0016] In some embodiments, the device unit includes a MOS transistor, wherein the gap is formed between gates of a pair of MOS transistors adjacent to each other along a gate line direction;
[0017] The gaps in the pattern of the semiconductor device are set to different gap distance values to obtain a plurality of patterns of the semiconductor device, comprising:
[0018] The gap between active regions in a semiconductor substrate where a pair of MOS transistors adjacent along the gate line are located is kept unchanged, and different length values of the gate ends of the MOS transistors extending beyond the active regions along the gate line are set, and the length values correspond to the gap distance values.
[0019] In some embodiments, the semiconductor device is a static random access memory, a dynamic random access memory, or a flash memory.
[0020] In some embodiments, the semiconductor device is the static random access memory, which includes a plurality of static random access memory cells arranged along the gate line direction, each of the static random access memory cells includes a MOS transistor with a common gate, wherein the gap is formed between the common gates of the MOS transistors of two adjacent static random access memory cells along the gate line direction.
[0021] A second aspect of the present disclosure provides a semiconductor device design system, wherein the semiconductor device includes at least one pair of device units that are adjacent to each other and separated by a gap; the semiconductor device design system includes:
[0022] A setting module, which sets different gap distance values for the gap in the pattern of the semiconductor device to obtain a plurality of patterns of the semiconductor device;
[0023] A manufacturing module, using a plurality of patterns of the semiconductor device to manufacture a plurality of the semiconductor devices respectively;
[0024] A testing module, for testing electrical performance of the plurality of semiconductor devices respectively, obtaining corresponding multiple groups of electrical performance data, and screening out target electrical performance data satisfying preset performance conditions from the multiple groups of electrical performance data, and using the gap distance value corresponding to the target electrical performance data as the target gap distance value;
[0025] The electrical performance data includes a bridge current between adjacent device units separated by the gap, and / or a leakage current of the device units.
[0026] In some embodiments, the preset performance condition includes that the leakage current corresponding to the target electrical performance data is at the picoampere level.
[0027] Using the semiconductor device design method of this embodiment, the different gap distance values between device unit patterns are dynamically adjusted based on the electrical performance data such as leakage current and / or bridge current, and finally the target electrical performance data that meets the preset performance conditions are screened out. The target electrical performance data is considered to be optimal, so the gap distance value corresponding to it can be used as the target gap distance value, and the target gap distance value is used as the final gap distance value between the corresponding device units in the future semiconductor device.
[0028] Therefore, compared with the related art which cannot provide an effective gap determination solution, the semiconductor device design method of the present embodiment can accurately determine the gap distance value between corresponding device units in the semiconductor device.
[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0031] Figure 1 It is a flow chart of a semiconductor device design method provided by an embodiment of the present disclosure.
[0032] Figure 2 and Figure 3 yes Figure 1 A schematic diagram of a pattern of a semiconductor device in a semiconductor device design method is shown.
[0033] Figure 4 A module structure diagram of a semiconductor device design system provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0035] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0036] In addition, the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.
[0037] like Figure 1 As shown, the embodiment of the present disclosure provides a semiconductor device design method, wherein the semiconductor device includes at least one pair of device units that are adjacent and separated by a gap, and the semiconductor device design method includes but is not limited to the following steps:
[0038] Step 110: setting different gap distance values for the gaps in the pattern of the semiconductor device to obtain a plurality of patterns of the semiconductor device;
[0039] Step 120: using the plurality of patterns of the semiconductor device to respectively manufacture a plurality of the semiconductor devices;
[0040] Step 130: testing the electrical performance of the plurality of semiconductor devices respectively to obtain a plurality of corresponding sets of electrical performance data, and screening out target electrical performance data that meets preset performance conditions from the plurality of sets of electrical performance data, and using the gap distance value corresponding to the target electrical performance data as the target gap distance value;
[0041] The electrical performance data includes a bridge current between adjacent device units separated by the gap, and / or a leakage current of the device units.
[0042] Using the semiconductor device design method of this embodiment, the different gap distance values between device unit patterns are dynamically adjusted based on the electrical performance data such as leakage current and / or bridge current, and finally the target electrical performance data that meets the preset performance conditions are screened out. The target electrical performance data is considered to be optimal, so the gap distance value corresponding to it can be used as the target gap distance value, and the target gap distance value is used as the final gap distance value between the corresponding device units in the future semiconductor device.
[0043] Therefore, compared with the related art which cannot provide an effective gap determination solution, the semiconductor device design method of the present embodiment can accurately determine the gap distance value between corresponding device units in the semiconductor device.
[0044] In the embodiment of the present disclosure, before manufacturing the same device unit in the semiconductor device, the above step 110 is performed, specifically using one or more electronic design automation (EDA) tools for testing semiconductor device design. In some embodiments, the EDA tool is a set of one or more sets of executable instructions executed by a processor or controller or a programmed computer to perform a specified function.
[0045] In performing step 110, a pattern design of a semiconductor device is generated or provided by a circuit engineer. In some embodiments, the design is generated or provided in the form of a schematic netlist such as a Simulation Program for Integrated Circuits (SPICE) netlist.
[0046] In some implementations, when executing step 110 , different gap distance values are set for the gap patterns between at least one stack of device units in the pattern of the semiconductor device, and accordingly a plurality of design patterns of the semiconductor device can be obtained.
[0047] Among them, different gap distance values can be automatically generated according to a certain algorithm. For example, based on a certain empirical value, the gap distance is automatically reduced according to a certain step length, so as to obtain multiple gradually decreasing gap distance values. The implementation method itself does not limit the specific value of the step length.
[0048] In the embodiments of the present disclosure, Figure 2 As shown, the device unit includes a MOS transistor T0, wherein a gap is formed between the gates of a pair of MOS transistors T0 and T1 adjacent to each other along a gate line direction LL, and a gap distance value H of the gap refers to the distance between the gates of the MOS transistors T0 and T1.
[0049] In this embodiment, performing step 110 to set different gap distance values for the gaps in the pattern of the semiconductor device to obtain multiple patterns of the semiconductor device specifically includes:
[0050] The gap between the semiconductor substrate active area AA where a pair of MOS transistors T0 and T1 adjacent along the gate line direction LL are located is kept unchanged, and different length values X of the gate end of the MOS transistor T0 exceeding the active area AA along the gate line direction are set, and the length value X corresponds to the gap distance value H.
[0051] refer to Figure 2 , the gap distance between the semiconductor substrate active area AA where a pair of MOS transistors T0 and T1 adjacent to each other along the gate line direction LL is Y=2X+H. Wherein, if Y is constant, X increases and H decreases. When actually designing the pattern of MOS transistors, H is reduced by increasing X, or H is increased by reducing X.
[0052] In some embodiments, the active region in the semiconductor substrate refers to an area where carriers are active. For example, for a MOS transistor, the active region refers to the source, drain, and the channel therebetween, and carriers flow between the source, drain, and channel after conduction.
[0053] In the embodiments of the present disclosure, the semiconductor device may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a flash memory (English: flash memory), or other logic circuits.
[0054] Taking SRAM as an example, it includes a plurality of SRAM cells arranged along the gate line direction LL, each RAM cell includes a MOS transistor with a common gate, wherein a gap is formed between the common gates of the MOS transistors of two adjacent SRAM cells along the gate line direction LL.
[0055] In the embodiment of the present disclosure, when multiple patterns of semiconductor devices are obtained by executing step 110, step 120 is executed to respectively manufacture multiple semiconductor devices using these patterns.
[0056] Specifically, the semiconductor device includes a semiconductor substrate and a plurality of device units formed in and / or above the semiconductor substrate. The semiconductor substrate includes but is not limited to bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate or a silicon-germanium substrate. In some embodiments, other semiconductor materials including group III, group IV and group V elements are used. Each of the device units includes at least part or the whole of an active element or a passive element. Examples of active elements include but are not limited to the above-mentioned MOS transistors and diodes.
[0057] Examples of MOS transistors include, but are not limited to, metal oxide field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PEFT / NEFT), etc., fin field effect transistors (FinFETs) with raised source / drain, and planar MOS transistors. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, resistors, and interconnects. Examples of interconnects include, but are not limited to, vias, conductive pads, wires, and conductive redistribution layers.
[0058] In the embodiment of the present disclosure, when a plurality of semiconductor devices are manufactured, step 130 is performed to test the electrical performance of the plurality of semiconductor devices respectively.
[0059] In one implementation, for a MOS transistor, the gap distance value H is set by setting different length values X of the gate end of the MOS transistor beyond the active area AA along the gate line direction LL, and X will affect the performance of the MOS transistor itself.
[0060] Therefore, this embodiment implements the electrical performance test by detecting the leakage current of the MOS transistor, wherein the smaller the leakage current, the better the performance of the MOS transistor.
[0061] In some embodiments, the preset performance condition includes that the leakage current corresponding to the target electrical performance data is in the picoampere level. A picoampere is 10 to the negative 12th power of an ampere.
[0062] In a further embodiment, the preset performance condition also includes: starting from the leakage current corresponding to the target electrical performance data, each leakage current thereafter shows a decreasing trend and the fluctuation value does not exceed the fluctuation value threshold. In other words, the leakage current corresponding to the target electrical performance data that meets the preset performance condition is not necessarily the minimum value, but starting from this leakage current, even if the length value X of the gate terminal is changed, the leakage current decreases slowly and no longer has a large fluctuation. Therefore, the length value x of the gate terminal corresponding to the leakage current at this time is used as the final target value.
[0063] In a corresponding embodiment, the electrical performance of the plurality of semiconductor devices is tested respectively, including:
[0064] When the corresponding device unit is controlled to be turned off, the leakage current between the input terminal and the output terminal of the device unit is measured. Figure 3 As shown, for a MOS transistor, the leakage current between its source S and drain D is measured.
[0065] In another embodiment, the preset performance condition includes that the bridge current corresponding to the target electrical performance data is lower than the expected value. As mentioned above, when the gap between device units is reduced, bridging problems will arise. Therefore, in this embodiment, a plurality of semiconductor devices are obtained by setting different gap distance values and specifically manufacturing them, and then the bridge current between two adjacent gate terminals is measured. There is no bridge current or the bridge current is small, and the corresponding gap distance value can meet the preset performance condition.
[0066] In one implementation, the leakage current and the bridging current may be measured simultaneously, and when both the leakage current and the bridging current satisfy the preset performance conditions, the gap distance value at this time is taken as the final value.
[0067] The present disclosure also provides a semiconductor device design system, wherein the semiconductor device includes at least one pair of device units that are adjacent and separated by a gap, such as Figure 4 As shown, the semiconductor device design system specifically includes:
[0068] A setting module 410 is configured to set different gap distance values for the gaps in the pattern of the semiconductor device to obtain a plurality of patterns of the semiconductor device;
[0069] A manufacturing module 420, using a plurality of patterns of the semiconductor device to manufacture a plurality of the semiconductor devices respectively;
[0070] The testing module 430 tests the electrical performance of the plurality of semiconductor devices respectively to obtain a plurality of corresponding sets of electrical performance data, and selects target electrical performance data that meets a preset performance condition from the plurality of sets of electrical performance data, and uses the gap distance value corresponding to the target electrical performance data as the target gap distance value;
[0071] The electrical performance data includes a bridge current between adjacent device units separated by the gap, and / or a leakage current of the device units.
[0072] By using the semiconductor device design system of the present embodiment, the gaps between device units in the semiconductor device can be accurately calculated, thereby achieving accurate design of the semiconductor device pattern.
[0073] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A semiconductor device design method, characterized in that: wherein the semiconductor device comprises at least one pair of device units adjacent to each other and separated by a gap; The semiconductor device design method comprises: Setting different gap distance values for the gaps in the pattern of the semiconductor device to obtain a plurality of patterns of the semiconductor device; Using a plurality of patterns of the semiconductor device, respectively manufacturing a plurality of the semiconductor devices; Testing the electrical performance of the plurality of semiconductor devices respectively to obtain corresponding sets of electrical performance data, and screening out target electrical performance data that meets preset performance conditions from the plurality of sets of electrical performance data, and using the gap distance value corresponding to the target electrical performance data as the target gap distance value; The electrical performance data includes a bridge current between adjacent device units separated by the gap, and / or a leakage current of the device units.
2. The semiconductor device design method according to claim 1, characterized in that: The preset performance condition includes that the leakage current corresponding to the target electrical performance data is at the picoampere level.
3. The semiconductor device design method according to claim 2, characterized in that: The preset performance condition also includes: starting from the leakage current corresponding to the target electrical performance data, each leakage current thereafter shows a decreasing trend and the fluctuation value does not exceed the fluctuation value threshold.
4. The semiconductor device design method according to claim 1, characterized in that: The step of testing the electrical performance of the plurality of semiconductor devices respectively comprises: When the device unit is controlled to be cut off, the leakage current between the input terminal and the output terminal of the device unit is measured.
5. The semiconductor device design method according to claim 1, characterized in that: The preset performance condition includes that the bridge current corresponding to the target electrical performance data is lower than an expected value.
6. The semiconductor device design method according to claim 1, characterized in that: The device unit comprises a MOS transistor, wherein the gap is formed between gates of a pair of MOS transistors adjacent to each other along a gate line direction; The gaps in the pattern of the semiconductor device are set to different gap distance values to obtain a plurality of patterns of the semiconductor device, comprising: The gap between active regions in a semiconductor substrate where a pair of MOS transistors adjacent along the gate line are located is kept unchanged, and different length values of the gate ends of the MOS transistors extending beyond the active regions along the gate line are set, and the length values correspond to the gap distance values.
7. The semiconductor device design method according to claim 6, characterized in that: The semiconductor device is a static random access memory, a dynamic random access memory or a flash memory.
8. The semiconductor device design method according to claim 7, characterized in that: The semiconductor device is the static random access memory, which includes a plurality of static random access memory cells arranged along the gate line direction, each of the static random access memory cells includes the MOS transistor with a common gate, wherein the gap is formed between the common gates of the MOS transistors of two adjacent static random access memory cells along the gate line direction.
9. A semiconductor device design system, characterized in that: wherein the semiconductor device comprises at least one pair of device units adjacent to each other and separated by a gap; The semiconductor device design system comprises: A setting module, which sets different gap distance values for the gap in the pattern of the semiconductor device to obtain a plurality of patterns of the semiconductor device; A manufacturing module, using a plurality of patterns of the semiconductor device to manufacture a plurality of the semiconductor devices respectively; A testing module, for testing electrical performance of the plurality of semiconductor devices respectively to obtain corresponding multiple sets of electrical performance data, and for selecting target electrical performance data that meets preset performance conditions from the multiple sets of electrical performance data, and taking the gap distance value corresponding to the target electrical performance data as the target gap distance value; The electrical performance data includes a bridge current between adjacent device units separated by the gap, and / or a leakage current of the device units.
10. The semiconductor device design system according to claim 9, characterized in that: The preset performance condition includes that the leakage current corresponding to the target electrical performance data is at the picoampere level.