Multi-depth trench isolation for electrostatic discharge protection devices

Abstract

The invention relates to multiple depth trench isolation for electrostatic discharge protection devices. Structures including electrostatic discharge protection devices and methods of forming the same are provided. The structure includes a semiconductor substrate having a top surface, an electrostatic discharge protection device including a base in the semiconductor substrate, and first and second trench isolation regions disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth is greater than the first depth.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices and integrated circuit manufacturing, and more particularly to structures including electrostatic discharge protection devices and methods of forming the same. Background Art

[0002] Integrated circuits may be exposed to random electrostatic discharge (ESD) events, which may cause damage to sensitive electronic devices of the integrated circuit. An ESD event is an unpredictable discharge of positive or negative current that occurs over a short period of time, during which a potentially large and damaging current is directed to the sensitive devices of the integrated circuit. ESD events may occur during post-manufacturing chip handling or after the chip is mounted on a printed circuit board or other carrier. ESD events may originate from a variety of sources, such as the human body, machine components, or chip carriers.

[0003] Precautions may be taken to protect the integrated circuit from damage during an ESD event. One such precaution is to provide an on-chip protection circuit designed to avoid damage to the sensitive devices of the integrated circuit during an ESD event. If an ESD event occurs, the protection circuit triggers the protection device to enter a low impedance state to conduct the ESD current to ground and thereby shunt the ESD current away from the sensitive devices of the integrated circuit. The protection device remains clamped in its low impedance state until the ESD current is exhausted and the ESD voltage is discharged to an acceptable level.

[0004] Improvements are needed in the structure of electrostatic discharge protection devices and methods of forming the same. Summary of the invention

[0005] In one embodiment, a structure includes a semiconductor substrate having a top surface, an electrostatic discharge protection device including a base located in the semiconductor substrate, a first trench isolation region disposed in the base of the electrostatic discharge protection device, and a second trench isolation region disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, and the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth is greater than the first depth.

[0006] In one embodiment, a method includes forming an electrostatic discharge protection device including a base located in a semiconductor substrate, forming a first trench isolation region disposed in the base of the electrostatic discharge protection device, and forming a second trench isolation region disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from a top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth is greater than the first depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals are used to represent similar features in different views.

[0008] Figure 1 A cross-sectional view showing a structure according to an embodiment of the present invention.

[0009] Figure 2 Display in Figure 1 A cross-sectional view of the structure at a later stage of fabrication.

[0010] Figure 3 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0011] Figure 4 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0012] Figure 5 A cross-sectional view showing a structure according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0013] Please refer to Figure 1 According to an embodiment of the present invention, a device structure 10 for an electrostatic discharge protection device includes a semiconductor substrate 12, a deep well 14, a deep trench isolation region 16, intermediate trench isolation regions 18, 19, and shallow trench isolation regions 20, 21, 22 in the semiconductor substrate. The semiconductor substrate 12 may include a semiconductor layer 15 surrounded by the deep well 14 and the deep trench isolation region 16 on multiple sides. The semiconductor substrate 12 may be composed of a semiconductor material, such as single crystal silicon. In one embodiment, the semiconductor layer 15 (which may be epitaxially grown) may be composed of a semiconductor material (such as single crystal silicon) that is doped to have n-type conductivity.

[0014] The deep well 14 is doped to have the same conductivity type as the semiconductor layer 15, but at a higher dopant concentration. In one embodiment, the deep well 14 may include a concentration of n-type dopants, such as arsenic or phosphorus, so that the deep well 14 has n-type conductivity. In one embodiment, the deep well 14 may be formed by introducing n-type dopants into the semiconductor substrate 12 by, for example, masked ion implantation. The implantation conditions (e.g., ion species, dose, and kinetic energy) may be selected to adjust the electrical and physical properties of the deep well 14.

[0015] The deep trench isolation region 16, the middle trench isolation regions 18, 19, and the shallow trench isolation regions 20, 21, 22 extend from the top surface 17 of the semiconductor substrate 12 to different depths in the semiconductor substrate 12. In particular, the deep trench isolation region 16 extends from the top surface 17 to a greater depth in the semiconductor substrate 12 than the middle trench isolation regions 18, 19. In one embodiment, the deep trench isolation region 16 may extend from the top surface 17 to a depth D1 in the semiconductor substrate 12, the middle trench isolation regions 18, 19 may extend from the top surface 17 to a depth D2 in the semiconductor substrate 12, and the shallow trench isolation regions 20, 21, 22 may extend from the top surface 17 to a depth less than the depth D2. The depth D2 of the middle trench isolation regions 18, 19 is greater than the depth of the shallow trench isolation regions 20, 21, 22, and the depth D1 of the deep trench isolation region 16 is greater than the depth D2 of the middle trench isolation regions 18, 19.

[0016] The deep trench isolation region 16 may be arranged to pass through a portion of the shallow trench isolation region 20. The intermediate trench isolation regions 18 and 19 may be arranged to pass through different portions of the shallow trench isolation region 22. The shallow trench isolation region 21 is laterally disposed between the deep trench isolation region 16 and the intermediate trench isolation regions 18 and 19. The shallow trench isolation regions 21 and 22 and the intermediate trench isolation regions 18 and 19 are surrounded by the deep trench isolation region 16.

[0017] The shallow trench isolation regions 20, 21, 22 may be formed by patterning shallow trenches using photolithography and etching processes, depositing a dielectric material (e.g., silicon dioxide) in the shallow trenches, and planarizing and / or recessing the deposited dielectric material. The deep trench isolation region 16 and the middle trench isolation regions 18, 19 may be formed by patterning trenches in the semiconductor substrate 12, lining the trenches with a dielectric collar 25, and filling the trenches with a conductor layer 23. The dielectric collar 25 may be composed of a dielectric material (e.g., silicon dioxide), which is an electrical insulator, and the conductor layer 23 may be composed of a conductor, such as doped polysilicon. The trenches used to form the middle trench isolation regions 18, 19 may be patterned with a narrower width than the trenches used to form the deep trench isolation region 16, which results in the middle trench isolation regions 18, 19 having a shallower depth than the deep trench isolation region 16. Before forming the dielectric collar 25 and the conductor layer 23, the doped region 13 may be formed by masked ion implantation at the base of the trench for forming the deep trench isolation region 16. In one embodiment, the doped region 13 may include a certain concentration of p-type dopants (such as boron) to make the doped region 13 have p-type conductivity.

[0018] Wells 24 and 26 may be disposed in the semiconductor substrate 12, and the well 24 is disposed between the well 26 and the top surface 17 in the vertical direction. The shallow trench isolation region 22 is completely disposed in the well 24, and a portion of the shallow trench isolation region 21 is disposed in the well 24. Wells 28 and 30 may be disposed in the semiconductor substrate 12 between the deep trench isolation region 16 and the wells 24 and 26. The wells 28 and 30 may be disposed between wells 32 and 34 and the top surface 17 in the vertical direction, respectively.

[0019] In one embodiment, wells 24, 26 may include a concentration of p-type dopant (e.g., boron) to provide p-type conductivity. Well 24 may have a higher dopant concentration than well 26. Well 24 may be formed by selectively implanting ions (e.g., ions including the p-type dopant) using an implantation mask having openings to define the desired location of well 24 in semiconductor substrate 12. Well 26 may be formed by selectively implanting ions (e.g., ions including the p-type dopant) using an implantation mask having openings to define the desired location of well 26 in semiconductor substrate 12. Implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of wells 24, 26.

[0020] In one embodiment, wells 28, 30 and wells 32, 34 may include a concentration of an n-type dopant (e.g., arsenic or phosphorus) to provide n-type conductivity. Wells 28, 30 may have a higher dopant concentration than wells 32, 34, and wells 32, 34 may have a higher dopant concentration than semiconductor layer 15 of semiconductor substrate 12. Wells 28, 30 may be formed by selectively implanting ions (e.g., ions including the n-type dopant) using an implantation mask having openings to define the desired locations of wells 28, 30 in semiconductor substrate 12. Wells 32, 34 may be simultaneously formed by selectively implanting ions (e.g., ions including the n-type dopant) using an implantation mask having openings to define the desired locations of wells 32, 34 in semiconductor substrate 12. Implantation conditions (e.g., ion species, dose, and kinetic energy) may be selected to adjust the electrical and physical properties of wells 28, 30 and wells 32, 34.

[0021] A doped region 41 is disposed in well 28, a doped region 42 is disposed in well 30, and a doped region 43 is disposed in well 24. Doped regions 41, 42, 43 are disposed adjacent to top surface 17. Doped region 43 is surrounded by shallow trench isolation region 22.

[0022] Doped regions 41, 42 may be doped to have the same conductivity type as wells 28, 30, but at a higher dopant concentration, and doped region 43 may be doped to have the opposite conductivity type as well as well 24. In one embodiment, doped regions 41, 42, 43 may include a concentration of an n-type dopant (e.g., arsenic or phosphorus) to provide n-type conductivity. Doped regions 41, 42, 43 may be simultaneously formed by selectively implanting ions (e.g., ions including the n-type dopant) using an implantation mask having openings to define the desired locations of doped regions 41, 42, 43 in semiconductor substrate 12. Implantation conditions (e.g., ion species, dose, and kinetic energy) may be selected to adjust the electrical and physical properties of doped regions 41, 42, 43.

[0023] Doped regions 44, 45 are disposed in the well 24. The doped regions 44, 45 are disposed adjacent to the top surface 17. The doped regions 44, 45 may be doped to have the same conductivity type as the well 24, but at a higher dopant concentration. In one embodiment, the doped regions 44, 45 may include a concentration of a p-type dopant (e.g., boron) to provide p-type conductivity. The doped regions 44, 45 may be formed simultaneously by selectively implanting ions (e.g., ions including the p-type dopant) using an implantation mask having openings to define the desired locations of the doped regions 44, 45 in the semiconductor substrate 12. Implantation conditions (e.g., ion species, dose, and kinetic energy) may be selected to adjust the electrical and physical properties of the doped regions 44, 45. The shallow trench isolation region 22 is disposed between the doped regions 44, 45 and the doped region 43.

[0024] The deep trench isolation region 16 may pass through the deep well 14 and into the portion of the semiconductor substrate 12 located below the deep well 14. In one embodiment, the intermediate trench isolation regions 18, 19 may pass completely through the well 24 and partially through the well 26, so that the bottom of the intermediate trench isolation regions 18, 19 is disposed within the well 26, and the bottom of the intermediate trench isolation regions 18, 19 terminates inside the well 26.

[0025] The device structure 10 for the electrostatic discharge protection device can be characterized by a bipolar transistor structure, which includes an emitter represented by a doped region 43, a base represented by wells 24 and 26, and a collector represented by a semiconductor layer 15, wells 28 and 30, and wells 32 and 34. The semiconductor layer 15, wells 28 and 30, and wells 32 and 34 of the collector are all doped to have the same conductivity type (e.g., n-type conductivity), but have various different dopant concentrations. The collector is doped to have the same conductivity type as the emitter and the opposite conductivity type to the base. In one embodiment, well 28 can be continuous with well 30, and continuous wells 28 and 30 can surround the base and emitter, and well 32 can be continuous with well 34, and continuous wells 32 and 34 can surround the base and emitter.

[0026] The intermediate trench isolation regions 18, 19 and the shallow trench isolation regions 22 are provided in the base. The intermediate trench isolation regions 18, 19 (surrounding the doped region 43 representing the emitter) extend to a depth D2 in the base. The shallow trench isolation regions 22 (also surrounding the doped region 43 representing the emitter) extend to a depth less than the depth D2 in the base. The base can be considered to surround the intermediate trench isolation regions 18, 19 by being physically located on multiple sides of the intermediate trench isolation regions 18, 19. In this regard, the intermediate trench isolation regions 18, 19 can partially pass through the base so that a portion of the well 26 extends below the intermediate trench isolation regions 18, 19. The deep trench isolation region 16 surrounds the emitter, base, and collector, and also surrounds the intermediate trench isolation regions 18, 19.

[0027] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1, and in the next manufacturing stage, a dielectric layer 46 may be formed, which includes segments disposed on the top surface 17 of the semiconductor substrate 12. The dielectric layer 46 may be composed of a dielectric material (e.g., silicon nitride) that is deposited and then patterned by photolithography and etching processes to form the segments. A segment of the dielectric layer 46 has an overlapping relationship with a portion of the doped region 41. Another segment of the dielectric layer 46 has an overlapping relationship with a portion of the doped region 42. Other portions of the doped regions 41, 42 (adjacent to the shallow trench isolation region 20) do not overlap with the segments of the dielectric layer 46. The segments of the dielectric layer 46 have an overlapping relationship with a portion of the doped region 43 adjacent to the shallow trench isolation region 22, and another portion of the doped region 43 does not overlap with the segments of the dielectric layer 46. The segments of the dielectric layer 46 may act as a silicide blocking layer.

[0028] The device structure 10 may include an interconnect structure 58 formed by middle-of-line processing and back-end-of-line processing. The interconnect structure 58 may include electrical connections 50, 52, 54 coupled to the ESD protection device. The electrical connections 50, 52, 54 may include metal features disposed in one or more dielectric layers of the interconnect structure 58.

[0029] Electrical connection 50 is physically and electrically connected to the portions of doped regions 41, 42 not covered by the sections of dielectric layer 46, and electrical connection 50 provides connection through doped regions 41, 42 to semiconductor layer 15, wells 28, 30, and wells 32, 34 that provide the collector. Electrical connection 52 is physically and electrically connected to doped regions 44, 45 in well 24 provided for the base. Electrical connection 54 is physically and electrically connected to doped region 43 that provides the emitter. Doped regions 44, 45 are connected to doped region 43 through electrical connection 52 to connect the base to the emitter. Silicide (not shown) may be formed on the portions of doped regions 41, 42, 43, 44, 45 not covered by the sections of dielectric layer 46.

[0030] The resistivity of the base is increased by the presence of the intermediate trench isolation regions 18, 19, which provide resistance within the device structure 10. The intermediate trench isolation regions 18, 19 are disposed in a lateral direction between the electrical connections 52 to the base and the emitter. Thus, the internal resistance between the emitter and the base introduced by the intermediate trench isolation regions 18, 19 can eliminate one or more external resistors connected between the base and the emitter in a conventional device structure, thereby reducing the footprint of the device structure 10. The intermediate trench isolation regions 18, 19 can also be used to reduce the trigger voltage of the device structure 10.

[0031] Please refer to Figure 3 , wherein similar reference numerals denote Figure 1 , and according to an alternative embodiment of the present invention, the deep well 14 can be eliminated, and an additional middle trench isolation region 60 can be formed together with the middle trench isolation regions 18, 19. In one embodiment, the middle trench isolation region 60 can be the same as the middle trench isolation regions 18, 19. The middle trench isolation region 60 can increase the internal resistance between the emitter and the base.

[0032] Please refer to Figure 4 , wherein similar reference numerals denote Figure 1 , and according to an alternative embodiment of the present invention, the device structure 10 for the electrostatic discharge protection device can be modified to form a vertical silicon controlled rectifier by eliminating the middle trench isolation region 18, adding doped regions 66, 68, and adding a trench isolation region 62, the trench isolation region 62 extending to a different depth in the semiconductor substrate 12 than the deep trench isolation region 16 or the middle trench isolation region 18. In particular, the trench isolation region 62 extends from the top surface 17 to a greater depth in the semiconductor substrate 12 than the middle trench isolation region 18, and extends to a shallower depth in the semiconductor substrate 12 than the deep trench isolation region 16. In one embodiment, the trench isolation region 62 may extend to a depth D3 in the semiconductor substrate 12 that is greater than the depth D2 of the middle trench isolation region 18 and less than the depth D1 of the deep trench isolation region 16.

[0033] The trench isolation region 62 may be arranged to pass through the shallow trench isolation region 21 and enter the semiconductor substrate 12 located below the shallow trench isolation region 21. The trench isolation region 62 is disposed between the deep trench isolation region 16 and the middle trench isolation region 18. The trench isolation region 62 surrounds the shallow trench isolation regions 21, 22 and the middle trench isolation region 18, and the trench isolation region 62 is surrounded by the deep trench isolation region 16. The trench isolation region 62 may be formed when the deep trench isolation region 16 and the middle trench isolation region 18 are formed, and may include portions of the dielectric collar 25 and the conductor layer 23. The trench used to form the trench isolation region 62 may be patterned with a larger width than the trench used to form the middle trench isolation region 18 and a narrower width than the trench used to form the deep trench isolation region 16, which results in the trench patterned to form the trench isolation region 62 having a greater depth than the trench patterned to form the middle trench isolation region 18.

[0034] Doped regions 66, 68 may be formed in semiconductor substrate 12 by introducing dopants having a given conductivity type in semiconductor substrate 12 by, for example, ion implantation. A patterned implantation mask may be formed to define selected areas on top surface 17 that are exposed for the ion implantation. Implantation conditions (e.g., ion species, dose, and kinetic energy) may be selected to adjust the electrical and physical properties of doped regions 66, 68. Doped regions 66, 68 are doped to have a conductivity type opposite to wells 28, 30, and wells 32, 34. In one embodiment, doped regions 66, 68 may include a concentration of p-type dopants (e.g., boron) to provide p-type conductivity.

[0035] Please refer to Figure 5 , wherein similar reference numerals denote Figure 1 , and according to an alternative embodiment of the present invention, the device structure 10 for the electrostatic discharge protection device can be modified to form a lateral bipolar junction transistor. The doped region 43 can represent the emitter (E) of the lateral bipolar junction transistor, the well 26 can represent the base (B) of the lateral bipolar junction transistor, and the wells 28, 30, and the wells 32, 34 can represent the collector (C) of the lateral bipolar junction transistor. The intermediate trench isolation regions 18, 19 (surrounding the doped region 43 representing the emitter) enter the well 26 representing the base and partially pass through the well 26. The resistivity of the base is increased by the presence of the intermediate trench isolation regions 18, 19, which provide resistance inside the device structure 10.

[0036] The method described above is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smart phone with a central processing unit.

[0037] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0038] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction in the reference frame that is within the horizontal plane.

[0039] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if there is at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "in direct contact with" another feature if there is at least one intermediate feature. Different features may "overlap" if one feature extends over and covers part of another feature.

[0040] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure, characterized in that: include: a semiconductor substrate having a top surface; An electrostatic discharge protection device, comprising a base located in the semiconductor substrate; A first trench isolation region is provided in the base of the electrostatic discharge protection device, the first trench isolation region extending from the top surface of the semiconductor substrate to a first depth in the base; as well as The second trench isolation region is disposed in the base of the electrostatic discharge protection device. The second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth is greater than the first depth.

2. The structure according to claim 1, characterized in that The electrostatic discharge protection device comprises a collector located in the semiconductor substrate and an emitter located in the semiconductor substrate, the collector and the emitter have a first conductivity type, and the base has a second conductivity type opposite to the first conductivity type.

3. The structure according to claim 2, characterized in that The second trench isolation region surrounds the emitter.

4. The structure according to claim 3, characterized in that The first trench isolation region surrounds the emitter, and the second trench isolation region passes through a portion of the first trench isolation region into the base.

5. The structure according to claim 2, characterized in that Also includes: A third trench isolation region is disposed in the semiconductor substrate, and the third trench isolation region extends from the top surface of the semiconductor substrate to a third depth greater than the second depth.

6. The structure according to claim 5, characterized in that The third trench isolation region surrounds the emitter, the base, the first trench isolation region and the second trench isolation region.

7. The structure according to claim 6, characterized in that Also includes: A fourth trench isolation region is disposed in the semiconductor substrate, and the fourth trench isolation region extends from the top surface of the semiconductor substrate to a fourth depth greater than the third depth.

8. The structure according to claim 7, characterized in that The fourth trench isolation region surrounds the collector, the emitter, the base, the first trench isolation region and the second trench isolation region.

9. The structure according to claim 1, characterized in that Also includes: A third trench isolation region is disposed in the semiconductor substrate, and the third trench isolation region extends from the top surface of the semiconductor substrate to the second depth in the base.

10. The structure according to claim 9, characterized in that The electrostatic discharge protection device includes a collector located in the semiconductor substrate and an emitter located in the semiconductor substrate, the collector and the emitter have a first conductivity type, the base has a second conductivity type opposite to the first conductivity type, and the second trench isolation region and the third trench isolation region surround the emitter.

11. The structure according to claim 10, characterized in that The first trench isolation region surrounds the emitter, the second trench isolation region extends through a first portion of the first trench isolation region into the base, and the third trench isolation region passes through a second portion of the first trench isolation region into the base.

12. The structure according to claim 9, characterized in that The base surrounds the second trench isolation region and the third trench isolation region.

13. The structure according to claim 9, characterized in that Also includes, A fourth trench isolation region is disposed in the semiconductor substrate, and the fourth trench isolation region extends from the top surface of the semiconductor substrate to the second depth in the base.

14. The structure according to claim 1, characterized in that The second trench isolation region partially passes through the base.

15. The structure according to claim 1, characterized in that Also includes: The third trench isolation region is arranged in the semiconductor substrate, the third trench isolation region surrounds the base, the first trench isolation region and the second trench isolation region, and the third trench isolation region extends to a third depth in the semiconductor substrate, and the third depth is greater than the second depth.

16. The structure according to claim 15, characterized in that The electrostatic discharge protection device comprises a collector located in the semiconductor substrate and an emitter located in the semiconductor substrate, the collector and the emitter have a first conductivity type, and the base has a second conductivity type opposite to the first conductivity type.

17. The structure according to claim 16, characterized in that The second trench isolation region surrounds the emitter, and the third trench isolation region surrounds the emitter and the collector.

18. The structure according to claim 1, characterized in that The second trench isolation region passes through a portion of the first trench isolation region into the base.

19. The structure according to claim 1, characterized in that The base surrounds the first trench isolation region.

20. A method, characterized in that include: forming an electrostatic discharge protection device, the electrostatic discharge protection device comprising a base located in a semiconductor substrate, forming a first trench isolation region, the first trench isolation region being disposed in the base of the electrostatic discharge protection device, and forming a second trench isolation region, wherein the second trench isolation region is disposed in the base of the electrostatic discharge protection device, The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, and the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth is greater than the first depth.

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